Retention of cache entries of a processor core during a shutdown state
Patent Information
- Application Number
- DE602018081033
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2017-11-01
- Filing Date
- 2018-09-14
- Publication Date
- 2025-04-09
- Estimated Expiration
- 2038-09-14
AI Technical Summary
Conventional processing systems fail to maintain cache coherence between powered-up caches and caches that are powered down, leading to performance degradation when processor cores exit a powered-down state due to the absence of up-to-date information in the caches.
The solution involves storing entries in a cache, such as a translation lookaside buffer (TLB) or a lower-level cache, in a retention region that receives a retention voltage while the processor core is in a powered-down state. This retention region can be implemented in a higher-level cache, external memory, or within the cache itself, allowing for the restoration of cache entries and invalidation information when the processor core powers up.
This approach accelerates the performance of processor cores when they exit a powered-down state by maintaining cache coherence and ensuring that up-to-date information is readily available, thereby reducing the overhead associated with reinitializing cache entries.