Sliding registration unit and control method therefor, gate driver switching

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a display device, and a method for driving the display device or the shift register unit.BACKGROUND

[0002] With the advancement of display technologies, compared with conventional liquid crystal display (LCD) devices, a new generation of organic light emitting diode (OLED) display devices has advantages of lower manufacturing costs, a faster response speed, higher contrast, a wider viewing angle, a greater operating temperature range, being without the need for a backlight unit, and being colorful and thin. Therefore, the OLED display technology has become the fastest growing display technology.

[0003] In order to improve process integration level and reduce the cost of an OLED panel, a Gate Driver on Array (GOA) technology is usually used, such that a gate switch circuit of a thin film transistor (TFT) can be integrated on an array substrate of the display panel, to form scan driving of the display panel. The gate driving circuit integrated on an array substrate using the GOA technology is also referred to as a GOA circuit or a shift register circuit. Both material and manufacturing process costs can be reduced by using the display device with the GOA circuit, since a binding part for the driving circuit is not required.

[0004] The US patent application US2016 / 307537A1 discloses a stage circuit and scan driver using the same. The US patent application US2019 / 221181A1 discloses a shifting register unit and control method thereof, grid driving circuit and display device. The US patent application US2018 / 301100A1 discloses a display device and gate drive circuit and unit. The US patent application US2018 / 211627A1 discloses a gate driving circuit including N number of cascaded-connected GOA driving units. The Korean patent application KR 2014 00 79 106 A discloses a gate shift register and display device.BRIEF DESCRIPTION

[0005] The invention is set out in the appended set of claims. Embodiments of the present disclosure provide a display device according to independent claim 1, a shift register unit according to independent claim 8, and a method for driving the display device or the shift register unit according to independent method claim 9.

[0006] According to a first aspect of the present disclosure, there is provided_a display device according to claims 1-8.

[0007] According to a second aspect of the present disclosure, there is provided a shift register unit according to claims 9 and 12.

[0008] According to a third aspect of the present disclosure, there is provided a method for driving the display device or the shift register unit, according to claims 10-11.

[0009] Based on the embodiments of the present disclosure, the voltage of the pull-up node and pull-down node can be better stabilized, the leakage current flowing through the input circuit from the pull-up node can be reduced, and the output signal can be controlled based on the control voltage signal.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to illustrate the technical solutions of the present disclosure more clearly, the drawings of the embodiments will be briefly described below. It should be appreciated that the drawings described below are only related to some of the embodiments of the present disclosure, rather than limiting the present disclosure, in which: FIG. 1 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure; FIG. 2 is a schematic block diagram of a shift register unit according to another embodiment of the present disclosure; FIG. 3 is an exemplary circuit diagram of the shift register unit shown in FIG. 2; FIG. 4 is a timing diagram of signals of a shift register unit according to an embodiment of the present disclosure; FIG. 5 is a timing diagram of signals of a shift register unit according to another embodiment of the present disclosure; FIG. 6 is a schematic flow chart of a method for driving the shift register unit as shown in FIG. 3; FIG. 7 is a circuit diagram of a 3T1C pixel circuit; FIG. 8 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure; and FIG. 9 is a schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] In order to make the object, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are merely part of the embodiments of the present disclosure, rather than all of the embodiments. According to the described embodiments, all the other embodiments obtained by those of ordinary skill in the art without creative labor also fall within the scope of protection of the present disclosure.

[0012] Hereinafter, the expression "the element A is coupled to the element B" means that the element A is "directly" connected to the element B or "indirectly" connected to the element B via one or more other elements, unless otherwise stated.

[0013] As used herein, unless otherwise stated, the singular form, "one", "this" or "the", is also intended to include the plural form.

[0014] The term "including" or "comprising", as used herein, refers to the presence of a feature, integer, step, operation, element and / or part, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, components, and / or combinations thereof.

[0015] As used herein, the expressions "first", "second", etc. are used to distinguish two individual entities or parameters with the same name, so "first", "second", etc. are only for the convenience of the description and shall not be construed as limiting the embodiments of the present disclosure.

[0016] FIG. 1 shows a schematic block diagram of a shift register unit 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the shift register unit 100 may include an input circuit 110, a next-stage start circuit 120, a control circuit 130, a stabilization circuit 140, and at least one output circuit (in FIG. 1, only one output circuit 150 is shown as an example, and other output circuits are schematically illustrated by dashed blocks).

[0017] The input circuit 110 may be coupled to a first clock signal terminal CLK1, a trigger signal terminal STU, a pull-up node Q, and a second clock signal terminal CLK2. The input circuit 110 may provide a trigger signal from the trigger signal terminal STU to a first node N1 (not shown in figure 1) according to a first clock signal from the first clock signal terminal CLK1. Moreover, the input circuit 110 may also provide a voltage of the first node N1 to the pull-up node Q according to a first clock signal from the first clock signal terminal CLK1. Specifically, the input circuit 110 may provide, under the control of the first clock signal from the first clock signal terminal CLK1, the trigger signal from the trigger signal terminal STU to the pull-up node Q via the first node N1. Further, the input circuit 110 may provide a second clock signal from the second clock signal terminal CLK2 to the first node N1 according to a voltage of the pull-up node. In this way, a potential of the first node N1 is higher than a potential of the first clock signal when the first node control circuit is enabled according to the pull-up node Q. Therefore, there is no leakage current flowing through the input circuit from the pull-up node, and then the voltage of the pull-up node can be maintained.

[0018] The next-stage start circuit 120 may be coupled to the pull-up node Q, the second clock signal terminal CLK2, a pull-down node QB, a first voltage signal terminal VSS, and a next-stage start signal output terminal CR. The next-stage start circuit 120 may output a next-stage start signal from the next-stage start signal output terminal CR according to the voltage of the pull-up node Q, a voltage of the pull-down node QB, a second clock signal from the second clock signal terminal CLK2, and the first voltage signal from the first voltage signal terminal VSS. Specifically, the next-stage start circuit 120 may provide, under the control of the voltage of the pull-up node Q, the second clock signal from the second clock signal terminal CLK2 to the next-stage start signal output terminal CR. In addition, the next-stage start circuit 120 may also provide, under the control of the voltage of the pull-down node QB, the first voltage signal from the first voltage signal terminal VSS to the next-stage start signal output terminal CR.

[0019] The control circuit 130 may be coupled to the pull-up node Q, the pull-down node QB, and a second voltage signal terminal VSSL. The control circuit 130 may control the voltage of the pull-down node QB according to the voltage of the pull-up node Q and a second voltage signal from the second voltage signal terminal VSSL, and control the voltage of the pull-up node Q according to the voltage of the pull-down node QB and the second voltage signal. Specifically, the control circuit 130 may provide, under the control of the voltage of the pull-up node Q, the second voltage signal from the second voltage signal terminal VSSL to the pull-down node QB. In addition, the control circuit 130 may also provide the second voltage signal from the second voltage signal terminal VSSL to the pull-up node Q under the control of the voltage of the pull-down node QB.

[0020] The stabilization circuit 140 may be coupled to a third clock signal terminal CLK3, the first voltage signal terminal VSS, a third voltage signal terminal VH, the pull-up node Q, and the pull-down node QB. The stabilization circuit 140 may control the voltage of the pull-up node Q and the voltage of the pull-down node QB according to a third clock signal from the third clock signal terminal CLK3, the first voltage signal VSS from the first voltage signal terminal VSS, and a third voltage signal from the third voltage signal terminal VH. Specifically, the stabilization circuit 140 may provide the first voltage signal from the first voltage signal terminal VSS to the pull-up node Q under the control of the third clock signal from the third clock signal terminal CLK3. Further, the stabilization circuit 140 may also provide the third voltage signal from the third voltage signal terminal VH to the pull-down node QB under the control of the third clock signal from the third clock signal terminal CLK3.

[0021] The shift register unit 100 according to an embodiment of the present disclosure may include at least one output circuit. Each of the at least one output circuit is configured to output an output signal from a signal output terminal G, according to the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal VSS, a control clock signal from a control clock signal terminal CLK, and a control voltage signal from a control voltage signal terminal VG.

[0022] As shown in FIG. 1, the shift register unit 100 includes one output circuit 150 as an example. The output circuit 150 may be coupled to the pull-up node Q, the pull-down node QB, the first voltage signal terminal VSS, the control clock signal terminal CLK, the control voltage signal terminal VG, and the signal output terminal G. The output circuit 150 may output an output signal from the signal output terminal G according to the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal VSS, the control clock signal from the control clock signal terminal CLK, and the control voltage signal from the control voltage signal terminal VG. Specifically, the output circuit 150 may provide the control voltage signal from the control voltage signal terminal VG to the signal output terminal G under the control of the voltage of the pull-up node Q. In addition, the output circuit 150 may also provide the first voltage signal from the first voltage signal terminal VSS to the signal output terminal G under the control of the voltage of the pull-down node QB.

[0023] In an embodiment of the present disclosure, a potential of the first voltage signal from the first voltage signal terminal VSS may be higher than a potential of the second voltage signal from the second voltage signal terminal VSSL. Therefore, when the control circuit 130 provides the second voltage signal to the pull-down node QB, the next-stage start signal and the output signal outputted from the next-stage start circuit 120 and the output circuit 150 are more stable. For example, the potential of the first voltage signal is -8V, and the potential of the second voltage signal is -10V.

[0024] In an embodiment of the present disclosure, a high level of the second clock signal begins when a high level of the first clock signal ends, and a high level of the third clock signal begins when a high level of the second clock signal ends.

[0025] At present, a shift register unit usually triggers a shift register signal under the control of a trigger signal, that is, outputs a gate driving signal, whereby only one row of pixels can be driven. An entire gate driving circuit uses a large number of shift register units, occupying a large area and resulting in high cost.

[0026] According to an embodiment of the present disclosure, the shift register unit may output at least one gate driving signal under the control of one trigger signal STU, that is, trigger at least one shift register signal. By controlling the respective control clock signals to adjust the respective output signals, the structure is simple, and the number of shift register units used in the display device is reduced.

[0027] It is noted that the second clock signal CLK2 for controlling the next-stage start circuit 120 does not provide a high level continuously, but provides a high level only during operation, and thus the power consumption of the shift register unit can be reduced.

[0028] FIG. 2 shows a schematic block diagram of a shift register unit 200 according to another embodiment of the present disclosure. As shown in FIG. 2, the input circuit 110, the next-stage start circuit 120, the control circuit 130, and the stabilization circuit 140 of the shift register unit 200 are the same as those in the shift register unit 100 shown in FIG. 1. Further, the shift register unit 200 further includes a first output circuit 151 and a second output circuit 152.

[0029] The first output circuit 151 can be coupled to the pull-up node Q, the pull-down node QB, the first voltage signal terminal VSS, the first control clock signal terminal CLKA, the first control voltage signal terminal VG1, and the first signal output terminal G1. The first output circuit 151 can output a first output signal G1 from the first signal output terminal G1 according to the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal from the first voltage signal terminal VSS, the first control clock signal from the first control clock signal terminal CLKA, and the first control voltage signal from the first control voltage signal terminal VG1. Specifically, the first output circuit 151 can provide the first control voltage signal from the first control voltage signal terminal VG1 to the first signal output terminal G1 under the control of the voltage of the pull-up node Q, or provide the first voltage signal from the first voltage signal terminal VSS to the first signal output terminal G1 under the control of the pull-down node QB.

[0030] The second output circuit 152 can be coupled to the pull-up node Q, the pull-down node QB, the first voltage signal terminal VSS, the second control clock signal terminal CLKB, the second control voltage signal terminal VG2, and the second signal output terminal G2. The second output circuit 152 can output a second output signal G2 from the second signal output terminal G2 according to the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal from the first voltage signal terminal VSS, the second control clock signal from the second control clock signal terminal CLKB, and the second control voltage signal from the second control voltage signal terminal VG2. Specifically, the second output circuit 152 can provide the second control voltage signal from the second control voltage signal terminal VG2 to the second signal output terminal G2 under the control of the voltage of the pull-up node Q, or provide the first voltage signal from the first voltage signal terminal VSS to the second signal output terminal G2 under the control of the pull-down node QB.

[0031] In an embodiment of the present disclosure, the first voltage signal from the first voltage signal terminal VSS and the second voltage signal from the second voltage signal terminal VSSL are low level signals. The third voltage signal from the third voltage signal terminal VH, the first control voltage signal from the first control voltage signal terminal VG1, and the second control voltage signal from the second control voltage signal terminal VG2 are high level signals.

[0032] According to an embodiment of the present disclosure, the shift register unit may output two gate driving signals (e.g., the first output signal G1 and the second output signal G2) under the control of one trigger signal STU, that is, trigger two shift register signals. By adjusting the output signals according to the first control clock signal CLKA and the second control clock signal CLKB, the structure is simple, and the number of shift register units used in the display device is reduced.

[0033] FIG. 3 shows an exemplary circuit diagram of the shift register unit 200 shown in FIG. 2. In an embodiment, the transistors employed may be N-type transistors or P-type transistors. Specifically, the transistors may be N-type or P-type field effect transistors (MOSFETs), or N-type or P-type bipolar transistors (BJTs). In an embodiment of the present disclosure, the gate of a transistor is referred to as a control electrode. Since the source and the drain of the transistor are symmetrical, the source and the drain are not distinguished, that is, the source of the transistor can be the first electrode (or the second electrode), and the drain can be the second electrode (or the first electrode). Further, any controlled switch device having a gating signal input can be used to implement the function of the transistor, and the controlled middle terminal of the switch device for receiving a control signal (e.g., for turning the controlled switch device on and off) is referred to as the control electrode, while the other two terminals are referred to as the first electrode and the second electrode, respectively. Hereinafter, the following detailed description will be given by example of N-type field effect transistors (NMOSs).

[0034] In an embodiment of the present disclosure, each of the at least one output circuit includes a pull-up transistor, a pull-down transistor, and a control transistor. A control electrode of the pull-up transistor is coupled to the pull-up node, a first electrode of the pull-up transistor is coupled to the control voltage signal terminal, and a second electrode of the pull-up transistor is coupled to the signal output terminal. A control electrode of the pull-down transistor is coupled to the pull-down node, a first electrode of the pull-down transistor is coupled to the first voltage signal terminal, and a second electrode of the pull-down transistor is coupled to the signal output terminal. A control electrode of the control transistor is coupled to the control clock signal terminal, a first electrode of the control transistor is coupled to the first voltage signal terminal, and a second electrode of the control transistor is coupled to the signal output terminal.

[0035] As shown in FIG. 3, the input circuit 110 may include a first transistor T1and a second transistor T2, and a twelfth transistor T12. A control electrode of the first transistor T1 is coupled to the first clock signal terminal CLK1, a first electrode of the first transistor T1 is coupled to the trigger signal terminal STU, and a second electrode of the first transistor T1 is coupled to the first node N1 (i.e. electrode of the second transistor T2). A control electrode of the second transistor T2 is coupled to the first clock signal terminal CLK1, a first electrode of the second transistor T2 is coupled to the first node N1 (i.e. second electrode of the first transistor T1), and a second electrode of the second transistor T2 is coupled to the pull-up node Q. A control electrode of the twelfth transistor T12 is coupled to the pull-up node Q, a first electrode of the twelfth transistor T12 is coupled to the first node N1, and a second electrode of the twelfth transistor T12 is coupled to the second clock signal terminal CLK2.

[0036] The next-stage start circuit 120 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor C. A control electrode of the fourth transistor T4 is coupled to the pull-up node Q, a first electrode of the fourth transistor T4 is coupled to the second clock signal terminal CLK2, and a second electrode of the fourth transistor T4 is coupled to the next-stage start signal output terminal CR. A control electrode of the fifth transistor T5 is coupled to the pull-down node QB, a first electrode of the fifth transistor T5 is coupled to the first voltage signal terminal VSS, and a second electrode of the fifth transistor T5 is coupled to the next-stage start signal output terminal CR. The first capacitor C is coupled between the pull-up node Q and the next-stage start signal output terminal CR.

[0037] The control circuit 130 includes a third transistor T3 and a fifteenth transistor T15. A control electrode of the third transistor T3 is coupled to the pull-down node QB, a first electrode of the third transistor T3 is coupled to the second voltage signal terminal VSSL, and a second electrode of the third transistor T3 is coupled to the pull-up node Q. A control electrode of the fifteenth transistor T15 is coupled to the pull-up node Q, a first electrode of the fifteenth transistor T15 is coupled to the second voltage signal terminal VSSL, and a second electrode of the fifteenth transistor T15 is coupled to the pull-down node QB.

[0038] The stabilization circuit 140 includes a thirteenth transistor T13 and a fourteenth transistor T14. A control electrode of the thirteenth transistor T13 is coupled to the third clock signal terminal CLK3, a first electrode of the thirteenth transistor T13 is coupled to the first voltage signal terminal VSS, and a second electrode of the thirteenth transistor T13 is coupled to the pull-up node Q. A control electrode of the fourteenth transistor T14 is coupled to the third clock signal terminal CLK3, a first electrode of the fourteenth transistor T14 is coupled to the third voltage signal terminal VH, and a second electrode of the fourteenth transistor T14 is coupled to the pull-down node QB.

[0039] The first output circuit 151 includes a sixth transistor T6 (corresponding to the pull-up transistor), a seventh transistor T7 (corresponding to the pull-down transistor), and an eighth transistor T8 (corresponding to the control transistor). A control electrode of the sixth transistor T6 is coupled to the pull-up node Q, a first electrode of the sixth transistor T6 is coupled to the first control voltage signal terminal VG1, and a second electrode of the sixth transistor T6 is coupled to the first signal output terminal (i.e., a second electrode of the seventh transistor T7). A control electrode of the seventh transistor T7 is coupled to the pull-down node QB, a first electrode of the seventh transistor T7 is coupled to the first voltage signal terminal VSS, and the second electrode of the seventh transistor T7 is coupled to the second electrode of the sixth transistor T6. A control electrode of the eighth transistor T8 is coupled to the first control clock signal terminal CLKA, a first electrode of the eighth transistor T8 is coupled to the first voltage signal terminal VSS, and a second electrode of the eighth transistor T8 is coupled to the second electrode of the sixth transistor T6. In the embodiment of the present disclosure, the width to a length ratio of the seventh transistor T7 is an integer multiple of a width to length ratio of the sixth transistor T6.

[0040] The second output circuit 152 includes a ninth transistor T9 (corresponding to the pull-up transistor), a tenth transistor T10 (corresponding to the pull-down transistor), and an eleventh transistor T11 (corresponding to the control transistor). A control electrode of the ninth transistor T9 is coupled to the pull-up node Q, a first electrode of the ninth transistor T9 is coupled to the second control voltage signal terminal VG2, and a second electrode of the ninth transistor T9 is coupled to the second signal output terminal (i.e., a second transistor of the tenth transistor T10). A control electrode of the tenth transistor T10 is coupled to the pull-down node QB, a first electrode of the tenth transistor T10 is coupled to the first voltage signal terminal VSS, and the second electrode of the tenth transistor T10 is coupled to the second electrode of the ninth transistor T9. A control electrode of the eleventh transistor T11 is coupled to the second control clock signal terminal CLKB, a first electrode of the eleventh transistor T11 is coupled to the first voltage signal terminal VSS, and a second electrode of the eleventh transistor T11 is coupled to the second electrode of the ninth transistor T9. In an embodiment of the present disclosure, a width to length ratio of the tenth transistor T10 is an integer multiple of a width to length ratio of the ninth transistor T9.

[0041] The operation process of the shift register unit shown in FIG. 3 will be described in detail below with reference to the timing diagram shown in FIG. 4. In the following description, the transistors in the shift register unit are all N-type transistors, as an example. The first voltage signal VSS and the second voltage signal VSSL are low level signals. The potential of the first voltage signal from the first voltage signal terminal VSS is higher than the potential of the second voltage signal from the second voltage signal terminal VSSL. The third voltage signal VH, the first control voltage signal VG1, and the second control voltage signal VG2 are high level signals.

[0042] In the example shown in FIG. 4, the first control clock signal CLKA and the second control clock signal CLKB are low level signals (VGL). Therefore, the eighth transistor T8 and the eleventh transistor T11 are maintained to be turned off.

[0043] In a first period (P1), the first clock signal CLK1 is a high level signal, the second clock signal CLK2 is a low level signal, the third clock signal CLK3 is a low level signal, and the trigger signal STU is a high level signal. During P1, the first transistor T1 and the second transistor T2 of the input circuit 110 are turned on, such that the trigger signal STU is provided to the pull-up node Q via the first node N1, to increase the voltage of the pull-up node Q. The fifteenth transistor T15 is turned on, such that the second voltage signal VSSL is provided to the pull-down node QB to pull the voltage of the pull-down node QB down. Therefore, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are turned off. Under the control of the voltage of the pull-up node Q, by controlling the ratio of the width to length ratio of the seventh transistor T7 to the width to length ratio of the sixth transistor T6 and controlling the ratio of the width to length ratio of the tenth transistor T10 to the width to length ratio of the ninth transistor T9, both the first output terminal G1 and the second signal output terminal G2 output a low level signal. The fourth transistor T4 is turned on to provide the second clock signal CLK2 to the next-stage start signal output terminal CR, that is, the next-stage start signal output terminal CR also outputs a low level signal. In real simulation, during P1, the signals outputted from the next-stage start signal output terminal CR, the first signal output terminal G1, and the second signal output terminal G2 vary slightly, but can still be regarded as low level signals. In the example, the width to length ratio of the seventh transistor T7 is set to be an integral multiple of the width to length ratio of the sixth transistor T6, and the width to length ratio of the tenth transistor T10 is set to be an integral multiple of the width to length ratio of the ninth transistor T9.

[0044] In a second period (P2), the first clock signal CLK1 is a low level signal, the second clock signal CLK2 is a high level signal, the third clock signal CLK3 is a low level signal, and the trigger signal STU is a low level signal. During P1, since the voltage of the pull-up node Q is increased to turn on the fourth transistor T4, the second clock signal CLK2 is transmitted to the next-stage start signal output terminal CR through the fourth transistor T4, so that the next-stage start signal output terminal CR outputs a high level signal. Through the capacitor C, the voltage of the pull-up node Q is further pulled up to a high level due to bootstrapping. The twelfth transistor T12 is turned on to provide the second clock signal CLK2 to the first node N1. In this way, the voltage of the first node N1 (i.e. a source voltage of the second transistor T2) is at a high level, and is higher than the potential of the first clock signal CLK1 (i.e. a gate voltage of the second transistor T2). The gate-source voltage Vgs of the second transistor T2 is below 0. Therefore, the second transistor T2 is turned off more thoroughly, further reducing the leakage current through the second transistor T2 and the first transistor T1 from the pull-up node Q to the trigger signal terminal STU. Therefore, the voltage of the pull-up node can be stabilized.

[0045] Further, the sixth transistor T6 and the ninth transistor T9 are turned on to provide the first control voltage signal VG1 to the first signal output terminal G1 and provide the second control voltage signal VG2 to the second signal output terminal G2, respectively. In the case where the voltage of the pull-up node Q is a third level signal, the fifteenth transistor T15 remains to be turned on to provide the second voltage signal VSSL to the pull-down node QB. Therefore, the voltage of the pull-down node QB (i.e. gate voltages of the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10) is equal to the potential of the second voltage signal VSSL at a low level. Since the source voltages of the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are provided with the first voltage signal VSS, the potential of which is higher than that of the second voltage signal VSSL, the gate-source voltage Vgs of these transistors are below 0. Therefore, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are turned off thoroughly, further reducing the leakage current from the next-stage start signal output terminal and the respective signal output terminals through such transistors. In this way, stable high level signals are outputted from the next-stage start signal output terminal CR, the first signal output terminal G1, and the second signal output terminal G2. Therefore, it can perform full swing output, realizing rail-to-rail output.

[0046] In a third period (P3), the first clock signal CLK1 is a low level signal, the second clock signal CLK2 is a low level signal, the third clock signal CLK3 is a high level signal, and the trigger signal STU is a low level signal. During P3, the thirteenth transistor T13 and the fourteenth transistor T14 are turned on to provide the first voltage signal VSS to the pull-up node Q and provide the third voltage signal VH to the pull-down node QB, such that the voltage of the pull-up node Q is pulled low and the voltage of the pull-down node QB is pulled high. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned off, and the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are turned on. A low level signal is outputted from the next-stage start signal output terminal CR, a low level signal is outputted from the first signal output terminal G1, and a low level signal is outputted from the second signal output terminal G2.

[0047] In a subsequent period, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 provides a high level signal sequentially, the trigger signal STU is maintained at a low level, and the next-stage start signal output terminal CR, the first signal output terminal G1 and the second signal output terminal G2 outputs low level signals.

[0048] In another embodiment of the present disclosure, one of the first control clock signal CLKA and the second control clock signal CLKB is a low level signal, and the other is a high level signal. For example, the first control clock signal CLKA is a low level signal (VGL), and the second control clock signal CLKB is a high level signal (VGH). Therefore, the eighth transistor T8 is turned off, and the eleventh transistor T11 is turned on. As shown in FIG. 5, the first output signal outputted from the first signal output terminal G1 is the same as that of FIG. 4, and the second signal output terminal G2 outputs a low level signal.

[0049] Alternatively, when the first control clock signal CLKA is a high level signal (VGH) and the second control clock signal CLKB is a low level signal (VGL), the eighth transistor T8 is turned on, and the eleventh transistor T11 is turned off. The first signal output terminal G1 outputs a low level signal, and the second output signal outputted from the second signal output terminal G2 is the same with that of FIG. 4.

[0050] Therefore, the two output signals can be controlled by correspondingly adjusting the first control clock signal CLKA and the second control clock signal CLKB.

[0051] In an embodiment of the present disclosure, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 may have the same clock period and the same ratio of high level to low level of 1:2.

[0052] FIG. 6 is a schematic flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure, wherein a control clock signal of a control clock signal terminal of at least one output circuit is a low level signal. In an embodiment of the present disclosure, the first voltage signal VSS and the second voltage signal VSSL are low level signals, and the third voltage signal VH and each control voltage signal VG of the at least one output circuit are high level signals.

[0053] In step S610, in the first period, a first clock signal (for example, a high level signal) is inputted through the first clock signal terminal, and a trigger signal is inputted through the trigger signal terminal, such that the input circuit is enabled to provide the trigger signal to a first node, and provide the voltage of the first node to the pull-up node, such that the pull-up node is increased to a high level. The control circuit controls the voltage of the pull-down node to be a low level. Since the second clock signal and the respective control voltage signal are at low levels, next-stage start signal output terminal of the next-stage start circuit outputs a low level signal, and the signal output terminal of respective output circuit outputs a low level signal.

[0054] In step S620, in the second period, a second clock signal (for example, a high level signal) is inputted through the second clock signal terminal, such that the next-stage start circuit is enabled to output a high level signal from the next-stage start signal output terminal of the next-stage start circuit, the voltage of the pull-up node continues rising to a high level, the voltage of the pull-down node is maintained at a low level, and the signal output terminal of the respective output circuit outputs a high level signal. Moreover, the input circuit provides the high level second clock signal to the first node, such that there is no leakage current flowing through the input circuit from the pull-up node.

[0055] In step S630, in the third period, a third clock signal (for example, a high level signal) is inputted through the third clock signal terminal, such that the stabilization circuit is enabled to change the voltage of the pull-up node to a low level and change the voltage of the pull-down node to a high level, the next-stage start signal output terminal of the next-stage start circuit outputs a low level signal, and the signal output terminal of the respective output circuit outputs a low level signal.

[0056] In another embodiment of the present disclosure, the control clock signal of the control clock signal terminal of one or more of the at least one output circuit is a high level signal. In this case, the signal output terminal of the one or more output circuits output low level signals.

[0057] From the above, according to an embodiment of the present disclosure, by changing the control clock signal of the control clock signal terminal of one or more of the at least one output circuit, one or more driving signals can be outputted under the control of one trigger signal. Furthermore, leakage currents and device power consumption can be reduced according to the embodiment of the present disclosure.

[0058] Generally, when the OLED display panel operates in a normal state, the threshold voltage Vth may be unstable. In this case, it may occur a shift of the threshold voltage Vth due to a long time of operation. Therefore, the design of pixel circuits of the OLED display panel needs to take compensation for the threshold voltage Vth, mobility compensation, and optical compensation into account. The shift register unit according to the embodiment of the present disclosure can be applied to, for example, an AMOLED 3T1C pixel circuit to perform better external compensation.

[0059] FIG. 7 shows a circuit diagram of a 3T1C pixel circuit. As shown in FIG. 4, the 3T1C circuit includes a switch transistor TFT1, a sensing transistor TFT2, a driving transistor TFT3, a storage capacitor CST, and a light emitting diode OLED. The switch transistor TFT1, the sensing transistor TFT2, and the driving transistor TFT3 are all N-type transistor TFTs.

[0060] A control electrode of the switch transistor TFT1 is coupled to the first signal output terminal G1 of the shift register unit 200 shown in FIG. 2, a first electrode of the switch transistor TFT1 is coupled to the data write signal Data, and a second electrode of the switch transistor TFT1 is coupled to a control electrode of the driving transistor TFT3. A control electrode of the sensing transistor TFT2 is coupled to the second signal output terminal G2 of the shift register unit shown in FIG. 2, a first electrode of the sensing transistor TFT2 is coupled to a sensing signal Sense, and a second electrode of the sensing transistor TFT2 is coupled to the second electrode of the driving transistor TFT3. The first electrode of the driving transistor TFT3 is coupled to a high level signal VDD. The storage capacitor CST is coupled between the second electrode of the switch transistor TFT1 and the second electrode of the driving transistor TFT3. The anode of the light emitting diode OLED is coupled to the second electrode of the driving transistor TFT3, and the cathode of the light emitting diode OLED is coupled to a low level signal VSS.

[0061] In an embodiment of the present disclosure, in a normal writing phase, the first output signal G1 and the second output signal G2 are configured firstly, that is, the first control clock signal CLKA and the second control clock signal CLKB are both low level signals. Thus, in the second period described above, the first output signal G1 and the second output signal G2 are both at high level. After a short time, the first control clock signal CLKA is maintained at low, the second control clock signal CLKB is configured to a high level, to maintain the first output signal G1 at high, and change the second output signal G2 to a low level so as to perform data writing. Under the control of the first output signal G1, the data write signal Data is transmitted to the switch transistor TFT1, that is, the control electrode of the driving transistor TFT3. Further, under the control of the data write signal Data, the high level signal VDD is transferred to the second electrode of the driving transistor TFT3, thereby driving the light emitting diode OLED to emit light.

[0062] In a sensing compensation phase, the first control clock signal CLKA and the second control clock signal CLKB are both at a low level. Therefore, in the second period described above, the first output signal G1 and the second output signal G2 are both maintained high. In addition to the operation of transferring the data write signal DATA to the control electrode of the driving transistor TFT3 to write data in the normal writing phase described above, under the control of the second output signal G2, the sensing compensation signal Sense is transferred to the second electrode of the sensing transistor TFT 2, that is, the second electrode of the driving transistor TFT3, and the voltage of the control electrode of the driving transistor TFT3 is pulled up, through the storage capacitor CST, to the voltage of the second electrode of the driving transistor TFT3, thereby further controlling the current driving the light emitting diode OLED.

[0063] In an embodiment of the present disclosure, the shift register unit outputs two driving signals, that is, the first output signal G1 and the second output signal G2, under the control of one trigger signal STU, so as to provide a better control of the 3T1C pixel circuit. The shift register unit of the embodiment of the present disclosure has a simple structure and can reduce power consumption and current leakage.

[0064] FIG. 8 shows a schematic structural diagram of a gate driving circuit 800 according to an embodiment of the present disclosure. As shown in FIG. 8, the gate driving circuit 800 may include a plurality of cascaded shift register units SR1, SR2, ..., SRn, SR(n+1), and so on. The shift register unit of each stage can adopt the structure of the shift register unit 100 as shown in FIG. 1.

[0065] In the gate driving circuit 800, ports of the respective stage of the shift register unit may include a first voltage signal terminal VSS, a second voltage signal terminal VSSL, a third voltage signal terminal VH, at least one control voltage signal terminal VG (only one shown), a first clock signal terminal CLK1, a second clock signal terminal CLK2, a third clock signal terminal CLK3, at least one control clock signal terminal CLK (only one shown), a trigger signal terminal STU, a next-stage start signal output terminal CR and at least one signal output terminal G (only one shown).

[0066] A next-stage start signal output terminal CR of the respective stages of shift register unit SR(n) is coupled to the trigger signal terminal STU of the next stage of shift register unit SR(n+1). A first clock signal terminal of a (3n+1)-stage of shift register unit is coupled to a third clock signal terminal of a (3n+2)-stage of shift register unit and to a second clock signal terminal of a (3n+3)-stage of shift register unit, a second clock signal terminal of the (3n+1)-stage of shift register unit is coupled to a first clock signal terminal of the (3n+2)-stage of shift register unit and to a third clock signal terminal of the (3n+3)-stage of shift register unit. A third clock signal terminal of the (3n+1)-stage of shift register unit is coupled to a second clock signal terminal of the (3n+2)-stage of shift register unit and to a first clock signal terminal of the (3n+3)-stage of shift register unit. N is a positive integer.

[0067] A first voltage signal of a low level (for example, -8V) is inputted to the first voltage signal terminal VSS, and a second voltage signal of a low level (for example, -10V) is inputted to the second voltage signal terminal VSSL, a third voltage signal of a high level (for example, 25V) is inputted to the third voltage signal terminal VH. Thus, the respective signal output terminal G can perform full swing output, realizing rail-to-rail output.

[0068] In an embodiment of the present disclosure, a high level of the second clock signal begins when a high level of the first clock signal ends, and a high level of the third clock signal begins when a high level of the second clock signal ends. Further, the first clock signal, the second clock signal, and the third clock signal may have a same clock period and a same ratio of high level to low level of 1:2.

[0069] FIG. 9 shows a schematic diagram of a display device 900 according to an embodiment of the present disclosure. The display device 900 includes an array substrate 950, wherein the array substrate 950 includes the gate driving circuit 800 shown in FIG. 8. The display device 900 can be, for example, a mobile phone, a tablet computer, a display screen, a wearable device, and the like.

[0070] The shift register unit according to an embodiment of the present disclosure can output at least one gate driving signal under the control of one trigger signal using only a small number of components, and adjust the output signal of each output circuit through the control clock signal of each output circuit. Therefore, it can be better applied to pixel circuits and reduce the complexity and area of the wiring of gate driving circuits. Furthermore, the shift register unit according to the embodiment of the present disclosure can also reduce signal noise, power consumption, and current leakage.

[0071] . The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A display device, arranged to generate a first clock signal, a second clock signal and a third clock signal, the display device comprising a shift register comprising a plurality of cascaded shift register units, each shift register unit comprising: an input circuit (110) configured to provide a trigger signal from a trigger signal terminal (STU) to a first node (N1) according to the first clock signal from a first clock signal terminal (CLK1), provide a voltage of the first node (N1) to a pull-up node (Q) according to the first clock signal, and provide the second clock signal from a second clock signal terminal (CLK2) to the first node (N1) according to a voltage of the pull-up node (Q) such that there is no leakage current flowing through the input circuit (110) from the pull-up node (Q); a next-stage start circuit (120) configured to output a next-stage start signal from a next-stage start signal output terminal (CR) according to the voltage of the pull-up node (Q), a voltage of a pull-down node (QB), a second clock signal from a second clock signal terminal (CLK2), and a first voltage signal from a first voltage signal terminal (VSS); a control circuit (130) configured to control the voltage of the pull-down node (QB) according to the voltage of the pull-up node (Q) and a second voltage signal from a second voltage signal terminal (VSSL), and control the voltage of the pull-up node (Q) according to the voltage of the pull-down node (QB) and the second voltage signal; a stabilization circuit (140) configured to control the voltage of the pull-up node (Q) and the voltage of the pull-down node (QB) according to the third clock signal from a third clock signal terminal (CLK3), the first voltage signal from the first voltage signal terminal (VSS), and a third voltage signal from a third voltage signal terminal (VH); and at least one output circuit (150) each configured to output an output signal from a signal output terminal (G) according to the voltage of the pull-up node (Q), the voltage of the pull-down node (QB), the first voltage signal, a control clock signal from a control clock signal terminal (CLK), and a control voltage signal from a control voltage signal terminal (VG); the display device is configured such that a high level of the second clock signal begins when a high level of the first clock signal ends, and a high level of the third clock signal begins when a high level of the second clock signal ends; wherein the input circuit (110) comprises a first transistor (T1), a second transistor (T2), and a twelfth transistor (T12); wherein a control electrode of the first transistor (T1) is coupled to the first clock signal terminal (CLK1), a first electrode of the first transistor (T1) is coupled to the trigger signal terminal (STU), and a second electrode of the first transistor (T1) is coupled to the first node (N1); wherein a control electrode of the second transistor (T2) is coupled to the first clock signal terminal (CLK1), the first electrode of the second transistor (T2) is coupled to the first node (N1), and a second electrode of the second transistor (T2) is coupled to the pull-up node (Q); and wherein a control electrode of the twelfth transistor (T12) is coupled to the pull-up node (Q), a first electrode of the twelfth transistor (T12) is coupled to the first node (N1), and a second electrode of the twelfth transistor (T12) is coupled to the second clock signal terminal (CLK2); wherein the stabilization circuit (140) comprises a thirteenth transistor (T13) and a fourteenth transistor (T14); wherein a control electrode of the thirteenth transistor (T13) is coupled to the third clock signal terminal (CLK3), a first electrode of the thirteenth transistor (T13) is coupled to the first voltage signal terminal (VSS), and a second electrode of the thirteenth transistor (T13) is coupled to the pull-up node (Q); wherein a control electrode of the fourteenth transistor (T14) is coupled to the third clock signal terminal (CLK3), a first electrode of the fourteenth transistor (T14) is coupled to the third voltage signal terminal (VH), and a second electrode of the fourteenth transistor (T14) is coupled to the pull-down node (QB) ; and wherein the at least one output circuit (150) comprises: a first output circuit (151) configured to output a first output signal from a first signal output terminal (G1) according to the voltage of the pull-up node (Q), the voltage of the pull-down node (QB), the first voltage signal from the first voltage signal terminal (VSS), a first control clock signal from a first control clock signal terminal (CLKA), and a first control voltage signal from a first control voltage signal terminal (VG1); and a second output circuit (152) configured to output a second output signal from a second signal output terminal (G2) according to the voltage of the pull-up node (Q), the voltage of the pull-down node (QB), the first voltage signal from the first voltage signal terminal (VSS), a second control clock signal from a second control clock signal terminal (CLKB), and a second control voltage signal from a second control voltage signal terminal (VG2).

2. The display device according to claim 1, wherein each of the at least one output circuit (150) comprises a pull-up transistor, a pull-down transistor, and a control transistor; wherein a control electrode of the pull-up transistor is coupled to the pull-up node (Q), a first electrode of the pull-up transistor is coupled to the control voltage signal terminal (VG), and a second electrode of the pull-up transistor is coupled to the signal output terminal (G); wherein a control electrode of the pull-down transistor is coupled to the pull-down node (QB), a first electrode of the pull-down transistor is coupled to the first voltage signal terminal (VSS), and a second electrode of the pull-down transistor is coupled to the signal output terminal (G); and wherein a control electrode of the control transistor is coupled to the control clock signal terminal (CLK), a first electrode of the control transistor is coupled to the first voltage signal terminal (VSS), and a second electrode of the control transistor is coupled to the signal output terminal (G).

3. The display device according to claims 1 or 2, wherein the next-stage start circuit (120) comprises a fourth transistor (T4), a fifth transistor (T5), and a first capacitor (C); wherein a control electrode of the fourth transistor (T4) is coupled to the pull-up node (Q), a first electrode of the fourth transistor (T4) is coupled to the second clock signal terminal (CLK2), and a second electrode of the fourth transistor (T4) is coupled to the next-stage start signal output terminal (CR); wherein a control electrode of the fifth transistor (T5) is coupled to the pull-down node (QB), a first electrode of the fifth transistor (T5) is coupled to the first voltage signal terminal (VSS), and a second electrode of the fifth transistor (T5) is coupled to the next-stage start signal output terminal (CR); and wherein the first capacitor (C) is coupled between the pull-up node (Q) and the next-stage start signal output terminal (CR);4. The display device according to claims 1 or 2, wherein the control circuit (130) comprises a third transistor (T3) and a fifteenth transistor (T15); wherein a control electrode of the third transistor (T3) is coupled to the pull-down node (QB), a first electrode of the third transistor (T3) is coupled to the second voltage signal terminal (VSSL), and a second electrode of the third transistor (T3) is coupled to the pull-up node (Q); and wherein a control electrode of the fifteenth transistor (T15) is coupled to the pull-up node (Q), a first electrode of the fifteenth transistor (T15) is coupled to the second voltage signal terminal (VSSL), and a second electrode of the fifteenth transistor (T15) is coupled to the pull-down node (QB).

5. The display device according to claim 1, wherein the first output circuit (151) comprises a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8); wherein a control electrode of the sixth transistor (T6) is coupled to the pull-up node (Q), a first electrode of the sixth transistor (T6) is coupled to the first control voltage signal terminal (VG1), a second electrode of the sixth transistor (T6) is coupled to the first signal output terminal (G1); wherein a control electrode of the seventh transistor (T7) is coupled to the pull-down node (QB), a first electrode of the seventh transistor (T7) is coupled to the first voltage signal terminal (VSS), and a second electrode of the seventh transistor (T7) is coupled to the first signal output terminal (G1); and wherein a control electrode of the eighth transistor (T8) is coupled to the first control clock signal terminal (CLKA), a first electrode of the eighth transistor (T8) is coupled to the first voltage signal terminal (VSS), and a second electrode of the eighth transistor (T8) is coupled to the first signal output terminal (G1); wherein a width to length ratio of the seventh transistor (T7) is an integer multiple of a width to length ratio of the sixth transistor (T6).

6. The display device according to claim 1, wherein the second output circuit (152) comprises a ninth transistor (T9), a tenth transistor (T10), and an eleventh transistor (T11); wherein a control electrode of the ninth transistor (T9) is coupled to the pull-up node (Q), a first electrode of the ninth transistor (T9) is coupled to the second control voltage signal terminal (VG2), and a second electrode of the ninth transistor (T9) is coupled to the second signal output terminal (G2); wherein a control electrode of the tenth transistor (T10) is coupled to the pull-down node (QB), a first electrode of the tenth transistor (T10) is coupled to the first voltage signal terminal (VSS), and a second electrode of the tenth transistor (T10) is coupled to the second signal output terminal (G2); and wherein a control electrode of the eleventh transistor (T11) is coupled to the second control clock signal terminal (CLKB), a first electrode of the eleventh transistor (T11) is coupled to the first voltage signal terminal (VSS), and a second electrode of the eleventh transistor (T11) is coupled to the second signal output terminal (G2); wherein a width to length ratio of the tenth transistor (T10) is an integer multiple of a width to length ratio of the ninth transistor (T9).

7. The display device according to claims 1 or 2, wherein the first clock signal, the second clock signal, and the third clock signal have a same clock period and a same ratio of high level to low level of 1:2.

8. The display device according to claim 1, wherein a potential of the first voltage signal is higher than a potential of the second voltage signal.

9. A shift register unit comprising a first transistor (T1), a second transistor (T2), a twelfth transistor (T12), a fourth transistor (T4), a fifth transistor (T5), a first capacitor (C), a third transistor (T3), a fifteenth transistor (T15), a thirteenth transistor (T13), a fourteenth transistor (T14), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), and an eleventh transistor (T11); wherein a control electrode of the first transistor (T1) is connected to a first clock signal terminal (CLK1), a first electrode of the first transistor (T1) is connected to a trigger signal terminal (STU), and a second electrode of the first transistor (T1) is connected to a first electrode of the second transistor (T2); wherein a control electrode of the second transistor (T2) is connected to the first clock signal terminal (CLK1), the first electrode of the second transistor (T2) is connected to the second electrode of the first transistor (T1), and a second electrode (T2) of the second transistor (T2) is connected to a pull-up node (Q); wherein a control electrode of the twelfth transistor (T12) is connected to the pull-up node (Q), a first electrode of the twelfth transistor (T12) is connected to the first electrode of the second transistor (T2), and a second electrode of the twelfth transistor (T12) is connected to a second clock signal terminal (CLK2); wherein a control electrode of the fourth transistor (T4) is connected to the pull-up node (Q), a first electrode of the fourth transistor (T4) is connected to the second clock signal terminal (CLK2), and a second electrode of the fourth transistor (T4) is connected to a next-stage start signal output terminal (CR); wherein a control electrode of the fifth transistor (T5) is connected to a pull-down node (QB), a first electrode of the fifth transistor (T5) is connected to a first voltage signal terminal (VSS), and a second electrode of the fifth transistor (T5) is connected to the next-stage start signal output terminal (CR); wherein the first capacitor (C) is connected between the pull-up node (Q) and the next-stage start signal output terminal (CR); wherein a control electrode of the third transistor (T3) is connected to the pull-down node (QB), a first electrode of the third transistor (T3) is connected to a second voltage signal terminal (VSSL), and a second electrode of the third transistor (T3) is connected to the pull-up node (Q); wherein a control electrode of the fifteenth transistor (T15) is connected to the pull-up node (Q), a first electrode of the fifteenth transistor (T15) is connected to the second voltage signal terminal (VSSL), and a second electrode of the fifteenth transistor (T15) is connected to the pull-down node (QB); wherein a control electrode of the thirteenth transistor (T13) is connected to a third clock signal terminal (CLK3), a first electrode of the thirteenth transistor (T13) is connected to the first voltage signal terminal (VSS), and a second electrode of the thirteenth transistor (T13) is connected to the pull-up node (Q); wherein a control electrode of the fourteenth transistor (T14) is connected to the third clock signal terminal (CLK3), a first electrode of the fourteenth transistor (T14) is connected to a third voltage signal terminal (VH), and a second electrode of the fourteenth transistor (T14) is connected to the pull-down node (QB); wherein a control electrode of the sixth transistor (T6) is connected to the pull-up node (Q), a first electrode of the sixth transistor (T6) is connected to a first control voltage signal terminal (VG1), and a second electrode of the sixth transistor (T6) is connected to a first signal output terminal (G1); wherein a control electrode of the seventh transistor (T7) is connected to the pull-down node (QB), a first electrode of the seventh transistor (T7) is connected to the first voltage signal terminal (VSS), and a second electrode of the seventh transistor (T7) is connected to the first signal output terminal (G1); wherein a control electrode of the eighth transistor (T8) is connected to a first control clock signal terminal (CLKA), a first electrode of the eighth transistor (T8) is connected to the first voltage signal terminal (VSS), and a second electrode of the eighth transistor (T8) is connected to the first signal output terminal (G1); wherein a control electrode of the ninth transistor (T9) is connected to the pull-up node (Q), a first electrode of the ninth transistor (T9) is connected to a second control voltage signal terminal (VG2), and a second electrode of the ninth transistor (T9) is connected to a second signal output terminal (G2); wherein a control electrode of the tenth transistor (T10) is connected to the pull-down node (QB), a first electrode of the tenth transistor (T10) is connected to the first voltage signal terminal (VSS), and a second electrode of the tenth transistor (T10) is connected to the second signal output terminal (G2); and wherein a control electrode of the eleventh transistor(T11) is connected to a second control clock signal terminal (CLKB), a first electrode of the eleventh transistor(T11) is connected to the first voltage signal terminal (VSS), and a second electrode of the eleventh transistor(T11) is connected to the second signal output terminal (G2).

10. A method for driving a shift register unit in a display device according to any one of claims 1 to 8 or a shift register unit according to claim 9, wherein a control clock signal of a control clock signal terminal (CLK) of at least one output circuit (150) is a low level signal, the method comprising: in a first period, inputting a first clock signal through a first clock signal terminal (CLK1), and inputting a trigger signal through a trigger signal terminal (STU), such that an input circuit (110) is enabled to provide the trigger signal to a first node (N1) and provide the voltage of the first node (N1) to a pull-up node (Q), a control circuit (130) controls a voltage of a pull-down node (QB) to be a low level, a next-stage start circuit (120) outputs a low level signal, and the respective output circuit (150) outputs a low level signal; in a second period, inputting a second clock signal through a second clock signal terminal (CLK2), such that a next-stage start circuit (120) is enabled to output a high level signal, the voltage of the pull-up node (Q) continues rising to a high level, the voltage of the pull-down node (QB) is maintained at a low level, and the respective output circuit (150) outputs a high level signal, a second clock signal is provided to the first node (N1) such that there is no leakage current flowing from the pull-up node (Q); and in a third period, inputting a third clock signal through a third clock signal terminal (CLK3), such that a stabilization circuit (140) is enabled to change the voltage of the pull-up node (Q) to a low level and change the voltage of the pull-down node (QB) to a high level, the next-stage start circuit (120) outputs a low level signal, and the respective output circuit (150) outputs a low level signal.

11. The method according to claim 10, wherein the control clock signal of the control clock signal terminal (CLK) of one or more of the at least one output circuit (150) is a high level signal, the method comprising: outputting a low level signal from a signal output terminal (G) of the one or more output circuits (150).

12. A gate driving circuit comprising a plurality of cascaded shift register units, wherein each shift register unit is a shift register unit according to claim 9; wherein a next-stage start signal output terminal (CR) of the respective stage of shift register unit is coupled to a trigger signal terminal (STU) of the next stage of shift register unit; wherein a first clock signal terminal (CLK1) of a (3n+1)-stage of shift register unit is coupled to a third clock signal terminal (CLK3) of a (3n+2)-stage of shift register unit and to a second clock signal terminal (CLK2) of a (3n+3)-stage of shift register unit; wherein a second clock signal terminal (CLK2) of the (3n+1)-stage of shift register unit is coupled to a first clock signal terminal (CLK1) of the (3n+2)-stage of shift register unit and to a third clock signal terminal (CLK3) of the (3n+3)-stage of shift register unit; and wherein a third clock signal terminal (CLK3) of the (3n+1)-stage of shift register unit is coupled to a second clock signal terminal (CLK2) of the (3n+2)-stage of shift register unit and to a first clock signal terminal (CLK1) of the (3n+3)-stage of shift register unit; wherein n is a positive integer.