SEMICONDUCTOR STORAGE DEVICES
Patent Information
- Application Number
- DE602019071169
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2018-05-23
- Filing Date
- 2019-02-01
- Publication Date
- 2025-06-18
- Estimated Expiration
- 2039-02-01
AI Technical Summary
Existing two-dimensional semiconductor devices face limitations in integration density due to the need for expensive patterning technologies to form fine patterns, and three-dimensional semiconductor memory devices are proposed to overcome these limitations.
A three-dimensional semiconductor memory device is designed with a high integration density, featuring vertically stacked sub-cell arrays, conductive lines, and data storing elements, where semiconductor patterns and insulating layers are alternately stacked to increase density without the need for expensive patterning technologies.
The proposed three-dimensional semiconductor memory device achieves a high integration density, enhancing performance and reducing costs by eliminating the need for expensive patterning technologies, while maintaining efficient connectivity through interlayered conductive lines.