Low-transition, low-gain avalanche detector

Description

BACKGROUND OF THE INVENTION1. Field of the Invention.

[0001] The present invention relates to low gain avalanche detectors (LGAD) and methods of making the same.2. Description of the Related Art.

[0002] Avalanche diodes are used as photon detectors in many applications. The detection process comprises (1) the avalanche diode generating electrons and holes in response to electromagnetic radiation, charged particles, or photons; (2) separating the electrons and holes in the diode using a strong reverse bias voltage applied to the diode; (3) using the strong reverse bias voltage to further accelerate the electrons in the diode and generate additional electrons through impact ionization (an internal gain mechanism); and (4) forming a detection signal using the multiple electrons generated through the impact ionization from each of the photo-generated electrons.

[0003] Figure 1 illustrates a Low-Gain-Avalanche-Detector (LGAD) having an n +< -type layer (cathode) forming a junction with a p-type multiplication layer. Electrons are photo-generated in a p-type bulk region in response to the electromagnetic radiation and the p -< type multiplication layer is the gain layer wherein the additional electrons are generated through the impact ionization. A p +< -anode is formed on the p-type bulk region so that an ohmic connection can be made between the p-type bulk and an anode plane that allows for the application of a reverse bias voltage across the anode and the cathode. Such an LGAD fabricated in silicon can be used for particle detection, particularly in the arena of ultra-fast (~10 ps) timing. However, the high electric fields needed to induce the impact ionization process lead to breakdown between the separated n-p junctions that are used to simultaneously deplete the sensors and establish the readout segmentation. As a result, working devices have included a Junction Termination Extension (JTE) that provides electrostatic isolation between neighboring implants, but at a cost of introducing a dead region between the sensor segments that is insensitive to the deposited charge from an incident charged particle or photon. The width of this dead region is 50 µm or more, making conventional LGAD sensors inefficient for granularity or spatial resolution scales much below 1mm.

[0004] However, particle physics (4D tracking) and photon science (high frame-rate X-Ray imaging) applications require granularity or spatial resolution at the 50 µm scale. Thus, there is a need to overcome the current granularity limits of LGAD sensors. The present disclosure satisfies this need.

[0005] The documents "Low Gain Avalanche Detectors for high energy physics" by Fernandez-Martines P et al. ,2015 10th Spanish Conference on Electron Devices (CDE), IEEE, 11 February 2015 (2015-02-11), pages 1-4, DOI: 10.1109 / CDE.2015.7087475; "Recent technological developments on LGAD and iLGAD detectors for tracking and timing applications", by Pellegrini G. et al., Nuclear Instruments & Methods in Physics research Section A, ELSEVIER BV * NORTH-HOLLAND, NL, vol. 831, 17 May 2016 (2016-05-17), pages 24-28, ISSN: 0168-9002, DOI: 10.1016 / J.NIMA.2016.05.066; and "Fabrication and performance of AC-coupled LGADs" by Gabriele Giacomini et al., ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 27 June 2019 (2019-06-27), DOI: 10.1088 / 1748-0221 / 14 / 09 / P09004, disclose known structures of low gain avalanche detectors.SUMMARY OF THE INVENTION

[0006] As discussed herein, avalanche diodes use high electric fields to provide signal gain by using a high electric field at or near a p-n junction to generate an "avalanche" of additional signal charge. However, the high electric field can also cause breakdown in the readout structure of the avalanche diode, resulting in a limit to the granularity of the readout from the diode.

[0007] The present invention is defined in the appended claims and describes a Low-Gain Avalanche Detector (LGAD) comprising a buried junction that localizes the high electric field region and isolates it from the readout structure, thereby solving the problem of granularity limits on the LGADs. In typical examples, a planar, highly-doped diode junction is buried several micrometers below the surface of the device, allowing for a low electric field region in the area close to the surface readout structure while the high electric field region in the area of the junction produces the gain characteristic of LGADs.

[0008] In typical embodiments, the buried diode junction eliminates the need for the Junction-Termination Extension (JTE) structure, employed in conventional LGADs, that limits achievable granularity. The significantly higher degree of granularity achievable using embodiments described herein opens up a range of additional applications for the LGAD.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Referring now to the drawings in which like reference numbers represent corresponding parts throughout: Figure 1: Conventional LGAD. Figure 2: Schematic of a Deep-Junction LGAD according to one or more examples, illustrating the use of the buried junction to localize the high electric-field region and isolate it from the readout structure. Figure 3: Two-dimensional electric field profile of the Baseline-1 configuration, at a bias voltage of 210V. The units of the axes are micrometers. Figure 4: Gain as a function of bias voltage for the Baseline-1 configuration. Figure 5: Integrated signal charge, summed over all channels, as a function of transverse position, for a pixel separation of 20 µm within the Baseline-1 model. Figure 6: Temporal signal profile as a function of bias voltage for the Baseline-1 configuration. Figure 7. Flowchart illustrating a method of making an avalanche diode. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made within the scope of the appended claims without departing from the scope of the present invention.Technical Description

[0011] The present disclosure describes an entirely novel approach to the problem of improving the granularity of LGAD sensors - the Deep Junction ("DJ-LGAD") LGAD comprising the high electric-field gain region (wherein impact ionization takes place) moved away from the readout structure.Example Structure

[0012] Figure 2 illustrates the LGAD comprises a diode (p-n) junction buried a few micrometers below and away from the upper surface of the LGAD (the upper surface comprising the surface where segmentation is imposed). In the example shown, such positioning of the high electric-field gain region avoids the need for the JTE.

[0013] More specifically, Figure 2 illustrates an example avalanche diode 200 including a semiconductor structure 202 including an n-type region 204; a p-type region 206; and a gain region 208 buried between the n-type region 204 and the p-type region 206. The gain region includes an n +< -type region 212 having a higher n-type dopant density than the n-type region; a p +< -type region 214 having a higher p-type dopant density than the p-type region; and a p-n junction 210 including an interface 210a between the n +< -type region and the p +< -type region.

[0014] The n-type region 204 includes a plurality of segments 218, each of the segments including a first surface 216 of the n-type region 204 and the semiconductor structure.

[0015] Figure 2 further illustrates the avalanche diode as including a readout structure 222 comprising a plurality of first electrodes 224, wherein at least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another. A second electrode 226 is deposited on a second surface 228 of the semiconductor structure / p-type region and an ohmic contact 230 is formed between the p-type region and the second electrode. The p-n junction is reverse biased by application of an electric field between the first electrodes in the readout structure and the second electrode. As illustrated in Figure 2, each of the segments include implanted regions 232 having a higher dopant density than the n-type region 204. The implanted regions 232 form an ohmic contact with the first electrodes. Also shown in Figure 2 are electrostatic isolation barriers 234 (e.g., p-type wells) electrically isolating the segments.

[0016] Figure 2 illustrates the LGAD as comprising a gain layer including both the n +< region (dark blue section) and the p +< region (dark red section), rather than just a dark red section. In other words, the gain layer comprises the full p-n junction, rather than just the p +< doped area. A key benefit of burying the entire junction, rather than just the highly-doped p +< region, is that application of a reverse bias (creating a depletion zone) establishes an electric field in the region of the junction that is similar to that of a parallel-plate capacitor. Specifically, application of the reverse bias voltage creates two planes comprising near equal (but opposite sign) high charge density, so that the electric field in the region of the junction is sufficiently high to induce the limited and controlled impact ionization that is characteristic of LGADs. The electric fields are much lower outside the highly doped junction region, however, thereby avoiding the need to provide isolation between the readout segmentation and the junction.Example Characterization

[0017] The structure of Figure 2 was simulated with version K_2015.06-SP2 of the Sentaurus Device simulation package from the Synopsys Corporation. A challenge of designing a workable DJ-LGAD is to determine the doping profiles that: (1) produce the right amount of impact ionization in the gain region, allowing for gain without breakdown; and (2) also permit the electric field in all other regions of the bulk (including the "N isolation layer" between the junction and the readout structure) to be (i) high enough to saturate the drift velocity but (ii) low enough so as to not induce additional, uncontrolled impact ionization that leads to breakdown between segments.

[0018] Table 1 illustrates a sample doping profile ("Baseline-1" configuration) that achieves these conditions (1) and (2), while maintaining electric fields at the readout surface low enough to allow for conventional segmentation techniques and avoid the use of a JTE. All further results presented herein are for the simulated behavior of this Baseline-1 configuration. Table 1: Doping profile parameters for the Baseline-1 version of the DJ-LGAD. The dopant densities or levels expressed herein in scientific notation MeN per centimeter cube (cm 3< ), where m is a real number and n is an integer, are equivalent to standard notation m x 10 n< .Element Doping Level Extent in Depth N isolation layerConstant doping of density 3e12 N / cm^3From 0 µm (surface) to beginning of N ++< "gain plate" layerN ++< gain plate (upper half of gain layer)Gaussian doping, peak of 3.0e16 N / cm^3Peak at 4 µm, Gaussian width of 0.17 µmP ++< gain plate (lower half of gain layer)Gaussian doping, peak of 3.0e16 N / cm^3Peak at 5.5 µm, Gaussian width of 0.17 µmP drift regionConstant doping of density 3.0e12 N / cm^3End of P ++< "gain plate" layer to 50 µmP stopConstant doping of density 1.0e13 N / cm^31 µm deep, 1µ wideN ++< implantConstant doping of density 1.0e19 N / cm^3At surfaceGain layer doping tolerance (N ++< and P ++< varied together)Effective operation between 2.9e^16 and 3.5e^16

[0019] Figure 3 shows the resulting two-dimensional electric field profile, as a function of depth into the Baseline-1 detector and of a lateral coordinate parallel to the surface of the device, for a bias voltage of 210V. For bias voltages above 100 Volts, the electric field in the p-type drift region and the n-type isolation region is relatively insensitive to the applied voltage, leading to stable charge collection properties. The impact ionization process, which depends upon electric field in the gain region, is also well controlled, leading to the smooth dependence of gain upon bias voltage shown in Figure 4.

[0020] Figure 5 shows the gain variation as a function of lateral position that results from the electric field depicted in Figure 3; uniformity at the + / -4% level is observed. Gain is defined by the collected charge in the LGAD over the collected charge in a same thickness silicon sensor without the gain layer structure.

[0021] Figure 6 shows the temporal signal profile as a function of applied bias voltage (obtained using the simulation). A sharp rising edge, conducive to a fast timing measurement, is observed for all bias voltages, with a slew-rate that grows monotonically with bias voltage. Consistent with the saturation drift velocity (approximately 100 µm per nanoseconds) of carriers in silicon, the majority of the charge within this 50 µm device is collected within 500 picoseconds, suggesting an achievable device repetition rate in excess of 1 GHz.Process steps

[0022] Figure 7 is a flowchart illustrating a method of making an avalanche diode (referring also to Figure 2).

[0023] Block 700 represents obtaining or creating a semiconductor structure (e.g., epitaxial layers) on a substrate. In one or more examples, the semiconductor structure is a silicon semiconductor structure and the substrate is a silicon substrate (or the semiconductor structure and the substrate may comprise or consist essentially of silicon). In one example, the semiconductor structure includes a bulk p-type region; a gain region including a p-n junction on or above the bulk p-type region; and an n-type region (isolation region) on or above the gain region (n-side up configuration). In another example, the semiconductor structure includes a bulk n-type region; a gain region including a p-n junction on or above the bulk n-type region; and the p-type region (isolation region) on or above the gain region (p-side up configuration). The gain region includes an n +< -type region having a higher n-type dopant density than the n-type region; a p +< -type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n +< -type region and the p +< -type region. The p +< -type region typically forms a j unction interface in physical contact with the n +< -type region. Example p-type dopants include, but are not limited to, boron, gallium, aluminum, and indium. Example n-type dopants include, but are not limited to, phosphorus, arsenic, antimony, bismuth and lithium.

[0024] Block 702 represents forming a readout structure so that the surface of the n-type (p-type) region forms the readout structure. The step comprises defining a plurality of segments in the n-type region or the p-type region depending on the configuration (n-side up or p-side up).

[0025] Block 704 represents creating or generating (e.g., depositing) a plurality of first electrodes forming an ohmic contact with the readout structure and a second electrode forming an ohmic contact with the p-type (n-type) region. At least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another. Established segmentation schemes for conventional (non-LGAD) silicon diode sensors may also be used. The step further comprises forming a first ohmic contact between the implanted regions and the first electrodes, and a second ohmic contact between the bulk p-type region and the bulk n-type region and a second electrode, so that the p-n junction is reverse biased by application of an electric field of appropriate polarity between the first electrodes and the second electrode. The second ohmic contact is typically formed on a second surface of the semiconductor structure opposite the first surface.

[0026] Block 706 represents the end result, an avalanche diode. The avalanche diode can be used in many applications, including but not limited to, as a pixel sensor (e.g., at the large hadron collider (LHC) or proposed Electron-Ion Collider (EIC)) with fast timing capabilities.Advantages and Improvements

[0027] As described above, conventional LGADs are biased with high electric fields required to induce the impact ionization process, leading to breakdown between the separated n-p junctions that are used to simultaneously deplete the sensors and establish the readout segmentation. As a result, working LGAD devices have included a Junction Termination Extension (JTE) that provides electrostatic isolation between neighboring implants, but at the cost of introducing a dead region between the sensor segments that is insensitive to the deposited charge from an incident particle. The width of this dead region is 50 µm or more, making conventional LGAD sensors inefficient for granularity scales much below 1mm. The following devices have been proposed to circumvent the JTE limit. (1) AC-coupled ("AC-LGAD") LGADs that eliminate the need for the JTE by making use of a completely planar (non-segmented) junction structure, while establishing the granularity entirely through the electrode structure, which is AC-coupled to the planar device through a thin layer of insulator. Since charge is not collected directly by the electrodes, there is a point-spread function that relates the signal location to the pad (electrode) response that is a property of the effective AC network formed by the highly doped gain layer just below the insulating layer and the electrode structure. The AC coupling also leads to a signal that is zero when integrated over all time, leading to a recovery period for which the polarity of collected charge is of opposite polarity to that of the signal pulse, potentially compromising the repetition rate of the device. (2) Inverse ("ILGAD") LGADs also eliminate the need for the JTE by making use of a planar junction structure. In this case, the electrode structure is placed on the side of the device opposite the junction. However, prototypes with appealing signal characteristics have yet to be achieved. In addition, the manufacture of these devices requires processing on both sides of the sensor, which is significantly more difficult than the single-sided processes used for conventional, AC, and DJ LGADs. (3) Trench-isolated ("TI-LGAD") LGADs attempt to replace the JTE with a physical trench etched around the edge of the detector segment, which is then filled with insulator. This structure might be used to reduce the dead area between segments to as little as 5 µm. However, much work remains to be done to show that this approach will produce a stable sensor, and to see how small the dead region can be made.

[0028] Therefore, these approaches (1)-(3) for increasing LGAD granularity make use of more complex, and less proven segmentation techniques. Exemplary device embodiments described herein, on the other hand, include the diode junction gain layer buried below a lightly-doped isolation layer, enabling the use of conventional segmentation techniques to achieve high granularity. This allows for the removal of constraints on the granularity of LGADs while maintaining their attractive properties of internal gain, timing resolution and repetition rate.Conclusion

[0029] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. a Low Gain Avalanche Detector (LGAD) (200), comprising a semiconductor structure (202) comprising: an n-type (respectively p-type) region (204a) comprising a plurality of segments (218) each comprising an implanted region (232) having a higher dopant density than the n-type (respectively p-type) region; a p-type (respectively n-type) region (206a); and a gain region (208) between the n-type (respectively p-type) region (204a) and the p-type (respectively n-type) region (206a), the gain region buried between the n-type (respectively p-type) region and the p-type (respectively n-type) region and the gain region comprising: an n+-type region (212) having a higher n-type dopant density than the n-type region; a p+-type region (214) having a higher p-type dopant density than the p-type region; and a p-n junction (210) between the n+-type region (212) and the p+-type region (214); a readout structure (222) comprising: a plurality of first electrodes (224), wherein: each of the first electrodes is on a different one of the segments (218), the first electrodes (224) are electrically isolated from one another; and each of the segments (218) comprises a first ohmic contact between the implanted region (232) and the one of the first electrodes (224) on the implanted region (232); a second ohmic contact (230) between the p-type (respectively n-type) region (206a) and a second electrode (226); and wherein the p-n junction (210) experiences a reverse bias electric field when an appropriate polarity bias is applied between the first electrodes (224) and the second electrode.

2. The LGAD of claim 1, wherein the semiconductor structure (202) consists essentially of silicon.

3. The LGAD of claim 1 or claim 2, further comprising: a first surface (216) of the n-type (respectively p-type) region (204a); the p-n junction (210) comprising a first interface (210a) between the n+-type region (212) and the p+-type region (214); a first distance D1 between the first interface (210a) and the first surface (216) is in a range of 2-10 micrometers; a second surface (228) of the p-type (respectively n-type) region (206a) on a side of the semiconductor structure opposite the first surface (216); and a second distance (D2), between the second surface (228) and the first interface (210a), in a range of 20 micrometers to 100 micrometers.

4. The LGAD of claim 3, wherein the first distance is in a range of 3 -6 micrometers.

5. The LGAD of any of the claims 1-4, wherein: the n+-type region (212) has a first n-type dopant density and the p+-type region (214) has a first p-type dopant density, and the first n-type dopant density is within 10% of the first p-type dopant density.

6. The LGAD of claim 5, wherein: the first n-type dopant density and the first p-type dopant density are in a range of 2.6e^16 - 3.8e^16 dopant atoms per cm3 the n-type region (204a) has a second n-type dopant density in a range of 1e^12-1e^14 atoms per cm3, and the p-type region (206a) has a second p-type dopant density in a range of 1e^12-1e^14 atoms per cm3.

7. The LGAD of any of the claims 1-6, wherein: when the LGAD 200 experiences depletion, the reverse bias electric field, a first n-type dopant density in the n+-type region (212) and a second p-type dopant density in the p+-type region (214) are in a range that achieves gain using impact ionization in the p-n junction (210) without breakdown of the p-n junction (210); and a second n-type dopant density in the n-type region (204a) and a second p-type dopant density in the p-type region (206a) are in a range such that: the reverse bias electric field does not induce impact ionization in the n-type region or the p-type region, the second p-type dopant density enables saturation of the drift velocity in the p-type region, and the second n-type dopant density enables saturation of the drift velocity in the n-type region.

8. The LGAD of any of the claims 1-7, wherein: starting at full depletion and as a function of increasing reverse bias voltage across the first electrodes (224) and second electrode (226), a gain of the LGAD increases monotonically until breakdown in the p-n junction (210); and the gain is characterized as the response of the LGAD with the p-n junction (210) divided by the response of the LGAD having: the p+-type region (214) replaced with a continuation of the p-type region (206a) having the same thickness as the p+-type region and the n+-type region (212) replaced with a continuation of the n-type region (204a) having the same thickness as the n+-type region.

9. The LGAD of any of the claims 1-8, wherein: each of the segments (218) has a surface area of 3 by 3 micrometers or greater, or the number density of the segments (218) is up to 105 segments per square millimeter.

10. The LGAD of any of the claims 1-9, further comprising: an electrostatic isolation barrier (234), comprising p-type (respectively n-type) dopants, between adjacent segments (218), wherein: the electrostatic isolation barriers (234) electrically isolate the first electrodes (218) from each other, and the electrostatic isolation barriers (234) extend to a depth that does not reach the p-n junction (210).

11. The LGAD of claim 10, wherein the barriers (234) comprise a third p-type (respectively n-type dopant) dopant density in a range of 1e^12-1e^14 dopant atoms per cm3.

12. The LGAD of claims 6 or 10, wherein: the dopant densities in the semiconductor structure (202) are tuned so that the gain of the LGAD , as a function of position along a length (L) of the segment (218), in any direction parallel to the first surface (216), does not vary by more than + / -10%, and for the p-type (respectively n-type) region (206a) comprising a bulk region having a thickness of 50 micrometers or less, the majority of a signal charge, in response to incidence of charged particles or photons on the LGAD, is collected on the first electrodes (224) within 500 picoseconds, enabling a repetition rate in excess of 1 GHz.

13. The LGAD of any of the claims 1-12, wherein: the implanted regions (232) comprise a fourth n-type (respectively p-type) dopant density in a range of 1e^17- 1.e^19 dopant atoms per cm314. The LGAD of any of the claims 1-13, wherein: the avalanche diode does not include a Junction Termination Extension (JTE) structure between the segments (218) , and the p-type (respectively n-type) region (206a) comprises a p-type bulk region (respectively n-type bulk region) so that the second ohmic contact (230) is between the p-type (respectively n-type) bulk region (206) and the second electrode (226).

15. A method of making a Low Gain Avalanche Detector (LGAD), comprising: obtaining or creating a semiconductor structure comprising : an n-type (respectively p-type) region (204a); a p-type (respectively n-type) region (206a); and a gain region (208) between the n-type region and the p-type region, the gain region buried between the n-type region and the p-type region and the gain region comprising : an n+-type region (212) having a higher n-type dopant density than the n-type region; a p+-type region (214) having a higher p-type dopant density than the p-type region; and a p-n junction (210) between the n+-type region and the p+-type region; the surface of the n-type (respectively p-type) region forming a readout structure (222), comprising: a plurality of segments (218) in the n-type (respectively p-type) region, each of the segments comprising an implanted region (232) having a higher dopant density than the n-type (respectively p-type) region; generating a plurality of first electrodes (224), wherein each of the first electrodes is on a different one of the segments and the first electrodes are electrically isolated from one another; forming a first ohmic contact between each of the implanted regions and the one of the first electrodes on the each of the implanted regions; and forming a second ohmic contact between the p-type (respectively n-type) region and a second electrode (226), so that the p-n junction (210) is reverse biased by application of an electric field of appropriate polarity between the first electrodes and the second electrode.