CONTACT CONNECTION ON GERMANIUM

Description

technical field

[0001] This description relates generally to electronic devices, and more specifically to electronic components including germanium and the processes for manufacturing electronic components. Previous technique

[0002] Some electronic components, such as transistors and diodes, utilize the properties of germanium. For example, a PIN-type photodiode—that is, a photodiode with an intrinsic semiconductor region sandwiched between N- and P-type doped semiconductor regions—can be based on germanium. This photodiode can then detect optical radiation with wavelengths between 0.9 µm and 1.5 µm.

[0003] In such a component, a region containing germanium is intended to be electrically connected to other devices via a conductive link. The electrical contact between this region and the conductive link is ensured by a contact area, or contact point.

[0004] The contact point is typically located at the bottom of an opening made in an insulating layer.

[0005] US 2017 / 213889 A1 describes a contact formation source-drain low resistance.

[0006] WO 2019 / 018846 A2 discloses microstructure-enhanced absorption photosensitive devices.

[0007] JP 2013 207231 A describes a semiconductor device comprising a second semiconductor film and a metallic element co-crystallized in a second mixed layer, which is layered on top of a first mixed layer. Summary of the invention

[0008] There is a need to reduce resistances and / or increase the reliability of known contact points on a semiconductor region containing germanium.

[0009] There is a need to simplify the known methods of making contacts on a semiconductor region containing germanium.

[0010] One embodiment provides a method for forming an electrical contact with a semiconductor region consisting mainly of germanium according to claim 1.

[0011] One embodiment provides an electronic device according to claim 2. Brief description of the drawings

[0012] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1is a partial, schematic cross-sectional view representing a step in a first implementation of a manufacturing process for a contact point; the figure 2 is a partial, schematic cross-sectional view representing another stage of the first embodiment; the figure 3 is a partial, schematic cross-sectional view representing another stage of the first embodiment; the figure 4 is a partial, schematic cross-sectional view representing another stage of the first embodiment; the figure 5 is a partial, schematic cross-sectional view representing a step in a second embodiment of a manufacturing process for a contact plug; the figure 6 is a partial, schematic cross-sectional view representing another stage of the second embodiment; the figure 7 is a partial, schematic cross-sectional view representing another stage of the second embodiment; the figure 8is a partial, schematic cross-sectional view representing a step in a third embodiment of a manufacturing process for a contact plug; the figure 9 is a partial, schematic cross-sectional view representing another stage of the third embodiment; the Figure 10 is a partial, schematic cross-sectional view representing another stage of the third embodiment; the figure 11 is a partial, schematic cross-sectional view representing a step in an implementation method, in the example of the second embodiment, of a process for forming an opening in an insulating layer covering a semiconductor region comprising germanium; the figure 12 is a partial, schematic cross-sectional view representing another stage in the implementation of the process for forming an opening; the figure 13is a partial, schematic cross-sectional view representing another stage in the implementation of the process for forming an opening; the figure 14 is a partial, schematic cross-sectional view representing another stage in the implementation of the process for forming an opening; the figure 15 is a partial, schematic cross-sectional view representing another stage in the implementation of the process for forming an opening; the figure 16 is a partial, schematic cross-sectional view representing a fourth embodiment of a manufacturing process for a contact plug, implementing the steps of figures 11 to 15 ; there figure 17 is a partial, schematic cross-sectional view representing one variant of the process for forming an opening; the figure 18is a partial, schematic cross-sectional view representing a step of a variant of the fourth embodiment, implementing the variant of the figure 17 ; there figure 19 is a partial, schematic cross-sectional view representing another stage of the variant of the fourth embodiment; the Figure 20 is a partial, schematic cross-sectional view representing a fifth embodiment of a manufacturing process for a contact plug, implementing the variant of the figure 17 ; there figure 21 is a partial, schematic cross-sectional view representing one embodiment of a photodiode; the figure 22 is a partial and schematic cross-sectional view, representing another embodiment of a photodiode. Description of the implementation methods

[0013] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0014] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, in the electronic components, elements other than a semiconductor region comprising germanium, a contact, and an electrical conductor have not been described, as the embodiments are compatible with known electronic components containing a germanium region.

[0015] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two linked or coupled elements, this means that these two elements can be connected or linked or coupled through one or more other elements.

[0016] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0017] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0018] THE figures 1 to 4 are partial and schematic cross-sectional views, representing steps in an implementation of a manufacturing process for a contact point on a region containing germanium.

[0019] The process is implemented during the fabrication of an electronic device comprising one or more components containing or based on germanium. The device may include, or be composed of, an integrated circuit electronic chip. Such a chip is defined as a portion of a semiconductor wafer and elements, such as electronic components, entirely located within and on one face of the wafer. In a particular, non-limiting example, the process can be implemented for the fabrication of a photodiode containing germanium.

[0020] At the stage of the figure 1 A substrate 100 is planned. Substrate 100 can be a portion of a semiconductor wafer, for example, germanium. Substrate 100 can also be a layer covering the top surface of a support such as, for example, a semiconductor wafer.

[0021] A semiconductor region 110 containing germanium is located on one side of the substrate 100, for example, the front or top face of the substrate 100. If the substrate 100 contains, or is made of, germanium, the region 110 is, for example, a doped region of the substrate. If the substrate 100 is made of a semiconductor other than germanium, for example, silicon, the semiconductor region 110 may have been formed, for example, in a cavity etched into the substrate 100. Preferably, the semiconductor region 110 is single-crystal, the substrate 100 being preferably single-crystal. The semiconductor region 110 may then result from epitaxy.

[0022] Region 110 is composed primarily, that is, predominantly, of germanium. In other words, region 110 consists of a semiconductor material with an atomic percentage of germanium greater than 50%, preferably greater than 90%. In a preferred example, region 110 is made of doped germanium. More preferably, region 110 is made of single-crystal germanium. In another example, region 110 is made of doped silicon-germanium.

[0023] A semiconductor layer 120 is formed on the semiconductor region 110, having an atomic percentage of silicon greater than 70%. The layer 120 may include, in addition to silicon, a metalloid other than silicon, preferably germanium. In a preferred example, the layer 120 is made of silicon. In another example, the layer 120 is made of silicon-germanium.

[0024] Preferably, the 120 semiconductor layer is single-crystal. To achieve this, the 120 layer can be obtained by epitaxy on the single-crystal 110 region. The thickness of the 120 semiconductor layer is less than a threshold thickness that allows the epitaxially grown layer to be single-crystal. This threshold thickness can be determined experimentally based on the composition of the 120 semiconductor layer and the 110 semiconductor region. This threshold is on the order of 2 nm for a silicon 120 layer epitaxially grown on the germanium 110 region. Alternatively, the 120 semiconductor layer is not single-crystal. The thickness of the 120 layer can then exceed the threshold thickness.

[0025] A metallic layer 130 is then formed over the semiconducting layer 120. Preferably, the metallic layer 130 comprises nickel; for example, it is substantially composed of nickel. Preferably, the layer 130 comprises, in addition to nickel, platinum and / or cobalt. In one preferred example, the metal of the layer 130 comprises, more preferably, consists of nickel and cobalt, with the atomic percentage of cobalt being between 5 and 20%. In another preferred example, the metal of the layer 130 comprises, more preferably, consists of nickel and platinum, with the atomic percentage of platinum being between 5 and 15%.

[0026] Preferably, the thickness of the metal layer 130 is greater than half that of the semiconducting layer 120. More preferably, the metal layer 130 has a thickness between 7 and 50 nm.

[0027] Preferably, before deposition of the metallic layer 130, the upper surface of the semiconductor layer 120 is prepared. The surface preparation step includes, for example, liquid-phase treatment with hydrofluoric acid, followed by plasma treatment. The plasma may be argon-based or, for example, of the type known commercially as Siconi™. The plasma treatment and the deposition of the metallic layer 130 are then carried out sequentially without interrupting the vacuum. This prevents the presence of impurities, such as oxides, between the semiconductor layer 120 and the metallic layer 130. Such impurities could arise from exposure to air after the deposition of layer 120, or after the liquid-phase surface preparation step. The semiconductor layer 120 and the metallic layer 130 are thus in direct contact with each other.

[0028] Preferably, after the formation of the metallic layer 130, a protective layer 140 is formed on top of the layer 130. This layer is preferably formed without void interruption after the deposition of the metallic layer 130. The layer 140 is intended to protect the structures located beneath the layer 140 against oxidation during subsequent process steps. Preferably, the protective layer 140 is made of titanium nitride. Alternatively, the protective layer 140 may be omitted.

[0029] At the stage of the figure 2 A first heat treatment is performed. More precisely, this heat treatment corresponds to annealing the structure obtained at the figure 1This first heat treatment is carried out at a temperature that allows the metal of the metallic layer 130 to react partially with the material of the semiconductor layer 120. This results in a layer 220 in place of the layer 120. The temperature of the first heat treatment is preferably less than or equal to 300°C, for example between 250°C and 300°C, which allows a partial reaction of the nickel-containing layer 130 with the material of the semiconductor layer 120.

[0030] Preferably, the first heat treatment is carried out in the presence of nitrogen. The nitrogen is preferably at atmospheric pressure or at a pressure less than 1 bar above atmospheric pressure. The duration of the first heat treatment is preferably between 10 s and 120 s.

[0031] Layer 220 comprises an intermetallic material, or intermetallic compound, that is, a combination of one or more metallic chemical elements and one or more chemical elements, typically metalloids, that can be used in the composition of a semiconductor. Preferably, the intermetallic material has a crystalline structure combining metallic and nonmetallic chemical elements. In layer 220, the nonmetallic chemical elements are substantially made up of the material of semiconductor layer 120. In particular, the fact that more than 70% of the atoms in semiconductor layer 120 are silicon implies that more than 70% of the nonmetallic atoms in layer 220 are silicon. In a preferred example, the intermetallic material of layer 220 is a nickel silicide or a silicide containing nickel.In another preferred example, the intermetallic material of layer 220 is a nickel germanium silicide or a germanium silicide comprising nickel.

[0032] Preferably, the thickness of the 130 metallic layer chosen at the step of the figure 1 is sufficient for some of the metal in layer 130 to react with an upper portion of the semiconductor region 110. This reaction produces a layer 210 located below layer 220. Layer 210 comprises, or preferably is made of, an intermetallic material. Because region 110 is primarily composed of germanium, the nonmetallic atoms in layer 210 are primarily germanium atoms. Thus, when the metallic layer 130 is nickel or contains nickel, the intermetallic material in layer 210 is nickel germanide or a germanide containing nickel.

[0033] Preferably, the thickness of the 130 metallic layer chosen at the step of the figure 1 is sufficient so that a part 230 of the metal layer 130 does not react with the semiconducting layer 120 and the semiconducting region 110.

[0034] At the stage of the figure 3 The protective layer 140, if present, is removed, along with the unreacted portion 230 of layer 130. This removal is selective with respect to the material of layer 220. The removal is carried out, for example, in an etching solution based on sulfuric acid and hydrogen peroxide, or alternatively, in an etching solution based on hydrochloric acid and nitric acid. Because layer 220 comprises, in addition to metallic elements, more than 70% silicon atoms, these solutions allow the materials of layers 130 and 140 to be etched without removing or altering layer 220.

[0035] At the stage of the figure 4A second heat treatment is performed. This heat treatment corresponds to annealing the structure obtained in the first step. figure 3 This transforms layers 210 and 220 into layers 410 and 420 respectively.

[0036] When layer 130 contains nickel, the heat treatment temperature is preferably greater than or equal to 390°C. This ensures that, after the second heat treatment, the intermetallic phase of layer 420 has a lower electrical resistivity than the other phases of this intermetallic. In particular, this allows layer 420 to contain the same proportion of metallic atoms as non-metallic atoms, for example, the same atomic proportions of nickel and silicon (NiSi). As an example, some of the nickel contained in layer 220 at the stage of the figure 3reacts with the semiconductor region 110 during the second annealing. The thickness of layer 410 is then greater than that of layer 210 ( figures 2 and 3 Alternatively, layer 210 is not formed during the first heat treatment, and only layer 410 is formed during the second heat treatment. The fact, mentioned above, that at the stage of the figure 1 the thickness of the metallic layer 130 is preferably greater than half that of the semiconducting layer 120, allows the 410 layer to be obtained during the second heat treatment.

[0037] Furthermore, when layer 130 contains nickel, the heat treatment temperature is preferably below 420°C. This optimizes the resistivity of the nickel germanide in layer 410 and prevents this resistivity from being degraded by excessively high temperatures.

[0038] The intermetallic zones defined by the layers 410 and 420 thus obtained constitute an electrical contact 400 on the semiconducting region 110.

[0039] One could have considered establishing a contact point that did not include layer 420. To achieve this, one could have imagined implementing steps similar to those of... figures 1 to 4 , but without forming the silicon layer 120. However, during a step, such as that of the figure 3 If the portion of a metallic layer that did not react was removed, contact between the germanium and an etching solution could have oxidized the germanium and dissolved the germanium oxide in the solution. This would have damaged the semiconductor region 110, resulting in reliability and contact strength issues.

[0040] Thus, the presence of the 420 layer allows for a 400 contact on germanium with better resistivity and reliability than a contact without such a layer.

[0041] THE figures 5 to 7 These are partial, schematic cross-sectional views representing steps in another embodiment of a process for manufacturing a contact on a semiconductor region 110 comprising germanium. The semiconductor region 110 is identical or similar to that described in relation to the figure 1 , and is preferentially located in the upper part of a substrate 100.

[0042] At the stage of the figure 5Preferably, a semiconductor layer 500 comprising silicon is formed on the upper surface of the semiconductor region 110. The layer 500 is made of silicon, or has an atomic percentage of silicon greater than 70%. As an example, the layer 500 is grown by epitaxy on the surface of the semiconductor region 110. The thickness of the layer 500 is, for example, between 1 nm and 3 nm, preferably on the order of 2 nm.

[0043] An electrically insulating layer 510 is then formed on the semiconductor layer 500. The insulating layer 510 can be made of silicon dioxide, preferably resulting from the hydrolysis of tetraethyl orthosilicate (TEOS). Preferably, the thickness of the insulating layer 510 is on the order of, or greater than, 100 nm.

[0044] At the stage of the figure 6An aperture 600 is etched through the insulating layer 510 at the location of the future contact point. Preferably, the aperture 600 is made only above a portion of the semiconductor region 110. The width of the aperture can be between 300 nm and 1.5 µm. The aperture 600 is compatible with any standard method for creating an aperture in an insulating layer, for example, photolithography followed by plasma etching (the etching mask is not shown). In practice, the aperture 600 is extended through the layer 500 to a level located in the semiconductor region 110. The difference in level, that is to say the distance in the direction orthogonal to the upper face of the substrate 100, between the bottom 602 of the aperture 600 and the upper face 604 of the semiconductor layer 500, is for example between 5 nm and 30 nm, preferably on the order of 10 nm.

[0045] A 120A semiconductor layer is then grown by epitaxy. The 120A layer is identical in composition and thickness to the 120 semiconductor layer of the process of figures 1 to 4 The semiconductor layer 120A grows from the bottom 602 and from the parts of the side walls of the opening 600 located below the upper level 604 of the layer 500. As a result, the semiconductor region defined by the layer 120A forms, with the remaining portions of the layer 500, a continuous semiconductor layer, i.e. without openings, covering the semiconductor region 110, this continuous layer comprising at least 70% silicon.

[0046] After that, the metallic layers 130 and possibly the protective layers 140 described in relation to the are successively formed figure 1The layers 130 and 140 cover the bottom of the opening 600 and the remaining portions of the insulating layer 510. Preferably, the total thickness of the metallic layer 130 and protective layer 140 is less than that of the insulating layer 510. In the example shown, the metallic layer 130 and protective layer 140 are formed by non-conformal deposition, i.e., the materials of these layers are deposited only on the upward-facing surfaces. Because the thickness of the metallic layer 130 is less than that of the insulating layer 510, a metallic region 130A is formed without contact with the rest of the layer 130, and located at the bottom of the opening 600. The step described here is not limiting, and any process enabling the formation of a metallic region 130A on only a part of the semiconducting region 110 may be used. Alternatively, the metallic layer 130 and / or the protective layer 140 may be formed by conformal deposition.

[0047] At the stage of the figure 7 , we implement the steps of figures 2 to 4 namely, successively, the first heat treatment, the removal of any protective layer 140 and the remaining portions of the metallic layer 130, and the second heat treatment. This results, on the region 110 composed mainly of germanium, in a contact comprising an intermetallic zone 420 formed from the semiconducting layer 120A. Among the non-metallic atoms of the zone 420, more than 70% are silicon atoms. Preferably, as for the layer 420 of the figure 4 The non-metallic atoms in zone 420 are silicon atoms. More preferably, zone 420 comprises nickel silicide.

[0048] The metallic layer 130 is chosen to be sufficiently thick to form, beneath the zone 420, an intermetallic zone 410, in which the non-metallic atoms are primarily germanium. More preferably, the zone 410 comprises, for example, nickel germanide.

[0049] Next, the opening 600 is filled with an electrical conductor 700. The conductor 700 makes it possible to establish an electrical connection with the semiconductor region 110. For example, the conductor 700 can be covered with, and in contact with, an electrical bonding track between components of an electronic chip.

[0050] One advantage of the process of figures 5 to 7 is that the contact with the semiconductor region 110, consisting of zones 420 and 410, is self-aligned with the conductor 700. In an electronic chip comprising several contacts obtained by the process of figures 5 to 7This allows for closer contact points than in a device where the contacts are not self-aligned in this way. Therefore, the component density of the chip can be increased, i.e., improved.

[0051] THE figures 8 to 10 These are partial, schematic cross-sectional views representing steps in another embodiment of a process for forming a localized contact zone on a semiconductor region 110 comprising germanium. The semiconductor region 110 is identical to that described in relation to the figure 1 In particular, the semiconductor region 110 is preferentially located on the front face side of a substrate 100.

[0052] At the stage of the figure 8The semiconductor region 110 is covered with a multilayer 800 comprising alternating silicon 802 and germanium 804 layers. More precisely, the 802 layers have a silicon atomic proportion greater than 70%. Preferably, the 802 layers are made of silicon, or of silicon-germanium, with a silicon atomic proportion greater than 70%. The 804 layers are made of germanium or are composed primarily of germanium. Preferably, the 804 layers are made of germanium, or of silicon-germanium composed primarily of germanium. As an example, the thickness of the multilayer 800 is greater than 10 nm, preferably on the order of 15 nm. Preferably, the 802 layers have the same thickness. Preferably, the 804 layers have the same thickness. Even more preferably, the 802 and 804 layers all have the same thickness.

[0053] Preferably, the 800 multilayer is formed by epitaxy on the upper surface of the single-crystal region 110. Each of the 802 and 804 layers then has a thickness less than a threshold thickness below which the layer remains single-crystal. In practice, this threshold, or critical thickness, depends on the composition of the 802 and 804 layers. For example, each of the 802 and 804 layers has a thickness on the order of, or less than, 2 nm. Thus, the resulting 800 multilayer is single-crystal.

[0054] We then implement steps similar to those of figures 5 and 6namely, the successive formation of an insulating layer 510, an aperture 600 that fully traverses the insulating layer 510, a metallic layer 130, and a possible protective layer 140. In practice, the aperture 600 extends to a level located within the multilayer 800. In the example shown, the bottom of the aperture 600 is located in a layer 804A among the layers 804, which are primarily composed of germanium. In another example, the bottom of the aperture 600 stops within one of the layers 802, or at an interface between one of the layers 802 and one of the layers 804. At least one of the layers 802, comprising at least 70% silicon, is not reached by the aperture 600 and is therefore left intact. In the example shown, two of the 802 layers are not etched.

[0055] At the stage of the figure 9 , we implemented the following steps successively: figures 2 and 3that is to say the first heat treatment, and the removal of any protective layer 140 and the remains of the metallic layer 130. Preferably, the thickness of the metallic layer 130 deposited in the step of the figure 8 is chosen sufficient so that each of the layers 802 and 804, as well as a portion of the semiconductor region 110, reacts with the metal of the metallic layer 130. The reaction of each of the layers 802, 804 with the material of the metallic region 130A produces a respective zone 902, 904 under the aperture 600. The portions of the structure located between the zones 902, 904, and the remainder of the multilayer 800, delimited in figure 9 The dotted lines 910 are not shown.

[0056] Preferably, layer 904A (shown as a dashed line), which results from the reaction of layer 804A with the material of metallic layer 130, is also removed. This removal is preferably carried out with the same etching solution used to remove the remaining portions of metallic region 130A. This is possible because the non-metallic atoms of region 904A are primarily germanium atoms. This avoids retaining region 904A, which would have been damaged by the etching solution. This also makes accessible the upper surface of region 902, which was beneath and in contact with region 904A before removal. Because more than 70%, or all, of the non-metallic atoms in region 902 are silicon, the etching solution leaves region 902 intact. Therefore, region 902 is not damaged by the etching process. Thus, the semiconductor region 110 is protected from the etching solution by at least one of the 902 zones.

[0057] At the stage of the Figure 10 , the second heat treatment is carried out, as described in relation to the figure 4 This transforms zones 902 and 904 into zones 1002 and 1004, respectively. The result is a contact consisting, in this example, of several superimposed intermetallic zones. Adjacent intermetallic zones are in contact with each other. Starting from the semiconductor region 110, the contact successively includes zone 410, resulting from the reaction of a portion of the semiconductor region 110 with the metallic layer 130; and: a 1002 zone having more than 70% of the non-metallic atoms made up of silicon; or several 1002 zones having more than 70% of the non-metallic atoms made up of silicon, separated by one or more 1004 zones having their non-metallic atoms made up mainly of germanium.

[0058] The remainder of the cavity in the opening 600 is then filled with an electrical conductor 700, preferably metallic. The area 1002 located in the upper part of the contact socket is in electrical contact with the conductor 700. Because the area 902 ( figure 9 ) upper was not altered during the removal of the unreacted parts of the metallic layer 130, and because there is no intermetallic zone from zone 904A between zone 1002 and electrical conductor 700, the resistance and reliability of the contact between the contact socket and conductor 700 are optimized.

[0059] In the preferred case of a single-crystal 800 stack, the entire contact assembly and the 110 semiconductor region are single-crystal. Therefore, the electrical resistance of the contact is lower than that of a non-single-crystal contact. This allows for a further improvement in electrical resistance.

[0060] THE figures 11 to 15 are partial and schematic cross-sectional views, representing successive stages of an implementation method, in the example of the second implementation method ( figures 5 to 7 ), of a process for forming an opening in the insulating layer covering a semiconductor region containing germanium. More specifically, the process is applied here to the formation, from the structure obtained in the step of the figure 5 , with an opening of 600 ( figure 6 ) in the insulating layer 510 covering the semiconductor region 110.

[0061] As mentioned in relation to the figure 5 The 510 layer is preferably made of silicon dioxide, more preferably resulting from the hydrolysis of TEOS. The 510 layer can also be made of silicon nitride.

[0062] In the example of the structure obtained in the step of the figure 5As mentioned above, an additional semiconductor layer 500 is located beneath the insulating layer 510. More precisely, the semiconductor layer 500 is situated between the semiconductor region 110 and the insulating layer 510. The semiconductor layer 500 is in contact with the insulating layer 510. The layer 500 is made of silicon, or has an atomic percentage of silicon greater than 70%, the layer 500 then being, for example, silicon-germanium. The silicon layer 500 in contact with the insulating layer 510 thus improves the stability of the insulating layer 510, compared to a structure lacking the layer 500.

[0063] At the stage of the figure 11, a first masking layer 1110 is formed on the insulating layer 510. By masking layer, we mean a layer intended to be traversed by one or more through openings and to be used during an etching step to allow etching reagents to pass only through these openings.

[0064] Preferably, the first masking layer 1110 is made of a dielectric material, that is, an electrically insulating material. One advantage is that such a material can be left in place on the insulating layer 510 without creating a short circuit between future conductive elements in contact with the first masking layer 1110. This eliminates the need to remove the first masking layer 1110.

[0065] The first masking layer 1110 may include, for example, at least one layer of a material chosen from the group consisting of: hafnium oxide HfO 2, preferably deposited by atomic layer deposition (ALD); aluminium oxide Al 2 O 3, preferably deposited by ALD; aluminium nitride AlN, preferably deposited by physical vapor deposition (PVD); zinc oxide ZnO, preferably deposited by PVD; and a silicon nitride such as SiN or Si 3 N 4, preferably deposited by chemical vapor deposition (CVD), more preferably at low pressure (LPCVD), i.e. in which the pressure is subatmospheric.

[0066] Next, on the first masking layer 1110, a second masking layer 1120 is formed, comprising an opening 1122. The opening 1122 is located directly above the location of the future opening 600. The second masking layer 1120 is made of polymer, and preferably results from the lithography of a positive or negative resin such as a photosensitive resin.

[0067] At the stage of the figure 12 In the first masking layer 1110, a through-hole 1210 is etched, located in line with the opening 1122 of the second masking layer 1120. The etching preferably stops on the upper surface of the insulating layer 510. Alternatively, the etching stops at a level located within the insulating layer 510. Thus, in line with the opening 1210, the insulating layer 510 is left in place, over at least part of its thickness, on the semiconductor layer 500 and the semiconductor region 110.

[0068] A possible step of removing etching residues (not shown), i.e., a cleaning step, can then be implemented. For example, cleaning is carried out using a hydrofluoric acid (HF) solution.

[0069] At the stage of the figure 13 The second masking layer is removed by oxygen-based etching, typically using plasma. For example, the plasma may consist only of oxygen or, in addition to oxygen, of carbon tetrafluoride (CF₄). The etching temperature is typically between 120 and 220°C. Such a plasma allows the removal of the second masking layer (1120) when it results from lithography or any process for forming a masking layer with openings that can be removed by oxygen-based etching.

[0070] At the stage of the figure 14The opening 600 is formed as an extension of the opening 1210 of the first masking layer 1110 by fluorine-based etching, that is, etching primarily with one or more reagents containing fluorine. "Primarily" means that more than half, preferably more than 90%, and even more preferably more than 99%, of the reactive molecules used for etching are fluorinated. More precisely, the etching is substantially oxygen-free, meaning that less than 5%, preferably less than 1%, of the reactive molecules used for etching contain oxygen. More preferably, the etching reagent(s) are oxygen-free. In this embodiment, the etching is reactive ion etching (RIE), for example, with octafluorocyclobutane C4F8.

[0071] The fact, mentioned above, that the first masking layer 1110 belongs to the group consisting of HfO₂, Al₂O₃, AlN, ZnO, SiN, and Si₃N₄ allows for selective etching of the insulating layer material 510 relative to the material of the first masking layer 1110. Indeed, in the preferred case where the insulating layer is silicon oxide resulting from the hydrolysis of TEOS, the etching rate of the insulating layer 510 is then more than 5 times faster than the etching rate of the masking layer material. In particular, according to a preferred embodiment, the first masking layer is HfO₂ or Al₂O₃, and the etching rate of the silicon oxide resulting from the hydrolysis of TEOS is then more than 10 times faster than the etching rate of the first masking layer material.

[0072] In practice, traces of engraving 1410 may remain on the sides and bottom of the opening 600. A cleaning step, described below, can then be planned in relation to the figure 15 .

[0073] At the stage of the figure 15 The etching residues are removed. As an example, for this purpose, an HF solution is used. The solution preferably has an HF concentration between 0.1% and 1% molar, and is applied for a duration of between 10 and 30 s.

[0074] Thus, at the end of the steps of figures 11 to 15 , the opening 600 in the insulating layer 510 covering the semiconductor region 110. Instead of making the opening 600 by the steps of figures 11 to 15One could form a single polymer masking layer directly onto the insulating layer 510, etch the aperture 600, and then remove the masking layer by oxygen-based etching. The thickness of layer 500, mentioned above, would then have been too small to prevent the layer 500 from being oxidized throughout its thickness, and for some of the germanium in the semiconductor region 110 to also be oxidized. This would have resulted in an extension of aperture 600 below the lower level of the insulating layer 510, as mentioned above in relation to the figures 6 And 8 .

[0075] Compared to steps involving a single layer of masking, the steps of figures 11 to 15These features allow the insulating layer 510 to protect the semiconductor layer 500 from oxidation during the removal of the polymer masking layer. Specifically, this leaves a region 120A of the semiconductor layer 500 at the bottom of the opening. This also allows the opening 600 to be formed without oxidizing the germanium in the semiconductor region 110, thus preventing damage to the semiconductor region 110 from oxidation.

[0076] Although the steps of figures 11 to 15 are implemented here in the example of the formation of the opening 600 in the insulating layer 510, steps similar to those of the figures 11 15These methods can be implemented to form any opening in any insulating layer covering a semiconductor region consisting primarily of germanium, the insulating layer preferably being silicon oxide and more preferably silicon oxide resulting from the hydrolysis of TEOS. In particular, the 500 layer may be omitted. Alternatively, the insulating layer may be silicon nitride, in which case those skilled in the art could define the material of the first masking layer to obtain a fluorine-based selective etching of the silicon nitride relative to the masking layer.

[0077] There figure 16 is a partial, schematic cross-sectional view representing a fourth embodiment of a manufacturing process for a contact plug, implementing the steps of figures 11 to 15 .

[0078] After the stages of figures 11 to 15 , we implement successively: in the manner described in relation to the figure 6 , the formation of metallic layers 130 ( figure 6 ) and possibly 140 protection ( figure 6 ) ; and in the manner described in relation to the figure 7 , the first heat treatment, the removal of any protective layer 140 and the remaining portions of the metallic layer 130, the second heat treatment and the filling of the opening 600 with an electrical conductor 700.

[0079] As mentioned above, this results, on the region 110 consisting mainly of germanium and preferentially doped, in a contact 400 comprising an intermetallic zone 420 formed from the semiconductor region 120A ( figure 6 ). The intermetallic zone results from the reaction of a 130A region ( figure 6 ) of the metallic layer 130 with the semiconducting region 120A.

[0080] As mentioned, the steps of figures 11 to 15These features prevent damage to the semiconductor region 110 from oxidation. Furthermore, the semiconductor region 110 is preferentially doped. The higher the doping level of the semiconductor region 110, the more susceptible it is to oxidation, particularly with doping resulting from ion implantation. The resulting contact 400 thus has lower resistance and higher reliability than a contact where the opening 600 was formed using a single-layer masking process.

[0081] Region 120A, which forms the intermetallic zone 420 by reaction with the metallic region 130A, is constituted by a portion of the semiconductor layer 500. Since the semiconductor layer 500 has an atomic percentage of silicon greater than 70%, more than 70% of the non-metallic atoms in the intermetallic zone 420 are silicon atoms. Alternatively, region 120A comprises, or is constituted by, a semiconductor layer formed on the portion of the semiconductor layer 500, or, in the absence of the semiconductor layer 500, directly on the semiconductor region 110.

[0082] The electrical conductor 700 is preferably obtained by forming a metallic layer over the entire upper surface of the structure. The portions of the metallic layer located above the upper level of the first masking layer 1110 are then removed. This removal is carried out, for example, by chemical polishing. The first masking layer 1110 can then advantageously serve as a stop layer.

[0083] Although, in the stages of figures 11 to 16 The first masking layer may be made of an electrically insulating material that can be left in place; this is not a limitation. Alternatively, the first masking layer 1110 may be made of a conductive material and removed after the opening 600 has been formed.

[0084] In this case, according to a preferred embodiment, the first masking layer 1110 and the metallic region 130A ( figure 6) preferably include one or more of the same metals. Thus, the first masking layer 1110 can advantageously be removed at the same time as the remaining portions of the metal layer 130 after the contact point has formed.

[0085] According to another preferred embodiment, the first masking layer 1110 and the protective layer 140 ( figure 6 The layers covering the metallic region 130A preferably comprise one or more of the same metals. Thus, the first masking layer 1110 can advantageously be removed at the same time as the protective layer 140.

[0086] There figure 17 is a partial, schematic cross-sectional view representing one variant of the implementation of the process of figures 11 to 15 .

[0087] The variant of the figure 17 corresponds to the process of figures 11 to 15 in which, at the stage of the figure 14The fluoride-based etching is, at least in part, carried out using an HF solution. The HF solution preferably has a higher concentration than the HF solution used in the cleaning step of the figure 15 , for example, greater than 5 mol%. Such an etching is substantially isotropic. As a result, the aperture 600 in the insulating layer is wider than the aperture 1112 in the first masking layer 1110. In other words, the flanks 1710 of the aperture 600 are overhung by the edges of the aperture 1112.

[0088] The fluoride-based etching step can be followed by a cleaning step corresponding to the step of the figure 15 .

[0089] THE Figures 18 and 19 are partial and schematic cross-sectional views representing stages of a variant of the fourth embodiment, implementing the variant of the figure 17 .

[0090] At the stage of the figure 18, the metallic layer 130 and, preferably, the protective layer 140 are formed, in the manner described in relation to the figure 6 The metallic layer 130 includes a metallic region 130A designed to react with the semiconducting region 120A to form an intermetallic zone. Due to the overhanging shape of the walls of the openings 600 and 1112, the metallic region 130A is advantageously separated from the rest of the layer 130, which facilitates the subsequent removal of the remaining portions of the layer 130 after the reaction.

[0091] At the stage of the figure 19 , a contact is formed comprising intermetallic zones 410 and preferably 420, and the opening 600 is filled with a conductor 700, in the manner described in relation to the figure 7 .

[0092] There Figure 20is a partial, schematic cross-sectional view representing a fifth embodiment of a manufacturing process for a contact plug, implementing the variant of the figure 17 .

[0093] The fifth embodiment differs from the second embodiment ( figures 5 to 7 ) in that, at the stage of the figure 7 , an electrically conductive layer 2010 covering the contact socket 400 is formed on the bottom and sides of the opening 600 before filling the opening 600 with the conductor 700.

[0094] The electrically conductive layer 2010 is preferably made of titanium nitride (TiN). This layer is in contact with the intermetallic zone 420. The thickness of the electrically conductive layer 2010 is preferably between 5 and 20 nm. The electrically conductive layer 2010 protects the upper surface of the contact 420, particularly against diffusion of the conductor material 700 into the intermetallic zone and / or against oxidation if the structure is exposed to air before the opening 600 is filled by the conductor 700. This reduces the resistance and increases the reliability of the contact compared to a contact not covered by the conductive layer 2010. Furthermore, the electrical conductivity of layer 2010 enables electrical contact between the contact and the conductor 700.

[0095] There figure 21This is a partial, schematic cross-sectional view representing one embodiment of a 2100 photodiode. More precisely, the manufacturing process for the 2100 photodiode here implements the fifth embodiment of the contact fabrication process. The photodiode fabrication process is compatible with the various contact embodiments described above.

[0096] To fabricate the 2100 photodiode, substrate 100 is preferably made of germanium. The germanium in substrate 100 is intrinsic, meaning it is either unintentionally doped or has a doping level less than 1016 atoms / cm3, preferably less than or equal to 1015 atoms / cm3. The germanium in substrate 100 is preferably single-crystal. Alternatively, substrate 100 can be silicon-germanium, preferably intrinsic and single-crystal.

[0097] The substrate 100 covers a silicon semiconductor wafer 2110. More precisely, an insulating layer 2120, typically made of silicon oxide, is placed between the semiconductor wafer 2110 and the substrate 100. The semiconductor wafer 2110, the insulating layer 2120, and the substrate 100 thus define a Semiconductor-On-Insulator (SOI) structure, more specifically, a Germanium-On-Insulator (GeOI) structure. The thickness of the insulating layer 2120 is typically on the order of 0.1 to 1 µm. The total thickness of the substrate 100 is, for example, on the order of 1 to 2 µm.

[0098] In substrate 100, a P-type doped germanium semiconductor region 110P and an N-type doped germanium semiconductor region 110N are formed. In other words, the 110N and 110P semiconductor regions have opposite conductivity types. The 110N and 110P semiconductor regions extend from the free, or accessible, face of substrate 100, that is, the front face (the top face in the orientation shown in the figure). The 110N and 110P semiconductor regions constitute the cathode and anode regions, respectively, of the photodiode 2100.

[0099] Preferably, the 110P and 110N semiconductor regions are obtained by creating cavities in the substrate 100 at the locations of the 110P and 110N semiconductor regions, and then filling the cavities by epitaxy with doped germanium. This ensures that the semiconductor regions are, at least in an upper portion intended for the formation of the contact points, single-crystal. Alternatively, the 110N and 110P semiconductor regions are obtained by ion implantation.

[0100] A 100I semiconductor region of substrate 100 separates the 110P and 110N semiconductor regions. The 100I semiconductor region is thus intrinsically germanium. For example, the distance separating the 110P and 110N semiconductor regions is between 1 µm and 20 µm.

[0101] Preferably, a silicon-germanium-2130 layer, preferably single-crystal, is formed on the structure, and in particular on the intrinsic region 100I. This silicon-germanium-2130 layer is preferably formed epitaxially on the substrate 100, more precisely on the free face of the substrate 100. The silicon-germanium-2130 layer is thus in contact with the substrate 100. The silicon-germanium-2130 layer preferably has a thickness less than the critical thickness below which it remains single-crystal during its epitaxial growth. Thus, the thickness of the silicon-germanium-2130 layer is typically less than 3 nm.

[0102] Preferably, the 500 semiconductor layer is then formed on top of the silicon-germanium 2130 layer. More preferably, before forming the 500 semiconductor layer, an intrinsic germanium 2140 layer is formed on top of the silicon-germanium 2130 layer. The germanium 2140 layer ensures, in particular, that the 500 semiconductor layer is monocrystalline. For this to occur, the 500 semiconductor layer has a sufficiently small thickness, as mentioned above. Indeed, without the germanium 2140 layer, the combined thickness of the silicon-germanium 2130 layer and the 500 semiconductor layer would be too great for the 500 semiconductor layer to remain monocrystalline.

[0103] Next, the insulating layer 510 is formed, and then, in the example shown, the fourth embodiment is implemented ( Figure 20) of the contact formation process. More specifically, the process is implemented to simultaneously form two contacts 400N and 400P with the respective semiconductor regions 110N and 110P. Each 400N, 400P contact thus comprises an intermetallic zone 420, in which more than 70% of the non-metallic atoms are silicon atoms, and, preferably, an intermetallic zone 410, in which the non-metallic atoms are primarily germanium atoms. The edges of the contacts are not shown (regions between dashed lines 2150). In the case where the silicon-germanium layer 2130 is provided, the contact may further comprise an intermetallic zone 2132 located on and in contact with the intermetallic zone 410. The intermetallic zone 2132 comprises silicon and germanium atoms.In cases where the germanium-2140 layer is provided, the contact may also include an intermetallic zone 2142, in which the nonmetallic atoms are primarily, and preferably exclusively, germanium atoms. The intermetallic zone 2142 lies between zones 2132 and 420.

[0104] In the resulting 2100 photodiode, the 2130 silicon-germanium layer, located between the 110I semiconductor region and the 510 insulating layer, is in contact with the intrinsic 100I region. This creates a single-crystal interface delimiting the 110I semiconductor region. Such an interface reduces the dark current of the photodiode compared to an interface with crystalline defects. Furthermore, the 2140 germanium layer is located between the 2130 silicon-germanium layer and the 510 insulating layer, preferably between the 2130 silicon-germanium layer and the 500 semiconductor layer. Because silicon-germanium has a wider band gap than germanium, carriers present in the 2140 germanium layer cannot access the intrinsic 110I region.These carriers can, for example, originate from defects at the interface of the semiconductor layer 500 with the insulating layer 510 and / or the germanium layer 2140. Because the layers 2130 and 2140 prevent these carriers from reaching the intrinsic region 100I, the dark current of the photodiode is reduced compared to the dark current of a photodiode lacking the 2130 and / or 2140 layers.

[0105] There figure 22 This is a partial, schematic cross-sectional view representing an alternative embodiment of a 2200 photodiode. The manufacturing process of the 2200 photodiode differs from that of the 2100 photodiode. figure 21in that, prior to the formation of the insulating layer 510, insulating trenches 2210 were formed, delimiting, on the intrinsic region 100I, a portion 2240 of the germanium layer 2140. Preferably, the insulating trenches 2210 are located directly above the edges of the intrinsic region 100I. The insulating trenches are then filled with an electrical insulator, preferably the insulator of the layer 510.

[0106] As an example, the 2210 trenches have a width between 100 nm and 300 nm. In the example shown, the trenches extend from the top face of the 500 semiconductor layer, through the 500 and 2140 layers, to the top face of the 2130 silicon-germanium layer. Alternatively, the 2210 trenches extend through the 2130 layer, for example at least to the top face of the 100 substrate.

[0107] The trenches 2210 thus constitute insulating zones delimiting a portion of the germanium-2140 layer on the intrinsic region 100I. These insulating zones are located between the germanium-2140 layer and the contacts 400N and 400P. The photodiode 2200 is compatible with any method for forming an intrinsic germanium layer located on the intrinsic region 100I and delimited by insulating zones situated between said germanium-2140 layer and the contacts. Therefore, alternatively, the germanium-2140 layer can be formed solely on the intrinsic region 100I.

[0108] The insulating zones 2210 prevent carriers present in the germanium layer 2140, mentioned above, from reaching the contacts 400N and 400P. Thus, the insulating zones allow the photodiode 2200 to exhibit a lower dark current than that of a photodiode, such as the photodiode 2100 of the figure 21, lacking the insulating zones 2210.

Claims

1. Method of forming an area (400) of electric contact with a semiconductor region (110) mainly made of germanium, comprising the forming of a first area (420) made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms, characterized in that: the contact area (400) comprises, between the first area (420) and the semiconductor region (110), a second area (410) made of a second intermetallic material where the non-metal atoms are mainly germanium atoms.

2. Electronic device comprising a semiconductor region (110) mainly made of germanium, and an area of electric contact (400) with the semiconductor region (110), the contact area (400) comprising a first area (420) made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms, and characterized in that: the contact area (400) comprises, between the first area (420) and the semiconductor region (110), a second area (410) made of a second intermetallic material where the non-metal atoms are mainly germanium atoms.

3. Method according to claim 1 or device according to claim 2, wherein the metal atoms of each of the first and second intermetallic materials are mainly nickel atoms and / or each of the first and second intermetallic materials comprises platinum and / or cobalt.

4. Method according to claim 1 or 3, or device according to claim 2 or 3, wherein the intermetallic material comprises germanium.

5. Method according to any of claims 1, 3, and 4, wherein the forming of the first area (420) successively comprises: a) the forming of at least one semiconductor layer (120; 120A; 802) covering the semiconductor region (110) and comprising at least 70% of silicon atoms; b) the forming of a metal region (130; 130A) on said at least one semiconductor layer (120; 120A; 802); c) the reacting of metal region (130; 130A) with at least a portion of said at least one semiconductor layer (120; 120A; 802); and d) preferably, the reacting of the material of the metal region (130; 130A) with that of the semiconductor region (110) .

6. Method according to claim 5, wherein step c) comprises: - a first thermal treatment, preferably at a temperature lower than 300°C; - a removal of portions of the metal region (230) which have not reacted during the first thermal treatment; and - a second thermal treatment, preferably at a temperature in the range from 390°C to 420°C.

7. Method according to claim 5 or 6, comprising, before step b), the forming of a protection layer (140), preferably made of titanium nitride, on the metal region (130, 130A).

8. Method according to any of claims 5 to 7, comprising the forming of an insulating layer (510) and of a first opening (600) extending through the insulating layer.

9. Method according to claim 8, comprising the forming, successively: - of an additional semiconductor layer (500) comprising at least 70% of silicon atoms; and - of an insulating layer (510) covering the additional semiconductor layer (500), the first opening (600) extending through the additional semiconductor layer (500), and said at least one semiconductor layer (120A) being formed in the opening (600) and forming, with the portions of the additional semiconductor layer (500) located around the opening (600), a continuous layer.

10. Method according to claim 13, successively comprising the forming: - of a multilayer (800), preferably monocrystalline, of first semiconductor layer (802) comprising at least 70% of silicon atoms alternating with second semiconductor layers (804) mainly made of germanium; and - of an insulating layer (510) covering the multilayer (800), the first opening extending through a portion of the multilayer (800) and said at least one semiconductor layer (802) being formed of the first layers (802) which have been left intact under the opening (600).

11. Method according to any of claims 8 to 10, wherein the forming of the first opening comprises: - the forming of a first masking layer (1110) on the insulating layer (510); - the forming on the first masking layer (1110) of a second masking layer (1120) comprising a second opening (1122); - the etching of a third opening (1210) in the first masking layer, in line with the second opening; - the removal of the second masking layer (1120) by oxygen-based etching; and - the forming of the first opening (600) in line with the third opening, by fluorine-based etching.

12. Method according to claim 11, wherein the first masking layer (1110) is made of an electrically-insulating material, preferably from the group formed of HfO2, Al2O3, AlN, ZnO, SiN, and Si3N4.

13. Method according to claim 11 or 12, wherein the fluorine-based etching comprises a C4F8-based plasma etching and / or an etching with a HF solution.

14. Method according to any of claims 11 to 13, wherein the second masking layer (1120) is a polymer layer resulting from a lithography.

15. Photodiode comprising a device according to any of claims 2 to 4 or comprising a contact area obtained by a method according to any of claims 1 and 3 to 14.