PARTICLE DETECTOR WITH A POROUS AREA OF SEMICONDUCTOR MATERIAL AND ASSOCIATED MANUFACTURING METHOD

Description

DOMAINE TECHNIQUE DE L'INVENTION

[0001] The technical field of the invention is that of detectors. More particularly, the invention relates to a detector, a detector based on so-called semiconductor technology (diode or transistor type), intended to measure a particle beam. ARRIERE-PLAN TECHNOLOGIQUE DE L'INVENTION

[0002] In experiments involving a particle beam, and in particular a high-energy particle beam, it is necessary to accurately measure the beam properties while minimizing its influence on the measurement as much as possible. The usual detection technologies for reading the beam are ionization chambers, scintillators and technology based on semiconductor components equipped with a rectifying junction. It is known to measure these beams with this type of rectifying detection to use Schottky-type semiconductor detectors, composed of a first layer of metal and a second layer of a semiconductor material or PIN, composed of a first layer of a p-doped semiconductor material, a second layer of an intrinsic semiconductor material and a third layer of an n-doped semiconductor material.This structure will give rise to an active zone, the one which allows the rectifier effect, mainly located in the intrinsic layer in which charges will be created when the beam passes.

[0003] It is known to make metal contacts acting as anode and cathode in order to be able to collect and measure these charges. Generally, these detectors are made in the thickness of a silicon wafer or other semiconductor material and can reach a thickness substantially equal to 300 µm. They therefore absorb a significant quantity of radiation. The first consequence of this absorption is to significantly disrupt the beam during measurement. In addition, since the radiation-matter interactions take place in a large volume of the material making up the detector, the degradation of the electrical and mechanical characteristics of the latter can be very rapid. Finally, charges are created outside the active zone and diffuse to the electrodes, adding noise to the measurement signal.In addition, the absorption of part of the beam in the material, which therefore leads to energy deposits from the absorbed particles, is also the cause of an accumulation of thermal energy which can cause, depending on the temperature level, not only a deviation of the beam reading but above all the destruction of the detector.

[0004] To partially solve this absorption problem, it is known to thin the part of the detector that the beam is forced to pass through during measurement. However, in order to collect the charges generated by the beam, the placement of electrodes on the beam path remains essential. The presence of these electrodes has two consequences. First of all, the materials used for the manufacture of these electrodes absorb a significant amount of the beam. In addition, the structure of the detector must be entirely between the electrodes. However, as already mentioned, the active zone is mainly concentrated in the intrinsic zone of the semiconductor material. In other words, a large part of the material crossed by the beam does not contribute directly to detection.

[0005] In order to overcome these drawbacks, patent EP3458878B1 proposes a detector in which an orifice has been provided in the central part of the detector in order to limit the absorption of the measured beam. However, such an orifice weakens the resulting detector, which makes the manufacture or handling of large detectors difficult.

[0006] There is therefore a need for a detector capable of measuring a beam of high-energy particles with good mechanical strength while avoiding excessive absorption of said beam by the detector and limiting the formation of unwanted charges in non-active areas. RESUME DE L'INVENTION

[0007] The invention provides a solution to the problems mentioned above by providing a detection device in which the beam only passes through the useful area of ​​the detector and a porous region. The porous region thus ensures good mechanical strength of the detector while minimizing the amount of beam absorbed while the rest of the structure allows the collection of charges generated by the beam in the active area in a manner offset from the path of the beam to be measured.

[0008] For this, a first aspect of the invention relates to a device for measuring a particle beam comprising a front face and a rear face as well as: a first part, called the central part, comprising means for forming a space charge zone intended to be crossed by a beam of particles to be measured, charge carriers of a first type and of a second type being generated by said beam when the latter crosses the space charge zone; a second part, called the peripheral part, comprising means for collecting at least one type of charge carrier from among the first type or the second type of charge carriers generated at the space charge zone; the central portion having a thickness less than or equal to the thickness of the peripheral portion, the peripheral portion surrounding the central portion such that a particle beam can pass through the central portion without passing through the peripheral portion.

[0009] The device is characterized in that it comprises, in a region of the central part and opening onto the rear face, a layer of a porous material forming a porous region such that the effective thickness perceived by the beam when it passes through the device at the level of the central part while passing through the porous region along an axis normal to the front face is less than the thickness of the central part, the space charge zone preferably being located outside the porous region.

[0010] A particle beam is understood to mean a beam of neutrons, protons, electrons or photons (for example, X-rays, gamma rays or UV rays). In other words, the notion of particles must be taken here in its broad sense. Effective thickness is understood to mean the thickness perceived by the beam when it passes through the porous medium. In other words, we can say that a porous material has an effective thickness t eff if the attenuation of the beam passing through this material is equivalent to the attenuation obtained with a material of the same nature but not porous with a real thickness t eff . It is important to note that the thickness of a porous material t mp is always greater than its effective thickness t eff , that's to say t mp > t eff . In fact, porosity makes it possible to reduce the amount of matter present in the beam path.

[0011] Thus, the particle beam to be measured only passes through the active zone, i.e., the space charge zone, preferably located outside the porous region, and the porous region of the detector. The disturbance caused by the detector on the beam is thus minimized without compromising the good mechanical strength of the latter. In addition, the reduction of interactions at the active zone and the porous region allows a substantial reduction in the detector temperature linked to the latter.

[0012] In addition to the characteristics which have just been mentioned in the preceding paragraph, the device according to one aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations.

[0013] In one embodiment, the central portion is made of a wide bandgap semiconductor material, preferably silicon carbide. A wide bandgap is understood to mean a gap whose energy is at least twice the energy of the silicon bandgap.

[0014] In one embodiment, the porous region is formed from a wide band gap semiconductor material.

[0015] In one embodiment, the space charge region is formed using a Schottky diode, a PN diode, or a PIN diode.

[0016] In one embodiment, the space charge region of the core portion is only located in a region of the core portion opposite the porous region.

[0017] In one embodiment, the space charge region of the central portion extends beyond the central portion opposite the porous region.

[0018] In one embodiment, the central portion comprises: a first layer of a semiconductor material; a second layer of a conductive material covering the first layer; the space charge region being formed by the Schottky diode formed by the first layer and the second layer, the porous region being formed in the first layer.

[0019] In one embodiment, the peripheral portion comprises: a third layer of a conductive material; a first layer of a semiconductive material covering the third layer and arranged in continuity with the first layer of the central part; a second layer of a conductive material covering the first layer and arranged in continuity with the second layer of the central part; the third layer of a conductive material ensuring the collection of a first type of charge carriers generated in the charge space region.

[0020] In one embodiment, the central portion comprises: a first layer of a semiconductor material doped in a first doping type; a second layer of a semiconductor material doped in a second doping type opposite to the first doping type, said second layer covering the first layer; a fourth layer of a conductive material, said fourth layer covering the second layer; the space charge region being formed by the PN diode formed by the first layer and the second layer, the porous region being formed in the first layer.

[0021] In one embodiment, the peripheral portion comprises: a third layer of a conductive material; a first layer of a semiconductor material doped in a first type of doping covering the third layer and arranged in continuity with the first layer of the central part; a second layer of a semiconductor material doped in a second type of doping opposite to the first type of doping covering the first layer, said second layer being arranged in continuity with the second layer of the central part; a fourth layer of a conductive material, said fourth layer covering the second layer, said fourth layer being arranged in continuity with the fourth layer of the central part; the third layer of a conductive material ensuring the collection of a first type of charge carriers generated in the space charge zone.

[0022] In one embodiment, the peripheral portion comprises: a third layer of a conductive material; a first layer of a semiconductor material doped in a first doping type covering the third layer and arranged in continuity with the first layer of the central part, the first layer of the central part and of the peripheral part having the same doping level; a sixth layer of a dielectric material (such as an oxide or nitride, undoped glass, etc.) covering the first layer; a fourth layer of a conductive material covering the sixth layer; the fourth layer forming a step between the peripheral portion and the central portion covering a lateral surface of the sixth layer so as to ensure continuity between the fourth layer of the central portion and the fourth layer of the peripheral portion, the third layer of a conductive material ensuring the collection of a first type of charge carriers generated in the charge space area.

[0023] In one embodiment, the central portion comprises: a fifth layer of a semiconductor material doped in a first doping type, at least a portion of the porous region being formed in the fifth layer; a first layer of a semiconductor material doped in a first doping type, said first layer covering the fifth layer, the doping level of the fifth layer being higher than the doping level of the layer; a second layer of a semiconductor material doped in a second doping type opposite to the first doping type, said second layer covering the first layer; a fourth layer of a conductive material, said fourth layer covering the second layer; the space charge region being formed by the PN diode formed by the fifth layer, the first layer and the second layer.

[0024] In one embodiment, the porous region is formed throughout the thickness of the fifth layer.

[0025] In one embodiment, a portion of the porous region is formed in the first layer in continuity with the porous region formed in the fifth layer. In other words, the porous region is formed over the entire thickness of the fifth layer and a portion of the thickness of the first layer.

[0026] In one embodiment, the peripheral portion comprises: a third layer of a conductive material; a fifth layer of a semiconductor material doped in a first doping type covering the third layer and arranged in continuity with the fifth layer of the central part; a first layer of a semiconductor material doped in a first doping type covering the fifth layer and arranged in continuity with the first layer of the central part, the doping level of the fifth layer being higher than the doping level of the first layer; a second layer of a semiconductor material doped in a second doping type opposite to the first doping type covering the first layer, said second layer being arranged in continuity with the second layer of the central part; a fourth layer of a conductive material, said fourth layer covering the second layer, said fourth layer being arranged in continuity with the fourth layer of the central part; the third layer of a conductive material ensuring the collection of a first type of charge carriers generated in the charge space region.

[0027] In one embodiment, the peripheral portion comprises: a third layer of a conductive material; a fifth layer of a semiconductor material doped in a first doping type covering the third layer and arranged in continuity with the fifth layer of the central portion; a first layer of a semiconductor material doped in a first doping type covering the fifth layer and arranged in continuity with the first layer of the central portion, the first layer of the central portion and the peripheral portion having the same doping level, the doping level of the fifth layer being higher than the doping level of the first layer; a sixth layer of a dielectric material covering the first layer; a fourth layer of a conductive material covering the sixth layer; the fourth layer forming a step between the peripheral portion and the central portion covering a lateral surface of the sixth layer so as to ensure continuity between the fourth layer of the central portion and the fourth layer of the peripheral portion, the third layer of a conductive material ensuring the collection of a first type of charge carriers generated in the charge space area.

[0028] A second aspect of the invention relates to a method of manufacturing a detector, from a semiconductor substrate doped in a first type of doping comprising a front face and a back face, the manufacturing method comprising; a step of epitaxy, on the front face of the substrate, of a first layer of an intrinsic semiconductor material; a step of epitaxy, on the front face of the substrate, of a second layer of a semiconductor material doped in a second type of doping opposite to the first type of doping; a step of deposition, on the rear face of the substrate, of a third layer of a conductive material; a step of photolithography of the third layer of a conductive material so as to provide at least a first opening within said layer; a step of etching, at the rear face of the part of the substrate not covered in the third conductive layer so as to form a porous region in the substrate opposite the first opening; a step of deposition, on the front face of the substrate, of a fourth layer of a conductive material.

[0029] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BREVE DESCRIPTION DES FIGURES

[0030] The figures are presented for information purposes only and in no way limit the invention and illustrate: there [ Fig. 1A ] a top view of a device according to an embodiment of the invention [ Fig. 1B ], a sectional view of a device according to one embodiment of the invention; the [ Fig. 2A ] And [ Fig. 2B ], a sectional view of the structure of the device according to two variants of a first embodiment; the [ Fig. 3 ], a sectional view of the structure of the device according to a second embodiment; the [ Fig. 4 ], a sectional view of the structure of the device according to a third embodiment; the [ Fig. 5 ], a sectional view of the structure of the device according to a fourth embodiment; the [ Fig. 6 ], a sectional view of the structure of the device according to a fifth embodiment; the [ Fig. 7 ], a sectional view of the structure of the device according to a sixth embodiment; the [ Fig. 8 ], a sectional view of the structure of the device according to a seventh embodiment; The [ Fig. 9 ], a flowchart of a manufacturing method according to the invention The [ Fig. 10] à [Fig. 15 ], the different stages of the manufacturing process according to the invention. DESCRIPTION DETAILLEE

[0031] The figures are presented for information purposes only and are in no way limiting of the invention. In the following, the porosity rate in percent will refer to the percentage of voids present in the material considered.

[0032] An aspect of the invention illustrated in [ Fig. 1A ] and to the [ Fig. 1B ] relates to a device for measuring a particle beam comprising a front face F and a rear face B.

[0033] The measuring device also comprises a first part, called the central part PC (or particle / electric charge conversion zone), comprising means for forming a space charge zone ZCE intended to be crossed by a particle beam FS to be measured, charge carriers of a first type and a second type being generated by said beam FS when the latter crosses the space charge zone ZCE.

[0034] It also comprises a second part, called the peripheral part PP (or even the electric charge harvesting zone), comprising means for collecting at least one type of charge carrier from among the first type or the second type of charge carriers generated at the space charge zone ZCE.

[0035] In addition, the central part PC has a thickness less than or equal to the thickness of the peripheral part PP, the peripheral part PP surrounding the central part PC such that a particle beam FS can pass through the central part PC without passing through the peripheral part PP. The device according to the invention further comprises, in a region of the central part and opening onto the rear face B, a layer of a porous material forming a porous region PO such that the effective thickness perceived by the beam FS when it passes through the device by passing through the porous region along an axis normal to the front face F is less than the thickness of the central part PC.

[0036] Effective thickness is the thickness perceived by the beam when it passes through the porous medium. In other words, we can say that a porous material has an effective thickness t eff if the attenuation of the beam passing through this material is equivalent to the attenuation obtained with a material of the same nature but not porous with a real thickness t eff . It is important to note that the thickness of a porous material t mp is always greater than its effective thickness t eff , that's to say t mp > t eff .

[0037] Thus, the device according to the invention makes it possible to measure a particle beam FS while minimizing the disturbances caused by the measurement on the output beam FS' while ensuring good mechanical strength of the device. Such a configuration makes it possible in particular to reduce the quantity of radiation absorbed by the device and therefore the number of radiation-matter interactions likely to disturb the measurement or degrade the measuring device. In addition, the use of a porous material makes it possible to obtain an effective thickness less than the thickness actually crossed by the beam, which makes it possible to minimize absorption while maintaining good mechanical strength of the detector. This is particularly advantageous in the case of large detectors.

[0038] The porous region can for example be obtained using a method comprising a step of immersing the semiconductor material in an electrolytic solution based on hydrofluoric acid, then a step of polarizing the semiconductor material so that a potential is present between the two surfaces of the material.

[0039] The crystalline semiconductor material is thus etched so as to obtain a porous region. Indeed, the polarization applied to the semiconductor material causes the formation of a current which allows a reaction with the semiconductor material and the etching of the latter in the form of pores of variable dimensions. In one embodiment, the pores have a diameter between 1 nm and 100 nm. The duration of the etching, the intensity of the current flowing between the electrodes, the concentration of hydrofluoric acid and additives present in the electrolyte are the main parameters determining the size of the pores, the porosity (in other words, the density of the material) and the depth of the porous region. Generally speaking, at a constant concentration of hydrofluoric acid, an increase in the electrical intensity results in an increase in the porosity and an increase in the duration, by greater porous thicknesses.Thus, such a method of forming a porous material allows good control over the porosity of the material, the latter generally being between 10% and 95%.

[0040] In one embodiment, the polarization of the wafer is provided by electrodes located on the face of the wafer on which the porous portion is to be formed. In an alternative embodiment, the polarization of the wafer is provided by electrodes located on the face opposite the face of the wafer on which the porous portion is to be formed.

[0041] It is interesting to note that, in the particular case of silicon carbide, the two faces of the wafer have different properties (carbon face and silicon face). For identical etching conditions, the pore morphologies obtained are then completely different depending on the face of the etched wafer.

[0042] For more details, the reader can refer to Julie LASCAUD's thesis entitled "Development of attenuating thin layers in porous silicon: Application to micro-machined capacitive ultrasonic transducers" and defended in 2017, and in particular to chapter 4.3 relating to the configuration of electrochemical cells or G. Gautier, J. Biscarrat, D. Valente, A. Gary and F. Cayrel, Systematic study of anodic etching of highly doped n-type 4H SiC in various HF based electrolytes, J. of Electrochemical society, vol. 160, No 9, pp. D372-D379, 2013 or G. Gautier, M. Capelle, F. Cayrel, J. Billoué, P. Poveda, X. Song and JF. Michaud, Room light anodic etching of highly doped n-type 4 H-SiC in high-concentration HF electrolytes: Difference between C and Si crystalline faces, Nanoscale Research Lett., vol. 7, pp. 367-373, 2012.

[0043] In one embodiment, the porous region PO may be of circular, rectangular or even square cross-section. More generally, it may take the form of any polygon. The size of this region is determined by the size of the beam to be measured. Preferably, the width of the beam is less than the width of the porous region. The width of the central region may therefore vary from one micron to around ten centimeters. Preferably, the entire central portion PC is opposite the porous region PO. In other words, the dimensions of the central portion PC are equal to that of the cross-section of the porous region PO.

[0044] Preferably, the central portion PC is centered relative to the entire device. The central portion PC, the porous region PO and / or the peripheral portion PP of the component may be made, at least in part, of a wide-gap semiconductor material, for example silicon carbide, or a semiconductor alloy composed of elements from column III-V or II-VI. For example, when the semiconductor is silicon carbide, the p-doping may be by implantation of boron or aluminum atoms and the n-doping by implantation of nitrogen atoms.

[0045] Preferably, the space charge zone ZCE of the PC core portion is only located in a region of the PC core portion facing the porous region. Alternatively, the space charge zone ZCE of the PC core portion extends beyond the PC core portion facing the porous region.

[0046] In a first embodiment illustrated in the figure 2A , the central part PC comprises a first layer 1 of a semiconductor material; and a second layer 2 of a conductive material covering the first layer 1. In this embodiment, the space charge region ZCE is formed by the Schottky diode formed by the first layer 1 and the second layer 2, the porous part being formed in the first layer 1.

[0047] Preferably, the porous region is between 1 and 1000 µm. Preferably, the diameter of the porous region is between 1 µm and 30 cm.

[0048] In one embodiment illustrated in figure 2B , the thickness of the central part PC is less than the thickness of the peripheral part PP, thus revealing an orifice on the rear face B at the level of the porous region PO. In one embodiment, in order to obtain such a structure, the fabrication of the porous region is carried out in two phases: during a first phase a very high current is applied during the anodization so as to carry out erosion (in other words, all the material is removed); during a second phase, the current is reduced so as to obtain the porous region as described previously. Thus, it is possible to modulate the thicknesses of void and porous material in the central part PC of the device. It is useful to note that this configuration is also compatible with the embodiments which will be described below.In other words, whatever the embodiment, the measuring device according to the invention may comprise an orifice at the level of porous region PO on the rear face B.

[0049] Preferably, in this embodiment, the peripheral part PP comprises a third layer 3' of a conductive material; a first layer 1' of a semiconductive material covering the third layer 3' and arranged in continuity with the first layer 1 of the central part PC; and a second layer 2' of a conductive material covering the first layer 1 and arranged in continuity with the second layer 2 of the central part PC.

[0050] In this configuration, called Schottky configuration, the space charge zone ZCE is formed by the Schottky diode consisting of the first layer 1 of a conductive material and the second layer 2 of a semiconductor material. The space charge zone ZCE is therefore located on the central part PC but also on the peripheral part PP. In addition, the third layer 3' of a conductive material ensures the collection of a first type of charge carriers generated in the space charge zone ZCE while the first layer 2,2' made of a conductive material ensures the collection of a second type of charge carriers generated in the space charge zone ZCE. The second layer 2,2' and the third layer 3,3' can be made of a metal such as copper, zinc or gold or even of single or multilayer graphene. Nickel, aluminum, titanium or tungsten can also be used.More generally, any conductive material suitable for the manufacturing or operating conditions of the device may be chosen. The material used for the second layer 2,2' may be different from the material used for the third layer 3,3'. Preferably, the materials used for the third layer 3' may be chosen so as to obtain an ohmic contact between the third layer 3' and the first layer 1' of the peripheral part PP.

[0051] Preferably, the doping level of the first layer 1 of the central PC part is identical to the doping level of the first layer 1' of the peripheral part. The manufacturing process is thus facilitated because it only requires a single doping level.

[0052] Alternatively, the doping level of the first layer 1 of the central part PC is lower than the doping level of the first layer 1' of the peripheral part PP. This configuration ensures a better distribution of the electric field and therefore allows the use of higher voltages for the polarization of the detector.

[0053] In an exemplary embodiment, the first layer 1, 1' has a thickness of between 500 nm and 50 microns. In one embodiment, the second layer 2, 2' has a thickness of between 10 nm and 200 nm, preferably substantially equal to 100 nm.

[0054] In a second embodiment of a device according to the invention illustrated in figure 3 , the central part PC comprises a first layer 1 of a semiconductor material doped in a first doping type; a second layer 2 of a semiconductor material doped in a second doping type opposite to the first doping type, said second layer 2 covering the first layer 1; and a fourth layer 4 of a conductive material, said fourth layer 4 covering the second layer 2. In this embodiment, the space charge region ZCE is formed by the PN diode formed by the first layer 1 and the second layer 2, the porous region being formed in the first layer 1.

[0055] Preferably, in this embodiment, the peripheral part PP comprises a third layer 3' of a conductive material; a first layer 1' of a semiconductor material doped in a first doping type covering the third layer 3' and arranged in continuity with the first layer 1 of the central part PC; a second layer 2' of a semiconductor material doped in a second doping type opposite to the first doping type covering the first layer 1', said second layer 2' being arranged in continuity with the second layer 2 of the central part PC; and a fourth layer 4' of a conductive material, said fourth layer 4' covering the second layer 2', said fourth layer 4' being arranged in continuity with the fourth layer 4 of the part PC. In one embodiment, the doping of the first layer 1,1' is n-type and the doping of the second layer 2,2' is p-type.

[0056] In this configuration, called PN configuration, the space charge zone ZCE is formed by the PN diode consisting of the first layer 1,1' of a semiconductor material doped in a first type of doping and the second layer 2,2' of a semiconductor material doped in a second type of doping opposite to the first type of doping. The space charge zone ZCE is therefore located on the central part PC but also on the peripheral part PP. In addition, the third layer 3' of the peripheral part ensures the collection of a first type of charge carriers generated in the space charge zone ZCE while the fourth layer 4,4', made of a conductive material, ensures the collection of a second type of charge carriers generated in the space charge zone ZCE. The third layer 3' and the fourth layer 4,4' can be made of a metal such as copper, zinc or gold or even of single or multi-layer graphene.Nickel, aluminum, titanium, or tungsten may also be used. More generally, any conductive material suitable for the manufacturing or operating conditions of the device may be chosen. The material used for the third layer 3' may be different from the material used for the fourth layer 4,4'. Preferably, the materials used for the third layer 3' may be chosen so as to obtain ohmic contact between the third layer 3' and the first layer 1' of the peripheral part PP. Similarly, the materials used for the fourth layer 4,4' may be chosen so as to obtain ohmic contact between the fourth layer 4,4' and the second layer 2,2'.

[0057] Preferably, the doping level of the first layer 1 of the central portion PC is identical to the doping level of the first layer 1' of the peripheral portion PP. Similarly, the doping level of the second layer 2 of the central portion PC is identical to the doping level of the second layer 2' of the peripheral portion. As explained previously, the manufacturing process is made easier because it only requires a single doping level.

[0058] In an exemplary embodiment, the doping of the first layer 1,1' is of n type and the doping of the second layer 2,2' is of p type. The doping level of the first layer 1,1' is between 5.10 14< and 5.10 19< atoms per cm3, preferably substantially equal to 5.10 15< atoms per cm3. The doping level of the second layer 2,2' is between 1.10 16< and 5.10 19< atoms per cm3, preferably substantially equal to 1.10 19< atoms per cm3.

[0059] Alternatively, the doping level of the first layer 1 of the central PC part is lower than the doping level of the first layer 1' of the peripheral part. Similarly, the doping level of the second layer 2 of the central PC part is lower than the doping level of the second layer 2' of the peripheral part. As explained previously, this configuration ensures a better distribution of the electric field, which allows the use of higher voltages for the polarization of the detector.

[0060] In a third embodiment illustrated in the figure 4 , the central part PC comprises a fifth layer 5 of a semiconductor material doped in a first doping type, at least a part of the porous region PO being formed in the fifth layer 5; a first layer 1 of a semiconductor material doped in a first doping type on the fifth layer of a semiconductor material, the doping level of the fifth layer 5 in the central part PC being higher than the doping level of the layer 1 of the central part; a second layer 2 of a semiconductor material doped in a second doping type opposite to the first doping type, said second layer 2 covering the first layer 1; and a fourth layer 4 of a conductive material, said fourth layer 4 covering the second layer 2.

[0061] In this embodiment, the peripheral part PP then comprises, in addition to the layers already described, a fifth layer 5' of a semiconductor material doped in a first type of doping arranged in continuity with the fifth layer 5 of the central part PC, the doping level of the fifth layer 5' of the peripheral part PP being higher than the doping level of the first layer 1' of the peripheral part PP, the fifth layer 5' being located between the third layer 3' and the first layer 1' of the peripheral part PP.

[0062] Thus in this configuration called PIN configuration, the PIN diode formed between the fifth layer 5.5', the first layer 1.1' and the first layer 2.2' allows better recovery of the charges generated in the central part PC by the beam FS of particles to be detected.

[0063] In one embodiment, the porous region PO is formed over the entire thickness of the fifth layer 5 of the central portion PC. In one embodiment, a portion of the porous region PO is formed in the first layer 1 in continuity with the porous region PO formed in the fifth layer 5. In other words, the porous region PO is formed over the entire thickness of the fifth layer 5 and a portion of the thickness of the first layer 1.

[0064] The fifth layer 5' of the peripheral part PP can for example be obtained from a layer covering the central part PC and the peripheral part, and in which a porous region has been formed over only part of the thickness leaving a layer at the peripheral part corresponding to the fifth layer 5' of the peripheral part PP and a layer 5 in the central part PC of low thickness so as to ensure the collection of the charges.

[0065] Preferably, the doping of the first layer 1,1' and the fifth layer 5' of the peripheral part PP is of n type and the doping of the second layer 2,2' is of p type. The doping level of the fifth layer 5' is between 1.10 16< and 1.10 19< atoms per cm 3< , preferably substantially equal to 1.10 18< atoms per cm3. The doping level of the first layer 1,1' is between 1.10 11< and 1.10 17< atoms per cm 3< , preferably substantially equal to 5.10 15< atoms per cm 3< . The doping level of the second layer 2,2' is between 1.10 16< and 5.10 19< atoms per cm 3< , preferably substantially equal to 1.10 19< atoms per cm3.

[0066] In an exemplary embodiment, the first layer 1,1' has a thickness of between 500 nm and 50 microns; the second layer 2,2' has a thickness of between 50 and 200 nm, preferably substantially equal to 100 nm; and the fifth layer has a thickness of between 250 and 350 microns, preferably substantially equal to 300 microns.

[0067] Since the beam to be measured only passes through the detector at the central part PC, it may be advantageous to move all the electrodes necessary for the recovery of the charge carriers to the peripheral part. For this, in a fourth embodiment illustrated in figure 5 , the central part PC comprises a first layer 1 of a semiconductor material doped in a first type of doping and a second layer 2 of a semiconductor material doped in a second type of doping opposite to the first type of doping, said second layer 2 covering the first layer 1. The central part is therefore devoid of electrode in this embodiment. In this embodiment, the space charge zone is also produced by the PN diode consisting of the first layer 1,1' of a semiconductor material doped in a first type of doping and the second layer 2,2' of a semiconductor material doped in a second type of doping opposite to the first type of doping. On the other hand, the charge carriers are recovered only at the peripheral part by the third layer 3' and fourth layer 4' of the peripheral part PP.In this configuration, the beam only passes through the first layer 1 and the second layer 2 of the central part at which the charge space zone is formed. In this embodiment, the fourth layer 4' is only on the peripheral part and therefore forms an orifice O1.

[0068] In the previous embodiment, the space charge zone ZCE is present in both the central part PC and the peripheral part PP of the device. However, it may be advantageous to have a space charge zone ZCE only in the central part PC of the detection device. For this, in a fifth embodiment illustrated in figure 6 , the peripheral part PP comprises a third layer 3' of a conductive material; a first layer 1' of a semiconductor material doped in a first type of doping covering the third layer 3' and arranged in continuity with the first layer 1 of the central part PC; a sixth layer 6' of a dielectric material covering the first layer 1'; and a fourth layer 4' of a conductive material covering the sixth layer 6'. Thus, the second layer 2,2' being present only in the central part PC of the device, the space charge zone ZCE is also restricted to the central part PC of the device.

[0069] In this embodiment, the fourth layer 4, 4' forms a step between the peripheral part PP and the central part PC covering a lateral surface of the sixth layer 6' so as to ensure continuity between the fourth layer 4 of the central part PC and the fourth layer 4' of the peripheral part PP. In this embodiment, the sixth layer 6' is only on the peripheral part and therefore forms an orifice O1.

[0070] However, in the previous embodiment, the fourth layer 4' of the central part PC covers the entire central part PC through which the beam to be measured passes. It may be advantageous in certain situations to reduce this absorption phenomenon. To this end, in a sixth embodiment illustrated in figure 7 , the fourth layer 4' of the central part only covers a part of the central part PC.

[0071] Furthermore, when the extent of the second layer 2,2' is limited to the central part PC, the MIS (Metal Insulating Semiconductor) structure formed at the peripheral part PP of the device formed by the first layer of the peripheral part 1', the sixth layer of the peripheral part 6' and by the fourth layer 4' of the peripheral part can disturb the measurement by inducing in particular capacitive effects. In order to prevent this phenomenon, in a seventh embodiment illustrated in figure 8 , the second layer 2' of the peripheral part only partially covers the first layer 1' of the peripheral part while ensuring continuity with the second layer 2 of the central part PC. In other words, the second layer 2,2' is present in the entire central part PC of the device as well as in an area of ​​the peripheral part PP. The presence of the second layer 2' over a larger area than the central part PC limits the formation of the MIS structure previously mentioned. This reduces the capacitive phenomena between the first layer of the peripheral part 1', the sixth layer of the peripheral part 6' and the fourth layer 4' of the peripheral part.

[0072] In order to obtain a device according to a first aspect of the invention, a second aspect of the invention illustrated in [ Fig. 9] à [Fig. 15 ] relates to a P100 manufacturing process. As illustrated in [ Fig. 10 ], this manufacturing is done from a substrate C5 having a doping of a first type, for example the n type. The substrate is intended to form the fifth layer 5,5' of the central part PC and of the peripheral part PP of the device according to a first aspect of the invention. Preferably, the substrate C5 is a substrate of SiC-4H type doped with n type, the doping level preferably being between 5.10 17< and 5.10 18< at.cm -3< , for example equal to 10 18< at.cm -3< . Preferably, this doping is a doping of nitrogen atoms.

[0073] As illustrated in [ Fig. 11 ], the method P100 according to a second aspect of the invention comprises a step PE1 of epitaxy, on the front face of the substrate C5, of a first layer C1 of an intrinsic semiconductor material. In other words, no doping step is carried out on this layer C1. This first layer C1 is intended to form the first layer 1,1' of the central part PC and of the peripheral part PP of the device.

[0074] As illustrated in [ Fig. 12 ], the method P100 then comprises a step PE2 of epitaxy, on the front face of the substrate C5, of a second layer C2 of a semiconductor material doped in a second type of doping opposite to the first type of doping, for example a p-type doping. Preferably, the doping of the second layer C2 is between 5.10 17< and 5.10 18< at.cm -3< , for example equal to 10 18< at.cm -3< . Preferably, this doping is a doping of aluminum atoms. This second layer C2 is intended to form the second layer 2,2' of the central part PC and of the peripheral part PP of the device.

[0075] The method P100 then comprises a step PE3 of depositing, on the rear face of the substrate C5, a third layer C3 of a conductive material, for example a layer of titanium or aluminum. This third layer C3 is intended to form the third layer 3' of the peripheral part of the device. The method also comprises a step PE4 of photolithography of the third layer C3 of a conductive material so as to provide at least a first opening within said layer C3. The structure obtained at the end of these two steps PE3, PE4 is illustrated in [ Fig. 13 ].

[0076] As illustrated in [ Fig. 14 ], the P100 method also comprises an etching step PE5, at the rear face of the part of the substrate C5 not covered in the third conductive layer C3 so as to form a porous region PO in the substrate C5 opposite the first opening.

[0077] In one embodiment, the substrate C5 is a SiC substrate. In this embodiment, the etching step PE5 is carried out using a solution based on hydrofluoric acid and ethanol having a concentration of between 5 and 30% by volume (in other words, the volume ratio between the hydrofluoric acid and the ethanol varies between 5 and 30% by total volume of the solution). In one embodiment, the etching step PE5 is carried out by applying an electrolysis current whose current density is between 10 mA / cm 2< to 80 mA / cm 2< for a duration of approximately 15 to 120 minutes. In one embodiment, the current density is adjusted during etching so as to obtain a porous region PO having a variable degree of porosity depending on the depth of the porous region PO.For any additional details relating to this PE5 etching step, the reader can refer to Julie LASCAUD's thesis entitled "Development of thin attenuating layers in porous silicon: Application to micro-machined capacitive ultrasonic transducers" already cited.

[0078] As illustrated in [ Fig. 15 ], the P100 method comprises a step PE6 of depositing, on the front face of the substrate C5, a fourth layer C4 of a conductive material, for example a layer of titanium or aluminum. This fourth layer C4 is intended to form the fourth layer 4,4' of the central part PC and the peripheral part PP of the device.

[0079] In one embodiment, the deposition step PE6 is preceded by a step of depositing a passivation layer on the front face of the substrate C5 and a lithography step so as to define the region(s) in which the fourth layer C4 of a conductive material will be deposited. This passivation layer is intended to form the sixth layer 6' of the peripheral part of the device, the region(s) opened during the lithography step then corresponding to the peripheral part PP of the device. In one embodiment, the passivation layer is obtained by the deposition of an oxide.

Claims

1. A device for measuring a particle beam comprising a front face (F) and a rear face (B) as well as: - a first part, referred to as the central part (PC), including means for forming a space charge zone (ZCE) for a particle beam (FS) to be measured to pass therethrough, charge carriers of a first type and of a second type being generated by said beam (FS) when the same passes through the space charge zone (ZCE); - a second part, referred to as the peripheral part (PP), including means for collecting at least one type of charge carrier among the first type or the second type of charge carriers generated at the space charge zone (ZCE); the central part (PC) having a thickness less than or equal to the thickness of the peripheral part (PP), the peripheral part (PP) surrounding the central part (PC) so that a particle beam (FS) can pass through the central part (PC) without passing through the peripheral part (PP), the device being characterised in that it includes, in a region of the central part and opening onto the rear face (B), a layer of a porous material forming a porous region (PO) so that the effective thickness perceived by the beam when it passes through the device at the central part (PC) by passing through the porous region along an axis normal to the front face (F) is less than the thickness of the central part (PC), the space charge zone (ZCE) being situated outside the porous region.

2. The measurement device according to the preceding claim, characterised in that the central part (PC) is made of a wide band gap semiconductor material.

3. The measurement device according to the preceding claim, characterised in that the semiconductor is silicon carbide.

4. The measurement device according to any of the preceding claims, characterised in that the space charge zone (ZCE) is formed by means of a Schottky diode, a PN diode or a PIN diode.

5. The measurement device according to any of the preceding claims, characterised in that the space charge zone (ZCE) of the central part (PC) is only located in a region of the central part (PC) facing the porous region (PO).

6. The measurement device according to any of claims 1 to 4, characterised in that the space charge zone (ZCE) of the central part (PC) extends beyond the central part (PC) facing the porous region (PO).

7. The measurement device according to any of claims 1 to 4, characterised in that the central part (PC) comprises: - a first layer (1) of a semiconductor material; - a second layer (2) of a conductive material covering the first layer (1); the space charge zone (ZCE) being formed by the Schottky diode formed by the first layer (1) and the second layer (2), the porous region (PO) being formed in the first layer (1).

8. The measurement device according to the preceding claim, characterised in that the peripheral part (PP) comprises: - a third layer (3') of a conductive material; - a first layer (1') of a semiconductor material covering the third layer (3') and disposed in continuity with the first layer (1) of the central part (PC); and - a second layer (2') of a conductive material covering the first layer (1) and disposed in continuity with the second layer (2) of the central part (PC); the third layer (3') of a conductive material ensuring collection of a first type of charge carriers generated in the charge space zone (ZCE).

9. The measurement device according to claim 5, characterised in that the central part (PC) comprises: - a first layer (1) of a semiconductor material doped with a first doping type; - a second layer (2) of a semiconductor material doped with a second doping type opposite to the first doping type, said second layer (2) covering the first layer (1); - a fourth layer (4) of a conductive material, said fourth layer (4) covering the second layer (2); the space charge zone (ZCE) being formed by the PN diode formed by the first layer (1) and the second layer (2), the porous region (PO) being formed in the first layer (1).

10. The measurement device according to the preceding claim, characterised in that the peripheral part (PP) comprises: - a third layer (3') of a conductive material; - a first layer (1') of a semiconductor material doped with a first doping type covering the third layer (3') and disposed in continuity with the first layer (1) of the central part (PC); and - a second layer (2') of a semiconductor material doped with a second doping type opposite to the first doping type covering the first layer (1'), said second layer (2') being disposed in continuity with the second layer (2) of the central part (PC); - a fourth layer (4') of a conductive material, said fourth layer (4') covering the second layer (2'), said fourth layer (4') being disposed in continuity with the fourth layer (4) of the central part (PC); the third layer (3') of a conductive material ensuring collection of a first type of charge carriers generated in the charge space zone (ZCE).

11. The measurement device according to claim 9, characterised in that the peripheral part (PP) comprises: - a third layer (3') of a conductive material; - a first layer (1') of a semiconductor material doped with a first doping type covering the third layer (3') and disposed in continuity with the first layer (1) of the central part (PC), the first layer (1) of the central part (PC) and of the peripheral part (PP) having the same doping level; - a sixth layer (6) of a dielectric material covering the first layer (1); - a fourth layer (4') of a conductive material covering the sixth layer (6); the fourth layer (4, 4') forming a step between the peripheral part (PP) and the central part (PC) covering a side surface of the sixth layer (6') so as to ensure continuity between the fourth layer (4) of the central part (PC) and the fourth layer (4') of the peripheral part (PP), the third layer (3') of a conductive material ensuring collection of a first type of charge carriers generated in the charge space zone (ZCE).

12. The device according to claim 5, characterised in that the central part (PC) comprises: - a fifth layer (5) of a semiconductor material doped with a first doping type, at least part of the porous region (PO) being formed in the fifth layer (5); - a first layer (1) of a semiconductor material doped with a first doping type, said first layer (1) covering the fifth layer (5), the doping level of the fifth layer (5) being higher than the doping level of the layer (1); - a second layer (2) of a semiconductor material doped with a second doping type opposite to the first doping type, said second layer (2) covering the first layer (1); - a fourth layer (4) of a conductive material, said fourth layer (4) covering the second layer (2); the space charge zone (ZCE) being formed by the PIN diode formed by the fifth layer (5), the first layer (1) and the second layer (2).

13. The device according to the preceding claim, characterised in that the peripheral part (PP) comprises: - a third layer (3') of a conductive material; - a fifth layer (5') of a semiconductor material doped with a first doping type covering the third layer (3') and disposed in continuity with the fifth layer (5) of the central part (PC); - a first layer (1') of a semiconductor material doped with a first doping type covering the fifth layer (5') and disposed in continuity with the first layer (1) of the central part (PC), the doping level of the fifth layer (5') being higher than the doping level of the first layer (1'); - a second layer (2') of a semiconductor material doped with a second doping type opposite to the first doping type covering the first layer (1'), said second layer (2') being disposed in continuity with the second layer (2) of the central part (PC); - a fourth layer (4') of a conductive material, said fourth layer (4') covering the second layer (2'), said fourth layer (4') being disposed in continuity with the fourth layer (4) of the central part (PC); the third layer (3') of a conductive material ensuring collection of a first type of charge carriers generated in the charge space zone (ZCE).

14. The device according to claim 12, characterised in that the peripheral part (PP) includes: - a third layer (3') of a conductive material; - a fifth layer (5') of a semiconductor material doped with a first doping type covering the third layer (3') and disposed in continuity with the fifth layer (5) of the central part (PC); - a first layer (1') of a semiconductor material doped with a first doping type covering the fifth layer (3') and disposed in continuity with the first layer (1) of the central part (PC), the first layer (1) of the central part (PC) and the peripheral part (PP) having the same doping level, the doping level of the fifth layer (5') being higher than the doping level of the first layer (1'); - a sixth layer (6) of a dielectric material covering the first layer (1); - a fourth layer (4') of a conductive material covering the sixth layer (6); the fourth layer (4, 4') forming a step between the peripheral part (PP) and the central part (PC) covering a side surface of the sixth layer (6') so as to ensure continuity between the fourth layer (4) of the central part (PC) and the fourth layer (4') of the peripheral part (PP), the third layer (3') of a conductive material providing collection of a first type of charge carriers generated in the charge space zone (ZCE).

15. A Method (P100) for manufacturing a detector according to one of the preceding claims, from a semiconductor substrate (C5) doped with a first doping type comprising a front face and a rear face, the manufacturing method (P100) comprising: - a step (PE1) of epitaxially growing, on the front face of the substrate (C5), a first layer (C1) of an intrinsic semiconductor material; - a step (PE2) of epitaxially growing, on the front face of the substrate (C5), a second layer (C2) of a semiconductor material doped with a second doping type opposite to the first doping type; - a step (PE3) of depositing, onto the rear face of the substrate, a third layer (C3) of a conductive material; - a step (PE4) of performing photolithography on the third layer (C3) of a conductive material so as to provide at least one first opening within said layer (C3); and - an etching step (PE5), at the rear face of the part of the substrate (C5) not covered in the third conductive layer (C3) so as to form a porous region (PO) in the substrate (C5) facing the first opening; - a step (PE6) of depositing, onto the front face of the substrate (C5), a fourth layer (C4) of a conductive material.