STRUCTURES WITH SUBSTANT PASSAGES

Description

BACKGROUNDField

[0001] The field relates to structures with through-substrate vias and methods for forming the same.Description of the Related Art

[0002] Semiconductor elements, such as integrated device dies or chips, may be mounted or stacked on other elements. For example, a semiconductor element can be mounted to a carrier, such as a package substrate, an interposer, a reconstituted wafer or element, etc. As another example, a semiconductor element can be stacked on top of another semiconductor element, e.g., a first integrated device die can be stacked on a second integrated device die. In some arrangements, a through-substrate via (TSV) can extend vertically through a thickness of the semiconductor element to transfer electrical signals through the semiconductor element, e.g., from a first surface of the semiconductor element to a second opposing surface of the semiconductor element. There is a continuing need for improved methods of forming TSVs. US2016 / 049371 discloses a 3D interconnect structure in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs). A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during a process flow. US2014 / 191414 discloses a semiconductor device comprising: a substrate including a first surface and a second surface that face each other, a planarization layer formed on the first surface of the substrate, a passivation layer formed on the planarization layer, and a through via contact penetrating the substrate, the planarization layer, and the passivation layer, and being exposed from the passivation layer. US2015 / 262839 discloses a method of forming a pattern, including: forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern. US2012 / 133010 discloses a semiconductor device including: a through-hole formed in a semiconductor layer; a through-hole insulting layer formed on a sidewall of the through-hole to retract from a front surface of the semiconductor layer; a through-electrode embedded in the through-hole via the through-hole insulating layer; and a sidewall insulating film formed on a sidewall of the through-electrode to be embedded in a retracting section of the through-hole insulating layer. US2019 / 096842 discloses a method including: depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.SUMMARY

[0003] According to an aspect of the present disclosure, there is provided a microelectronic structure according to claim 1. Further features of the microelectronic structure according to embodiments of the present disclosure are provided in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation. Figure 1A illustrates a step in a process for forming a through-substrate via in a microelectronic structure. Figure 1B illustrates another step in the process for forming the through-substrate via in the microelectronic structure. Figure 1C illustrates another step in the process for forming the through-substrate via in the microelectronic structure. Figure 1D illustrates another step in the process for forming the through-substrate via in the microelectronic structure. Figure 1E illustrates another step in the process for forming the through-substrate via in the microelectronic structure. Figure 1F illustrates another step in the process for forming the through-substrate via in the microelectronic structure. Figure 2 shows heights of vias formed at different locations of a 12 inch wafer. Figure 3 is a wafer distribution map after TSV reveal for an 8 inch wafer showing vias with lengths that are too long and vias with lengths that are too short. Figure 4 is a distribution map showing thickness variations on an 8 inch wafer after TSV planarization. Figure 5 is a schematic cross sectional side view of a structure having surface non-uniformity. Figure 6 is a schematic cross sectional side view of a microelectronic structure, according to an embodiment. Figure 7A illustrates a step in a method for forming a microelectronic structure, according to an embodiment. Figure 7B illustrates another step in the method for forming the microelectronic structure. Figure 7C illustrates another step in the method for forming the microelectronic structure. Figure 7D illustrates another step in the method for forming the microelectronic structure. Figure 7E illustrates another step in the method for forming the microelectronic structure. Figure 7F illustrates another step in the method for forming the microelectronic structure. Figure 7G illustrates the microelectronic structure bonded to a carrier. Figure 7H illustrates the microelectronic structure bonded to the carrier after a removal process. Figure 7I illustrates the microelectronic structure bonded to the carrier after another removal process. Figure 7J illustrates the microelectronic structure bonded to a wafer. Figure 7K illustrates the microelectronic structure bonded to the wafer after removal of the carrier. Figure 7L illustrates singulated elements mounted to another element. Figure 8A is a cross sectional view of a via structure. Figure 8B is a cross sectional view of a via structure, according to an embodiment. DETAILED DESCRIPTION

[0005] Figures 1A to 1F illustrates various conventional processing steps for forming TSVs in a microelectronic structure 1. In Figures 1A to 1F, the microelectronic structure comprises a portion of a semiconductor wafer (a bulk semiconductor portion 12). The illustrated via structures comprise via-middle structures, in which active circuitry 10 (e.g., transistors or other active circuit elements) can be formed on or in an active surface 12a of a bulk semiconductor portion 12, one or more insulating layers 14 can be formed over the active circuitry 10, and an opening 16 for a through-substrate via (TSV) can be formed through the one or more insulating layers 14 and a portion of the bulk semiconductor portion 12 (see Figure 1A). A via structure 18 can be provided in the opening 16 as shown in Figures 1B and 1C. Conductive overburden from electroplating the via structure 108 in Figure 1B can be removed (e.g., polished away) in Figure 1C. As shown in Figure 1D, a conductive pad 20 can be provided over the one or more insulating layers 14 and electrically connected to the via structure 18. The conductive pad 20 can be configured to electrically connect to another element. For example, the conductive pad 20 can be a front side interconnect contact (FIC) or a front side redistribution layer (FRDL). Contact pads 20 of the microelectronic structure 1 (a first element) can be directly bonded to contact pads of a second element. As shown in Figure 1B, in some arrangements, a metallization layer 22 (e.g., a back-end-of line (BEOL) or redistribution layer (RDL)) can be provided over or within the one or more insulating layer(s) 14. The metallization layers 22 can be connected by conductive interconnects 24. As explained herein, in various embodiments, the microelectronic structure 1 (e.g., the first element) can be directly bonded to the second element without an intervening adhesive. An insulating bonding layer of the first element can be directly bonded to an insulating bonding layer of the second element. Any suitable number of elements can be stacked and directly bonded to one another.

[0006] As shown in Figures 1E and 1F, a frontside of the microelectronic structure 1 can be attached to a carrier 26 by way of an adhesive 28. The carrier 26 can comprise a temporary handle wafer that is used to support the microelectronic structure 1 during processing, such as back grinding. The adhesive 28 can comprise an organic adhesive in some embodiments, and can be sensitive to high temperatures. Accordingly, the use of the adhesive 28 to attach the carrier 26 to the microelectronic structure 1 may limit the temperatures that can be applied during processing. In other embodiments, however, the carrier 26 can be directly bonded to the frontside of the microelectronic structure 1 without an adhesive 28. While the frontside (e.g., a second surface) is attached to the carrier 26, the backside (e.g., a first surface) of the semiconductor portion 12 can be grinded down to expose the via structure 18. As shown in Figure 1F, a dielectric layer 29 may be deposited on the back side surface of the semiconductor portion 12. A backside metallization layer 31, for instance, a redistribution layer (RDL), can be provided over the dielectric layer 29 and can be configured to electrically connect to the via structure 18.

[0007] The conventional via formation process has several problems that lead to non-uniform via lengths. For example, the etch process used to form the openings for the vias is non-uniform across the substrate (e.g., wafer), particularly for the high aspect ratio openings used for vias, which leads to via openings having different depths. Indeed, as shown in Figure 2, for a 12 inch wafer, the etch process that is used to form the via openings can have a non-uniformity of approximately 7 microns. In some areas of the wafer, the etch depth will be higher, while some areas of the wafer with have low etch depths, other areas of the wafer will have etch depths between the low and high etch depts. The varying depth of the etched via openings accordingly leads to different via structure lengths once the conductive material (e.g., copper) is filled into the openings. The selectively etched TSV cavities can be lined with a dielectric layer, the surface of the dielectric liner can be coated with a suitable barrier or adhesion layer prior to filling the cavity with the conductive layer, e.g., copper.

[0008] Figure 3 is a wafer distribution map after TSV reveal for an 8 inch wafer showing vias with lengths that are too long and vias with lengths that are too short. A too long via is a via with a length that is more than a desired or predetermined length range, and a too short via is a via with a length that is less than optimized desired or predetermined length range. Figure 4 is a distribution map showing thickness variation (4 µm variation) on an 8 inch wafer after TSV planarization. As shown in Figures 3 and 4, the different via lengths can lead to a significant loss in yield. For instance, dies that have TSVs that are too short to be fully revealed or effective, and dies that have TSVs that are too long to fracture during TSV planarization or cannot be used. For example, some dies within the wafer may have TSVs that are too short to be effectively used in the die. Other vias are too long or break off during grinding or polishing, leaving the vias buried in the semiconductor portion of the device, making it relatively difficult to forming a backside interconnection to a pad or RDL. Additionally, in some processes, non-uniform TSVs may result from incomplete or non-uniform plating procedures. For example, in such processes, the via openings may be etched uniformly, but the plating process through the high aspect ratio openings may not uniformly fill the via openings. This process variation reduces the number of dies that are effective. Accordingly, non-uniform TSV lengths may result from a variety of different processing methods.

[0009] Figure 4 illustrates the thickness variation on an 8" wafer that can be measured after TSV planarization. As can be seen, the thickness of the wafer can vary by 4 microns. Some regions of the wafer can have a thickness of up to 58.09 microns, while other regions of the wafer can have a thickness of 56.09 microns, while other regions of the wafer can have lower thicknesses around 54.67 microns. Wafer thickness variation can also cause some TSVs to be rendered ineffective and lead to lower levels of process control.

[0010] As explained above, due to, e.g., die thickness non-uniformity and TSV opening etch non-uniformity, the lengths of the TSVs may vary considerably across the wafer after grinding the backside of the semiconductor portion to reveal the TSVs. Accordingly, as the backside of the bulk semiconductor portion is grinded or otherwise thinned, the exposed vias may protrude from the backside of the thinned semiconductor portion by varying lengths (and some vias, as explained above, may remain unexposed and buried in the semiconductor portion). To reduce the non-uniform lengths of the TSVs while preventing breakage of the protruding TSVs, one or more backside dielectric layers can be provided over the backside of the semiconductor portion and over the TSVs. While it may be possible to employ solder bumping despite some degree of TSV height (protrusion from the backside) variability, the variability leads to a lack of levelness and makes stacking difficult. Some stacking technologies (such as direct hybrid bonding) are especially sensitive to topographical variations.

[0011] In conventional TSV processing of the type shown in Figures 1A-1F, one or more backside dielectric layers 29 can be provided over the backside of the semiconductor portion 12 and over the revealed TSVs. For example, in some processes, a barrier layer (e.g., a dielectric barrier layer, such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, etc.) can be deposited over the backside of the semiconductor portion 12, over a sidewall of the exposed TSVs, and over the exposed end surfaces of the exposed TSVs. A second dielectric layer (such as silicon oxide or any other suitable dielectric) can be deposited over the dielectric barrier layer, including over the upper surface of the barrier layer, over the portion of the barrier layer that extends along the sidewall of the exposed TSVs, and over the portion of the barrier layer that is disposed along the end surface of the exposed TSVs. After depositing the backside dielectric layer(s), the vias and portion(s) of the dielectric layer(s) can be grinded or polished (or otherwise removed) to planarize the vias and reduce non-uniformities.

[0012] As an example, Figure 8A illustrates a via structure 18 that is formed using a conventional via-middle or via-last process after grinding or polishing the via structure 18, a portion of a dielectric layer 30 (e.g., a Low Temperature Oxide (LTO) layer), and a portion of a dielectric barrier layer 32 (e.g., a copper (Cu) diffusion barrier layer). For example, the LTO deposition process may involves depositing a dielectric layer using a silane such as, for example, tetraethoxysilane (TEOS), at a temperature of 200°C or less. As opposed to the LTO, a High Temperature Oxide (HTO) layer can have a higher stable temperature. The HTO layer may be capable of being deposited at a temperature greater than 200°C. In some embodiments, the HTO layer may be capable of being deposited at a temperature of 250°C or greater. In some embodiments, the HTO layer be capable of being deposited at a temperature of 300°C or greater, or 350°C or greater. For example, the HTO can comprise a 400°C TEOS. In Figure 8A, the dielectric barrier layer 32 extends on the thinned backside of the bulk semiconductor portion and along a sidewall 34 of the conductive via structure 18 (e.g., along a sidewall of a dielectric liner 36). The dielectric layer 30 is disposed on the dielectric barrier layer 32 (for example a SixOyNz layer) and terminates at the portion of the dielectric barrier layer 32 extending along the sidewall 34 of the via structure 18. In the structure shown in Figure 8A, the dielectric layer 30 does not contact the dielectric liner 36 of the via structure 18.

[0013] In conventional processes, the dielectric layer 30 (and the dielectric barrier layer 32) can be deposited using a suitable deposition process (e.g., plasma-enhanced chemical vapor deposition (PE-CVD) process). However, as explained above, the adhesive used to attach the temporary carrier to the microelectronic device is typically still in place during the dielectric depositions, and is typically sensitive to high temperature processing. Accordingly, in conventional processes, the backside dielectric layers (which can comprise barrier materials like silicon nitride and lower k materials like silicon oxide in some arrangements) are generally deposited at low temperature, e.g., at temperatures less than 200°C, or less than 300°C. Deposition of the dielectric layer 30 at low temperatures may form a low quality, low temperature silicon oxide layer. Indeed, voids may grow rapidly within the low temperature oxide (LTO) layer as the device is subsequently annealed, such as at 200°C and above. Low quality dielectric layers may be problematic for some applications, such as direct bonding processes. The presence of voids may render the dielectric surfaces unsuitable for subsequent processing, such as direct bonding. Further, as shown in Figure 5, the non-uniformity of wafer or die thicknesses can accumulate on the bonding surface, such that additional layers deposited on the element may exacerbate the non-uniformity. When multiple elements are stacked (e.g., directly bonded), the non-uniformity of thicknesses can negatively affect flatness and reduce bonding effectiveness in wafer-to-wafer (W2W) and die-to-wafer (D2W) applications, and can similarly negatively affect transfer or lamination of additional device layers.

[0014] Various embodiments disclosed herein address the challenges in via formation and direct bonding due to via opening etch non-uniformity, die or wafer thickness non-uniformity, and backside dielectric layer quality. Figure 6 is a schematic cross sectional side view of a microelectronic structure 2, according to an embodiment. As shown in Figure 6, the backside dielectric layer can be formed before TSV reveal as an embedded layer 50 between two elements 44, 48 (e.g., two semiconductor elements). The disclosed embodiments can provide better TSV depth uniformity and better wafer or die thickness uniformity. Moreover, instead of depositing low quality LTO as the backside dielectric layer, the disclosed embodiments enable the use of high quality high temperature oxide (HTO) layer(s) as the backside dielectric layer, because it is formed well before the low temperature adhesive is employed for carrier attachment. The use of HTO as the dielectric layer can beneficially be used in applications in which a LTO layer would be undesirable, such as direct bonding applications.

[0015] Figures 7A-7L illustrate a method for forming a microelectronic structure 3 (see Figures 7I-7K), according to various embodiments which are not part of the invention. Figure 7A is a schematic cross sectional side view showing a first element 40 and a second element 42 bonded to the first element 40. A bulk semiconductor portion 44 of the first element 40 and the bulk semiconductor portion 48 of the second element 42 can be intervened by a first dielectric barrier layer 46 and a second dielectric layer 50. As shown in Figure 7A, a semiconductor substrate (the bulk semiconductor portion 44 of the first element 40 or the bulk semiconductor portion 48 of the second element 42) is provided with an embedded dielectric layer (the second dielectric layer 50). For example, any of several silicon-on-insulator (SOI) processes can be employed to provide the embedded dielectric layer (the second dielectric layer 50). In one example, the first element 40 (e.g., a first semiconductor element) can be directly bonded to the second element 42 (e.g., a second semiconductor element) without an intervening adhesive along a bond interface 52. In some embodiments, the bond interface 52 can be within the second dielectric layer 50. As explained in more detail below, nonconductive bonding surfaces of the first and second elements 40, 42 can be prepared for direct bonding. For example, the nonconductive or dielectric bonding surfaces can be polished to a high degree of smoothness, and activated and / or terminated with a suitable species. The first and second elements can be brought into direct contact, and the nonconductive bonding surfaces of the first and second elements can form direct covalent bonds without an intervening adhesive.

[0016] One or more embedded dielectric layer(s) can be provided along the bond interface between the first and second elements. As shown in Figure 7A, the first dielectric barrier layer 46 can be provided (e.g., deposited) on the bulk semiconductor portion 48 of the second element 42. The first dielectric barrier layer 46 can comprise any suitable barrier layer that prevents or reduces diffusion of conductive material (e.g., copper), such as silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, diamond-like carbon, etc. The second dielectric layer 50 can be provided on the bulk semiconductor portion 48 of the second element 42 between the first dielectric barrier layer 46 and the bulk semiconductor portion 48 of the second element 42. The second dielectric layer 50 can comprise a high temperature silicon oxide (HTO) material in some embodiments. In some embodiments, the second dielectric layer 50 can comprise silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN). For example, the second dielectric layer 50 can comprise SiO2, SiNx, or SiCNO.

[0017] In some embodiments, the second dielectric layer 50 can be provided on the second element 42, and the second dielectric layer 50 of the second element 42 can be directly bonded to the bulk semiconductor portion 44 of the first element 40. In such an embodiment, the bond interface 52 can lie along the interface between the embedded dielectric layer (the second dielectric layer 50) and the first element 40. In other embodiments, the second dielectric layer 50 can be provided on the first element 40, and the second dielectric layer 50 of the first element 40 can be directly bonded to the bulk semiconductor portion 48 of the second element 42. In such an embodiment, the bond interface can lie along the interface between the embedded dielectric layer (the second dielectric layer 50) and the second element 42. In still other embodiments, a first portion of the embedded dielectric layer (the second dielectric layer 50) can be provided on the first element 40, and a second portion of the embedded dielectric layer (the second dielectric layer 50) can be provided on the second element 42, the first and second portions of the embedded dielectric layer (the second dielectric layer 50) can be directly bonded to one another. In such an embodiment, the bond interface can extend in the interior of the embedded dielectric layer (the second dielectric layer 50) between the first and second portions. The embedded dielectric layer (the second dielectric layer 50) can have a thickness in a range of 0.5 microns to 3 microns, or in a range of 1 micron to 2 microns. The thickness of the embedded dielectric layer can be chosen to balance stresses with the back end of line (BEOL) dielectrics designed to be formed on the opposite side of the first element.

[0018] Because the embedded dielectric layer (the second dielectric layer 50) is formed before attachment to a carrier, high temperature deposition processes can be used to deposit the dielectric layer on the first and / or second elements 40, 42. For example, in some embodiments, the embedded dielectric layer (the second dielectric layer 50) can comprise a high temperature oxide (HTO) dielectric layer that has superior qualities as compared to the LTO layer used in conventional techniques. The HTO layer may have fewer defects when heated to temperatures greater than 300°C or greater than 350°C. In some embodiments, the HTO layer can have a relatively low level of hydrogen in the form of SiH or OH bonds, as compared to LTO layers. For example, an LTO layer can have a hydrogen content of at least 5% or at least 10%. Further the LTO layer can be porous and can absorb moisture. The presence of hydrogen and / or moisture can diffuse to the bond interface 52 during annealing and cause the formation of voids in LTO layers. Moreover, a density of the LTO film can typically be lower such that polish rates and etch rates may be higher than an HTO layer by about 10% to 20%. Beneficially, the HTO layer used in the disclosed embodiments can have a higher density than an LTO layer, which can accommodate faster polish and etch rates. Moreover, the HTO layer can have a hydrogen content of less than 5%, less than 3%, or less than 1% in various embodiments. In various embodiments, the HTO can be chemically stable at temperatures above, for example 200°C, above 300°C, or above 400°C. In other embodiments, the dielectric film (e.g., the second dielectric layer 50) may be formed at low temperature and or with unique deposition processes to obtain high quality dielectric with, for example, Si, O, N, C. With the flexibility to deposit the dielectric layer first, the composition of the film may be designed for improved performance for a variety of factors including diffusion resistance to metals, etch selectivity, thermal conductivity. This dielectric layer (the second dielectric layer 50) may be engineered to optimize the property for the specific application. In some embodiments, the second dielectric layer 50 can be deposited or grown. The second dielectric layer 50 can comprise thermal oxide created by annealing, for example. In some embodiments, the second dielectric layer 50 can comprise a relatively thin native oxide, such as about 1 nm thick native oxide. The surface can be treated to grow the oxide thicker to form thermal oxide with, for example, a thickness in a rage of 300 nm to 500 nm. For example the surface can be annealed in the presence of oxygen and / or moisture.

[0019] Turning to Figure 7B, the bulk semiconductor portion 44 of the first element 40 can be thinned (e.g., grinded and / or polished) to form a thinned bulk semiconductor portion 44'. A surface of the thinned bulk semiconductor portion 44' can serve as an active front surface 54 of the device (the first element 40) in some embodiments. Active integrated circuitry, such as transistors, etc. (not shown) can be formed in or on the active surface 54, and BEOL metallization layers thereover, either before or after TSV formation shown in Figures 7C-7E.

[0020] In Figure 7C, a multi-step etch recipe can be used to controllably form openings 56 for via structures 57 (see Figures 7E-7L). In a first step, a first plasma etch chemistry can be used to etch through the bulk semiconductor portion 44' of the first element 40 (which can comprise silicon in some embodiments). The first etch chemistry can have high etch selectivity (e.g., about 60:1) between the bulk semiconductor portion 44' (e.g., silicon) and embedded dielectric layer (e.g, the first dielectric barrier 46 layer which can comprise silicon oxide). For example, in some embodiments, a Bosch etch procedure (which can use, e.g., SF 6 as an etchant) can be used to selectively and controllably form the openings 56 entirely through the silicon bulk semiconductor portion 44'. Due to the Bosch etch process, a first sidewall of the bulk semiconductor portion adjacent the via structure 57 in the first element can have first artifacts indicative of the first etching process. For example, the first etch process (e.g., the Bosch etch) can leave first artifacts having ridges 58 that leave a surface roughness profile along the first sidewall of the bulk semiconductor portion. Because of the high etch selectivity, the embedded dielectric layer(s) (e.g., the first dielectric barrier layer 46) can serve as an etch stop layer to prevent over-etching into the second dielectric layer 50 and / or the bulk semiconductor portion 48 of the underlying second element 42.

[0021] A second etch step can include a second etch chemistry (e.g., a dielectric etch chemistry) that etches through the first dielectric barrier layer 46, the second dielectric layer 50 (e.g., silicon oxide), and into a portion of the bulk semiconductor portion 48 (e.g., silicon) of the second semiconductor element 42. The second etch chemistry can accordingly etch completely through the first and second dielectric layers 46, 50, and into the bulk semiconductor portion 48 of the second element 42 by a controllable amount. The second etch can form second artifacts along the sidewalls of the first dielectric layer 46, the second dielectric barrier layer 50, and the bulk semiconductor portion 48 of the second element 42. The second artifacts can be visually different from the first artifacts upon inspection with optical imaging techniques. For example, the surface roughness of the second artifacts can differ from the surface roughness of the first artifacts. In one embodiment, the surface roughness of the second artifacts can be lower (e.g., smoother) than the surface roughness of the first artifacts.

[0022] The second etch can etch into the bulk semiconductor portion 48 of the second element 42 by a depth less than 5 microns, less than 3 microns, or less than 1 micron, e.g., in a range of 0.05 microns to 5 microns, in a range of 0.05 microns to 3 microns, in a range of 0.05 microns to 1 micron, in a range of 0.05 microns to 0.5 microns, in a range of 0.25 microns to 5 microns, in a range of 0.25 microns to 3 microns, in a range of 0.25 microns to 1 micron, or in a range of 0.5 microns to 1 micron. Because the via etch proceeds through only a reduced (thinned) thickness of the first element 40, and because a selective etch has been performed through the remaining semiconductor bulk thickness to stop on the embedded dielectric (the first dielectric layer 46 and the second dielectric barrier layer 50), and because etch depth into the bulk semiconductor portion 48 of the second element 42 is so small compared to the overall thickness of the die, etch uniformity can be controlled to a uniformity of approximately less than 1 micron.

[0023] Turning to Figure 7D, a dielectric liner layer 54 of the via structure 57 can be provided in the openings 56 along the sidewall of the bulk semiconductor portion 44' of the first element 40, along the sidewalls of the first dielectric barrier layer 46 and the second dielectric layer 50, and along the sidewall of the bulk semiconductor portion 48 of the second element 42. The dielectric liner layer 54 can comprise any suitable dielectric, such as silicon oxide, silicon nitride, etc. A barrier layer (not shown) can be provided in the opening 56 on the dielectric liner layer 54. The barrier layer can comprise a conductive barrier layer in some embodiments to prevent or reduce migration of the conductive material (such as copper). The conductive barrier layer of the via structure 57 can comprise, for example, a metal or metal nitride, such as titanium nitride, tantalum nitride, or any other suitable barrier layer.

[0024] Turning to Figure 7E, a seed layer (not shown) can be provided over the semiconductor portion of the first element 40 and into the openings 56 over the barrier layer in the openings 56. Conductive vias 62 (e.g., copper) can be provided (e.g., electroplated) into the openings 56 over the seed layer (not shown). The seed and / or adhesion layer(s) can be removed from over an upper surface of the silicon bulk semiconductor portion 44' of the first element 40 by polishing (e.g., chemical mechanical polishing, or CMP) and / or wet etch techniques. The via formation process may also have low thickness variation, e.g., less than 1 micron thickness variation.

[0025] In Figure 7F, one or more dielectric and metallization layers, such as back-end-of-line (BEOL) layers 64 can be provided over the upper surface (front surface) of the bulk semiconductor portion 44' of the first element 40 and connected to the conductive vias 62. The BEOL layer(s) 64 can comprise traces to route electrical signals form the TSVs 62 to other portions of the microelectronic structure. In other embodiments, the BEOL layers 64 can be provided prior to the TSV etch of Figure 7C. In Figure 7G, a temporary carrier 66 can be adhered to the BEOL structure with a temporary adhesive 68. As explained above, the temporary adhesive 68 may be sensitive to high temperature processing. Because the embedded dielectric layer (the first dielectric layer 46 and the second dielectric barrier layer 50) has already been provided, there is no need for a subsequent backside dielectric deposition at high temperatures, and, therefore, the temporary adhesive 68 can be used to attach the carrier 66. In other embodiments, the carrier 66 can be directly bonded to the BEOL 64 without an adhesive.

[0026] Turning to Figure 7H, the second element 42 (including the bulk semiconductor portion 48 thereof) at a backside of the structure can be removed to expose the via structures 57. In some embodiments, the second element 42 can be backgrinded and / or polished to reveal the TSV structures 57. Once the semiconductor portion 48 of the second element 42 has been removed, the TSV structures 57 protrude from the second dielectric layer 50. Because the via openings 56 were formed with depths having a high degree of uniformity (e.g., the depth of the etch into the bulk semiconductor portion 48 of the second element 42 can be highly controlled due the selective nature of the majority of depth to stop on the embedded dielectric 50, and due its low aspect ratio), the lengths of the via structures 57 extending beyond the second dielectric layer 50 can have a high degree of uniformity. As shown in Figure 7H, as compared with conventional processes, the disclosed embodiment need not use an additional dry etch, and need not use low temperature nitride (LTN) barrier and LTO dielectric layers, is therefore considerably simpler and less costly than typical backside TSV reveal processing.

[0027] In Figure 7I, the backside of the microelectronic structure 3 can be polished and planarized to remove the protruding portions of the TSV structures 57. For example, the backside can be polished using a CMP process to a high degree of smoothness. In some embodiments, the CMP chemistry can be selected to recess the TSV structures 57 below the HTO dielectric surface to facilitate subsequent direct hybrid bonding. The higher quality HTO dielectric layer may be suitable for directly bonding to another element or structure. For example, as shown in Figure 7J, and as explained below, the microelectronic structure 3 can be directly bonded to another device wafer 4 or stack of multiple wafers in a wafer-to-wafer (W2W) process. In Figure 7K, the temporary carrier 66 and adhesive 68 can be removed. The microelectronic structure 3 can be integrated into a larger electronic system, or additional layers of elements can be integrally formed on or laminated (e.g., bonded) on the microelectronic structure 3. The bonded wafers can be singulated into a plurality of bonded elements 5 or dies.

[0028] Figure 7L illustrates an alternative die-to-wafer (D2W) process, in which the microelectronic structure in wafer form can be provided on a dicing frame 70 and diced or singulated. Diced element 6 can be prepared for direct bonding, and picked and placed onto another element, such as a wafer 4, an integrated device die(s), a stack of multiple wafers, etc. The diced element 6 (e.g., diced microelectronic structures) can be directly bonded to the other element without an adhesive, as explained in more detail below. In some embodiments, the diced element 6 can comprise one of the elements 5.

[0029] As explained above, Figure 8A shows the via structure 18 formed using a conventional backside TSV reveal, barrier deposition and LTO deposition process. Figure 8B illustrates the via structure 57 formed according to the embodiments disclosed herein. As shown in Figure 8B, a bulk semiconductor portion 44' of the first element 40 can have a first surface 72 and a second surface 74 opposite the first surface 72. The via structure 57 can extend at least partially through (e.g., completely through) the bulk semiconductor portion 44' along a direction non-parallel to the first surface 72. A first dielectric barrier layer 46 can be disposed on the first surface 72 of the bulk semiconductor portion 44' and extending to the via structure 57. In the illustrated embodiment, the first dielectric barrier layer 46 is disposed directly on and contacts the bulk semiconductor portion 44', although in other embodiments, additional layer(s) may intervene between the first dielectric barrier layer 46 and the bulk semiconductor portion 44'. A second dielectric layer 50 can be disposed on the first dielectric barrier layer 46 and can extend to the via structure 57. In the illustrated embodiment, the second dielectric layer 50 is disposed directly on and contacts the first dielectric barrier layer 46, but in other embodiments, additional layer(s) may intervene between the first dielectric barrier layer 46 and the second dielectric layer 50.

[0030] The via structure 57 can include a conductive via 62 and a dielectric liner 54 disposed around the conductive via 62. The second dielectric layer 50 can extend to (e.g., and can contact) the dielectric liner 54 without an intervening barrier. The via structure 57 can comprise a second barrier layer 78 extending along the conductive via between the metal (e.g., copper) of the conductive via 62 and the dielectric liner 54. As explained above, the second dielectric layer 50 can comprise a high temperature silicon oxide layer (HTO). Further, as explained above, a first sidewall 80 of the bulk semiconductor portion 44' adjacent the via structure 57 can have first artifacts indicative of a first etching process and a second sidewall 82 of the dielectric layer 50 adjacent the via structure 57 can have second artifacts indicative of a second etching process different from the first etching process. The first and second artifacts have different surface roughness profiles along the first and second sidewalls 80, 82. For example, the first artifacts comprise ridges indicative of a Bosch etch process. In some embodiments, the first artifacts comprises ridges and the second artifacts do not comprise ridges. In some other embodiments, the first artifacts comprise ridges with a first surface roughness and the second artifacts comprise ridges with a second surface roughness that is different (e.g., smoother) than the first surface roughness. Such artifacts can be visible through a scanning electron microscope (SEM) image of the final product.

[0031] As explained above, the first dielectric barrier layer 46 can comprise silicon nitride, although other types of dielectric materials can be used as explained above. The via structure 57 can extend completely through the bulk semiconductor portion 44', the first dielectric barrier layer 46, and the second dielectric layer 50. The via structure 57 can have an end surface 84 that is flush with, or recessed slightly relative to, a surface 86 of the second dielectric layer 50 that is opposite the bulk semiconductor portion 44'. In various embodiments, it can be advantageous to slightly recess the end surface 84 of the conductive via structure 57 relative to the surface 86 of the dielectric layer 50, to allow for thermal expansion during annealing and to form a direct metallic bond. Alternatively, the via structure 57, and particularly the conductive via 62 of the via structure 57 (e.g., copper) can be recessed from the second dielectric (HTO) surface by less than 30 nm, by less than 20 nm, particularly less than 15 nm or less than 10 nm, to facilitate subsequent direct hybrid bonding. The end surface 84 of the via structure 57 and the surface 86 of the dielectric layer 50 can comprise planarized surfaces.Examples of Direct Bonding Methods and Directly Bonded Structures

[0032] Various embodiments disclosed herein relate to directly bonded structures in which two elements can be directly bonded to one another without an intervening adhesive. Two or more semiconductor elements (such as integrated device dies, wafers, etc.) may be stacked on or bonded to one another to form a bonded structure. Conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in the bonded structure.

[0033] In some embodiments, the elements are directly bonded to one another without an adhesive. In various embodiments, a non-conductive or dielectric material of a first element can be directly bonded to a corresponding non-conductive or dielectric field region of a second element without an adhesive. The non-conductive material can be referred to as a nonconductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques. For example, dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749.

[0034] In various embodiments, direct hybrid bonds can be formed without an intervening adhesive. For example, dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or etchants to activate the surfaces. In some embodiments, the surfaces can be terminated with a species after activation or during activation (e.g., during the plasma and / or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surface, and the termination process can provide additional chemical species at the bonding surface that improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the surfaces. In other embodiments, the bonding surface can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. Further, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and / or bonding interfaces. Thus, in the directly bonded structures, the bonding interface between two dielectric materials can comprise a very smooth interface with higher nitrogen content and / or fluorine peaks at the bonding interface. Additional examples of activation and / or termination treatments may be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749.

[0035] In various embodiments, conductive contact pads of the first element can also be directly bonded to corresponding conductive contact pads of the second element. For example, a hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently direct bonded dielectric-to-dielectric surfaces, prepared as described above. In various embodiments, the conductor-to-conductor (e.g., contact pad to contact pad) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988.

[0036] For example, dielectric bonding surfaces can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact pads (which may be surrounded by nonconductive dielectric field regions) may also directly bond to one another without an intervening adhesive. In some embodiments, the respective contact pads can be recessed below exterior (e.g., upper) surfaces of the dielectric field or nonconductive bonding regions, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. The nonconductive bonding regions can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure can be annealed. Upon annealing, the contact pads can expand and contact one another to form a metal-to-metal direct bond. Beneficially, the use of Direct Bond Interconnect, or DBI ®< , techniques commercially available from Xperi of San Jose, CA, can enable high density of pads connected across the direct bond interface (e.g., small or fine pitches for regular arrays). In some embodiments, the pitch of the bonding pads, or conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns or less than 10 microns or even less than 2 microns. For some applications the ratio of the pitch of the bonding pads to one of the dimensions of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2. In other applications the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 to 3 microns. In various embodiments, the contact pads and / or traces can comprise copper, although other metals may be suitable.

[0037] Thus, in direct bonding processes, a first element can be directly bonded to a second element without an intervening adhesive. In some arrangements, the first element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element can comprise a carrier or substrate (e.g., a wafer).

[0038] As explained herein, the first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process. In one application, a width of the first element in the bonded structure is similar to a width of the second element. In some other embodiments, a width of the first element in the bonded structure is different from a width of the second element. Similarly, the width or area of the larger element in the bonded structure may be at least 10% larger than the width or are of the smaller element. The first and second elements can accordingly comprise non-deposited elements. Further, directly bonded structures, unlike deposited layers, can include a defect region along the bond interface in which nanovoids are present. The nanovoids may be formed due to activation of the bonding surfaces (e.g., exposure to a plasma). As explained above, the bond interface can include concentration of materials from the activation and / or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments that utilize an oxygen plasma for activation, an oxygen peak can be formed at the bond interface. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.

[0039] In various embodiments, the metal-to-metal bonds between the contact pads can be joined such that copper grains grow into each other across the bond interface. In some embodiments, the copper can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface. The bond interface can extend substantially entirely to at least a portion of the bonded contact pads, such that there is substantially no gap between the nonconductive bonding regions at or near the bonded contact pads. In some embodiments, a barrier layer may be provided under the contact pads (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the contact pads, for example, as described in US 2019 / 0096741.

[0040] In one embodiment, a microelectronic structure is disclosed. The microelectronic structure includes a bulk semiconductor portion having a first surface and a second surface opposite the first surface. The microelectronic structure includes a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure includes a first dielectric barrier layer disposed on the first surface of the bulk semiconductor portion and extending to the via structure. The microelectronic structure includes a second dielectric layer disposed on the first dielectric barrier layer and extending to the via structure.

[0041] In some embodiments, the via structure comprises a conductive via and a dielectric liner disposed around the conductive via, the second dielectric layer extending to the dielectric liner. In some embodiments, the via structure comprises a second barrier layer extending along the conductive via between the conductive via and the dielectric liner. In some embodiments, the second dielectric layer comprises a dielectric layer that includes silicon oxynitride. In some embodiments, the second dielectric layer comprises a high temperature silicon oxide layer. In some embodiments, the second dielectric layer comprises a dielectric layer that includes silicon oxycarbonitride. In some embodiments, a first sidewall of the bulk semiconductor portion adjacent the via structure has first artifacts indicative of a first etching process and a second sidewall of the dielectric layer adjacent the via structure has second artifacts indicative of a second etching process different from the first etching process. In some embodiments, the first and second artifacts have different surface roughness profiles along the first and second sidewalls. In some embodiments, the first artifacts comprise ridges indicative of a Bosch etch process. In some embodiments, the first dielectric barrier layer comprises silicon nitride. In some embodiments, the via structure extends completely through the bulk semiconductor portion, the first dielectric barrier layer, and the second dielectric layer. In some embodiments, the via structure has an end surface that is recessed relative to a surface of the second dielectric layer that is opposite the bulk semiconductor portion. In some embodiments, the end surface of the via structure and the surface of the dielectric layer comprise planarized surfaces. In the embodiments, the second dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along a bonding interface. In some embodiments, the second surface of the bulk semiconductor portion comprises an active surface that includes active circuitry, one or more insulating layers over the active surface, and back-end-of-line layers over the one or more insulating layers.

[0042] In another embodiment, the dielectric layer of the microelectronic structure comprises a silicon oxynitride layer.

[0043] A method of forming a microelectronic structure which is not part of the invention, is disclosed. The method can include providing a semiconductor structure including an embedded dielectric layer; etching an opening through a front side of semiconductor structure to stop on the embedded dielectric layer; continuing to etch the opening through the embedded dielectric layer; depositing a conductive material into the opening to form a conductive via; and revealing the conductive via from a back side of the semiconductor structure.

[0044] Providing the semiconductor structure can comprise providing a bulk semiconductor portion and a base substrate, the embedded dielectric layer disposed between the bulk semiconductor portion and the base substrate. Continuing to etch the opening can comprise etching partially into the base substrate. Revealing the conductive via can comprise removing the base substrate. The method can comprise forming at least a portion of the embedded dielectric layer on one of the bulk semiconductor portion and the base substrate. Forming the at least a portion of the embedded dielectric layer can comprise forming a first barrier dielectric layer and a second dielectric layer on the first barrier dielectric layer. The method can comprise forming a first portion of the embedded layer on the bulk semiconductor portion and a second portion of the embedded dielectric layer on the base substrate. The method can comprise after depositing the conductive material, annealing the microelectronic structure. Revealing can comprise polishing the back side of the semiconductor structure. The method comprises directly bonding the polished back side of the semiconductor structure to another element without an intervening adhesive. Directly bonding comprises directly bonding a polished surface of the embedded dielectric layer and the conductive via to the another element without an intervening adhesive along a bonding interface.

[0045] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," "include," "including" and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to." The word "coupled", as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word "connected", as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Moreover, as used herein, when a first element is described as being "on" or "over" a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word "or" in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

Claims

1. A microelectronic structure comprising: a bulk semiconductor portion (44') having a first surface (72) and a second surface (74) opposite the first surface (72); a via structure (57) extending at least partially through the bulk semiconductor portion (44') along a direction non-parallel to the first surface (72); a first dielectric barrier layer (46) disposed on the first surface (72) of the bulk semiconductor portion (44') and extending to the via structure (57); and a second dielectric layer (50) disposed on the first dielectric barrier layer (46) and extending to the via structure (57); characterised in that the second dielectric layer (50) and the via structure (57) are directly bonded to another element (4) without an intervening adhesive along a bonding interface.

2. The microelectronic structure of Claim 1, wherein the via structure (57) comprises a conductive via (62) and a dielectric liner (54) disposed around the conductive via, the second dielectric layer (50) extending to the dielectric liner (54).

3. The microelectronic structure of Claim 2, wherein the via structure (57) comprises a second barrier layer (78) extending along the conductive via (62) between the conductive via (62) and the dielectric liner (54).

4. The microelectronic structure of any one of Claims 1 to 3 wherein the second dielectric layer (50) comprises a dielectric layer that includes silicon oxynitride.

5. The microelectronic structure of any one of Claims 1 to 3, wherein the second dielectric layer (50) comprises a high temperature silicon oxide layer.

6. The microelectronic structure of any one of Claims 1 to 3 wherein the second dielectric layer (50) comprises a dielectric layer that includes silicon oxycarbonitride.

7. The microelectronic structure of any one of Claims 1 to 6, wherein a first sidewall (80) of the bulk semiconductor portion (44') adjacent the via structure (57) has first artifacts indicative of a first etching process and a second sidewall (82) of the dielectric layer adjacent the via structure (57) has second artifacts indicative of a second etching process different from the first etching process.

8. The microelectronic structure of Claim 7, wherein the first and second artifacts have different surface roughness profiles along the first and second sidewalls.

9. The microelectronic structure of Claim 8, wherein the first artifacts comprise ridges indicative of a Bosch etch process.

10. The microelectronic structure of any one of Claims 1 to 9, wherein the first dielectric barrier layer (46) comprises silicon nitride.

11. The microelectronic structure of any one of Claims 1 to 10, wherein the via structure (57) extends completely through the bulk semiconductor portion (44'), the first dielectric barrier layer (46), and the second dielectric layer (50).

12. The microelectronic structure of any one of Claims 1 to 11, wherein the via structure (57) has an end surface (84) that is recessed relative to a surface (86) of the second dielectric layer (50) that is opposite the bulk semiconductor portion (44').

13. The microelectronic structure of Claim 12, wherein the end surface of the via structure and the surface of the dielectric layer comprise planarized surfaces.

14. The microelectronic structure of any one of Claims 1 to 13, wherein the second surface (74) of the bulk semiconductor portion (44') comprises an active surface that includes active circuitry, one or more insulating layers over the active surface, and one or more back-end-of-line layers over the one or more insulating layers.