SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Patent Information
- Application Number
- DE602022016250
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2022-08-04
- Filing Date
- 2022-08-17
- Publication Date
- 2025-06-18
- Estimated Expiration
- 2042-08-17
AI Technical Summary
Existing semiconductor structures, such as dynamic random access memory (DRAM), face challenges in miniaturization due to complex manufacturing processes and high power consumption, particularly in capacitor-less two-transistor (2T0C) DRAM structures.
The semiconductor structure comprises a substrate with a semiconductor pillar and a gate pillar extending perpendicular to the substrate plane, surrounded by a first word line and a semiconductor layer that covers the semiconductor pillar and surrounds the gate pillar, allowing for reduced area occupation and improved integration.
This configuration significantly reduces the area occupied by transistor projections on the substrate, enhancing the integration level of the semiconductor structure and reducing power consumption by eliminating the need for capacitors and re-writing operations.