LED DISPLAY PIXEL FOR A DISPLAY SCREEN

Description

[0001] This patent application claims priority from French patent application FR21 / 12579 and French patent application FR21 / 12580. Domaine technique

[0002] This disclosure relates generally to display pixels comprising light-emitting diodes for a display screen. Technique antérieure

[0003] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, a display screen generally comprises for the display of each pixel of the image at least three components, also called display sub-pixels, which each emit light radiation substantially in a single color (for example, red, green and blue). The superposition of the radiation emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the display pixel of the display screen is called the assembly formed by the three display sub-pixels used for the display of a pixel of an image. Each display sub-pixel may comprise a light source, in particular a light-emitting diode.

[0004] Display pixels can be distributed in a matrix fashion, with each display pixel located at the intersection of a row (or line) and a column of the matrix. Typically, each row of display pixels is selected in succession, and the display pixels in the selected row are programmed to display the desired image pixels.

[0005] An active matrix is ​​a screen driver architecture that keeps all pixel lines active for the entire duration of an image, unlike so-called passive matrices where each line is only active for a time T=Tframe / N (where Tframe is the duration of the image and N is the number of lines on the screen). This optimizes the operation of the light-emitting diodes. In addition, it is possible to send low levels of voltage or current to the matrix control lines, which allows for the display of larger data streams.

[0006] In the context of a screen based on micrometric light-emitting diodes, the size of the light-emitting diodes is generally smaller than the surface area available on the screen for the image pixel due to the high intrinsic brightness of the light-emitting diodes. One method of manufacturing a display screen consists of depositing these unitary light-emitting diodes on a support, also called a panel, containing the control electronics. Another manufacturing method consists of using display pixels comprising light-emitting diodes and a circuit for controlling the light-emitting diodes. These are then referred to as smart pixels. This makes it possible in particular to simplify the production of an active matrix, since the control electronics for the light-emitting diodes of the display pixel are essentially embedded on the display pixel. Document WO 2018 / 185433 describes an example of a smart pixel.

[0007] The trend is to increase the number of display pixels on the screen. This leads to an increase in the cost and manufacturing time of the display screen, which depends in particular on the number of operations to place the display pixels on the panel, which is not desirable.

[0008] It is desirable that the dimensions of the display pixels be as small as possible to reduce the quantity of semiconductor materials composing the display pixels and therefore reduce the manufacturing costs of these display pixels. However, fixing small display pixels to the panel can then be difficult, in particular to ensure a suitable electrical connection between conductive pads of the display pixels and conductive tracks of the panel. This problem is all the more sensitive in view of the current trend towards increasing the number of display pixels on the screen.

[0009] CN 112 349 707 A, EP 3 690 944 A1 and WO 2019 / 236325 A1 disclose display blocks according to the prior art. Summary of the invention

[0010] An object of an embodiment is to provide one of the display pixels comprising light emitting diodes for a display screen overcoming all or part of the disadvantages of existing light emitting diode display pixels.

[0011] An object of an embodiment is that the number of operations for placing the display pixels on the display screen panel is reduced.

[0012] An object of an embodiment is that the precision constraints for connecting display pixels to a panel are reduced.

[0013] One embodiment provides a display unit comprising: an optoelectronic circuit comprising light-emitting diodes of at least two display pixels and having a first face for emitting the light radiation of the light-emitting diodes; and diffusing structures covering the optoelectronic circuit, each diffusing structure being in contact with a portion of the first emission face and having a second face for emitting the light radiation of the light-emitting diodes of one of the display pixels, the ratio between the sum of the areas of the second emission faces and the area of ​​the first emission face being greater than 2.

[0014] This allows the use of small display pixels while maintaining a large emitting surface for each display pixel.

[0015] According to one embodiment, the display pixels are separated by first separating elements that do not allow the light radiation from the light-emitting diodes to pass through and the diffusing structures are separated by second separating elements that do not allow the light radiation from the light-emitting diodes to pass through, the first separating elements being aligned with the second separating elements at the first emission face. Each diffusing structure can receive only the light radiation from the light-emitting diodes of one of the display pixels. This makes it possible to avoid optical crosstalk between the display pixels of the same display block.

[0016] Each diffusing structure aims to distribute the light radiation emitted by the light-emitting diodes of the display pixel in contact with this diffusing structure over the entirety of the second emission face associated with the diffusing structure. According to one embodiment, the second emission face is a diffusing surface. According to one embodiment, each diffusing structure is at least partly composed of a diffusing material. According to one embodiment, each diffusing structure is at least partly composed of a waveguide. According to one embodiment, each diffusing structure comprises patterns distributed over a surface and reflecting or diffusing the light radiation. According to one embodiment, the surface density of the patterns increases as one moves away from the optoelectronic circuit.

[0017] According to one embodiment, the display block comprises an electrically insulating sheath surrounding the optoelectronic circuit, the diffusing structures covering the sheath, in contact with the sheath or separated from the sheath by a film of air via spacers interposed between the sheath and the diffusing structures.

[0018] According to one embodiment, the optoelectronic circuit comprises a third face opposite the first face and first electrically conductive pads exposed on the third face, the display block comprising electrically conductive tracks in contact with the first electrically conductive pads and extending by second electrically conductive pads extending over the sheath.

[0019] One embodiment provides a display unit comprising: an optoelectronic circuit comprising light-emitting diodes of at least one display pixel, a first face for emitting light radiation from the light-emitting diodes, a third face opposite the first face, and first electrically conductive pads exposed on the third face; an electrically insulating sheath surrounding the optoelectronic circuit; and electrically conductive tracks in contact with the first electrically conductive pads and extending into second electrically conductive pads extending over the sheath.

[0020] The spacing between the second conductive pads can be increased relative to the spacing between the first conductive pads. This facilitates subsequent placement of the pixel blocks on a panel, by reducing constraints on the accuracy of positioning the pixel blocks at the time of transfer to the panel.

[0021] According to one embodiment, at least one of the diffusing structures contains phosphors. According to one embodiment, the phosphors comprise quantum dots. According to one embodiment, at least two diffusing structures contain different phosphors. According to one embodiment, the light-emitting diodes each emit a first light radiation at a first wavelength, and wherein the diffusing structures comprise a first diffusing structure comprising first phosphors adapted to convert the first light radiation into a second light radiation at a second wavelength different from the first wavelength and a second diffusing structure comprising second phosphors adapted to convert the first light radiation into a third light radiation at a third wavelength different from the first wavelength and the second wavelength.

[0022] According to one embodiment, the display pixels of the optoelectronic circuit are contiguous and the first emission face is centered relative to the surface formed by the second emission faces. According to one embodiment, the optoelectronic circuit comprises four display pixels.

[0023] According to one embodiment, the optoelectronic circuit comprises a single circuit for controlling all the light-emitting diodes of the display pixels. The optoelectronic circuit therefore comprises the light-emitting diodes associated with several display pixels which are controlled by the same control circuit. This advantageously makes it possible to reduce the number of conductive pads required for powering / controlling these display pixels. This facilitates the subsequent placement of the pixel blocks on a panel, by reducing the constraints on the precision of the positioning of the pixel blocks at the time of transfer to the panel.

[0024] An embodiment also provides a display screen comprising a panel and a plurality of display blocks, as defined above, attached to the panel.

[0025] According to one embodiment, the display pixels of the display blocks are arranged in rows and columns, and the optoelectronic circuit of each display block comprises at least four display pixels belonging to at least two adjacent rows and at least two adjacent columns.

[0026] An embodiment also provides a method of manufacturing display blocks as defined above, comprising the following steps: a) forming a plate comprising a plurality of said optoelectronic circuits; b) cutting the plate to separate said optoelectronic circuits; and c) for each separate optoelectronic circuit, forming diffusing structures covering the optoelectronic circuit.

[0027] According to one embodiment, the method further comprises, in step a), the formation of first separation elements in each optoelectronic circuit separating the display pixels, and, in step c), the formation of second separation elements separating the diffusing structures and aligned with the first separation elements.

[0028] An embodiment also provides a method for manufacturing a display screen as defined above comprising placing the display blocks on the panel. The reduced number of first conductive pads per display pixel, and the formation of the second conductive pads makes it possible to increase the spacing between the second conductive pads. This facilitates the placement of the display blocks on a panel, by reducing the constraints on the precision of the positioning of the display blocks at the time of transfer to the panel.

[0029] According to one embodiment, the sheath completely surrounds the optoelectronic circuit and the minimum dimension of the sheath in a plane parallel to the third face is between 5 µm and 5 mm. According to one embodiment, the maximum dimension of the optoelectronic circuit in a plane parallel to the third face is between 10 µm and 200 µm and the maximum dimension of the display block in said plane parallel to the third face is between 100 µm and 500 µm. According to one embodiment, the maximum distance between the centers of the first electrically conductive pads is between 0.5 µm and 2 mm and the minimum distance between the centers of the second electrically conductive pads is between 1 µm and 5 mm, preferably between 5 µm and 3 mm.

[0030] According to one embodiment, the optoelectronic circuit comprises only four first electrically conductive pads.

[0031] An embodiment also provides a method of manufacturing display blocks as defined above, comprising the following steps: a') forming a plate comprising a plurality of said optoelectronic circuits; b') cutting the plate to separate said optoelectronic circuits; and c') for each separate optoelectronic circuit, forming the electrically insulating sheath surrounding the optoelectronic circuit; and d') for each separate optoelectronic circuit, forming the electrically conductive tracks in contact with the first electrically conductive pads and extending through the second electrically conductive pads extending over the sheath. Brève description des dessins

[0032] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 represents, in a partial and schematic manner, an example of a display screen; the figure 2 is a partial, schematic top view of an example of a display pixel arrangement of a display screen; figure 3 is a partial, schematic top view of another example of a display pixel arrangement of a display screen; figure 4 is a partial and schematic side section of an embodiment of a group of pixels; the figure 5 is a partial and schematic top view of the embodiment of the pixel group of the figure 4 ; there figure 6 is a partial and schematic bottom view of the embodiment of the pixel group of the figure 4 ; there figure 7 is a partial and schematic top view of an embodiment of a display screen; the figure 8 is a partial and schematic sectional view illustrating an embodiment of a diffusing structure; the figure 9 a partial and schematic sectional view illustrating another embodiment of a diffusing structure; figure 10 is a partial and schematic sectional view illustrating another embodiment of a diffusing structure; the figure 11 is a partial and schematic sectional view illustrating another embodiment of a diffusing structure; the figure 12 is a partial and schematic sectional view illustrating another embodiment of a diffusing structure; the figure 13 is a partial and schematic sectional view illustrating another embodiment of a diffusing structure; the figure 14 is a partial, schematic, sectional view of a more detailed embodiment of the structure of a display pixel of the pixel group of the figure 4 ; there figure 15 illustrates a step of an embodiment of a method of manufacturing a display screen; the figure 16 illustrates another step in the process; the figure 17 illustrates another step in the process; the figure 18 illustrates another step in the process; the figure 19 illustrates another step in the process; the figure 20 illustrates another step in the process; the figure 21 illustrates another step in the process; the figure 22 illustrates another step in the process; the figure 23 illustrates another step in the process; the figure 24 illustrates another step in the process; the figure 25 illustrates another step in the process; the figure 26 illustrates another step in the process; the figure 27 represents an image displayed by a known display screen; the figure 28 represents the image displayed by a known display screen with light-emitting diode display pixels; the figure 29 represents the image displayed by a known display screen with light-emitting diode display pixels; the figure 30 represents the image displayed on a display screen comprising the pixel groups of the figure 4 according to an arrangement of pixel groups; the figure 31 represents the image displayed on a display screen comprising the pixel groups of the figure 4 according to another arrangement of the pixel groups; and the figure 32 represents the image displayed on a display screen comprising the pixel groups of the figure 4 according to another arrangement of pixel groups. Description des modes de réalisation

[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0034] Unless otherwise specified, when two elements are connected together, this means directly connected without intermediate elements other than conductors, and when two elements are connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements. Furthermore, the terms "insulator" and "conductor" are considered here to mean "electrically insulating" and "electrically conducting" respectively.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures or to a display screen in a normal position of use.

[0036] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0037] In the remainder of the description, the internal transmittance of a layer corresponds to the ratio between the intensity of the radiation leaving the layer and the intensity of the radiation entering the layer. The absorption of the layer is equal to the difference between the number 1 (which corresponds to a perfect transmittance for which all the incident light is transmitted) and the internal transmittance. In the remainder of the description, a layer is said to be transparent to radiation when the absorption of radiation through the layer is less than 75%. In the remainder of the description, a layer is said to be absorbent or opaque to radiation when the absorption of radiation in the layer is greater than 75%. In the remainder of the description, the refractive index of a material corresponds to the refractive index of the material for the wavelength range of the radiation emitted by the light source.Unless otherwise stated, the refractive index is considered substantially constant over the wavelength range of the radiation emitted by the light source, e.g., equal to the average of the refractive index over the wavelength range of the radiation emitted by the light source.

[0038] There figure 1 represents, in a partial and schematic manner, an example of a display screen 10. The display screen 10 comprises display pixels 12 i,j for example arranged in M ​​rows and in N columns, M being an integer varying from 1 to 8000 and N being an integer varying from 1 to 16000, i being an integer varying from 1 to M and j being an integer varying from 1 to N. By way of example, in figure 1 , M and N are equal to 6. Each display pixel 12 i,j is connected to a source of a low reference potential Gnd, for example ground, via an electrode 14 i and to a source of a high reference potential Vcc via an electrode 16 j . As an example, the electrodes 14 i are shown aligned according to the rows in figure 1 and the 16 j electrodes are shown aligned along the columns in figure 1 , the reverse arrangement being possible. The supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd.

[0039] For each row, the display pixels 12 i,j of the row are connected to a row electrode 18 i . For each column, the display pixels 12 i,j of the column are connected to a column electrode 20 j . The display screen 10 comprises a selection circuit 22 connected to the row electrodes 18 i and adapted to provide a selection and timing signal Com i on each row electrode 18 i . The display screen 10 comprises a data supply circuit 24 connected to the column electrodes 20 j and adapted to provide a data signal Data j on each column electrode 20 j . The selection circuit 22 and the control circuit 24 are controlled by a circuit 23, comprising for example a microprocessor.

[0040] When the display pixels are smart pixels, the manufacturing process may include individually placing each display pixel on a panel. The panel may include conductive tracks, with each display pixel being attached to the panel so as to connect contact pads of the display pixel to the conductive tracks. With the trend toward increasing display resolution, the number of operations for individually placing the display pixels may be significant, increasing the time and cost of manufacturing the display.

[0041] Each display pixel may comprise a control circuit covered by a display circuit. The display circuit comprises at least one LED, preferably at least three LEDs. The control circuit may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin-film transistors, also called TFT transistors (English acronym for Thin-Film Transistor). The control circuit further comprises the contact pads.A method of manufacturing the display pixel includes forming a plurality of display circuits on a plate, called an optoelectronic plate, forming a plurality of control circuits on a plate, called a logic plate, attaching the optoelectronic plate to the logic plate, and cutting the stack of the optoelectronic plate and the logic plate to separate the display pixels.

[0042] One possibility for reducing the number of operations for placing display pixels on the display panel is to group several display pixels into a group of solid display pixels, each group of pixels comprising, for example, four display pixels. When the display pixels are manufactured from the stack of an optoelectronic plate and a logic plate as described above, this amounts to cutting the stack of the optoelectronic plate and the logic plate to separate the groups of pixels instead of separating the display pixels individually. The placing operations are performed on the groups of display pixels instead of the individual display pixels. The number of manipulations is thus reduced.Each group of pixels then comprises a stack of a global control circuit integrating the control circuits of the display pixels of the group of pixels and a global display circuit comprising the display circuits of the display pixels of the group of pixels.

[0043] THE figures 2 And 3 are each a schematic top view of a portion of an exemplary display screen 25 comprising pixel groups 26, four pixel groups 26 being shown in the figures 2 And 3 , each group of pixels 26 comprising four display pixels Pix.

[0044] In figure 2 , the light-emitting diodes CA of the display pixels Pix of each group of pixels 26 are contiguous. A disadvantage is that, when the lateral dimensions of the display pixels Pix are reduced, the display pixels Pix of the same group of pixels 26 may not be individually distinguished by an observer who will then perceive a single image pixel.

[0045] In figure 3 , each group of pixels 26 comprises a logic circuit CL, on which the light-emitting diodes CA of the display pixels are arranged, having lateral dimensions large enough so that the light-emitting diodes CA of the display pixels of the same group of pixels 26 are not contiguous. The display pixels Pix of the same group of pixels 26 can thus be distinguished individually by an observer who will then perceive distinct image pixels. A disadvantage is that a significant part of the surface, seen from above, of the group of pixels 26 does not participate in the emission of light while it presents a cost in terms of manufacturing the overall control circuit and the overall display circuit.

[0046] THE figures 4 , 5, et 6 are partial and schematic views, respectively in side section, from above, and from below of an embodiment of a block 28 of pixels. The section of the figure 4 is carried out according to line IV-IV on the figures 5 et 6 .

[0047] Block 28 includes a group 26 of pixels, which includes at least two display pixels. On the figures 4 , 5, et 6 , the pixel group 26 comprises four display pixels Pix. The pixel group 26 comprises a global control circuit 30, which integrates the control circuits of the display pixels Pix and which is covered by a global display circuit 32 which integrates the display circuits of the display pixels Pix. According to one embodiment, the display pixels can be controlled independently of each other. The global control circuit 30 is then configured to control the display pixels independently of each other.

[0048] The overall control circuit 30 comprises a lower face 34 and an upper face 35 opposite the lower face 34, the faces 34 and 35 preferably being parallel. The lower face 34 of the overall control circuit 30 forms the lower face of the pixel group 26. The overall control circuit 30 further comprises conductive pads 36 exposed on the lower face 34. The overall control circuit 30 may comprise a semiconductor substrate, not shown, covered with at least one level of metallization, not shown. In particular, the overall control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular MOS transistors, or TFT transistors.The overall control circuit 30 may further comprise conductive through vias 37 extending over a portion of the thickness of the overall control circuit 30 and making it possible to connect the conductive pads 36 to other electronic components of the overall control circuit or to connect the conductive pads 36 directly to the overall display circuit 32.

[0049] The overall display circuit 32 comprises a lower face 38 and an upper face 39 opposite the lower face 38, the faces 38 and 39 preferably being parallel. The upper face 39 of the overall display circuit 32 forms the upper face of the pixel group 26. The lower face 38 of the overall display circuit 32 is fixed to the upper face 35 of the overall control circuit 30.

[0050] The overall display circuit 32 comprises for each display pixel Pix at least one LED light-emitting diode, preferably at least three LED light-emitting diodes. The overall display circuit 32 may comprise a single-layer or multi-layer structure 33 covering the LED light-emitting diodes and forming the upper face 39. The majority, preferably all, of the radiation emitted by the LED light-emitting diodes of the display pixels is emitted by the upper face 39 of the overall display circuit 32. Preferably, the overall display circuit 32 comprises only the LED light-emitting diodes, and the conductive elements of these LED light-emitting diodes and the overall control circuit 30 comprises all of the electronic components necessary for controlling the LED light-emitting diodes of the overall display circuit 32.Alternatively, the overall display circuit 32 may also include other electronic components in addition to the LEDs. The LEDs may be 2D LEDs, also known as planar LEDs, comprising a stack of planar layers, or 3D LEDs each comprising a three-dimensional semiconductor element covered with an active area.

[0051] The pixel block 28 further comprises a sheath 40 surrounding the pixel group 26. The sheath 40 extends over all of the lateral faces of the pixel group 26. The sheath 40 comprises a lower face 44 and an upper face 45 opposite the lower face 44, the faces 44 and 45 preferably being planar and parallel. The lower face 44 of the sheath 40 forms, with the lower face 34 of the pixel group 26, a lower face 46 of the pixel block 28, also called the contact face hereinafter. Preferably, the lower face 44 of the sheath 40 and the lower face 34 of the pixel group 26 are planar and coplanar, so that the contact face 46 is planar. Preferably, the upper face 45 of the sheath 40 and the upper face 39 of the pixel group 26 are planar and coplanar. The sheath 40 is preferably an insulating material. For example, the sheath 40 is made of silicon oxide (SiO 2 ).

[0052] The pixel block 28 comprises conductive tracks 48 and conductive pads 50, four conductive tracks 48 and four conductive pads 50 being shown as an example in figure 6 The conductive tracks 48 extend on the lower face 34 of the group of pixels 26 and on the lower face 44 of the sheath 40 and the conductive pads 50 rest on the lower face 44 of the sheath 40. Each track 48 is connected, at one end, to one of the conductive pads 50 and is connected, at a first end, to one of the conductive pads 36 of the group of pixels 26. The conductive tracks 48 and the conductive pads 50 are for example made of aluminum (Al) or copper (Cu).

[0053] The block of pixels 28 further comprises diffusing structures 52, the number of diffusing structures 52 being equal to the number of display pixels Pix of the group of pixels 26. Each diffusing structure 52 receives the radiation emitted by one of the display pixels Pix. Each diffusing structure 52 covers a portion of the upper face 45 of the sheath 40 and a portion of the upper face 39 of the group of pixels 26. The transmission of the radiation from the overall display circuit 32 of the group of pixels 26 to the diffusing structures 52 takes place in particular via the upper face 39 of the group of pixels 26 in contact with the diffusing structures 52. Each diffusing structure 52 comprises an upper face 54 for the emission of the radiation emitted by one of the display pixels Pix.

[0054] The pixel block 28 comprises first separating elements 55 present in the overall display circuit 32 and separating the display pixels Pix, and second separating elements 56 separating the diffusing structures 52. The first and second separating elements 55, 56 do not allow the radiation emitted by the light-emitting diodes LED to pass through. The first separating elements 55 are aligned with the second separating elements 56. The first separating elements 55 extend for example over the majority, preferably over at least 75%, more preferably over the entire thickness of the single-layer or multi-layer structure 33 and the light-emitting diodes LED up to the overall control circuit 30. The second separating elements 56 may correspond to air-filled trenches extending over the entire thickness of the diffusing structures 52, or walls reflecting the radiation emitted by the display pixels.These separating elements 55, 56 thus make it possible to prevent the light emitted by a display pixel Pix from diffusing onto the adjacent display pixel, which would modify its spectrum and its emission intensity, and would harm the sharpness of the displayed image. According to one embodiment, all the side walls of each diffusing structure 52 do not allow the radiation emitted by the light-emitting diodes LED to pass through. For this purpose, the outer side walls of the diffusing structure 52 may be covered with a coating opaque to the radiation emitted by the light-emitting diodes LED and / or reflecting the radiation emitted by the light-emitting diodes LED and / or with an air film. This makes it possible to avoid optical crosstalk between adjacent pixel blocks 28.

[0055] For each display pixel Pix, the diffusing structure 52 partially fulfills a waveguide function for the radiation emitted by the display pixel Pix so that, in operation, substantially at least 50%, preferably at least 75%, more preferably at least 90%, even more preferably 100% of the face 54 of the diffusing structure 52 emits light. The ratio between the sum of the areas of the emission faces 54 of the diffusing structures 52 and the area of ​​the upper face 39 of the group of pixels 26 is greater than 2, preferably greater than 5, preferably greater than 50, more preferably greater than 500.

[0056] According to one embodiment, each display pixel comprises first, second and third display sub-pixels adapted to emit radiation at first, second, and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light, i.e., radiation whose wavelength is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0057] The sheath 40 may be reflective for the radiation emitted by the display pixels. For example, the sheath 40 may be composed of an opaque material that is reflective for the radiation emitted by the display pixels. The sheath 40 may be made of a transparent or diffusing material. In this case, a portion of the radiation emitted by the overall display circuit 32 may reach the diffusing structures 52 by passing through the sheath 40. Preferably, the separating elements 55 then further comprise third separating elements extending into the sheath 40 in the extension of the second separating elements 56. As a variant, a reflective wall for the radiation emitted by the display pixels may be interposed between the sheath 40 and the side walls of the group of pixels 26 to prevent a portion of the radiation emitted by the overall display circuit 32 from penetrating into the sheath 40.

[0058] The pixel block 28 may have a generally cylindrical shape with a cross section that may have different shapes, such as, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal. For example, on the figures 5 et 6 , the pixel block 28 is shown with a square cross section. The pixel group 26 may have a generally cylindrical shape with a cross section that may have different shapes, such as, for example, an oval, circular or polygonal shape, including triangular, rectangular, square or hexagonal. For example, on the figures 5 et 6 , the pixel group 26 is shown with a square cross section. The maximum lateral dimension of the pixel block 28 in top view may be between 100 µm and 500 µm. The maximum lateral dimension of the pixel group 26 in top view may be between 10 µm and 200 µm. The cladding 40 may completely surround the pixel group 26 and the minimum dimension of the cladding 40 in the plane of the lower face 34 may be between 5 µm and 5 mm. The thickness of the pixel block 28 may be between 20 µm and 750 µm. The thickness of the pixel group 26 may be between 20 µm and 750 µm. The thickness of the sheath 40 measured orthogonally to the lower face 34 may be identical to the thickness of the pixel group 26. The thickness of the overall control circuit 30 may be between 10 µm and 725 µm. The thickness of the overall display circuit 32 may be between 10 µm and 725 µm.In bottom view, the distance between the center of a pad 50 and the center of the pixel group 26 may be between 50 µm and 300 µm. The thickness of each separating element 56, 55 measured in the top view may be between 2 µm and 3 µm. The maximum distance between the centers of the electrically conductive pads 36 may be between 0.5 µm and 2 mm and the minimum distance between the centers of the pads 50 may be between 1 µm and 5 mm, preferably between 5 µm and 3 mm.

[0059] There figure 7 is a schematic top view of a portion of an exemplary display screen 60 comprising pixel blocks 28, with four pixel blocks 28 shown in the figure 7 , each block of pixels 28 comprising four display pixels Pix. A gap 61 may be present between two adjacent blocks of pixels 28. The gap 61 may have a thickness of between 1 µm and 50 µm. At least 50%, preferably at least 75%, of the surface of the display screen 60 seen by an observer corresponds to emission surfaces of groups of pixels 26. The display pixels Pix of the same group of pixels 26 can thus be distinguished individually by an observer who will then perceive distinct image pixels. Furthermore, the entire upper face 39 of the group of pixels 26 participates in the emission of light.

[0060] Each diffusing structure 52 may have a single-layer structure or a multi-layer structure. The diffusing power of the face 54 at a given location on the face 54 is referred to as the percentage between the optical power leaving the face 54 for a unit area at said given location and the optical power injected into the diffusing structure 52 by the overall display circuit 32. According to one embodiment, the diffusing power of the face 54 is between 0.5% and 50% at any location on the face 54.

[0061] There figure 8 is a partial and schematic sectional view of an embodiment of the diffusing structure 52. According to one embodiment, the diffusing structure 52 comprises texturing on the emission face 54. The diffusing structure 52 may correspond to a layer of transparent material to which a surface texturing is applied. The texturing may correspond to polishing. The layer of transparent material may be made of polymer, silicone, or silicon oxide. The thickness of the layer of transparent material may be between 0.01 µm and 100 µm. The arithmetic mean roughness Ra of the emission face 54 is between 0.1 µm and 5 µm.

[0062] According to one embodiment, each diffusing structure 52 is a layer of a diffusing material.

[0063] There figure 9 is a schematic view illustrating an example of a diffusing material comprising a matrix 62 in which reflective particles 63 are dispersed. The matrix 62 may be made of a material transparent to the radiation emitted by the display pixels Pix. The matrix 62 may comprise silicon oxide (SiO 2 ), a silicone polymer, an epoxy polymer, an acrylic polymer or a polycarbonate. The particles 63 are, for example, particles of titanium oxide (TiO 2 ). The thickness of the layer of a diffusing material may be between 2 µm and 2 mm.

[0064] Each diffusing structure 52 may at least partly have a waveguide structure. This advantageously makes it possible to guide the radiation emitted by display pixel Pix throughout the diffusing structure 52 so that the emission of the radiation occurs over the entire corresponding emission face 54.

[0065] There figure 10 is a partial and schematic sectional view of another embodiment of the diffusing structure 52 having in part a waveguide structure and comprising, from top to bottom: an upper sheath 64 delimiting the emission face 54; a core 66; a lower sheath 68, the core 66 being sandwiched between the lower sheath 68 and the upper sheath 64; and micrometric-sized relief patterns 70 resting on the lower sheath 68 on the side of the core 66.

[0066] The core 66 may have a single-layer structure or a multi-layer structure. In the case where the core has a multi-layer structure, all the layers composing the core 66 have substantially the same refractive index. The upper cladding 64, the lower cladding 68, and the patterns 70 may be composed of the same material or different materials. The patterns 70 may be of the same material as the lower cladding 68. In particular, the patterns 70 and the lower cladding 68 may constitute a single-piece structure. In particular, the patterns 70 and the lower sheath 68 may correspond to an air film at least for the part of the diffusing structure 52 facing the sheath 40. As a variant, for the part of the diffusing structure 52 facing the sheath 40, the lower sheath 68 corresponds to an air film and spacers interposed between the sheath 40 and the core 66 form the patterns 70.The refractive index of the material making up the core 66 is greater than the refractive index of the material making up the upper cladding 64, the lower cladding 68 and the patterns 70 or, in the case where the upper cladding 64, the lower cladding 68 and / or the patterns 70 are made of different materials, the refractive indices of the materials making up the upper cladding 64, the lower cladding 68 and the patterns 70. The upper cladding 64 may not be present, the emission face 54 then corresponding to the upper face of the core 66. The lower cladding 68 may not be present between the core 66 and the cladding 40 and be replaced by a film of air between the core 66 and the cladding 40, held by spacers interposed between the core 66 and the cladding 40. The refractive index of the lower cladding 68 in contact with the upper face 39 of the pixel group 26 is lower than the refractive index of the single-layer or multi-layer structure 33.The upper sheath 64 comprises a face 72 in contact with the core 66. Preferably, the face 72 is flat and parallel to the upper face 54. The lower sheath 68 comprises a face 74 on which the patterns 70 rest and which is, outside the patterns 70, in contact with the core 66. The upper sheath 64 can also serve as a protective covering for the core 66.

[0067] The patterns 70 increase the extraction of the radiation injected into the waveguide 52. The patterns 70 may have the same shape or different shapes. For example, each pattern 70 may include a planar face 76 inclined relative to the upper face 54. For example, each pattern 70 may have a prismatic shape. Alternatively, the patterns 70 may rest on the upper cladding 64 on the side of the core 66.

[0068] According to one embodiment, the thickness of the core 66 may be between 2 µm and 1 mm. According to one embodiment, the thickness of the upper cladding 64 may be between 1 µm and 150 µm, preferably between 30 µm and 80 µm. According to one embodiment, the thickness of the lower cladding 68 may be between 1 µm and 150 µm. The maximum height of each pattern 70, measured relative to the face 74, may be between 0.5 µm and 100 µm, preferably between 1 µm and 10 µm. The patterns 70 may each have a width of less than 20 µm, preferably less than 12 µm, more preferably between 2 µm and 6 µm.

[0069] According to one embodiment, the core 66 may be made of polycarbonate (PC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), or cyclic olefin polymer (COP). According to one embodiment, the upper cladding 64, the lower cladding 68, and / or the patterns 70 may be made from an optically clear adhesive (OCA), in particular a liquid optically clear adhesive (LOCA), or from a low refractive index material, or from an epoxy / acrylate glue, or from a film of a gas or a gas mixture. According to one embodiment, the refractive index of the core 66 is between 1.45 and 1.7, and the refractive index of the upper cladding 64, the lower cladding 66, and the patterns 70 is between 1 and 1.55.The difference between the refractive index of the core 66 and the refractive index of the upper cladding 64, the lower cladding 66, and the patterns 70 is greater than 0.07, preferably greater than 0.1. The waveguide 52 may be made using a sheet-to-sheet procedure, or a roll-to-roll procedure. The patterns 70 may be made by die-casting or by inkjet printing.

[0070] There figure 11 is a partial and schematic sectional view of another embodiment of the diffusing structure 52 having in part a structure of the waveguide having a structure similar to that shown in figure 10 , with the difference that the patterns 70 are provided at the interface between the core 66 and the upper sheath 64. Furthermore, in figure 11 , the emitting face 54 has a texturing improving the diffusion of the emitted light. For example, the texturing comprises the formation of impressions in the upper face 54 forming lenses of micrometric size.

[0071] There figure 12 is a partial, schematic sectional view of another embodiment of the diffusing structure 52 having in part a waveguide structure having a structure similar to that shown in figure 10 with the difference that the patterns 70 promote the diffusion of the light guided by the waveguide. Alternatively, the patterns 70 are not present. In this case, the interface between the lower cladding 68 and the core 66 is inclined relative to the interface between the upper cladding 64 68 and the core 66 and relative to the emission face 54.

[0072] There figure 13 is a partial and schematic sectional view of another embodiment of the diffusing structure 52 having a structure similar to that shown in figure 12 with the difference that the patterns 70 which promote the dispersion of the light guided by the waveguide are located on the upper face 54.

[0073] The surface density of the patterns 70 of the diffusing structure 52 may not be constant. In particular, the surface density of the patterns 70 may increase as one moves away from the radiation injection zone in the diffusing structure 52. For example, when the radiation is injected into the diffusing structure 52 on an edge of the diffusing structure 52, the surface density of the patterns 70 increases as one moves away from this edge. The variation in the surface density of patterns makes it possible to maintain uniformity in the spectral density of the flux of the front radiation emitted by the emission face 54 while the spectral density of the flux of the radiation propagating in the diffusing structure 52 decreases as one moves away from the radiation injection zone in the diffusing structure 52.

[0074] There figure 14 is a partial, schematic, sectional view of a more detailed embodiment of the pixel group 26 comprising three display subpixels.

[0075] According to one embodiment, the overall control circuit 30 comprises from bottom to top in figure 14 : a semiconductor substrate 80, for example monocrystalline silicon, an insulating layer 82 delimiting the lower face 34 and the conductive pads 36 exposed on the lower face 34;MOS transistors 84 or other types conventionally used in integrated circuits, for example bipolar transistors (BJTs), formed in and on the substrate 80. These transistors could also be thin-film transistors (TFTs) deposited on a substrate of a nature other than silicon, for example a polymer substrate, or even deposited directly on the back face of the LEDs. In this case the LEDs form the substrate and the manufacturing process is done in reverse order compared to what was described previously, that is to say the metallization levels first (stack 85) and the passive and active components last;a stack 85 of insulating layers, for example made of silicon oxide and / or silicon nitride, covering the substrate 80 and the conductive tracks 86 of several metallization levels formed between the insulating layers of the stack 85 including in particular pads 88 exposed on the upper face 35 of the overall control circuit 30, the conductive tracks 86 of the first metallization level possibly being made of polycrystalline silicon and forming in particular the gates of the MOS transistors 82 and the conductive tracks 86 of the other metallization levels possibly being metal tracks, for example made of aluminum, silver, copper or zinc; and the conductive and laterally insulated vias 37, also called TSV (English acronym for Through Silicon Vias) passing through the substrate 80 and connecting the pads 36 to pads 90 of the first metallization level of the stack 85. ;

[0076] According to one embodiment, the overall display circuit 32 comprises from bottom to top in figure 14 : a support 91 forming the lower face 38 of the overall display circuit 32 in contact with the upper face 35 of the overall control circuit 30 and comprising conductive pads 92 exposed on the lower face 38, in contact with the pads 90, and a multilayer insulating structure 93, for example made of silicon oxide and silicon nitride, extending between the pads 92 and covering the pads 92 and comprising openings 94 exposing portions of the pads 92; microwires or nanowires 95, called wires hereinafter (six wires being shown), each wire 95 being in contact with one of the pads 92 through one of the openings 94; an insulating layer 96 extending on the lateral sides of a lower portion of each wire 95 and extending on the insulating layer 93 between the wires 95;a shell 98 comprising a stack of semiconductor layers covering an upper portion of each wire 95 and extending over the insulating layer 96 between the wires 95, the shell 98 comprising in particular an active layer which is the layer from which the majority of the radiation provided by the light-emitting diode is emitted and comprising, for example, confinement means, such as multiple quantum wells; a conductive and reflective layer 100, extending over the shell 98 between the wires 95; a transparent conductive layer 102 forming an electrode covering, for each wire 95, the shell 98 and extending, in addition, over the conductive layer 100 between the wires 95;photoluminescent blocks 104 covering certain sets of light-emitting diodes LED or blocks transparent to the radiation emitted by the light-emitting diodes, each photoluminescent block comprising phosphors adapted, when excited by the light emitted by the associated light-emitting diodes LED, to emit light at a wavelength different from the wavelength of the light emitted by the associated light-emitting diodes LED; an insulating layer 106 covering the upper face of each block 104, the insulating layer 106 possibly not being present; a protective layer 108 covering the insulating layers 106, the side faces of the blocks 104 and the electrode layer 102 between the blocks 104;walls 110 between the blocks 104, each wall 110 possibly comprising a core 112 surrounded by a coating 114 reflecting the wavelength of the radiation emitted by the photoluminescent blocks 104 and / or the light-emitting diodes LED; a colored filter 116 covering at least some of the photoluminescent blocks 104; and an encapsulation layer 118 covering the entire structure.;

[0077] The separating elements 55 described above are not shown in figure 4 and can surround all display subpixels.

[0078] Each wire 95 may have an elongated semiconductor structure. Each wire 95 may have a generally cylindrical shape with a cross section that may have different shapes, such as, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal. Each wire 95 has, for example, an average diameter, corresponding for example to the diameter of the disc having the same area as the cross section of the wire 95, of between 5 nm and 5 µm, preferably between 100 nm and 2 µm, more preferably between 200 nm and 1.5 µm and a height greater than or equal to greater than 1 time, preferably greater than or equal to 3 times and even more preferably greater than or equal to 5 times the average diameter, in particular greater than 500 nm, preferably between 1 µm and 50 µm. The wires 95 comprise at least one semiconductor material.The semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, e.g., GaN, AlN, InN, InGaN, AlGaN or AlInGaN, a II-VI compound, or a combination of two or more of these compounds.

[0079] The conductive layer 102 is adapted to polarize the active layers of the shells 98 and to allow the electromagnetic radiation emitted by the light-emitting diodes to pass through. The material forming the conductive layer 102 may be a transparent and conductive material such as graphene, or silver, or a transparent and conductive oxide (or TCO, acronym for Transparent Conducting Oxide), in particular indium-tin oxide (or ITO, acronym for Indium Tin Oxide), zinc oxide doped or not with aluminum, or with gallium or boron. For example, the conductive layer 102 has a thickness of between 20 nm and 500 nm, preferably between 20 nm and 100 nm.

[0080] The conductive layer 100, the conductive tracks 86 and the conductive pads 36, 88, 92 may be made of metal, for example aluminum, silver, platinum, nickel, copper, gold or ruthenium or an alloy comprising at least two of these compounds, in particular the PdAgNiAu alloy or the PtAgNiAu alloy.

[0081] Each of the insulating layers 85, 93, 96, 106, 108, 118 is made of a material chosen from the group comprising silicon oxide (SiO 2 ), silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4 ), silicon oxynitride (in particular of general formula SiO x N y , for example Si 2 ON 2 ), hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), or aluminum oxide (Al 2 O 3 ).

[0082] According to one embodiment, all the light-emitting diodes of a display pixel Pix emit light radiation at the same wavelength. The diffusing structure 52 covering this display pixel Pix can then contain phosphors adapted, when excited by the light emitted by the display pixel, to emit light at the desired color. This makes it possible to carry out the conversion of the wavelength of the radiation at the diffusing structure 52 and not at the display pixel. Therefore, compared to the structure of the display pixel described previously in relation to the figure 14 , the photoluminescent blocks 104 and the color filters 116 may not be present. Furthermore, the power density received by the phosphors present in the diffusing structures 52 is lower than the power density received by the phosphors when they are integrated directly into the display pixels. This is advantageous in particular when the phosphors comprise quantum dots whose conversion properties can degrade over time all the more quickly as the power density received by these quantum dots is high.

[0083] THE figures 15 à 26 are partial and schematic sectional views of structures obtained at successive stages of an embodiment of the display screen 60 shown in figure 7 .

[0084] There figure 15 represents the structure obtained after a step of forming an optoelectronic plate 120 and a step of forming a logic plate 122. The optoelectronic plate 120 comprises a support 124 having an upper face 126 and a lower face 128 and light-emitting diodes LED formed on the upper face 126. The optoelectronic plate 120 comprises light-emitting diodes LED of the global display circuits of several groups of pixels. The logic plate 122 comprises the global logic control circuits of several groups of pixels.

[0085] There figure 16 represents the structure obtained after a step of fixing the optoelectronic plate 120 on the logic plate 122 on the side of the light-emitting diodes LED and the removal of the support 124 from the optoelectronic plate 120. The stack 130 of the logic plate 122 and the optoelectronic plate 122 minus the support 124 is called a display pixel plate thereafter.

[0086] There figure 17 represents the structure obtained after a step of forming an optical structure 132 on the optoelectronic plate 120 and forming the second separating elements 55 in the optical structure 132 and the light-emitting diodes LED. The optical structure 132 may have a single-layer structure or a multi-layer structure. The second separating elements 55 may comprise opaque and / or reflective walls. The optical structure 132 may comprise the photoluminescent blocks and the color filters described above. Alternatively, the optical structure 132 may not be present.

[0087] There figure 18 represents the structure obtained after a step of fixing the display pixel plate 130 to a handle 134 on the side of the optoelectronic plate 120.

[0088] There figure 19 represents the structure obtained after a step of thinning the logic plate 122, a step of forming TSVs 37 through the thinned logic plate 122, and the formation of conductive pads 36, on the side of the lower face of the display pixel plate 130, electrically connected to the TSVs 37.

[0089] There figure 20 represents the structure obtained after a step of cutting the display pixel plate 130 to separate the pixel groups 26. This step can be carried out by sawing. Each pixel group 26 thus delimited comprises an overall display circuit 32 comprising the light-emitting diodes LED of at least two display pixels, preferably four display pixels, and an overall circuit 30 for controlling the light-emitting diodes of the display pixels of the pixel group 26.

[0090] There figure 21 represents the structure obtained after a step of transferring at least one group of pixels 26 from the handle 134 to a handle 136, the group of pixels 26 being fixed to the handle 136 on the side of the overall display circuit 32. According to one embodiment, this transfer step may comprise a first transfer of the group of pixels 26 from the handle 134 to an intermediate handle, not shown, the group of pixels 26 being fixed to the intermediate handle on the side of the overall control circuit 30 and the transfer of the group of pixels 26 from the intermediate handle to the handle 136.

[0091] There figure 22 represents the structure obtained after a step of forming a dielectric layer on the handle 136 and on the display pixel block, a planarization step to expose the overall control circuit 30 of the pixel group 26 and thus delimit the sheath 40 surrounding the pixel group 26, and a step of forming the tracks 48 and the contact pads 50, the tracks 48 extending on the overall control circuit 30 of the pixel group 26 and on the sheath 40, the contact pads 50 resting on the sheath 40. The planarization step may comprise a CMP step. The pixel block 28 is then partially formed. For each pixel block 28, the pixel group 26 of the pixel block 28 comprises the light-emitting diodes associated with several display pixels which are controlled by the same overall control circuit 30.This advantageously makes it possible to reduce the number of conductive pads 36 required for powering / controlling these display pixels. The reduced number of conductive pads 36 per display pixel, and the formation of the contact pads 50 makes it possible to increase the spacing between the contact pads 50. This facilitates the subsequent installation, described below, of the pixel blocks 28 on a panel, by reducing the constraints on the precision of the positioning of the pixel blocks 28 at the time of transfer to the panel.

[0092] There figure 23 represents the structure obtained after a step of transferring the partially formed pixel block 28 from the handle 136 to another handle 137 on the side of the overall control circuit 30 of the pixel group 26, for example by means of a layer of glue 138.

[0093] There figure 24 represents the structure obtained after a step of forming a diffusing layer 139 on the cladding 40 and the pixel group 26. According to one embodiment, the formation of the diffusing layer 139 comprises the formation on the emissive face of the display pixel block of a layer of a diffusing material. According to one embodiment, the formation of the diffusing layer comprises the formation on the emissive face of the display pixel block of a layer of a transparent material and the formation of a texturing on the surface of the layer.

[0094] There figure 25 represents the structure obtained after the formation of the second separation elements 56 in the diffusing layer 139 to obtain the diffusing structures 52. The second separation elements 56 are formed in alignment with the first separation elements 55 of the pixel group 26, and, when present, with the third separation elements present in the cladding 40. According to one embodiment, the formation of the first separation elements 56 comprises the formation of trenches in the diffusing structure 52. According to another embodiment, the formation of the second separation elements 56 comprises the formation, in the diffusing structure 52, of reflective walls over the entire thickness of the diffusing structure 52.The alignment of the second separating elements 56 with the first separating elements 55 is advantageously easier and more precise to achieve by forming the second separating elements 56 in the diffusing structure 52 resting on the pixel group 26 and the cladding 40 compared to the case where it would be obtained by depositing the pixel group 26, containing the first separating elements 55, on the diffusing structure 52 containing the second separating elements 56. The pixel block 28 is then obtained.

[0095] There figure 26 represents the structure obtained after a step of transferring blocks of pixels 28 onto a display screen panel 140. The panel 140 may comprise a support 142 on which conductive tracks 144 extend. Each contact pad 50 of each block of pixels 28 is in contact with one of the conductive tracks 144. The transfer may be carried out by individual blocks of pixels 28 or by groups of blocks of pixels 28. The enlargement and the respective spacing of the contact pads 50 relative to the conductive pads 36 advantageously makes it possible to reduce the precision constraints and allows faster and less expensive positioning of the blocks of pixels 28 on the panel 140.

[0096] Tests were carried out including displaying the image of the figure 27 on different display screens. For these tests, the pixel groups each comprise four display pixels. The figures 28, 29, 30, 31, et 32 were obtained by simulations.

[0097] THE figures 28 et 29 each represent the image as it appears to an observer when the display screen has the structure shown in figure 2 , the area occupied by the groups of pixels in top view corresponding to 1% of the surface of the display screen in figure 28 and 1% of the display screen area in figure 29 The image pixels of the four display pixels in the same group are difficult to distinguish by an observer.

[0098] THE figures 30, 31, et 32 each represent the image as it appears to an observer when the display screen has the structure shown in figure 7 , the area occupied by the pixel blocks in top view corresponding to 100% of the display screen area in figure 30 , at 80% of the display screen area in figure 31 , and 64% of the display screen area in figure 32The image pixels of the four display pixels of the same group are distinguishable by an observer.

[0099] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the diffusing structure may include a waveguide-forming portion as shown in figures 10 to 13and a part made of a diffusing material. Furthermore, although in the embodiments described above, the group of pixels 26 comprises two chips fixed to each other, it is clear that the group of pixels can comprise a single chip, the overall circuit for controlling the light-emitting diodes being produced in an integrated manner with the light-emitting diodes or not being integrated into the group of pixels. Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above. The scope of the invention is defined by the claims.

Claims

1. Display block (28) comprising: - an optoelectronic circuit (26) comprising light-emitting diodes (LED) of at least two display pixels (Pix) and having a first surface of emission (39) of the light radiations of the light-emitting diodes; and characterized in that it comprises: - diffusing structures (52) covering the optoelectronic circuit (26), each diffusing structure being in contact with a portion of the first emission surface (39) and having a second surface of emission (54) of the light radiations of the light-emitting diodes of one of the display pixels, the ratio of the sum of the areas of the second emission surfaces (54) to the area of the first emission surface (39) being greater than 2.

2. Display block according to claim 1, wherein the display pixels (Pix) are separated by first separation elements which do not let through the light radiations of the light-emitting diodes (LED) and wherein the diffusing structures (52) are separated by second separation elements (56) which do not let through the light radiations of the light-emitting diodes (LED), the first separation elements (55) being aligned with the second separation elements (56) at the level of the first emission surface (39).

3. Display block according to claim 1 or 2, wherein each second emission surface (54) is a diffusing surface.

4. Display block according to claim 1 or 2, wherein each diffusing structure (52) is at least partly made of a diffusing material or at least partly formed of a waveguide.

5. Display block according to claim 1 or 2, wherein each diffusing structure (52) comprises patterns (70) distributed on a surface and reflecting or diffusing the light radiations.

6. Display block according to any of claims 1 to 5, comprising an electrically-insulating sheath (40) surrounding the optoelectronic circuit (26), the diffusing structures (52) covering the sheath, in contact with the sheath or separated from the sheath by an air film via spacers interposed between the sheath and the diffusing structures.

7. Display block according to claim 6, wherein the optoelectronic circuit (26) comprises a third surface (34) opposite to the first surface (39) and first electrically-conductive pads (36) exposed on the third surface, the display block (28) comprising electrically-conductive tracks (48) in contact with the first electrically-conductive pads (36) and continued by second electrically-conductive pads (50) extending on the sheath (40).

8. Display block according to any of claims 1 to 5, wherein each diffusing structure (58) only receives the light radiation of the light-emitting diodes (LED) of one of the display pixels.

9. Display block according to any of claims 1 to 8, wherein at least one of the diffusing structures (52) contains luminophores.

10. Display block according to any of claims 1 to 9, wherein the display pixels (Pix) of the optoelectronic circuit (26) are contiguous and wherein the first emission surface (39) is centered with respect to the surface formed by the second emission surfaces (54).

11. Display block according to any of claims 1 to 10, wherein the optoelectronic circuit (26) comprises four display pixels (Pix).

12. Display block according to any of claims 1 to 11, wherein the optoelectronic circuit (26) comprises a single circuit for controlling (30) all the light-emitting diodes (LED) of the display pixels (Pix).

13. Display screen (60) comprising a slab (140) and a plurality of display blocks (28) according to any of claims 1 to 12 bonded to the slab.

14. Display screen according to claim 13, wherein the display pixels (Pix) of the display blocks (28) are arranged in rows and in columns, and wherein the optoelectronic circuit (26) of each display block comprises at least four display pixels (Pix) belonging to at least two adjacent rows and to at least two adjacent columns.

15. Method of manufacturing display blocks (28) according to any of claims 1 to 12, comprising the following steps: a) forming of a wafer (130) comprising a plurality of said optoelectronic circuits (26); b) cutting of the wafer to separate said optoelectronic circuits; and c) for each separate optoelectronic circuit, forming of the diffusing structures (52) covering the optoelectronic circuit (26).

16. Method according to claim 14, further comprising, at step a), the forming of first separation elements (55) in each optoelectronic circuit (26) separating the display pixels (Pix), and, at step c), the forming of second separation elements (56) separating the diffusing structures and aligned with the first separation elements.