Semiconductor assembly with waveguide and glass substrate

Description

TECHNICAL FIELD

[0001] The invention relates to a semiconductor assembly and a method of making a semiconductor assembly.BACKGROUND

[0002] Silicon photonics are a good candidate for low cost and high performance components, such as for increasing data centric technology. But packaging silicon photonics can be challenging, and result in compatibility and integration challenges due to mode field diameter mismatch and tight alignment tolerance. It is desired to have a low cost and efficient packaging technology that address these concerns, and other technical challenges.

[0003] Documents US 2021 / 041649 A1 and EP 3 872 547 A1 reflect the state of the art. Document EP 4 155 788 A1 is relevant within the terms of Article 54(3) EPC.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various assemblies discussed in the present document. FIG. 1 illustrates a semiconductor assembly in an example not encompassed by the wording of the claims but which is considered useful for understanding the invention. FIG. 2 illustrates a semiconductor assembly in an example. FIG. 3 a flow diagram of a method of making a semiconductor assembly in an example not encompassed by the wording of the claims but which is considered useful for understanding the invention. FIG. 4 illustrates a system level diagram. DETAILED DESCRIPTION

[0005] A semiconductor assembly in accordance with the invention is defined in claim 1. A method of making a semiconductor assembly in accordance with the invention is defined in claim 10.

[0006] Note that the examples and / or embodiments discussed hereinbelow in relation to any of the figures 1, 3A-I and 4 are not encompassed by the wording of the claims but are considered useful for understanding the invention.

[0007] Disclosed herein is a semiconductor assembly and method of making the same for Silicon Photonics (SiP) packaging with a waveguide. Here, laser based technology is used to integrate a photonic integrated circuit (PIC), an electronic integrated circuit (EIC) and a substrate, with low-loss coupling between an optical fiber and SiP packaging. Laser made glass-to-glass bonds are used, and an embedded waveguide is made through laser direct writing (LDW).

[0008] Silicon photonics (SiP) is a combination of silicon integrated circuits and semiconductor lasers, from which photonic integrated circuits (PICs) can be made. PICs can produce or detect optical light with single or multiple frequencies. PICs can extend, enable, and increased data transmission, while consuming less power than conventional circuits. Such PICs can allow for energy efficient bandwidth scaling. PICs can allow for faster data transmission over longer distances compared to traditional electronics.

[0009] However, silicon photonics packaging can be challenging. Fiber coupling compatibility and integration with electronic integrated circuits (EIC) can be difficult due to mode field diameter mismatches and tight alignment tolerances. The use of waveguides in glass can be a good solution for such SiP packaging, due in part to the optical and mechanical properties of glass.

[0010] Discussed herein, laser based technology can be leveraged to integrate PICs, EICs, and substrates. Laser based technology can also enable in situ waveguide formation in glass substrates to create low-loss coupling between SiP packages and coupling fibers. In situ formation of the waveguide can minimize the coupling loss between PIC and the package. Both low temperature glass-to-glass bonding by laser and embedded waveguide in glass by laser direct writing can be used. The discussed methods and devices can allow for creation of low loss and high voltage compatible SiP packaging.

[0011] FIG. 1 illustrates a semiconductor assembly 100 in an example. The semiconductor assembly 100 can include a first glass substrate 110, a second glass substrate 112, a glass adapter 114, a first integrated circuit 120, a second integrated circuit 130 with an optical port 132, a waveguide 140, a fiber port 144, a bridge die 150 with connections 152, and a substrate 160.

[0012] In the assembly 100, the substrate 160 can host the glass substrates 110 and112. The bridge die 150 can be situated in the glass substrate 112, connecting the first integrated circuit 120 and the second integrated circuit 130. The waveguide 140 can be situated within a glass adapter 114, and aligned with an optical port 132 of the second integrated circuit 130.

[0013] The glass substrates 110, 112, and adapter 114, can be, for example, a silicon dioxide or borosilicate glass. In some cases, alternative glass materials can be used. Shown in FIG. 1, the glass substrates 110, 112 are two stacked and bonded glass substrates, while the glass adapter 114 is a separate piece hosting the waveguide 140 and fiber coupling unit. In some cases, more or less glass substrates can be stacked and used. The glass substrates 110, 112 can serve, for example, as an interposer between the first and second integrated circuit dies 120, 130. In assembly 100, the bridge die 150 can be at least partially embedded in the glass substrate 110.

[0014] The glass substrates 110, 112 can be bonded to each other, such as through laser techniques. In some cases, the glass substrates 110, 112 can be fused together by one or more bonds, such as by laser scanning. The two glass substrates can be bonded in a hermetic and gas-tight seal.

[0015] The glass adapter 114 can, for example, be a coupling adapter for connecting the second integrated circuit 130 (e.g., a PIC) to one or more optical fibers. The coupling adapter can include a coupling port 144, and host the waveguide 140 itself. The waveguide 140 can be a laser-modified pathway through the glass adapter 114.

[0016] The first integrated circuit 120 can be an electronic integrated circuit. The second integrated circuit 130 can be a photonic integrated circuit (PIC). A PIC can be configured to produce and receive multiple optical signals, such as in the visible or infrared (IR) spectrum. In some cases, either or both of the first integrated circuit 120 and the second integrated circuit 130 can be encapsulated by an over-mold layer (not shown). The second integrated circuit 130 can include single or multiple optical port 132 where optical signals exit the second integrated circuit 130 towards the waveguide 140 in the glass adapter 114.

[0017] The waveguide 140 can be a laser-modified waveguide situated in the glass adapter 114. The glass adapter 114 can be a separate piece of glass bonded to the other glass substrate and aligned with the second integrated circuit die 130. The waveguide 140 can be in the glass adapter 114, extending between the coupling port 144 and the optical port 132 of the second integrated circuit 130.

[0018] The waveguide 140 can be configured to guide electromagnetic waves, such as an optical signal produced by the second integrated circuit 130 and provided at the optical port 132, from the assembly 100 out towards an outlet. The waveguide 140 can be connected to one or more optical fibers or other types of outputs for such an optical signal. For example, the waveguide 140 can be aligned with the coupling port 144 which is size and shaped for connection to an optical fiber. In some cases, such a coupling port 144 can include V-grooves for connection with an optical fiber.

[0019] The waveguide 140 can be a laser-modified guide, such as by laser direct writing (LDW), as discussed below with reference to FIGS. 3A-I below. The waveguide 140 can be manufactured within the glass adapter 114 (e.g., the coupling adapter) for proper alignment with the optical port 132 on the second integrated circuit 130. For example, the waveguide 140 can be cut at an angle allowing for appropriate alignment and guidance of optical signals produced by the second integrate circuit 130 (e.g., a PIC). In some cases, the waveguide 140 can be curved, as shown in FIG. 2. In some cases, the coupling port 144 can exit out the glass adapter 114 on a top surface, a side surface, or other appropriate surface.

[0020] The bridge die 150 can be an embedded multi-die interconnect bridge (EMIB). The bridge die 150 can additionally include connections 152, such as vias, traces, or other electrical connections so as to connect the first integrated circuit die 120 with the second integrated circuit die 130. The bridge die 150 can be partially or fully embedded in one or more of the glass substrates 110, 112. In some cases, the bridge die 150 can be encapsulated with a mold material. In some cases, the bridge die 150 can be a silicon bridge. In some cases, the bridge die 150 can be an active die, or a passive die.

[0021] When included in a device, the assembly 100 can be partially or fully encased in a housing. The assembly 100 can be used, for example, in a device with a touch screen, keyboard, or other input feature. When shown in cross-section, the architecture of the assembly 100 can be detected. Additionally, the structure of the waveguide 140 in the glass substrates 110, 112, 114, and any coupling adapter can be detected from a cross section, as can a change in refractive index between the glass substrates and the waveguide 140.

[0022] FIG. 2 illustrates a semiconductor assembly 200 with an in situ manufactured waveguide in an example. Assembly 200 includes similar components to those of assembly 100 discussed above, connected in the same fashion. However, the waveguide 240 of assembly 200 is of a different shape. The waveguide 240 is curved instead of angled. For this reason, the waveguide 240 can exit to the coupling port 144 at a top surface of the assembly 200 instead of a side surface. This can allow for flexibility in connections to optical fibers.

[0023] FIGS. 3A-3I illustrate a method 300 of making a semiconductor assembly in an example. The method 300 can include laser based glass bonding of substrates and laser based waveguide formation. These techniques can be accomplished by laser direct writing (LDW).

[0024] First, two glass substrates 110, 112, can be prepared (FIG. 3A). Here, the first glass substrate 110 can include plated through glass via (TGV) 111, and the second glass substrate 112 can include non-plated TGV 113 and a cavity 155. In some cases, multiple cavities can be used, and multiple bridges or other non-bridge devices can be included. Next, the two glass substrates 110, 112, are bonded together by laser scanning (FIG. 3B). In this process, a hermetic and gas-tight seal can be achieved. This method can be accomplished with low heat load. Optionally, a carrier 162 can be used. In some cases, a protection film can be used instead of a carrier 162.

[0025] After the glass substrate bonding, the TGV 113 can be plated (FIG. 3C). The bridge die 150 can then be placed in the cavity 155 (FIG. 3D) and encapsulated in a mold material 157 (FIG. 3E). In some cases, a dielectric material, such as ABF, can be used to encapsulate. The top surface of bridge die cavity 155 can be treated with planar or polish techniques to make it even with the glass 112 surface after bridge encapsulation. In some cases, the bridge die cavity 155 can be underfilled after placement of the first and second integrated circuit dies 120, 130.

[0026] The first and second integrated circuit dies 120, 130 can be placed and electrically connected to the bridge die 150 (FIG. 3F). The first and second integrated circuit dies 120, 130 can be bonded to the bridge die 150 and TGV 113 in the glass substrate 112.

[0027] Once the first and second integrated circuit dies 120, 130 are placed and bonded, the glass adapter 114, which serves as a coupling adapter, can be bonded to the glass substrate 112 (FIG. 3G). The glass adapter 114 can be bonded through laser writing to the glass substrate 112.

[0028] The glass adapter 114 can be a pre-fabricated coupling adapter including the waveguide 140. The glass adapter 114 can further include coupling port 144 for compatibility with optical fibers. The glass adapter 114 can be placed so that it is aligned with the optical port 132 of the second integrated circuit die 130 (a PIC). In some cases, the waveguide 140 can be pre-fabricated in the glass adapter 114. In some cases, the waveguide 140 can be fabricated in situ after placement of the glass adapter 114 and alignment with the optical port 132 (FIG. 3H).

[0029] The pre-fabricated glass adapter 114 can include a pre-fabricated coupling port 144. The coupling port 144 can include etched or otherwise made V-grooves. In some cases, micro-lens arrays fabricated with laser direct writing and chemical etching can be used. In some cases, an isolator can be included to prevent back-reflection in the adapter 114. The coupling port 144 can be on a side or top surface of the adapter 114.

[0030] In situ formation of the waveguide 140 can be done by laser technology. The waveguide can be formed in the glass adapter 114 by laser formation, such as by LDW. The position of the waveguide 140 can be adjusted during formation, based on the placement of the PIC (the second integrated circuit die 130). This can be dynamically updated during the in situ process. In some cases, reference marks can be made on the carrier substrate 162 earlier during the process for easier alignment.

[0031] LDW can include focusing laser energy in three dimensions within the glass adapter 114 and locally transforming the glass adapter 114 media in a linear path. In an example, transforming can include locally modifying an index of refraction due to interaction with laser light. For example, with the waveguide 140, the refractive index of the glass adapter 114 at the waveguide 140 can differ from the refractive index of the rest of the glass adapter 114, once formed. The waveguide can be a local change in the glass, such as a structural modification (e.g., local stresses, material phase change, or material density change) caused by the laser writing.

[0032] Formation of the waveguide 140, such as by LDW, can be done after placement of the glass adapter 114 to maximize coupling efficiency and alignment with the second integrated circuit die 130. In this case, metrology can be used to measure the positioning of both the glass adapter 114 and the second integrated circuit die 130; this methodology can be used to obtain x, y, z coordinate positions. The waveguide 140 can then be formed along an appropriate writing route based on the metrology x, y, z coordinate positions.

[0033] LDW can be sensitive depending on laser focus. Thus, RI can be modulated in the focal plane (or with depth of focus) owing the high laser peak intensity. The focal depth of the laser can be precisely controlled during writing of the waveguide 140. For example, a depth of focus of 1 micrometer can be used with a 0.65 NA lens. By comparison, a depth of focus of 0.4 micrometer can be used with a 0.85 NA lens. The use of such precise LDW techniques for waveguide formation can allow for proper alignment and reduce misalignment. During writing, the z or x-y positions can be varied along the scanning path by controlling the laser beam position. For example, with a propagation loss in the laser can be less than about 0.1 dB / cm.

[0034] Once the glass adapter 114 is attached and the waveguide 140 is formed, the assembly 100 can be attached to a substrate 160 and removed from a carrier 162 (FIG. 3I). At this point, the assembly can be further packaged for use in a device, and optical fibers can be attached via the glass adapter 114.

[0035] FIG. 4 illustrates a system level diagram, depicting an example of an electronic device (e.g., system) that may include a photonic assembly and / or methods described above. In one embodiment, system 400 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 400 includes a system on a chip (SOC) system.

[0036] In one embodiment, processor 410 has one or more processor cores 412 and 412N, where 412N represents the Nth processor core inside processor 410 where N is a positive integer. In one embodiment, system 400 includes multiple processors including 410 and 405, where processor 405 has logic similar or identical to the logic of processor 410. In some embodiments, processing core 412 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 410 has a cache memory 416 to cache instructions and / or data for system 400. Cache memory 416 may be organized into a hierarchal structure including one or more levels of cache memory.

[0037] In some embodiments, processor 410 includes a memory controller 414, which is operable to perform functions that enable the processor 410 to access and communicate with memory 430 that includes a volatile memory 432 and / or a non-volatile memory 434. In some embodiments, processor 410 is coupled with memory 430 and chipset 420. Processor 410 may also be coupled to a wireless antenna 478 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, an interface for wireless antenna 478 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0038] In some embodiments, volatile memory 432 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and / or any other type of random access memory device. Non-volatile memory 434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0039] Memory 430 stores information and instructions to be executed by processor 410. In one embodiment, memory 430 may also store temporary variables or other intermediate information while processor 410 is executing instructions. In the illustrated embodiment, chipset 420 connects with processor 410 via Point-to-Point (PtP or P-P) interfaces 417 and 422. Chipset 420 enables processor 410 to connect to other elements in system 400. In some embodiments of the example system, interfaces 417 and 422 operate in accordance with a PtP communication protocol such as the Intel ®< QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0040] In some embodiments, chipset 420 is operable to communicate with processor 410, 405N, display device 440, and other devices, including a bus bridge 472, a smart TV 476, I / O devices 474, nonvolatile memory 460, a storage medium (such as one or more mass storage devices ) 462, a keyboard / mouse 464, a network interface 466, and various forms of consumer electronics 477 (such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset 420 couples with these devices through an interface 424. Chipset 420 may also be coupled to a wireless antenna 478 to communicate with any device configured to transmit and / or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.

[0041] Chipset 420 connects to display device 440 via interface 426. Display 440 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 410 and chipset 420 are merged into a single SOC. In addition, chipset 420 connects to one or more buses 450 and 455 that interconnect various system elements, such as I / O devices 474, nonvolatile memory 460, storage medium 462, a keyboard / mouse 464, and network interface 466. Buses 450 and 455 may be interconnected together via a bus bridge 472.

[0042] In one embodiment, mass storage device 462 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 466 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and / or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0043] While the modules shown in FIG. 4 are depicted as separate blocks within the system 400, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 416 is depicted as a separate block within processor 410, cache memory 416 (or selected aspects of 416) can be incorporated into processor core 412.

[0044] The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The invention is solely limited by the appended claims.

Claims

1. A semiconductor assembly (200) comprising: a lower first glass substrate (110); an upper electronic integrated circuit, EIC, (120) attached to the first glass substrate (110); an upper photonic integrated circuit, PIC (130) configured to produce and / or receive an optical frequency, the PIC being attached to the first glass substrate (110) and comprising an optical port (132); a bridge die (150) electrically connecting the PIC (130) and the EIC (120), wherein the bridge die(150) is attached to the first glass substrate (110); and a coupling adapter (114) for connecting the PIC (130) to an optical fiber,the coupling adapter (114) being bonded to the first glass substrate (110) and comprising: a coupling port (144) configured for connecting the PIC (130) to an optical fiber; and a waveguide (240) formed in the coupling adapter (140) and extending between the coupling port (144) and the optical port (132) of the PIC (130), wherein the waveguide (240) is curved upwardly so that it exits to the coupling port at a top surface of the assembly (200).

2. The assembly (200) of claim 1, further comprising a second glass substrate (112), wherein the first glass substrate (110) and the second glass substrate (112) are bound to each other by one or more glass-to-glass bonds.

3. The assembly (200) of claim 1, further comprising an optical fiber connecting to the coupling port (144).

4. The assembly (200) of claim 1, wherein the coupling port (144) comprises V-grooves.

5. The assembly (200) of claim 1, wherein the coupling adapter (114) comprises a glass adapter.

6. The assembly (200) of claim 1, wherein the bridge die (150) is silicon bridge die.

7. The assembly (200) of claim 1, wherein the EIC (120) and the PIC (130) are coupled to each other through the bridge die (150) and one or more through one or more power delivery pathways.

8. The assembly (200) of claim 1, further comprising a second glass substrate (112).

9. The assembly (200) of claim 1, wherein the waveguide (240) comprises a laser-modified pathway.

10. A method of making a semiconductor assembly (200), the method comprising: attaching a bridge (150) die to a lower first glass substrate (110); attaching an upper electronic integrated circuit , EIC, (120) to the first glass substrate (110) and the bridge die (150); attaching an upper photonic integrated circuit, PIC, (130) to the first glass substrate (110) and the bridge die (150), wherein the EIC (120) is electrically coupled to the PIC (130) through the bridge die (150) and wherein the PIC (130) is configured to produce and / or receive an optical frequency and comprises an optical port (132); bonding a coupling adapter (114) to the first glass substrate (110), the coupling adapter (114) comprising a coupling port (144) for connecting the PIC (130) to an optical fiber; and forming a waveguide (240) in the coupling adapter (114), the waveguide (240) aligning with the PIC (130) and extending between the coupling port (144) and the optical port (132) of the PIC (130), the waveguide (240) being curved upwardly so that it exits to the coupling port (144) at a top surface of the assembly (200), wherein forming the waveguide (240) comprises a laser direct writing.

11. The method of claim 10, further comprising attaching a second glass substrate (112) to the first glass substrate (110) prior to attaching the bridge die (150), wherein attaching the second glass substrate (112) comprises using glass to glass bonding with a laser.