DOUBLE REBORE DRILLING FOR COST-EFFECTIVE PCB MILLIMETER WAVE PHASE-CONTROLLED GROUP ANTENNAS

Description

BACKGROUNDField

[0001] This disclosure relates generally to a millimeter wave (mmWave) antenna and, more particularly, to a mmWave phased array antenna including interconnected back-drilled vias.Discussion of the Related Art

[0002] Cellular telecommunications companies began deploying fifth generation (5G) radio technology standard for cellular networks in 2019. The 5G radio standard utilizes a higher frequency spectrum than previous generations of commercial communications technologies. MmW phased array antennas are being designed and developed for the 5G protocol that provides increased performance over 4G systems while also reducing costs. 5G mmWave antennas typically require precise manufacturing of printed circuit boards (PCBs) because antenna features on the order of a wavelength are at the limits of manufacturing tolerance of the PCB fabrication process.

[0003] One of the most challenging RF circuits for the development of a PCB based phased array antenna design is the transition structures, i.e., vias, between layers in the PCB. For example, the transition from the feed layer to the radiating elements, where these vias tend to be the largest vias on the PCB structure, is difficult to produce. Generally, these antenna designs include a high layer count PCB that tends toward using microvias as interconnect structures between the layers. This makes for a complex PCB fabrication process that is not suited to low cost high volume manufacturing. Furthermore, there have been PCB fabrication development methods to support fine pitch ball grid array (BGA) packages in application specific integrated circuit (ASIC) designs, where a conventional PCB is used, with plated through hole (PTH) vias, and then a number of subsequent prepreg layers using microvias are added to the PCB structure as a technique to provide trace routing to "break out" of the fine pitch BGA, which otherwise using PTH via technology would prove challenging, or even impossible as pin counts on the BGA ASIC increase. US 20100126010 A1 discloses phased array antennas, wherein the tile sub-array comprises a board and an upper multi-layer board, the board comprises two vias extending to the bottom surface of the board and extending to the top surface of the board, the two vias are interconnected by interconnect, the multi-layer board comprises on each of the top and bottom side dielectric layers that constitute prepreg buildup layers, the beamforming circuitry is provided at the lower portion of the board, and the radiating elements are located at a top side of the board. US 2020212539 A1 discloses a phased array antenna, wherein the plurality of conductive layers and the plurality of via holes may form a plurality of feeding paths, the plurality of via holes may be filled with a conductive material, the conductive patch and the wireless communication circuit may be electrically connected through the plurality of feeding paths, and the conductive patch may be fed through the plurality of feeding paths. Watanabe, A. O., et al., "Low-Loss Impedance-Matched Sub-25-µm Vias in 3-D Millimeter-Wave Packages", IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 10, No. 5, May 2020, pages 870-876 discloses the development of sub-25-µm microvias designed for high-density, 3-D millimeter-wave 5G antenna packages. These microvias are located in the buildup layers to provide vertical electrical interconnections between the redistribution layers and the core substrate.SUMMARY

[0004] The following discussion discloses and describes a mmWave phased array antenna that has particular application to be used in a 5G radio. The antenna is provided as defined by the appended set of claims.

[0005] Additional features of the disclosure will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a profile view of a mmWave phased array antenna including interconnected back-drilled vias; and Figure 2 is a layout illustration of the mmWave antenna showing a beamforming IC, a patch antenna and the interconnected back-drilled vias. DETAILED DESCRIPTION

[0007] The following discussion of the embodiments of the disclosure directed to a mmWave phased array antenna including interconnected back-drilled vias is merely exemplary in nature, and is in no way intended to limit the disclosure or its applications or uses. For example, the discussion herein refers to the antenna as being part of a phased array antenna for a 5G radio. However, as will be appreciated by those skilled in the art, the antenna will have other applications.

[0008] Figure 1 is a profile view a mmWave phased array antenna 10 and figure 2 is a layout illustration of a portion of the mmWave antenna 10, where the antenna 10 can be part of a 5G radio. The antenna 10 includes a PCB structure 12 having a stack of layers 14 including core dielectric layers 16, dielectric insulating prepreg layers 18, copper layers 20 and a feed layer 22, where the number, thickness, configuration, material, etc. of the layers 14 would be designed for a particular antenna as would be well understood by those skilled in the art. Prepreg buildup layers 26 are formed on a top of the PCB structure 12 and stacked microvias 28 are formed through the layers 26, where the layers 26 and the microvias 28 support BGA breakup. A beamforming IC 32 is provided on top of the buildup layers 26 and includes the circuitry necessary for beam phase combining and beam steering for multiple radiating elements in the phased array antenna 10 in a manner well understood by those skilled in the art, where the vias 28 provide an electrical connection to the beamforming IC 32. Multiple beamforming ICs would be employed in the phased array antenna 10. Prepreg buildup layers 36 are formed on a bottom of the PCB structure 12 and stacked microvias 38 are formed through the layers 36, where the layers 36 and the microvias 38 support BGA breakup. A patch antenna radiating element 40 is formed on an outermost one of the layers 36 and would be one of many radiating elements formed on the PCB structure 12 to provide the phased array antenna 10, where the radiating element 40 could be formed of ½ oz copper, and where the vias 38 provide an electrical connection to the radiating element 40.

[0009] Prior to the layers 26 and 36 being formed on the PCB structure 12, a via structure 50 is formed in the PCB structure 12 to provide an electrical connection between the vias 28 and 38, and thus between the beamforming IC 32 and the radiating element 40. A hole 52 is drilled from the top side of the PCB structure 12 and a via 54 is formed in part of the hole 52 and the rest of the hole 52 is filled with a dielectric 56. A hole 60 is drilled from the bottom side of the PCB structure 12 and a via 62 is formed in part of the hole 60 and the rest of the hole 60 is filled with a dielectric 64, where the holes 52 and 60 are provided as close together as the manufacturing tolerances will allow. An interconnect 66 in the feed layer 22 electrically couples the vias 54 and 62. A stub 68 of the via 54 extends past the interconnect 66 adjacent to the dielectric 56 and a stub 70 of the via 62 extends past the interconnect 66 adjacent to the dielectric 64 and have a length for impedance matching purposes between the vias 54 and 62.

[0010] Figure 2 shows an additional set of vias 80 and 82 connected by an interconnect 84 and orthogonal to the vias 54 and 62 to support another signal polarization.

[0011] The foregoing discussion discloses and describes merely exemplary embodiments of the present disclosure. One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims that various changes, modifications and variations can be made therein without departing from the scope of the disclosure as defined in the following claims.

Claims

1. An antenna (10) comprising: a printed circuit board, PCB, structure (12) including a plurality of layers (14), said PCB structure (12) including a first via hole (52) formed into the layers (14) through one side of the PCB structure (12) and partially filled with a first via (54) and a second via hole (60) formed into the layers (14) through an opposite side of the PCB structure (12) and partially filled with a second via (62), wherein the first and second vias (54, 62) are electrically coupled by an interconnect (66); prepreg buildup layers (26) formed on the one side of the PCB structure (12) and prepreg buildup layers (36) formed on the opposite side of the PCB structure (12); at least one beamforming integrated circuit, IC, (32) formed on the prepreg buildup layers (26) on the one side of the PCB structure (12); and at least one antenna radiating element (40) formed on the prepreg buildup layers (36) on the opposite side of the PCB structure (12), wherein the prepreg layers (26) on the one side of the PCB structure (12) include microvias (28) electrically coupled to the beam forming IC (32) and the first via (54) and the prepreg buildup layers (36) on the opposite side of the PCB structure (12) include microvias (38) electrically coupled to the at least one antenna radiating element (40) and the second via (62).

2. The antenna (10) according to claim 1 wherein the first via (54) includes a first stub (68) that extends beyond the interconnect (66) and the second via (62) includes a second stub (70) that extends beyond the interconnect (66).

3. The antenna (10) according to claim 1 wherein the at least one antenna radiating element (40) is a patch antenna radiating element (40).

4. The antenna (10) according to claim 1 wherein the interconnect (66) is in a feed layer (22) in the PCB structure (12).

5. The antenna (10) according to claim 1 wherein the antenna (10) is a phased array antenna, the at least one beamforming IC (32) is a plurality of beamforming ICs and the at least one antenna radiating element (40) is a plurality of antenna radiating elements.

6. The antenna (10) according to claim 1 wherein the portion of the first via hole (52) that is not filled with the first via (54) is filled with a dielectric (56) and the portion of the second via hole (60) that is not filled with the second via (62) is filled with a dielectric (64).

7. A phased array antenna (10) comprising: a printed circuit board, PCB, structure (12) including a plurality of layers (14), said PCB structure (12) including a first via hole (52) formed into the layers (14) through one side of the PCB structure (12) and partially filled with a first via (54) and a second via hole (60) formed into the layers (14) through an opposite side of the PCB structure (12) and partially filled with a second via (62), wherein the first and second vias (54, 62) are electrically coupled by an interconnect (66) provided in a feed layer (22) of the plurality of layers (14); prepreg buildup layers (26) formed on the one side of the PCB structure (12) and prepreg buildup layers (36) formed on the opposite side of the PCB structure (12); at least one beamforming integrated circuit, IC, (32) formed on the prepreg buildup layers (26) on the one side of the PCB structure (12); and at least one patch antenna radiating element (40) formed on the prepreg buildup layers (36) on the opposite side of the PCB structure (12), wherein the prepreg layers (26) on the one side of the PCB structure (12) include microvias (28) electrically coupled to the beam forming IC (32) and the first via (54) and the prepreg buildup layers (36) on the opposite side of the PCB structure (12) include microvias (38) electrically coupled to the at least one antenna radiating element (40) and the second via (62).

8. The antenna (10) according to claim 7 wherein the first via (54) includes a first stub (68) that extends beyond the interconnect (66) and the second via (62) includes a second stub (70) that extends beyond the interconnect (66).

9. The antenna (10) according to claim 7 wherein the portion of the first via hole (52) that is not filled with the first via (54) is filled with a dielectric (56) and the portion of the second via hole (60) that is not filled with the second via (62) is filled with a dielectric (64).