IMAGE CAPTURE DEVICE

Description

Domaine technique

[0001] This description relates generally to the field of electronic devices and more particularly to the field of image acquisition devices, and in particular to devices comprising a stack of an infrared image sensor and a visible image sensor. Technique antérieure

[0002] An image acquisition device has already been proposed comprising a stack of several sensors and in particular sensors of different types, for example an infrared image sensor and a visible image sensor, for example with a view to simultaneously or successively acquiring a visible image and depth map of the same scene.

[0003] Document US 2016 / 315113 A1 describes an image sensor according to the prior art.

[0004] There is a need for improvement in image acquisition devices having stacked sensors, and in methods of manufacturing them. Summary of the invention

[0005] For this, one embodiment provides an image sensor comprising: a plurality of photo-detection pixels formed in and on a semiconductor substrate; and an interconnection network covering one face of the semiconductor substrate, the interconnection network comprising a level of conductive vias in contact, by their lower face, with the photo-detection pixels, in which said conductive vias are made of doped polycrystalline silicon and have greater doping on their lower face side than on their upper face side.

[0006] According to one embodiment, said conductive vias have a doping gradient decreasing from the upper face of the substrate.

[0007] According to one embodiment, the conductive vias are doped with phosphorus or arsenic atoms.

[0008] Another embodiment provides a method of manufacturing an image sensor comprising: the formation of a plurality of photo-detection pixels in and on a semiconductor substrate; and the formation of a level of conductive vias of an interconnection network, the vias being in contact by their lower face with the photo-detection pixels, the conductive vias being made of doped polycrystalline silicon and having greater doping on the side of their lower face than on the side of their upper face.

[0009] According to one embodiment, said vias have a doping gradient decreasing from the upper face of the substrate.

[0010] According to one embodiment, the formation of the conductive vias comprises a step of forming openings in an insulating layer, in contact with the photo-detection pixels.

[0011] According to one embodiment, the formation of the conductive vias comprises, after the step of forming the openings, the following successive steps: forming an amorphous silicon film on and in the openings; ex-situ doping of said film by the implantation of dopants; and filling the openings with an amorphous silicon layer.

[0012] According to one embodiment, at the end of the film doping step, said film has a doping of the order of 1.10 21< at / cm 3< .

[0013] According to one embodiment, the amorphous silicon of the film is further doped in situ during its deposition.

[0014] According to one embodiment, the silicon of said layer is doped in situ during its deposition.

[0015] According to one embodiment, the formation of the conductive vias comprises, after the step of forming the openings, the following successive steps: filling the openings with an amorphous silicon layer; and ex-situ doping of said layer, in the vicinity of the semiconductor substrate, by the implantation of dopants.

[0016] According to one embodiment, the silicon of said layer is further doped in situ during its deposition.

[0017] According to one embodiment, at the end of the layer doping step, said layer has a doping, in the vicinity of the substrate, of the order of 1.10 21< at / cm 3< .

[0018] According to one embodiment, the method comprises, after the formation of the openings in the insulating layer in contact with the photo-detection pixels, a step of amorphizing the surface of the substrate and the surface of conductive grids made of polycrystalline silicon at the bottom of the openings.

[0019] Another embodiment provides an image acquisition device comprising a first image sensor and a second image sensor as defined above, the first image sensor and the second image sensor being stacked. Brève description des dessins

[0020] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 is a partial and schematic sectional view of an image acquisition device according to one embodiment; the figure 2 is a more detailed sectional view of part of the image acquisition device of the figure 1 ; there figure 3A , there figure 3B , there figure 3C , there figure 3D , there figure 3E , there figure 3F , there figure 3G , there figure 3H , there figure 3I , there figure 3J , there figure 3K , there figure 3L, figure 3M , there figure 3N , there figure 3O and the figure 3P are sectional views illustrating steps of a method of manufacturing the part of the image acquisition device illustrated in figure 2 according to a first mode of implementation; the figure 4A and the figure 4B are sectional views illustrating steps of a method of manufacturing the part of the image acquisition device illustrated in figure 2 according to a second mode of implementation; and the figure 5 is a sectional view illustrating a step in a method of manufacturing the portion of the image acquisition device illustrated in figure 2 according to a third mode of implementation. Description des modes de réalisation

[0021] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0022] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, only steps allowing the production of an interconnection network of a sensor have been detailed below. The production of the other elements of the image acquisition device, for example the production of the photoreceptors and the associated reading circuits, has not been detailed, the described embodiments being compatible with the usual productions of these elements or the production of these elements being within the reach of the person skilled in the art from the indications of the present description.

[0023] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0024] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0025] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0026] There figure 1 is a partial and schematic sectional view of an image acquisition device 11 according to one embodiment.

[0027] The image acquisition device 11 corresponds, for example, to the assembly of a first structure 13 corresponding to a first image sensor, and a second structure 15 corresponding to a second image sensor. The first image sensor is, for example, an infrared image sensor and the second image sensor is, for example, a visible image sensor, for example a color image sensor. In this example, the two infrared 13 and visible 15 sensors are stacked one above the other.

[0028] By way of example, each of the sensors 13 and 15 comprises a set of pixels formed in and on a semiconductor substrate. Each pixel comprises, for example, a photoreceptor, for example a photodiode, and a reading circuit for the photoreceptor. Thus, the sensor 13 comprises a set of pixels 17 and the sensor 15 comprises a set of pixels 19. Furthermore, each of the sensors 13 and 15 comprises an interconnection network for the pixels of the sensor. The sensor 13 thus comprises an interconnection network 21 and the sensor 15 comprises an interconnection network 23. In the example shown, the infrared sensor 13 is arranged on the visible sensor 15. The lower face of the interconnection network 21 of the sensor 13 is in contact with the upper face of the interconnection network 23 of the sensor 15. The set of pixels 17 of the infrared sensor 13 is arranged on the side of the upper face of the interconnection network 21.The set of pixels 19 of the visible sensor 15 is arranged on the lower face side of the interconnection network 23.

[0029] The device 11 is, in the example illustrated in figure 1 , intended to be illuminated from its lower face. The visible radiation is absorbed by the photodetectors of the pixels of the sensor 15, which allows the acquisition of an image in the wavelength range of the visible spectrum. The sensor 15 is, on the other hand, substantially transparent to infrared radiation. These rays are absorbed by the photodetectors of the sensor 13, which allows the acquisition of an image in the wavelength range of the infrared and near infrared spectrum.

[0030] In each of the sensors 13 and 15, the sensor pixels are for example arranged in a matrix according to rows and columns.

[0031] There figure 2 is a more detailed sectional view of part of the image acquisition device 11 of the figure 1 . More precisely, the figure 2 represents in more detail the part of the device 11 of the figure 1 surrounded by dotted lines in figure 1 , that is to say a part of the interconnection network 23 and a part of the set of pixels 19 of the sensor 15.

[0032] In figure 2 , a part of a pixel P of the sensor 15 is shown. By way of example, each pixel P comprises a photodetector, not shown, formed in and on a substrate 25. The substrate 25 is for example made of a semiconductor material, for example silicon. Each photodetector is for example connected to a reading circuit comprising transistors comprising gates 27, formed on the substrate 25. The gates 27 are, for example, made of polycrystalline silicon, for example doped with a first conductivity type, for example N type, for example doped with phosphorus atoms.

[0033] The upper faces of the substrate 25 and the gates 27 are for example covered by an insulating layer 29, for example crossed by vias 41 connecting the interconnection network 33 to all of the photodetectors and their reading circuits. For example, the layer 29 is made of a nitride and / or an oxide, for example a silicon nitride (Si x N y ), a silicon carbonitride (SiC x N y ) and / or a silicon dioxide (SiO 2 ). For example, the layer 29 comprises a first sub-layer on and in contact with the upper face of the substrate 25 and the upper face of the gates 27 and a second sub-layer on and in contact with the upper face of the first sub-layer. The first sub-layer is for example made of silicon dioxide. The second sub-layer is for example made of silicon nitride.

[0034] The interconnection network 23 consists of a stack or network of electrically conductive levels and electrically insulating levels in which interconnection elements are formed. figure 2 , three levels are represented in the interconnection network 23, a first level 31 called the lower level, covering the upper face of the substrate 25, for example on and in contact with the upper face of the layer 29, a second level 33 covering the first level, for example on and in contact with the upper face of the first level, and a third level covering the second level, for example on and in contact with the upper face of the second level. In practice, the network 23 may comprise a number of levels other than three, for example greater than three.

[0035] For example, each level includes a layer of insulating material in which conductive tracks and vias are formed.

[0036] The lower level 31 thus comprises, for example, an electrically insulating layer 37 in which electrically conductive vias 39 and electrically conductive tracks 41 are formed. Similarly, the second level 33 comprises, for example, an electrically insulating layer 43 in which electrically conductive vias 45 and electrically conductive tracks 47 are formed and the third level 35 comprises, for example, an electrically insulating layer 49 in which electrically conductive vias 51 and electrically conductive tracks 53 are formed.

[0037] For example, the vias 39 are in contact, by their lower face, with the substrate 25 or with the gates 27 of the transistors of the pixel reading circuits, and, by their upper face, with the lower face of the tracks 41. The vias 45 are for example in contact, by their lower face, with the upper face of the tracks 41, and, by their upper face, with the lower face of the tracks 47. The vias 51 are for example in contact, by their lower face, with the upper face of the tracks 47, and, by their upper face, with the lower face of the tracks 53.

[0038] The layers 37, 43 and 49 are for example made of silicon dioxide (SiO 2 ) and / or silicon nitride (Si x N y ) and / or silicon carbonitride (SiC x N y ). By way of example, the layers 37, 43 and 49 each correspond to a stack of the aforementioned materials.

[0039] Vias 45 and 51 and tracks 47 and 53 are for example made of metal, for example a transition metal, for example tungsten, copper, cobalt or ruthenium. For example, vias 45 are made of tungsten, and vias 51 and tracks 53 and 47 are made of copper.

[0040] For example, the levels of the interconnection network 23 are separated by encapsulation layers.

[0041] In the example shown, an encapsulation layer 55 thus covers the second level and an encapsulation layer 57 covers the third level of the interconnection network 23. The encapsulation layers 55 and 57 are, for example, made of an electrically insulating material making it possible to act as a barrier to the diffusion of copper or certain ions in the silicon of the layers 37, 43 and 49. By way of example, the encapsulation layers 55 and 57 are made of a material other than copper, for example silicon nitride or silicon carbonitride (SiCN).

[0042] Similarly, the vias 45 and 51 and tracks 53 and 47 are for example surrounded by a layer making it possible to act as a barrier to the diffusion of the material of the vias, for example copper or tungsten, into the silicon of the layers 43 and 49. In the example shown, the vias 51 and the tracks 53 and 47 are for example surrounded, for example encapsulated, by a barrier layer 56 and the via 45 is for example surrounded by a barrier layer 58. The barrier layer 56 is for example made of tantalum nitride (TaN) and the barrier layer 58 is for example made of titanium and / or titanium nitride (TiN).

[0043] For example, the conductive tracks 41 of the level 31 are arranged on and in contact with a layer 63 and are covered and in contact with a layer 59. The layers 63 and 59 are for example both made of a dielectric material, for example nitride, for example silicon nitride.

[0044] The transparency of the sensor 15, to the radiation captured by the sensor 13, is provided by the transparency of all the elements described above and more particularly of all the photodetectors 19 and the interconnection network 23.

[0045] For example, the set of pixels 19 of the sensor 15 is transparent to infrared radiation. The interconnection network 23 may, however, comprise electrical connection elements (electrical connection tracks and / or vias), for example metallic, which are not transparent to infrared radiation.

[0046] In this example, although it is not represented in figure 2 , it is planned to move the tracks and vias of the upper levels of the interconnection network 23 to the periphery of the P pixels. This allows a transparent passage for infrared radiation to be left opposite a central part of the P pixels.

[0047] The vias 39 of the lower level 31 of the interconnection network 23 allow contact to be made on the upper face of the gates 27 as well as at different locations on the surface of the substrate 25, for example on reading nodes of the P pixels. Their deportation to the periphery of the P pixels is therefore not possible.

[0048] According to one aspect of an embodiment, provision is made to form the vias 39 and the tracks 41 of the first level of the interconnection network 23 in doped polycrystalline silicon, which has the advantage of being transparent to infrared radiation. In order to promote ohmic contact with the underlying components while maximizing transparency, provision is further made to dope the vias 39 with a decreasing doping gradient starting from their lower face.

[0049] This makes it possible to improve the transparency of the interconnection network 23 to infrared radiation opposite the pixels P, and thus to increase the flux received by the infrared sensor 13.

[0050] There figure 3A , there figure 3B , there figure 3C , there figure 3D , there figure 3E , there figure 3F , there figure 3G , there figure 3H , there figure 3I , there figure 3J , there figure 3K , there figure 3L , there figure 3M , there figure 3N , there figure 3O and the figure 3P are sectional views illustrating steps of a method of manufacturing the part of the image acquisition device illustrated in figure 2 according to a first mode of implementation.

[0051] There figure 3A illustrates a starting structure of the process. More specifically, the figure 3A illustrates very schematically only part of the elements of a pixel P.

[0052] The structure illustrated in figure 3A comprises the substrate 25 in and on which the plurality of photodetectors and readout transistors are formed. As an example, the structure illustrated in figure 3A includes the gates 27 of read transistors formed on the substrate 25 and, for example, separated from the substrate 25 by a gate insulator layer (not detailed in the figure).

[0053] In the starting structure of the figure 3A , the substrate 25 and the grids 27 are for example covered by the layer 29. By way of example, the layer 29 is formed in a conformal manner, that is to say that it is deposited with a constant thickness over the entire surface of the structure.

[0054] For example, layer 29 is covered by an insulating layer 61. For example, layer 61 is made of an oxide, for example silicon dioxide (SiO 2 ). For example, layer 61 covers layer 29 with a thickness of between 190 nm and 500 nm, for example between 300 nm and 450 nm, for example of the order of 380 nm.

[0055] The layer 61 is, for example, covered by a dielectric layer 63. The layer 63 is, for example, made of a nitride, for example silicon nitride (Si x N y ) or silicon carbonitride (SiC x N y ). For example, the layer 63 has a thickness of between 10 nm and 100 nm, for example between 30 nm and 70 nm.

[0056] There figure 3B illustrates a structure obtained at the end of a step of forming openings 65 in the structure illustrated in figure 3A .

[0057] More particularly, during this step, the openings 65 are formed from the upper face of the structure illustrated in figure 3A , so that they open onto the upper face of the substrate 25 or the upper face of the grids 27. The openings 65 thus pass through the layer 63, the layer 61 and the layer 29.

[0058] During this step, for example, several openings 65 are formed. An opening 65 is for example formed opposite each grid 27 and an opening 65 is for example formed opposite each reading node (not shown) of the substrate 25.

[0059] The openings 65 are, for example, formed by etching through a masking layer not shown. For example, the openings 65 have a width of between 50 nm and 150 nm, for example between 90 nm and 100 nm.

[0060] There figure 3C illustrates a structure obtained at the end of a step of depositing a silicon film 67 on the structure illustrated in figure 3B . More particularly, the film 67 is deposited on the upper face of the layer 63 and in the openings 65, more particularly in the bottom and on the sides of the openings 65.

[0061] When it is deposited, the film 67 is, for example, made of amorphous silicon. For example, the film 67 is, for example, deposited in a conformal manner, that is to say that it is deposited over the entire upper face of the structure illustrated in figure 3B with a substantially constant thickness. The film 67 has, for example, a thickness of between 19 nm and 40 nm, for example of between 30 nm and 35 nm. For example, the film 67 is formed by low pressure chemical vapor deposition or LPCVD.

[0062] For example, the material constituting the film 67 is doped during its deposition on the upper face of the structure illustrated in figure 3B , we speak of in-situ doping. The material constituting the film 67 is, for example, doped with a first type of conductivity, for example of the N type, for example doped with arsenic or phosphorus atoms. For example, at the end of this step, the film 67 has a doping of the order of 3.10 19< at / cm 3< .

[0063] For example, the deposition of the film 67 is preceded by a step of treating the surface of the structure illustrated in figure 3C .

[0064] There figure 3D illustrates a structure obtained following a doping step of film 67 of the structure illustrated in figure 3C . During this step, we come for example to dope the structure illustrated in figure 3C by implantation of doping elements through its upper face, we speak here of ex-situ doping.

[0065] For example, this step is carried out without a mask or masking layer. However, the layer 63 can act as a masking layer by protecting the layer 61 from the implantation of dopants 67i. Thus, during this step, only the film 67 is doped and more particularly the bottom of the openings 65 is, among other things, doped. This doping step consists of the implantation in the film 67 of atoms of the first conductivity type, for example of the N type, for example of arsenic or phosphorus atoms. The doping is, for example, carried out with a dose of between 2.10 14< at / cm 2< and 1.10 16< at / cm 2< , for example of between 5.10 14< at / cm 2< and 1.10 16< at / cm 2< .

[0066] For example, at the end of this step, the film 67 has a doping between 4.10 19< at / cm 3< and 4.10 22< at / cm 3< , for example of the order of 1.10 21< at / cm 3< .

[0067] There figure 3E illustrates a structure obtained at the end of a step of filling the openings 65 of the structure illustrated in figure 3D .

[0068] During this step, we fill the openings 65 and cover the upper face of the structure illustrated in figure 3D by amorphous silicon so as to form a layer 69 on and in contact with the doped layer 67. For example, the amorphous silicon used during this step is doped in situ during its deposition, for example of the first type of conductivity, for example of the N type, for example with arsenic or phosphorus atoms. The amorphous silicon used to form the layer 69 is for example doped in the order of 1.10 20< at / cm 3< .

[0069] Optionally, at the end of this step, an additional doping step may be provided and more particularly a localized doping step of the second conductivity type, for example of the P type, for example doped with boron atoms or boron difluoride (BF 2 ). For example, the purpose of this step is to locally dope the parts of the layer 69 located in a part of the openings 65 and more precisely the parts of the layer 69 located in the openings 65 which are in contact with a zone of the substrate 25 preferably doped P. The localized doping is for example carried out through a masking layer, for example made of resin.

[0070] There figure 3F illustrates a structure obtained following a step of polishing the upper face of the structure illustrated in figure 3E . In this figure, an enlargement of a portion of the structure comprising a via 39 is also shown.

[0071] During this step, the layer 69 and the film 67 are removed so as to reveal the upper face of the layer 63. The parts of the layer 69 and the film 67 remaining in the openings 65 thus form the vias 39. At the end of this step, the upper face of the vias 39 are flush with the upper face of the layer 63. The polishing step is, for example, carried out by a mechanical process, for example a chemical-mechanical process or CMP (from the English "Chemical Mechanical Polishing"). For example, this step makes it possible to flatten the upper face of the structure down to the layer 63 allowing the end of flattening to be checked.

[0072] The polishing step is, for example, followed by an annealing step allowing the activation of the doping of the vias 39. For example, the annealing step is carried out at a temperature greater than 800°C, for example greater than 900°C, for example between 900°C and 1050°C.

[0073] At the end of this step, the material of the vias 39 changes from an amorphous state to a polycrystalline state. The vias 39 are, at the end of this step, made of doped polycrystalline silicon. The vias 39 being formed from the film 67 and the layer 69, their dopings are greater in the vicinity of the substrate 25, the vias 39 thus have a decreasing doping gradient starting from the upper face of the substrate 25.

[0074] There figure 3G illustrates a structure obtained at the end of a step of depositing a layer 73 on the upper face of the structure illustrated in figure 3F .

[0075] For example, during this step, the layer 73 is more particularly deposited on and in contact with the upper face of the layer 63 and the upper face of the vias 39. The layer 73 is for example made of a dielectric material, for example silicon oxide, for example silicon dioxide (SiO 2 ). For example, the layer 73 is deposited by plasma-enhanced chemical vapor deposition or PECVD (from the English "Plasma Enhanced Chemical Vapor Deposition"). For example, the layer 73 has a thickness of between 100 nm and 500 nm, for example of the order of 155 nm.

[0076] There figure 3H illustrates a structure obtained at the end of a step of forming openings 75 in the layer 73 of the structure illustrated in figure 3G .

[0077] This step is similar to the step of forming the openings 65 in the layers 61, 63 and 29 described in connection with the figure 3B with the difference that the openings 75 are formed from the upper face of the layer 73 and that they open onto the upper face of the layer 63 and onto the upper face of the vias 39. For example, the openings 75 are wider than the openings 65, the openings 65 accommodating the vias 39 and the openings 41 accommodating the first track level 41 of the interconnection network. For example, each via 39 is surmounted by an opening 75.

[0078] There figure 3I illustrates a structure obtained at the end of a step of filling the openings 75 of the structure illustrated in figure 3H .

[0079] In this step, we first fill the openings 75 and cover the upper face of the structure illustrated in figure 3H by amorphous silicon, for example doped in situ.

[0080] In a second step, the excess amorphous silicon deposited on the upper face of the structure is removed so as to reveal the upper face of the layer 73. For example, this step is carried out by polishing. The polishing step is, for example, carried out by a mechanical process, for example a chemical-mechanical process or CMP (from the English "Chemical Mechanical Polishing"). The part of amorphous silicon remaining in the openings 75 thus forms the tracks 41. At the end of this step, the upper face of the tracks 41 are flush with the upper face of the layer 73.

[0081] The polishing step is, for example, followed by an annealing step. For example, the annealing step is carried out at a temperature above 800°C, for example above 900°C, for example between 900°C and 1050°C.

[0082] At the end of this step, the material of the tracks 41 passes from an amorphous state to a polycrystalline state.

[0083] There figure 3J illustrates a structure obtained at the end of a step of depositing a layer 59 on the upper face of the structure illustrated in figure 3I .

[0084] During this step, the upper face of layer 73 and the upper face of tracks 41 are more particularly covered with a layer 59.

[0085] The layer 59 is, for example, formed as a full wafer. For example, the layer 59 is formed conformally. For example, the layer 41 has a thickness of between 10 nm and 100 nm, for example between 30 nm and 70 nm. The layer 41 is, for example, deposited by PECVD.

[0086] The layer 59 is, for example, made of a dielectric material, for example a nitride, for example silicon nitride (Si x N y ) or silicon carbonitride (SiC x N y ).

[0087] The formation of layer 59 completes the formation of the lower level 31 of the interconnection network 23. Steps 3K to 3O illustrate the formation of an additional level of the interconnection network 23, for example the second level 33, these steps are therefore, for example, repeated until the desired number of levels in the interconnection network 23 is obtained.

[0088] There figure 3K illustrates a structure obtained at the end of a step of forming a layer 79 on the upper face of the structure illustrated in figure 3J followed by a step of forming openings 81 in layers 79 and 59.

[0089] For example, the step of forming layer 79 is similar to the step of forming layer 79 described in connection with the figure 3K and the step of forming the openings 81 is similar to the step of forming the openings 41 described in relation to the figure 3H .

[0090] For example, the openings 81 are formed opposite the tracks 41 and open onto the tracks 41.

[0091] There figure 3L illustrates a structure obtained at the end of a step of cleaning the bottom of the openings 81 and forming a layer 82 on the upper face of the structure illustrated in figure 3K .

[0092] For example, during this step, the bottom of the openings 81 is first cleaned, for example using an argon plasma.

[0093] In a second step, a full plate layer 82 is formed, comprising for example a sub-layer 82a and a sub-layer 82b, on the upper face of the structure illustrated in figure 3K and more particularly on the upper face of the layer 79 and on the sides and in the bottom of the openings 81.

[0094] For example, the sub-layer 82a is made of titanium. The sub-layer 82a has, for example, a thickness of less than 50 nm, for example less than 30 nm, for example between 5 nm and 30 nm. The sub-layer 82a is, for example, formed by a physical vapor deposition (PVD) process. The sub-layer 82b is, for example, formed on and in contact with the sub-layer 82a. For example, the sub-layer 82b is made of silicon nitride. The sub-layer 82b is, for example, formed by the deposition of successive atomic layers (ALD). The sub-layer 82b makes it possible, for example, to protect the sub-layer 82a from oxidation.

[0095] There figure 3M illustrates a structure obtained following an annealing step of the structure illustrated in figure 3L so as to form an intermetallic silicide 83 from the layer 82.

[0096] During this step, the structure undergoes annealing to react the titanium of the sub-layer 82a with the silicon of the tracks 41 so as to form, in the bottom of the openings 81, a thin film of an intermetallic compound called silicide. The silicide is for example based on silicon and titanium, the silicide is a titanium disilicide (TiSi 2 ) or a titanium silicide (TiSi) depending on the annealing applied.

[0097] There figure 3N illustrates a structure obtained at the end of a step of filling the openings 81 of the structure illustrated in figure 3M , so as to form the vias 45.

[0098] In this step, we first fill the openings 81 and cover the upper face of the structure illustrated in figure 3M with a metallic material. For example, the metallic material is copper, tungsten or cobalt.

[0099] For example, the filling of the openings 81 is carried out while the parts of the layer 82 which have not reacted with the silicon of the contacts 41, during the step of forming the silicide 83, are kept on the sides of the openings 81. The layer 82 thus has a barrier function to the diffusion of the material of the vias 45 into the layer 79.

[0100] In a second step, the excess metallic material deposited on the upper face of the structure is removed so as to reveal the upper face of the layer 79. For example, this step is carried out by polishing. The polishing step is, for example, carried out by a mechanical process, for example a chemical-mechanical process or CMP (from the English "Chemical Mechanical Polishing"). What remains of metallic material in the openings 81 thus forms the tracks 45. At the end of this step, the upper face of the tracks 45 are flush with the upper face of the layer 79.

[0101] There figure 3O illustrates a structure obtained at the end of a step of forming a layer 87 on the upper face of the structure illustrated in figure 3N followed by a step of forming openings 89 in layer 87.

[0102] For example, the step of forming layer 87 is similar to the step of forming layer 73 described in connection with the figure 3G and the step of forming the openings 89 is similar to the step of forming the openings 41 described in connection with the figure 3H .

[0103] For example, each via 45 is surmounted by an opening 89.

[0104] There figure 3P illustrates a structure obtained at the end of a step of filling the openings 89 of the structure illustrated in figure 3O , so as to form tracks 47.

[0105] During this step, we first deposit a barrier layer, not shown, full plate on the upper face of the structure illustrated in figure 3O , and more precisely in the bottom and on the sides of the openings 89. This barrier layer makes it possible, for example, to prevent the diffusion of copper atoms in the layer 87. For example, the barrier layer is made of tantalum and / or tantalum nitride (TaN). For example, the barrier layer comprises a first sub-layer made of tantalum nitride. For example, the barrier layer comprises a second sub-layer made of tantalum.

[0106] In a second step, the contacts 47 are formed in the openings 89, on and in contact with the barrier layer. For example, the contacts 47 are made of a metallic material, for example copper.

[0107] For example, the contacts 47 are formed by deposition of a layer of copper, for example full plate. The deposition of the copper layer is, for example, followed by electrolytic growth of this layer.

[0108] For example, at the end of the electrolytic growth step, a polishing step, for example mechanochemical, is carried out so as to uncover the upper face of the layer 87. At the end of this step, the upper face of the contacts 47 are flush with the upper face of the layer 87.

[0109] Although not shown, the formation of level 33 of the interconnection network 23 is, for example, completed by the formation of a layer of a dielectric, for example of a nitride, for example of silicon nitride (Si x N y ) or silicon carbonitride (SiC x N y ).

[0110] An advantage of the first embodiment is that it allows the doping of the part of the film 67 located on the sides of the openings 65, thus creating a more conductive zone on the side of the vias 39 and lowering the resistance of these.

[0111] There figure 4A and the figure 4B are sectional views illustrating steps of a method of manufacturing the part of the image acquisition device illustrated in figure 2 according to a second mode of implementation.

[0112] The second embodiment differs from the first embodiment in that, upon completion of the step described in relation to the figure 3B , the openings 65 are filled with a layer 93 of silicon without prior formation of the film 67 (as has been described in relation to the figure 3C ) and in that layer 93 undergoes implantation following its deposition.

[0113] There figure 4A illustrates a structure obtained at the end of a step of depositing the layer 93 in the openings 65 and on the surface of the structure illustrated in figure 3B .

[0114] During this step, we fill the openings 65 and cover the upper face of the structure illustrated in figure 3B and by amorphous silicon so as to form the layer 93 on and in contact with the layer 63. For example, the layer is, during this step, doped in situ during its deposition, for example of the first type of conductivity, for example of the N type, for example with arsenic or phosphorus atoms. The amorphous silicon used to form the layer 93 is, for example, doped in the order of 1.10 19< at / cm 3< .

[0115] There figure 4B illustrates a structure obtained following a doping step of layer 93 of the structure illustrated in figure 4A . During this step, we come for example to dope the structure illustrated in figure 4A by its upper face.

[0116] For example, this step is performed without a mask or masking layer. However, layer 63 can act as a masking layer by protecting layer 61 from the implantation of 93i dopants.

[0117] Thus, during this step, only layer 93 is doped and more particularly the parts of layer 93 located in openings 65 are, among other things, doped. This doping step consists of the implantation in the aforementioned layer of arsenic or phosphorus atoms. For example, the doping of layer 93 corresponds to deep doping, that is to say that the parts of layer 93 located at the bottom of openings 65 will be more doped than the parts of layer 93 located at the surface of openings 65. The doping is, for example, carried out with a dose between 2.10 14< at / cm 2< and 1.10 16< at / cm 2< , for example between 5.10 14< at / cm 2< and 1.10 16< at / cm 2< .

[0118] At the end of this step, the layer 93 has, for example, a doping, in the vicinity of the substrate 25 and the grids 27, of between 4.10 19< at / cm 3< and 4.10 22< at / cm 3< , for example of the order of 1.10 21< at / cm 3< .

[0119] Optionally, at the end of this step, an additional doping step can be provided and more particularly a localized doping step of the second type of conductivity, for example of the P type similarly to what has been described in relation to the figure 3E .

[0120] At the end of this step, the second embodiment is identical to the first embodiment, the doping step is then followed by the steps illustrated in figures 3F à 3O .

[0121] The step described in relation to the figure 3F polishing and annealing of the structure, allows the vias 39 to be formed from the layer 93. During this step, the material of the vias 39 changes from an amorphous state to a polycrystalline state. The vias 39 are, at the end of this step, made of doped polycrystalline silicon with a decreasing doping gradient starting from the upper face of the substrate 25.

[0122] There figure 5 is a sectional view illustrating a step in a method of manufacturing the portion of the image acquisition device illustrated in figure 2 according to a third mode of implementation.

[0123] The third embodiment is similar to the first embodiment except that it includes a step of treating the upper face of the structure illustrated in figure 3B .

[0124] During this step, for example, we amorphize the upper face of the structure illustrated in figure 3B and more particularly, the parts of the surface of the grids 27 and of the substrate 25 located opposite the openings 65. This step allows a crystallographic rearrangement of the parts mentioned above and thus a better electrical contact with the via 39 formed subsequently in the openings 65.

[0125] For example, this step consists of the implantation of neutral ions 27i, for example argon, nitrogen, fluorine, silicon or germanium.

[0126] For example, at the end of this step, the third embodiment is identical to the first embodiment.

[0127] Alternatively, the step illustrated in figure 5is followed by a step of forming polycrystalline silicon contacts not having a doping gradient. In this case, the ohmic contact between the vias 39 and the substrate 25 or the gates 27 remains improved due to the crystallographic rearrangement resulting from the step of surface amorphization of the silicon at the bottom of the openings 65.

[0128] An advantage of the described embodiments is that they allow polycrystalline silicon vias 39 to be formed in a lower level of the interconnection network with a doping gradient, thereby improving ohmic contact with the gates 27 or the substrate 25.

[0129] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0130] In particular, the second and third embodiments may be combined.

[0131] Furthermore, the described embodiments can be applied in the context of a device comprising a single sensor illuminated by its upper face. The interconnection network is then made transparent to the radiation captured by the detectors of the same sensor.

[0132] Again, the embodiments are not limited to the numerical value examples or material examples mentioned in this description.

[0133] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Image sensor (15) comprising: - a plurality of photodetection pixels (19) formed inside and on top of a semiconductor substrate (25); and - an interconnection network (23) coating a surface of the semiconductor substrate, the interconnection network comprising a level (31) of conductive vias (39) in contact, by their lower surface, with the photodetection pixels, wherein said conductive vias are made of doped polysilicon and characterized in that said vias have a heavier doping on their lower surface side than on their upper surface side.

2. Sensor according to claim 1, wherein said conductive vias (39) have a decreasing doping gradient starting from the upper surface of the substrate (25).

3. Image sensor according to claim 1 or 2, wherein the conductive vias (39) are doped with phosphorus or arsenic atoms.

4. Method of manufacturing an image sensor (15) comprising: - the forming of a plurality of photodetection pixels (19) inside and on top of a semiconductor substrate (25); and - the forming of a level (31) of conductive vias (39) of an interconnection network (23), the vias (39) being in contact by their lower surface with the photodetection pixels, the conductive vias (39) being made of doped polysilicon and having a heavier doping on their lower surface side than on their upper surface side.

5. Method according to claim 4, wherein said vias (39) have a decreasing doping gradient starting from the upper surface of the substrate.

6. Method according to claim 4 or 5, wherein the forming of the conductive vias (39) comprises a step of forming of openings (65) in an insulating layer (61), in contact with the photodetection pixels (19).

7. Method according to claim 6, wherein the forming of the conductive vias (39) comprises, after the step of forming of the openings (65), the following successive steps: - forming of an amorphous silicon film (67) on top and inside of the openings (65); - ex-situ doping of said film (67) by the implantation of dopants; and - filling of the openings (65) with a amorphous silicon layer (69).

8. Method according to claim 7, wherein at the end of the step of doping of the film (67), said film has a doping in the order of 1.1021 at / cm3.

9. Method according to claim 7 or 8, wherein the amorphous silicon of the film (67) is further doped in-situ during its deposition.

10. Method according to any of claims 7 to 9, wherein the silicon of said layer (69) is doped in-situ during its deposition.

11. Method according to claim 6, wherein the forming of the conductive vias (39) comprises, after the step of forming of the openings (65), the following successive steps: - filling of the openings (65) with an amorphous silicon layer (93); and - ex-situ doping of said layer (93), in the vicinity of the semiconductor substrate (25), by the implantation of dopants.

12. Method according to claim 11, wherein the silicon of said layer (93) is further doped in-situ during its deposition.

13. Method according to claim 11 or 12, wherein at the end of the step of doping of the layer (93), said layer has a doping, in the vicinity of the substrate (25), in the order of 1.1021 at / cm3.

14. Method according to any of claims 6 to 13, comprising, after the forming of the openings (65) in the insulating layer (61) in contact with the photodetection pixels, a step of amorphization of the surface of the substrate (25) and of the surface of polysilicon conductive gates (27) at the bottom of the openings (65).

15. Image acquisition device (11) comprising a first image sensor (13) and a second image sensor (15) according to any of claims 1 to 3, the first image sensor and the second image sensor being stacked.