METHOD FOR PRODUCING AN ELECTRONIC CHIP WITH A MEMORY CIRCUIT AND A MEMORY CIRCUIT

Description

Technical field

[0001] This description relates generally to the field of electronic chips and more particularly to the field of electronic chips comprising a memory circuit based on a phase change material and their manufacturing methods. Prior art

[0002] A phase change material is a material that has the ability to change its crystalline state under the effect of heat, and more specifically to switch between a crystalline state and an amorphous state, which is more highly resistive than the crystalline stage. This phenomenon is used to define two memory states, for example 0 and 1, differentiated by the resistance measured across the phase change material.

[0003] There is a need for improvement of electronic chips comprising a memory circuit comprising memory points based on a phase change material, and of their manufacturing methods. Examples of the prior art are found in documents US2005169043 A1 and US2009285015 A1. Summary of the invention

[0004] One embodiment overcomes all or part of the drawbacks of electronic chips comprising a memory circuit based on a phase change material and their manufacturing methods.

[0005] One embodiment provides a method for manufacturing an electronic chip comprising the following successive steps: a) forming a first layer on and in contact with a second semiconductor layer doped with a first conductivity type, the second layer being on and in contact with a third semiconductor layer doped with a second conductivity type opposite to the first conductivity type; b) doping the first layer so as to form, on the second layer, a first sub-layer doped with the first conductivity type and a second sub-layer doped with the second conductivity type; c) forming islands in the first layer organized according to a matrix of rows and columns on the surface of the second layer; and d) forming memory points based on a phase change material on the islands of the first layer, the second layer, the third layer and the second sub-layer of the first layer forming a bipolar transistor.

[0006] According to one embodiment, the method comprises, after step c), an epitaxy step e) during which a fourth semiconductor layer is formed between the islands of the first layer.

[0007] According to one embodiment, the method comprises, after step e), a step of doping a zone of the fourth layer of the first conductivity type.

[0008] According to one embodiment, the method comprises, between steps c) and e), a step of forming electrically insulating spacers around the islands.

[0009] According to one embodiment, trenches are formed in the second and third layers, between said islands, in the direction of the lines.

[0010] According to one embodiment, a memory point is formed opposite each island.

[0011] According to one embodiment, the first layer is made of silicon.

[0012] According to one embodiment, the first layer is made of polycrystalline silicon and is formed by deposition.

[0013] According to one embodiment, said islands and memory points are formed in a memory area of ​​the chip, the chip further comprising a logic area, and in step c), MOS transistor gates of a logic circuit are further formed in the first layer, at the same time as the islands.

[0014] According to one embodiment, the first layer is made of monocrystalline silicon and is formed by epitaxy.

[0015] Another embodiment provides an electronic chip comprising islands in a first layer organized according to a matrix of rows and columns, the islands being arranged on the surface of a second semiconductor layer doped with a first conductivity type, itself located on and in contact with a third semiconductor layer doped with a second conductivity type opposite to the first conductivity type, the first layer comprising a first sub-layer doped with the first conductivity type, on the second layer and a second sub-layer doped with the second conductivity type, the islands being surmounted by memory points based on phase change material, the second layer, the third layer and the second sub-layer of the first layer constituting a bipolar transistor.

[0016] According to one embodiment, each island is surrounded laterally by electrically insulating spacers.

[0017] According to one embodiment, the first layer is made of polycrystalline silicon.

[0018] According to one embodiment, the first layer is made of monocrystalline silicon.

[0019] According to one embodiment, the electronic chip is formed by said method. Brief description of the drawings

[0020] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:

[0021] there Figure 1A and the Figure 1B illustrate two partial and schematic sectional views of an example of an electronic chip;

[0022] there Figure 2A and the Figure 2B illustrate two partial and schematic sectional views of an electronic chip according to one embodiment;

[0023] there figure 3 , there figure 4 , there Figure 5 , there figure 6, there figure 7 , there figure 8 and the figure 9 are sectional views illustrating steps of a method of manufacturing the electronic chip illustrated in Figures 2A and 2B according to a first mode of implementation; and

[0024] there figure 10 and the figure 11 are sectional views illustrating steps of a method of manufacturing the electronic chip illustrated in Figures 2A and 2B according to a second mode of implementation. Description of the embodiments

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, only the steps allowing the production of the memory circuit have been detailed below, the formation of the other elements of the chip, for example a logic circuit located next to the memory circuit, being within the scope of the person skilled in the art.

[0027] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0030] There Figure 1A and the Figure 1B illustrate two partial and schematic sectional views of an example of electronic chip 11, the Figure 1A being a view along section plane AA of the Figure 1B and the Figure 1B being a view along the section plane BB of the Figure 1A .

[0031] More specifically, the Figure 1Aand the Figure 1B illustrate a portion of the electronic chip 11 and more precisely a portion of a memory circuit of the electronic chip 11. By way of example, the electronic chip 11 comprises, in a portion not shown, a logic circuit adjacent to the memory circuit.

[0032] The electronic chip 11 comprises memory points M for example organized, in top view, according to a matrix of rows and columns. As an example, the memory points M illustrated in Figure 1A are memory points M of the same line while the memory points illustrated in Figure 1B are memory points of the same column. We speak respectively of word lines (wordlines) and bit lines (bitlines), each memory point M being located at the intersection of a bit line and a word line. In Figure 1A , only four bit lines are represented and in Figure 1Bonly five word lines are represented. However, in practice, a memory circuit may include a number of bit lines and word lines other than four and five respectively, for example greater than four and five.

[0033] For example, the memory points M are based on a phase change material 33, for example based on a chalcogenide material, for example an alloy of germanium, antimony and tellurium (GeSbTe) called GST. In each memory point, the phase change material is, for example, controlled by a heating metallic resistive element 35 located under the phase change material, for example in contact, by its upper face, with the lower face of the phase change material 33, and surrounded laterally by a thermal insulator 37. The phase change material 33 is, for example, surmounted by metallizations 41, for example made of a conductive material. For example, in each memory point M, the metallic elements 35 and 41 respectively form a lower electrode and an upper electrode of the variable resistance resistive element formed by the phase change material 33.For example, the memory points M of the same bit line are surmounted by the same metallization 41. In other words, the upper electrodes 41 of the memory points M of the same bit line are interconnected. The metallizations 41 are, for example, coupled to potential application nodes Va.

[0034] The chip 11 comprises a semiconductor layer 13 doped with a first conductivity type, for example of the N type, for example doped with arsenic or phosphorus atoms. The layer 13 is, for example, made of silicon. The layer 13 rests on a semiconductor layer 15 doped with a second conductivity type, opposite to the first conductivity type, for example of the P type, for example doped with boron atoms. The layer 15 is, for example, made of silicon.

[0035] For example, the chip 11 comprises gate patterns 17 arranged on the upper face of the layer 13, for example extending longitudinally in the direction of the bit lines. The gate patterns 17 comprise, for example, a central portion 19 surrounded laterally by spacers 21. The central portion 19 of each gate pattern 17 is, for example, made of a semiconductor material, for example silicon, for example polycrystalline silicon. The spacers 21 are, for example, made of an electrically insulating material, for example silicon nitride.

[0036] In this example, the gate patterns 17 extend, in top view, between the bit lines of the memory point matrix M. In other words, in this example, in top view, any two consecutive bit lines of the memory point matrix M are separated from each other by one and only one gate pattern 17 extending over the entire length of said bit lines. The gate patterns 17 are, for example, laterally separated by a semiconductor layer 23, for example formed by epitaxy from the upper face of the layer 13. The layer 23 is, for example, made of silicon, for example monocrystalline silicon. By way of example, each memory point M is connected, for example connected, to the layer 23 by means of a via 39. By way of example, the via 39 is in contact, by its upper face, with the lower face of the resistive heating element 35 of the memory point M.Via 39 is for example in contact, by its lower face, with the upper face of layer 23.

[0037] The layer 23 comprises, for example, first regions 25, for example doped with the second conductivity type, for example of the P type, and extending between certain grid patterns 17, directly above the memory points M of the matrix. The regions 25 are, for example, more heavily doped than the layer 15. Each region 25 is, for example, surmounted by a memory point. By way of example, for each memory point M, the corresponding via 39 electrically connects the heating element 35 of the memory point to the underlying region 25.

[0038] The layer 23 further comprises second regions 27, for example doped with the first conductivity type, for example of the N type, and extending between other gate patterns 17. The regions 27 are, for example, more heavily doped than the layer 13. The regions 27, unlike the regions 25, are for example not surmounted by memory points M but by contact recovery vias 29. The vias 29 allow the contact recovery of the word lines. For example, within the same word line, two vias 29 are spaced apart by, for example, four memory points M (belonging respectively to four consecutive bit lines). For example, the contact recovery are connected to a node for applying a potential Vb applied to the word line concerned.

[0039] The regions 27 and 25 are, for example, laterally delimited by the gate patterns 17 and by isolation trenches 31, for example, very shallow isolation trenches (SSTI, from the English "Super Shallow Trench Isolation"). The isolation trenches 31 prevent, for example, leakage of electric current between two successive bit lines. The trenches 31 are then, for example, located under the gate patterns 17. For example, the trenches 31 are linear and each gate pattern is located on and in contact with a trench 31. For example, each trench 31 extends longitudinally in the direction of the bit lines, over the entire length of the bit lines. For example, the trenches 31 extend, vertically, in the layer 13, from the upper face of the layer 13 over only a portion of the thickness of the layer 13.The isolation trenches 31 are for example filled with a dielectric material, for example silicon oxide. The depth of the trenches 31 is for example between 20 nm and 40 nm.

[0040] For example, the chip 11 comprises isolation trenches 43, for example shallow trench isolation (STI) trenches. The depth of the trenches 43 is for example greater than the depth of the trenches 31. The trenches 43 extend, for example, from the upper face of the layer 13, into the layer 13 and into a portion of the layer 15. For example, the trenches 43 make it possible to separate and therefore electrically isolate strips of the layer 13 directly above each word line. For example, each trench 43 extends longitudinally in the direction of the word lines, over the entire length of the word lines. The isolation trenches 43 are for example filled with a dielectric material, for example silicon oxide. The depth of the trenches 43 is for example between 300 nm and 400 nm.

[0041] In the example of the Figures 1A and 1B, for each memory point M, the area 25 located directly above the memory point, the layer 13 (and the area 27) and the layer 15 define a bipolar transistor T1, here of the PNP type, for selecting the memory point. Each memory point M is for example associated with a bipolar transistor T1. In this example, the region 25 constitutes an emitter region of the transistor T1, the region 13 (and the area 27) constitutes a base region of the transistor T1 and the layer 15 constitutes a collector region of the transistor T1. For example, the collector is common to all the transistors T1 of the matrix and is, for example, connected to ground. In this example, the base region 13 is common to all the transistors T1 of the same word line of the memory circuit.

[0042] In the example of the Figure 1A, the grid patterns 17 have in particular the function of respecting surface density constraints of grid patterns at the scale of the chip and of the semiconductor wafer in and on which the chip is formed. These patterns do not have an electrical function in the memory circuit. Grid patterns of similar structure having an electrical function can, on the other hand, be provided in a logic circuit located next to the memory circuit.

[0043] The presence of the gate patterns 17 within the memory circuit can, however, pose certain problems. For example, despite the presence of the isolation trenches 31 and the spacers 21, parasitic leakage currents between the gate patterns 17 and the regions 25 (or 27) can exist, which can disrupt the programming or reading of the memory points M.

[0044] There Figure 2A and the Figure 2Billustrate two partial and schematic sectional views of an electronic chip 45 according to one embodiment.

[0045] More specifically, the Figure 2A illustrates a view along section plane AA of the Figure 2B and the Figure 2B illustrates a view along section plane BB of the Figure 2A .

[0046] The 45 electronic chip illustrated in Figures 2A and 2B is similar to chip 11 shown in Figures 1A and 1B with the difference that the PN junction formed in Figures 1A and 1B by regions 25 and layer 13 is formed, in Figures 2A and 2B , in islands 47 on the surface of layer 13. The islands 47 replace the grid patterns 17 of the Figures 1A and 1B , not present in the memory circuit of chip 45.

[0047] The electronic chip 45 thus comprises islands 47, for example parallelepiped. The islands 47 are located on the surface of the layer 13 and form a grid or matrix comprising rows and columns similar to the matrix of memory points M1. Each island 47 comprises a stack of a semiconductor layer 49 doped with the second conductivity type, for example P type and a semiconductor layer 51 doped with the first conductivity type, for example N type, the layer 51 being on and in contact with the layer 13 and the layer 49 being on and in contact with the layer 51. For example, the layer 49 is made of silicon. For example, the layer 51 is made of silicon. For example, the layers 51 and 49 are respectively more heavily doped than the layers 15 and 13.

[0048] For example, the islands 47 are completely surrounded laterally by spacers 53. In other words, the islands have their four sides covered with spacers 53. For example, the spacers are made of an electrically insulating material, for example silicon nitride.

[0049] The memory points M1 of the chip 45 are formed on and in contact with the islands 47, each memory point M1 being associated with a single island 47 and each island 47 being associated with a single memory point M1. A memory point M1 thus has its via 39 located on and in contact with the layer 49.

[0050] Similar to what has been described in relation to the Figures 1A and 1B , the islands 47 are separated laterally from each other by the epitaxial layer 23 comprising regions 27 facing the vias 29 for resuming contact of the word lines. However, contrary to what has been described in relation to the Figures 1A and 1B, layer 23 does not include regions 25 and layer 23 remains, for example undoped, outside regions 27.

[0051] For example, contrary to what has been described in relation to the Figures 1A and 1B , the chip 45 does not include insulating trenches 31, thus eliminating an etching step and reducing the manufacturing costs of the electronic chip by increasing the yield of the manufacturing process. For example, the PN junction of the layers 49 and 51 is, for each memory point M, isolated by the spacers 53.

[0052] In the embodiment of the Figures 2A and 2B, for each memory point M1, layers 49 and 51 of the underlying island 47, layer 13 and layer 15 constitute a bipolar transistor T2 for selecting the memory point, here of the PNP type. In this example, layer 49 constitutes an emitter region of transistor T2, layer 49 and layer 13 constitute a base region of transistor T2, and layer 15 constitutes a collector of transistor T2. For example, base region 13 is common to all transistors T2 of the same word line of the memory circuit. For example, the collector is common to all transistors T2 of the memory circuit and is, for example, connected to a ground.

[0053] An advantage of the embodiment described in connection with the Figures 2A and 2B is that the leakage currents are reduced with respect to a chip such as illustrated in Figures 1A and 1B .

[0054] Another advantage of the embodiment described in connection with the Figures 2A and 2Bis that it allows the elimination of isolation trenches 31 which allows the reduction of chip manufacturing costs.

[0055] Yet another advantage of the embodiment described in connection with the Figures 2A and 2B is that it can reduce the distance between two bit lines and therefore reduce the size of a chip.

[0056] Examples of methods for manufacturing such a chip will now be described in relation to the figures 3 to 11 .

[0057] THE figures 3 to 9 illustrate, by means of partial and schematic sectional views, successive stages of a process for manufacturing a chip as illustrated in Figures 2A and 2B according to a first mode of implementation.

[0058] There figure 3illustrates a starting structure comprising a memory zone Zm, in which a memory circuit is to be formed, and a logic zone Zl, in which a logic circuit is to be formed comprising, for example, metal oxide semiconductor transistors called MOS (from the English "Metal Oxide Semiconductor"). In figure 3 , the memory area Zm is represented on the right and the logical area Zl is represented on the left.

[0059] In the following description, only the formation of the memory circuit will be detailed.

[0060] The structure illustrated in figure 3 comprises layer 15, for example of the second conductivity type, for example of the P type.

[0061] The structure further comprises, in the logic zone Z1, a buried layer 55, for example insulating, for example made of an oxide, for example silicon oxide, and a layer 57, for example semiconducting, for example silicon. For example, the stack of layers 15, 55 and 57 forms a substrate of the SOI type (from the English "Silicon on Insulator"). In its memory zone Z1, the structure comprises the layer 13 formed on the layer 15. The memory zone of the structure illustrated in figure 3does not include a layer 55 or a layer 57. For example, the plane of the upper face of the layer 13 and the plane of the upper face of the layer 57 are the same. For example, the logic Z1 and memory Zm zones are covered by a layer 59 made of a dielectric material and a conductive layer 61, the layer 59 extending continuously over the entire surface of the structure, on and in contact with the upper face of the layers 57 and 13, and the layer 61 extending over the entire surface of the structure, on and in contact with the upper face of the layer 59. The layer 61 is, for example, a conductive gate layer, for example made of an alloy based on titanium nitride (TiN).Layer 59 is, for example, a gate insulator layer, for example made of a material having a dielectric constant greater than the dielectric constant of silicon dioxide, for example a zirconium and / or hafnium oxide, for example silicon dioxide, hafnium silicide or hafnium silicon oxynitride.

[0062] For example, layers 13 and 15 are made of the same material and come from the same substrate having undergone dopant implantations at different depths.

[0063] There figure 4 illustrates a structure obtained at the end of a step of depositing a semiconductor layer 63 on the upper face of the structure illustrated in figure 3 .

[0064] More particularly, during this step, we first locally remove layers 59 and 61 opposite the memory zone Zm, for example over the entire surface of the memory zone Zm.

[0065] The removal of layers 59 and 61 is, for example, carried out by photolithography followed by etching.

[0066] During this step, layers 59 and 61 can be kept on all or part of the surface of the logical zone Zl.

[0067] Layer 63 is then deposited, for example full plate, on the entire upper face of the structure.

[0068] At the end of the step of depositing layer 63, it covers layer 13 in memory zone Zm and layer 61 in logic zone Zl. More particularly, in the example shown, layer 63 is in contact with the upper face of layer 13 in memory zone Zm and with the upper face of layer 61 in logic zone Zl.

[0069] Layer 63 is, for example, made of silicon, for example monocrystalline silicon. As a variant, layer 63 is made of polycrystalline silicon. For example, layer 63 has a thickness, taken in memory zone Zm opposite layer 13, of between 20 nm and 80 nm, for example of between 40 nm and 50 nm.

[0070] Layer 63 in the logic area is, for example, intended to form gate contact recovery regions of the transistors of the logic circuit.

[0071] There Figure 5 illustrates a structure obtained following a doping step of layer 63.

[0072] More particularly, during this step, a lower part of the layer 63 is doped with the first type of conductivity, for example of the N type, so as to form the layer or sub-layer 51 and an upper part of the layer 63 with the second type of conductivity, for example of the P type, so as to form the layer or sub-layer 49. The doping of the lower part of the layer 63 and the doping of the upper part of the layer 63 are, for example, carried out successively.

[0073] For example, the doping of layer 63 forming layer 51 is carried out before the doping of layer 61 forming layer 49.

[0074] Alternatively, the doping of layer 63 forming layer 49 is carried out before the doping of layer 61 forming layer 51.

[0075] The step of doping the lower part of layer 63 to form layer 51 results, for example, in the doping of an upper part of layer 13 underlying layer 63, thus forming a layer or sub-layer 13'.

[0076] For example, layers 51, 49 and 13' are more heavily doped than layers 13 and 15.

[0077] There figure 6 illustrates a structure obtained at the end of a step of forming the islands 47, the step of forming the islands 47 being distinct from the doping step described in relation to the Figure 5 .

[0078] More particularly, during this step, trenches are etched in layers 49 and 51 laterally delimiting islands 47. For example, islands 47 are arranged in a matrix, according to rows and columns. For example, outside islands 47, layers 49 and 51 are completely removed, the trenches etched between islands 47 opening onto the upper face of layer 13, for example on the upper face of layer 13'. For example, the islands are formed with a pitch, for example constant, between 20 nm and 300 nm, for example between 100 nm and 200 nm, for example of the order of 118 nm. For example, one column of islands 47 out of five is omitted (i.e. etched) in order to leave room for the vias 29 for reconnecting the word lines as described in relation to the Figures 2A and 2B .

[0079] The etching of layers 49 and 51 is, for example, carried out by a dry etching process, for example a conventional polycrystalline silicon etching process.

[0080] For example, during this step, in logic zone Zl, the gates of the transistors are also etched. The etching steps in logic zone Zl and in memory zone Zm are for example carried out within the same etching step, the etching mask being adapted for both zones.

[0081] There figure 7 illustrates a structure obtained at the end of a step of forming the spacers 21 on the sides of the islands 47, for example over the entire periphery of the islands 47.

[0082] For example, during this step, the spacers 21 are for example formed in memory zone Zm simultaneously with spacers around transistor gates in logic zone Zl.

[0083] There figure 8illustrates a structure obtained at the end of a step of forming the layer 23. The step of forming the layer 23 is, for example, distinct from the step of forming the islands 47, the islands 47 not being formed from the layer 23.

[0084] For example, layer 23 is formed by epitaxy from the upper face of layer 13, or where appropriate of layer 13'. The step of forming layer 23 is, for example, carried out after the step of forming spacers 21. Layer 23 is, for example, made of silicon, for example monocrystalline silicon.

[0085] For example, layer 23 has a thickness of between 5 nm and 50 nm, for example between 10 nm and 30 nm.

[0086] There figure 9 illustrates a structure obtained following a localized doping step of layer 23.

[0087] More particularly, during this step, the regions 27 are formed by localized doping of the layer 23. The regions 27 are for example formed by doping of the first conductivity type, for example of the N type. The region 27 is for example more heavily doped than the layer 13. The regions 27 are for example formed in place of the omitted column of islands 47, that is to say that each region 27 is comprised between four columns of islands 47.

[0088] At the end of this step, the memory points M1 are for example formed on and in contact with the islands 47.

[0089] THE Figures 10 and 11 illustrate steps of a method of forming the illustrated chip in connection with the Figures 2A and 2B according to a second mode of implementation.

[0090] More particularly, the process illustrated in relation to the Figures 10 and 11 differs from the process illustrated in relation to the figures 3 to 9in that the islands 47 are formed in an epitaxial layer.

[0091] There figure 10 illustrates a structure obtained at the end of a step of forming layer 63 on the upper face of the structure illustrated in figure 3 .

[0092] At this stage, unlike what was previously described in relation to the figure 3 , layer 63 is formed over the entire upper surface of the structure, in the memory area Zm and the logic area Zl, without prior removal of layers 61 and 59 from the memory area.

[0093] Layer 63 is thus in contact, by its lower face, with the upper face of layer 61 over the entire surface of the structure.

[0094] There figure 11 illustrates a structure obtained at the end of a step of forming an epitaxial layer 65.

[0095] The formation of layer 65 is, for example, preceded by a step of removing, in the memory zone Zm, layer 63 and layers 61 and 59. This step is, for example, carried out through a hard mask, for example based on nitride. This mask makes it possible, for example, to keep layer 63 and layers 61 and 59 in the logic zone to form the gates of the MOS transistors there. For example, at the end of the removal step, the upper face of layer 13 is uncovered. This step is, for example, carried out by photolithography then etching.

[0096] Following the step of removing layers 63, 61 and 59, layer 65 is formed by epitaxy from the upper face of layer 13. Layer 65 will therefore grow in the opening left by the removal of layers 61, 59 and 63. For example, at the end of this step, the upper face of the formed structure is flattened so that the plane of the upper face of layer 63 merges with the plane of the upper face of layer 65. For example, layer 65 has a thickness of between 20 nm and 80 nm, for example between 40 nm and 50 nm.

[0097] The rest of the process is similar to the process described in relation to the figures 5 to 9 . More specifically, following the steps described in relation to the Figures 10 and 11 , we come to dope layer 65, form islands 47, form layer 23 and memory points M1.

[0098] In this embodiment, the doping of the layer 63 comprises a doping of the first type of conductivity, on a lower part, in order to form the layer or sub-layer 51 and of the second type of conductivity, on an upper part, in order to form the layer or sub-layer 49. The islands 47 thus comprise two layers 49 and 51 in monocrystalline silicon.

[0099] An advantage of the embodiment described in connection with the Figures 10 and 11 is that it allows to increase the quality of the materials forming the emitter-base PN junction of the selection transistor T2 of each memory point.

[0100] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the embodiments are not limited to the exemplary numerical values ​​or the exemplary materials mentioned in this description.

[0101] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Electronic chip manufacturing method (45), comprising the following successive steps: a) forming of a first layer (63; 65) on top of and in contact with a second doped semiconductor layer (13) of a first conductivity type (N), the second layer being on top of and in contact with a third doped semiconductor layer (15) of a second conductivity type (P) opposite to the first conductivity type; b) doping of the first layer (63; 65) to form, on the second layer, a first doped sub-layer (51) of the first conductivity type (N) and a second doped sub-layer (49) of the second conductivity type (P); c) forming of islands (47) in the first layer (63; 65) organized in an array of rows and columns at the surface of the second layer (13); and d) forming of memory cells (M1) based on a phase-change material (33) on the islands (47) of the first layer (63; 65), the second layer (13), the third layer (15), and the second sub-layer (49) of the first layer (63; 65) forming a bipolar transistor (T2)and characterized in, after step c), an epitaxy step e) during which a fourth semiconductor layer (23) is formed between the islands (47) of the first layer (63; 65), and, between steps c) and e), a step of forming of electrically-insulating spacers (21) around the islands (47).

2. Method according to claim 1, comprising, after step e), a step of doping of an area (27) of the fourth layer (23) of the first conductivity type (N).

3. Method according to claim 1 or 2, wherein trenches (43) are formed in the second (13) and third (15) layers, between said islands (47), in the row direction.

4. Method according to any of claims 1 to 3, wherein during step d) of forming memory cells (M1), one of said memory cells (M1) is formed in front of each island (47).

5. Method according to any of claims 1 to 4, wherein the first layer (63; 65) is made of silicon.

6. Method according to claim 5, wherein the first layer (63) is made of polysilicon and is formed by deposition.

7. Method according to claim 6, wherein said islands (47) and memory cells (M1) are formed in a memory area (Zm) of the chip, the chip further comprising a logic area (Zl), and wherein, at step c), are further formed, in the first layer (63), at the same time as the islands (47), gates of MOS transistors of a logic circuit.

8. Method according to claim 6, wherein the first layer (65) is made of single-crystal silicon and is formed by epitaxy.

9. Electronic chip (45) comprising islands (47) in a first layer (63; 65) organized in an array of rows and of columns, the islands (47) being arranged at the surface of a second doped semiconductor layer (13) of a first conductivity type (N), itself located on top of and in contact with a third doped semiconductor layer (15) of a second conductivity type (P) opposite to the first conductivity type (N), the first layer (63; 65) comprising a first doped sub-layer (51) of the first conductivity type (N), on the second layer (13) and a second doped sub-layer (49) of the second conductivity type (P), the islands (47) being topped with memory cells (M1) based on a phase-change material (33), the second layer (13), the third layer (15), and the second sub-layer (49) of the first layer (63; 65) forming a bipolar transistor (T2) and characterized in that each island (47) is laterally surrounded with electrically-insulating spacers (21), the device further comprising a fourth semiconductor layer (23) is formed between the islands (47).

10. Electronic chip according to claim 9, wherein the first layer (63) is made of polysilicon.

11. Electronic chip according to claim 9, wherein the first layer (65) is made of single-crystal silicon.

12. Electronic chip (45) according to claim 9 formed by a method according to any of claims 1 to 8.