THREE-DIMENSIONAL STRUCTURE OF NOR MEMORIES

Description

Champ d'application

[0001] The present invention relates to the field of integration of data storage circuits based on three-dimensional memory structures. More particularly, the invention relates to an optimal connection configuration of a three-dimensional memory structure based on resistive non-volatile memories with its peripheral circuitry produced on a different semiconductor substrate. Problème technique

[0002] Emerging non-volatile memory technologies enable denser and more compact memory circuits compared to conventional planar structures. However, current solutions for three-dimensional storage circuits have a major constraint, which consists of the difficulty of individually accessing each memory cell of the structure to perform read and / or write operations. This connectivity constraint induces the need for sequential operation. This type of operation increases the time required for read and / or write operations and thus reduces the performance of the storage circuit.

[0003] The NOR architecture presents a promising candidate for increasing access parallelism and thus increasing the performance of 3D storage circuits. Indeed, in a NOR memory architecture, all memory cells are accessible for reading and writing independently and individually without the need to preselect or inhibit adjacent memory cells. This offers programming flexibility and a considerable gain in execution time. However, the implementation of a NOR architecture in a three-dimensional memory structure on a single substrate presents at least the following technical constraints: The use of large peripheral circuits for memories. These peripheral circuits cover, for example, a plurality of sense amplifiers and read and write control circuits. This considerably increases the circuit area and the physical implementation complexity; The need to use several levels of metal tracks to achieve the complex interconnections between memory cells and peripheral circuits. This constraint is all the more important with the increase in the size of the three-dimensional memory structure; and The low performance of memory cells used in three-dimensional memory structures compared to transistors at advanced technology nodes.

[0004] Thus, there is a need to design new 3D storage circuit architectures, which are less complex, more dense and at the same time present flexibility of read / write access and improved performance in terms of execution speed. Art antérieur / Restrictions de l'état de l'art

[0005] Known two-dimensional (planar) NOR Flash solutions feature a structure with the ability to parallelize write and read operations. The disadvantage of this type of structure is that parallelization comes at the expense of its spatial density. This presents a limitation on the number of memory cells on a predetermined surface.

[0006] Known three-dimensional (cubic) NAND solutions feature a structure with improved spatial density. The disadvantage of this type of structure is that parallelization of read / write operations is very limited. Sequential access is imposed by shared electrical access to the input / output nodes between the memory cells connected in series in this type of structure.

[0007] An example of the prior art is found in document US2022 / 0157845 A1. The document discloses a three-dimensional NOR type memory structure. Réponse au problème et apport solution

[0008] To overcome the limitations of existing solutions from the point of view of density and parallelism of operations, the invention proposes a circuit based on a three-dimensional memory structure produced on a first semiconductor substrate and vertically connected to peripheral circuits produced on a second semiconductor substrate. The second semiconductor substrate is superimposed on the three-dimensional memory structure. The connection between the peripheral circuits and the memory cells of the 3D memory structure is made through vertical connections (in the form of vias) and a distribution of confined connection pads between the 3D structure and the second semiconductor substrate.

[0009] The device according to the invention has an optimal distribution of the connection pads allowing the 3D memory structure to be divided into several independent memory cell sub-matrices. This makes it possible to obtain a “NOR” type structure and to improve the parallelism of memory cell reading and writing operations. The invention thus allows the implementation of an innovative block-based division and routing to have NOR type access. This makes it possible to obtain fine granularity in the three-dimensional structure, offering the possibility of high parallelization in reading and writing.

[0010] In addition, the device according to the invention can be produced with a considerably higher number of memory cells than known solutions in NOR type non-volatile memory (2D NOR flash for example). This offers the advantage of multiplying storage capacities. Thus, the device is capable of parallelizing a considerable number of data processing operations to obtain better performance.

[0011] The device according to the invention further makes it possible to reduce the complexity of peripheral circuits by using transistors with advanced technology nodes occupying less surface area and having improved performance. For example, the transistors with advanced technology nodes cover transistors having a technology node of less than 28nm. Résumé / Revendications

[0012] The subject of the invention is a data storage circuit, of the NOR type, comprising: a three-dimensional memory structure, produced on a first semiconductor substrate, and comprising a plurality of memory planes of rank i ranging from 1 to N, with N a natural integer greater than 1, each plane forming a two-dimensional matrix of non-volatile, resistive and programmable memory cells. Each memory cell has a selection node, a first input / output node and a second input / output node. Said matrix comprises M rows of rank j ranging from 1 to M and K columns of rank k ranging from 1 to K, with M and K two non-zero natural integers.

[0013] For each memory plane: the first input / output nodes of the memory cells belonging to the same column are interconnected; and the second input / output nodes of the memory cells belonging to the same column are interconnected. The three-dimensional memory structure has an upper surface comprising a plurality of connectors distributed on said surface; each connector being connected to at least one of the first or second input / output nodes of the same column; a control circuit configured to apply control voltages to the nodes of each memory cell; and produced on a second semiconductor substrate; the control circuit being superimposed on said upper surface; an interconnection structure comprising: a plurality of connection pads arranged between the control circuit and said upper surface; each connection pad connecting the control circuit to a dedicated connector; each connection pad being connected to an elementary group of memory cells belonging to distinct memory planes. Said plurality of connection pads forms a periodic repetition of a unitary pattern in a plane parallel to the upper surface.

[0014] According to a particular aspect of the invention, each connection pad has a first dimension along a first direction and a second dimension along a second direction. The width along the first direction of the unitary pattern along the first direction being equal to said first dimension multiplied by 4* nb x , with nb x the number of connectors covered by the connection pad area belonging to the same memory plane along the second direction. The length being equal to twice the second dimension of said connection pad along the second direction.

[0015] According to a particular aspect of the invention, the interconnection structure further comprises for each elementary group: a first connection track for interconnecting the first input / output nodes of the memory cells belonging to columns of the same rank k of a plurality of distinct memory planes; a second connection track for interconnecting the second input / output nodes of the memory cells belonging to columns of the same rank k of a plurality of distinct memory planes.

[0016] According to a particular aspect of the invention, the data storage circuit further comprises a dielectric layer encapsulating the three-dimensional memory structure and supporting the plurality of connection pads.

[0017] According to a particular aspect of the invention, the interconnection structure further comprises a set of vias passing through the dielectric layer. Each via among the set of vias being intended to connect a connection pad to an associated connector.

[0018] According to a particular aspect of the invention, the data storage circuit further comprises at least one reading circuit produced on the second semiconductor substrate.

[0019] According to a particular aspect of the invention, each reading circuit comprises an inverter capable of carrying out a differential reading of two memory cells belonging to two adjacent columns and having a first common input / output node and having two second input / output nodes intended to receive complementary control signals.

[0020] According to a particular aspect of the invention, each memory cell comprises: a programmable resistive storage structure having: an upper electrode connected to the second input / output node of said memory cell; and a lower electrode; a selection transistor having a gate connected to the selection node of said memory cell and connecting the lower electrode to the first input / output node of said memory cell.

[0021] According to a particular aspect of the invention, each column of memory cells comprises: A stack of a plurality of selection transistors in a first direction; each selection transistor being of the wrapping gate type and comprising a conduction channel, perpendicular to the first direction, made of a semiconductor material and having two ends; the first end of the channel corresponding to the source of the selection transistor and the second corresponding to the drain of the transistor; a first metal pillar in the first direction connecting the sources of the different selection transistors; a second dielectric layer parallel to the first direction and laterally covering the drains of the selection transistors; at least one metal layer parallel to the first direction and deposited on the dielectric layer; a second metal pillar in the first direction having lateral contact with the at least one metal layer; for each selection transistor, the assembly formed by the source, the dielectric layer and the metal layer constitutes an elementary resistive storage structure.

[0022] According to a particular aspect of the invention, the area of ​​a connection pad is equal to the area of ​​an area of ​​the upper surface comprising a single connector. The unitary pattern comprises three connection pads. The unitary pattern covers an elementary group of memory cells belonging to six successive distinct memory planes.

[0023] According to a particular aspect of the invention, the area of ​​a connection pad is equal to the area of ​​a zone of the upper surface comprising at least six connectors. The unitary pattern comprises at least six connection pads. The unitary pattern covers an elementary group of memory cells belonging to at least 96 successive distinct memory planes.

[0024] According to a particular aspect of the invention, the unitary pattern comprises a first subgroup of connection pads and a second subgroup of connection pads, the subgroups being symmetrical with respect to each other according to a central point of the unitary pattern.

[0025] According to a particular aspect of the invention, the unitary pattern covers two groups of an equal number of column(s), each group of column(s) being connected to the same number of connection pads. Description détaillée

[0026] Other features and advantages of the present invention will become more apparent upon reading the following description in relation to the following appended drawings. [ Fig. 1a ] there figure 1a illustrates a cross-sectional view of an elementary programmable resistive storage structure. Fig. 1b ] there figure 1b illustrates a memory cell used to produce the storage circuit according to the invention. Fig. 2 ] there figure 2 illustrates an electrical diagram of the three-dimensional memory structure used in the storage circuit according to the invention. Fig. 3a ] there figure 3a illustrates a sectional view of the thin-film structure of a column of memory cells of the storage circuit according to the invention. Fig. 3b ] there figure 3b illustrates a sectional view of the thin-film structure of two adjacent columns of memory cells of the storage circuit according to the invention. Fig. 3c ] there figure 3c illustrates a sectional view of the thin-film structure of the connection pillars of the selection signals of the storage circuit according to the invention. Fig. 3d ] there figure 3d illustrates a perspective view of the three-dimensional memory structure used in the storage circuit according to the invention. Fig. 4a ] there figure 4a illustrates a perspective view of the storage circuit according to the invention. Fig. 4b ] there figure 4b illustrates a sectional view of the storage circuit according to a first embodiment of the invention. Fig. 4c ] there figure 4c illustrates a sectional view of the storage circuit according to a second embodiment of the invention. Fig. 5a ] there figure 5a illustrates a top view of the upper surface of the three-dimensional memory structure used in the storage circuit according to the invention. Fig. 5b ] there figure 5b illustrates a top view of the three-dimensional memory structure illustrating a first distribution of the connection pads according to the invention. Fig. 5c ] there figure 5c illustrates a partial top view of the three-dimensional memory structure illustrating a second distribution of the connection pads according to the invention. Fig. 5d ] there figure 5d illustrates a partial top view of the three-dimensional memory structure illustrating the sizing of a unitary pattern of the distribution of the connection pads according to the invention. Fig. 5e ] there figure 5e illustrates an overall top view of the three-dimensional memory structure illustrating the second distribution of the connection pads according to the invention. Fig. 6a ] There figure 6a illustrates a first example of a reading circuit compatible with the invention. Fig. 6b ] There figure 6b illustrates a second example of a reading circuit compatible with the invention.

[0027] We will begin by describing the operating principle of an elementary programmable resistive storage structure. figure 1a illustrates a sectional view of an elementary programmable resistive storage structure. The elementary storage structure S1 consists of the stack of thin layers in the following order: at least a first layer C1 made of an electrically conductive material forming a lower electrode EL2; a second layer C2 made of a dielectric material and at least a third layer C3 made of electrically conductive material forming an upper electrode EL1. The characteristics of the materials constituting the layers of elementary memory structure S1 make it possible to obtain operation as a resistive memory with a variable conductive filament. The second layer C2 is referred to in the remainder of the description as the “central layer”.

[0028] Alternatively, it is possible to produce each electrode EL1 and / or EL2 by a stack of several conductive layers.

[0029] As an example and without loss of generality, the first layer C1 (and therefore the lower electrode EL2) and the third layer C3 (and therefore the upper electrode EL1) are made of titanium nitride TiN. The thickness of each of the layers C1(EL2) and C3(EL1) is of the order of a few tens of nanometers, more particularly equal to 100nm.

[0030] As an example and without loss of generality, the central layer C2 is made of hafnium oxide. The thickness of the central layer C2 is of the order of a few nanometers, more specifically equal to 10nm.

[0031] The operation of a resistive elementary storage structure S1 requires the formation of a conductive filament through at least part of the electrically insulating central layer C2.

[0032] Initially, the elementary storage structure S1 is a MIM (metal, insulator, metal) type structure with infinite resistance between the two electrodes EL1 and EL2. First, the filament F must be formed through at least part of the volume of the central layer C2. The formation of the filament makes it possible to obtain a variable resistance by modulating the length l of the formed conductive filament. To form the filament, a positive electrical formation voltage is applied to the upper electrode EL1. The electrical formation voltage has a sufficiently high amplitude and / or duration to cause the generation of oxygen vacancies in the central layer C2. Indeed, the applied electrical formation voltage must exceed a predetermined value in order to tear oxygen ions from the crystal lattice of the central metal oxide layer.The ions will merge towards the upper electrode EL2 to form a conductive filament F through the central layer made up of oxygen vacancies.

[0033] Once the conductive filament F is formed, we obtain the behavior of a resistive element with a variable resistance R depending on the length of the conductive filament F. When the electrical potential of the upper electrode V EL1 is lower than that of the lower electrode V EL2 , the elementary storage structure S1 sees a negative voltage V reset across its terminals. In this case, oxygen ions will fill part of the oxygen vacancies forming the conductive filament. This results in a reduction in the length of the conductive filament. Thus, the resistance of the resistive element increases. We speak of a high resistive state and a RESET type write operation. Conversely, when the electrical potential of the upper electrode V EL1 is higher than that of the lower electrode V EL2 , the elementary storage structure S1 sees a positive voltage V set across its terminals.The length of the conductive filament F increases by the same mechanism described for the wire forming operation. Thus, the resistance of the resistive element decreases. This is called a low resistive state and a SET type write operation.

[0034] The applied voltage V set must be greater in absolute value than a first voltage threshold to transition from a high resistive state to a low resistive state. Similarly, the applied voltage V reset must be greater in absolute value than a second voltage threshold to transition from a low resistive state to a high resistive state.

[0035] The following convention is chosen as an example: when the elementary storage structure S1 is configured to store binary data in the high logic state (x= 1), it is in a low resistive state. Conversely, when the elementary storage structure S1 is configured to store binary data in the low logic state (x= 0), it is in a high resistive state. An inverse convention is also possible.

[0036] There figure 1b illustrates an electrical diagram of a memory cell CM according to the invention. The memory cell CM comprises a memory structure S1 and a selection transistor T1. The memory cell CM further comprises a selection node WL, a first input / output node SL and a second input / output node BL. The upper electrode EL1 of the storage structure S1 is connected to the second input / output node BL of the memory cell CM. The selection node WL is intended to receive a selection signal VWL. The gate of the selection transistor T1 is connected to the selection node WL. The selection transistor T1 is connected so as to connect the lower electrode EL2 to the first input / output node SL. Thus, the memory cell CM can only be written in SET or RESET when the transistor T1 is in the on state. In addition, the transistor T1 makes it possible to limit the current flowing through the storage structure S1 during a SET operation.Current limitation protects the S1 structure from the risk of internal structural destruction due to the presence of high potential currents during the transition from a high resistive state to a low resistive state.

[0037] Generally, it is possible to produce, within the framework of the invention, memory cells of the OxRAM, CbRAM or any other non-volatile resistive memory technology.

[0038] In general, the invention relates to a data storage circuit 1 of the NOR type comprising a three-dimensional memory structure 10, a control circuit 20 and an interconnection structure 30. The three-dimensional memory structure 10 is intended to store data in the memory cells CM which compose it. The control circuit 20 is configured to apply control voltages VBL, VSL and VWL to the nodes of each memory cell. The interconnection structure 3 is intended to connect the control circuit 20 to the three-dimensional memory structure 10 so as to propagate the control signals associated with each of the memory cells CM.

[0039] In order to clearly explain the invention, we will begin by describing the three-dimensional memory structure 10. The figure 2 illustrates an electrical diagram of the three-dimensional memory structure used in the storage circuit according to the invention.

[0040] The three-dimensional memory structure 10 comprises a plurality of successive memory planes P i of ranks i from 1 to N, with N a natural integer greater than 1. The memory planes P i extend parallel to the geometric plane (X,Y) in an orthonormal reference frame (X,Y,Z). Each memory plane forms a two-dimensional matrix of memory cells CM. Each matrix comprises M rows L j and K columns C k . As an illustrative example, the number of rows per matrix is ​​equal to 3.

[0041] In each memory plane P i , the selection nodes WL of the memory cells belonging to the same row L j are interconnected by a common selection line WL ij. In each memory plane P i , the first input / output nodes SL of the memory cells belonging to the same column C k are interconnected by a common source line denoted SL k. In each memory plane P i , the second input / output nodes BL of the memory cells belonging to the same column C k are interconnected via a common bit line denoted BL k .

[0042] Advantageously and without loss of generality, in each memory plane P i , the memory cells CM of a column C k of odd order share the same source line with the memory cells of the next adjacent column C k + 1 of even order. As a non-limiting example, each memory cell CM of a column C k of odd order receives via a bit line BL k a control signal VBL k complementary to that of the memory cell of the next adjacent column C k + 1 of even order, denoted VBL kb on the bit line BL kb. This architecture offers the advantage of a more compact three-dimensional structure with an optimization of the number of bit lines and source lines.

[0043] The WL ij selection lines are independent of each other. When a logic operation is performed in parallel on all planes (YZ), any memory cell can be opened or closed thanks to an independent WL ij selection node. The WL ij selection lines are independent within a single plane (YZ), all cells unused during a logic operation will be closed. This limits leakage currents in the columns of rank j across all memory planes P i .

[0044] There figure 3a illustrates a sectional view of an embodiment of the thin-film structure of a column C k+1 of four memory cells CM of a three-dimensional memory structure 10 according to the invention. The materials used are presented for non-limiting illustration purposes.

[0045] Column C k+1 comprises a first metal pillar for producing the common source line SL k and a second metal pillar for producing the common intersection line BL kb . The column further comprises a stack of four independent gate-all-around transistors separated by an insulating material. Each transistor corresponds to the selection transistor T1 of a memory cell. Each transistor comprises a silicon DC conduction channel having a first end corresponding to the drain and a second end corresponding to the source. The use of gate-all-around transistors makes it possible to considerably reduce the leakage currents of the structure. In addition, the gate-all-around transistors have the possibility of being stacked on top of each other in order to produce a dense structure according to the invention.The side wall on the drain side of all the transistors is covered with a succession of layers. The succession of layers comprises in this order a first layer of a dielectric material C'2 such as hafnium oxide (HfO 2 ), then a first metallic layer C'3 of Titanium (Ti), then a second metallic layer of titanium nitride (TiN) for example. The succession of layers obtained at each drain of a transistor T1 forms a resistive storage structure S1 corresponding to the stack of the . figure 1a . The upper electrode EL1 consists of the entire first metallic layer of titanium and the second metallic layer of titanium nitride. The central layer C2 is the hafnium oxide layer. The lower electrode EL2 corresponds to the end of the channel of the transistor T1. Advantageously, it is possible to deposit an additional metallic layer between the end of the channel of the transistor T1 and the first layer of a dielectric material C'2 to improve the electrical contact at the lower electrode EL2.

[0046] A transistor T1 and the resistive storage structure S1 connected to it together form a memory cell CM according to the invention. This produces a stack of four memory cells CM.

[0047] Column C k+1 is obtained by making the following arrangement: the first metal pillar SL k in contact with all the second ends corresponding to the source; and the second metal pillar BL kb placed in contact with all the upper electrodes EL1.

[0048] The first metal pillar SL k propagates to the upper face Sur1 of the three-dimensional memory structure 10 in order to form the first associated connector. The second metal pillar BL k+1 propagates to the upper face Sur1 of the three-dimensional memory structure 10 in order to form the second associated connector. The connectors at the upper surface constitute the access points to the bit lines and source lines in order to apply the control voltages VBL and VSL during a reading and / or writing of a selected memory cell CM.

[0049] The structure presented in the figure 3a allows the circuit according to the invention to be physically implemented with improved geometric density compared to known NOR type non-volatile memories. More particularly, the memory structure 10 allows a plurality of 1T1R type memory cells (one transistor and one resistor) to be implemented with a more compact three-dimensional structure compared to known solutions.

[0050] There figure 3b illustrates a cross-sectional view of the thin-film structure of two adjacent columns C k and C k+1 of the same memory plane P i and sharing a common source line SL k . The two adjacent columns then have a common connection pillar corresponding to the common source line SL k . The set formed by these two columns C k and C k+1 is denoted ENS k . The set ENS k is delimited on each side by a left delimiting pillar SP g and a right delimiting pillar SP d . Thus, each memory plane P i is composed of a repetition of ENS k sets separated by delimiting pillars filled with a dielectric material.

[0051] In the illustrated example, each column comprises a stack of three memory cells. Thus, each set ENS k comprises six memory cells CM, two delimiting pillars SP g and SP d, three connection pillars BL k , SL k and BL kb which open onto three connectors, and three selection tracks WL 1 to WL 3 .

[0052] There figure 3c illustrates a cross-sectional view of the thin-film structure of the connection pillars of the selection signals of the same memory plane P i . It should be recalled that for each plane P i , a VWL ij selection signal is propagated for each line of the plane L j . The propagation of each VWL ij selection signal is carried out by a metallic selection track which crosses the plane P i horizontally. Electrical access to each selection track is carried out by a dedicated selection pillar. Each selection pillar is a metallic pillar which propagates vertically connecting the associated horizontal track to a connector located on the upper surface Sur1. This gives three connectors for each memory plane P i. The difference in level between the horizontal selection tracks induces a staircase structure formed by the pillars.

[0053] Advantageously, the pillars of the VWL selection signals ij are separated from each other by delimiting pillars similar to those described previously.

[0054] There figure 3d illustrates a perspective view of the three-dimensional memory structure 10 used in the storage circuit according to the invention. The 3D matrix structure is produced on a semiconductor substrate SUB1. The upper surface Surf1 comprises a plurality of connectors SL, BL and WL. The connectors are distributed in several rows along the X axis. Each row of connectors corresponds to a memory plane P i of rank i. At the end of each row of connectors, there are M=3 WL selection connectors. The number of WL selection connectors corresponds to the number of lines L j of a memory plane. For each row, the connectors are distributed according to the repetition of the triplet BL k , SL k , BL k+1 corresponding to the electrical accesses to the lines of a set of memory cells ENS k . It is observed that the triplets are separated by the ends by pillars of apparent delimiters on the upper surface Sur1.

[0055] We have thus described the distribution of the connectors BL, SL and WL of the memory cells of the three-dimensional memory structure 20. The connectors represent the electrical accesses for applying the control and selection signals during a read and write operation of any one of the memory cells CM ijk , with i the rank of the memory plane P i, j the rank of the row L j of the memory cell L j , and k the rank of its column C k . Each memory cell CM ijk is selectable by the connector associated with its selection node WL ij . The writing and reading of the memory cell CM ijk is carried out by applying a first voltage VSL to its first associated connector SL ik and applying a second voltage VBL to its second associated connector BL ik .

[0056] There figure 4a illustrates a perspective view of the storage circuit 1 according to the invention. The data storage circuit 1 comprises the three-dimensional memory structure 10 described, a control circuit 20 and an interconnection structure 30. The control circuit 20 is configured to apply control voltages VBL, VSL and VWL to the nodes of each memory cell. The interconnection structure 3 is intended to connect the control circuit 20 to the three-dimensional memory structure 10 through the connectors at the upper surface Sur1 of said structure 10.

[0057] The control circuit 20 is a CMOS type integrated circuit produced on the upper face of a second semiconductor substrate SUB2. The lower face of the second semiconductor substrate SUB2 is superimposed on the upper surface Sur1 of the three-dimensional memory structure 10. This produces a stack along the Y axis formed by the three-dimensional memory structure 10 and the control circuit 20. Production on two separate semiconductor substrates has several advantages: Improving the spatial density of the storage circuit; The possibility of implementing the control circuit by CMOS transistors at advanced technological nodes (<28 nm). Because it is difficult to implement transistors of this type on the same substrate supporting the three-dimensional memory structure 10. This difficulty is explained by the following factors: the selection transistors integrated in the three-dimensional structure are optimized for density, and not for logic performance. The manufacturing process on the same substrate requires the construction of each transistor of the control circuit according to the same structure of the selection transistors of the three-dimensional structure. This implies a considerable reduction in performance of the control circuit compared to the use of transistors at advanced technological node; and The establishment of a vertical connection (along Y) and not horizontal (along the plane of the first substrate SUB1).This allows the reduction of the number of levels of metal tracks required to connect the control circuit 20 to the three-dimensional memory structure 10.

[0058] It has already been established that the electrical access to each node BL, SL and WL of a memory cell CM ijk is done via the connectors distributed on the upper surface Sur1. The interconnection structure 30 makes it possible to establish the electrical connection between the connectors of the memory structure 10 and the control circuit 20 in the stacking configuration described. The interconnection structure 30 is a confined interface between the memory structure 10 and the control circuit 20. The interconnection structure 30 comprises a plurality of bonding pads 31, 32, 33 arranged between the control circuit 20 and said upper surface Sur1. The bonding pads 31, 32, 33 are metal layers which extend along a plane parallel to the upper surface Sur1 with a thickness of between 10nm and 500nm.

[0059] In order to better understand the physical implementation of the interconnect structure 30, the figure 4b illustrates a partial sectional view of the storage circuit 1 representing a connection pad 31 according to a first embodiment. We will illustrate a single connection for the sake of simplification of the illustration without loss of generality.

[0060] In order to propagate a control signal VBL k1 provided from the control circuit 20 to at least one first associated input / output node BL k1, the interconnection structure 30 comprises: a first via 39 passing through the second semiconductor substrate SUB2 to transmit the control signal VBL k1; a connection pad 31 arranged between the second semiconductor substrate SUB2 and said upper surface Sur1; a second via 38 connecting the connection pad 31 to a horizontal connection track 41. The horizontal connection track 41 is deposited on the upper surface Sur1. The first via 39 is a TSV (acronym Through Silicon Via) type via. It propagates to the upper metal level Mx of the control circuit 20. This embodiment corresponds to a “Back-to-Face” type assembly because the assembly interface is between the upper surface Sur1 of the three-dimensional memory structure 10 and the lower face of the second substrate SUB2.

[0061] In the context of the invention, a connection pad 31 is common to a plurality of memory cells CM belonging to several successive planes P i1 to P i2 (i1 <i2) et appartenants à des colonnes C k de même rang k. La mise en commun de plots de connexion 31 est réalisée par la piste de connexion 41 horizontale.

[0062] Advantageously, the three-dimensional memory structure 10 is encapsulated in a dielectric layer 60. The connection pad is arranged on the dielectric layer 60 so as to establish an electrical connection with the second via 38. The second via 38 passes through the dielectric layer 60 to the metal track 41 and / or a connector at the upper surface Sur1.

[0063] The stacked assembly of the control circuit 20 to the three-dimensional memory structure 10 is carried out by the “hybrid bonding” technique. Hybrid bonding is understood to mean a simultaneous direct bonding of the metal-metal type and of the dielectric-dielectric type. By exploiting the conductivity of the metal and the insulating nature of the dielectric, the hybrid bonding is used to manufacture a plurality of connection pads. Before assembly, the lower face is manufactured so as to obtain a dielectric surface comprising a first group of metal pads. Similarly, the upper surface of the dielectric encapsulation layer 60 comprises a second group of metal pads having the same planar coordinates as those of the first group. Then, a hybrid bonding is used to carry out the 3D assembly while creating the interconnections at the connection pads 31, 32 and 33.By way of non-limiting example, the connection pads 31, 32 and 33 are copper pads and the hybrid bonding is of the Copper-Copper and SiO 2 -SiO 2 type.

[0064] The same structure described previously remains valid for making connections associated with the first SL input / output nodes and the WL selection nodes.

[0065] The connection pads 31, 32 and 33 must be distinct from each other to avoid short circuits and must be placed at the same time as close as possible to the associated memory cells to improve the performance of the reading and writing operations. Thus, it is necessary to optimize the spatial distribution of the connection pads 31 with respect to the upper surface Sur1.

[0066] Alternatively, the figure 4c illustrates a partial sectional view of the storage circuit 1 representing a connection pad 31 according to a second embodiment. We will illustrate a single connection for the sake of simplification of the illustration without loss of generality. The second embodiment corresponds to a “Face-to-Face” type assembly. Indeed, the assembly interface is between the upper surface Sur1 of the three-dimensional memory structure 10 and the upper face of the control circuit 20. More particularly, each connection pad 31, 32 and 33 is assembled to a metal layer of the upper metal level Mx of the control circuit 20 by the hybrid bonding technique described previously. In this embodiment, there is no need to use a via 39 crossing the entire substrate SUB2 to establish the electrical connection between the control circuit 20 and a connection pad 31.This connection is made directly by hybrid bonding assembly, respecting the alignment between the connection pad and the metal layer of the upper metal level Mx of the associated control circuit 20.

[0067] This embodiment makes it possible to overcome the constraints imposed by TSV type vias and thus improve the density of the assembled structure.

[0068] THE figures 5a - 5 e are intended to illustrate spatial distribution configurations of the connection pads 31, 32 and 33 according to several embodiments of the invention.

[0069] There figure 5a illustrates a top view of a cutout of the upper surface Sur1 of the three-dimensional memory structure 20 before the placement of the connection pads 31. As a non-limiting example, the three-dimensional memory structure 10 of the figure 3d organized in triplets BL k , SL k , BL kb corresponding to the electrical accesses to the lines of a set of memory cells ENS k The sets of memory cells ENS k are separated by the end of the visible delimitation pillars on the upper surface Sur1. This is a view according to the plane (X,Z) in the orthonormal reference frame previously used. The upper surface Sur1 can be cut into several rectangular zones of equal surface. Each rectangular zone is centered at an associated connector or at the visible end of an associated delimitation pillar.

[0070] Each row of the matrix formed by the rectangular areas illustrated has a memory plane P i . The adjacent connectors belonging to the same memory plane P i are separated from each other by a first distance I 1 . The adjacent memory planes P i are separated from each other by a second distance I 2 . By scanning the matrix formed by the rectangular areas, we obtain a horizontal step (along the X axis) equal to the first distance I 1 and a vertical step (along the Z axis) equal to I 1 + I 2 . According to this division, each rectangular area covers a column of M memory cells.

[0071] For example, the first distance I 1 is equal to 160 nm and the second distance I 2 is equal to 100 nm which gives a rectangular area of ​​0.0416 µm 2< .

[0072] After the introduction of the spatial division of the upper surface, the following section is devoted to the description of the distribution of the connection pads on this surface according to the invention.

[0073] There figure 5b illustrates a top view of the three-dimensional memory structure illustrating the distribution of the connection pads 31 according to a first embodiment of the invention. In this embodiment, it is assumed that the area of ​​a connection pad is equal to that of a rectangular zone of the previous cutting.

[0074] The plurality of connection pads is formed by the periodic repetition of a unit pattern 50. In the illustrated case, each unit pattern 50 covers two consecutive columns C k and C k+1 of memory cells CM belonging to six memory planes P i . Each column C k comprises M memory cells. Thus, each unit pattern 50 covers an elementary group 51 of memory cells. A unit pattern 50 covers a sub-matrix of 6 rows and 4 pillars according to the division of the figure 5a (6x4 rectangular regions)

[0075] In the illustrated embodiment, each elementary group 51 then comprises “M*2 columns*6 memory planes” CM ijk memory cells for three connection pads 31, 32 and 33. The connection pads coincide with their vias (represented by hatching) passing through to the connectors.

[0076] The first connection pad 31 is connected to the connector BL k of the memory cell of the first column of the elementary group 51 and belonging to the initial plane P i1 of the elementary group 51. The first connection pad 31 is placed in the coordinate zone (1,1) in the sub-matrix corresponding to the unitary pattern 50. The second input / output nodes BL of the memory cells belonging to the first column are interconnected via the metal track 41.

[0077] The second connection pad 32 is connected to the connector SL k of the memory cells of the third plane P i1+2 of the elementary group 51. The second connection pad 31 is placed in the coordinate zone (3,2) in the sub-matrix corresponding to the unitary pattern 50. The first input / output nodes SL of the memory cells belonging to the whole of the unitary pattern 50 are interconnected via the metal track 40.

[0078] The third connection pad 32 is connected to the connector BL k+1 of the memory cell of the second column of the elementary group 51 and belonging to the penultimate plane P i1+4 of the elementary group 51. The third connection pad 31 is placed in the coordinate zone (5,3) in the sub-matrix corresponding to the unitary pattern 50. The second input / output nodes BL of the memory cells belonging to the second column are interconnected via the metal track 42.

[0079] Thanks to the optimized distribution of the connection pads described above, it is possible to achieve a NOR type memory architecture. Indeed, the described interconnection structure makes it possible to optimize access to the different memory cells so as to increase parallelism compared to routing on the three-dimensional structure directly. As a result, it is possible to perform read and write operations independently in each elementary group 51 corresponding to a unitary pattern. This makes it possible to perform read and write operations in parallel thanks to this independence. The increase in parallelism makes it possible to overcome the constraints of the state of the art and more specifically the constraints of a NAND structure.Indeed, in a NAND structure, the operation of the memory cells is interdependent in the three-dimensional structure, requiring the application of inhibition signals to avoid unwanted write or read operations. In addition, sequential access in a NAND structure involves the polarization of all the transistors in series to turn them on and access the target memory cell. Thus, the 3D NOR structure according to the invention and the proposed connectivity make it possible to combine at the same time the compactness of a 3D structure with the parallelism of operations of a NOR memory structure. Thus, the structure according to the invention has a direct access for each input output node BL,SL and each selection node WL.

[0080] There figure 5c illustrates a top view of the three-dimensional memory structure illustrating the distribution of the connection pads 31 according to a second embodiment of the invention. In this embodiment, it is assumed that the area of ​​a connection pad is greater than that of a rectangular area of ​​the previous cutting. In other words, in horizontal section, the area of ​​a connection pad is greater than the area of ​​a lower via 38.

[0081] As an illustrative and non-limiting example, we consider that a connection pad is a square with side e=1µm and thus, the area of ​​a pad is equal to 1µm 2< . We consider that a rectangular area of ​​the cutting of the upper surface has the following dimensions: the first distance I 1 is equal to 160 nm and the second distance I 2 is equal to 100nm which gives a rectangular area of ​​0.0416 µm 2< . Thus, each connection pad covers an area corresponding to four memory planes P i (along the z axis) and four columns C n (along the x axis) corresponding to 8 rectangular areas of the cutting. The connection pads must be spaced by a distance equivalent to four memory planes P i (along the z axis). The illustrated distribution corresponds to an optimal distribution pattern allowing the following constraints to be respected: A surface area of ​​the connection pads of the order of µm 2<; A spacing between the connection pads greater than or equal to the side of a connection pad.

[0082] The unitary pattern of the connection pads according to the invention must have a minimal area while respecting the aforementioned constraints. Minimizing the area of ​​the unitary pattern makes it possible to maximize the number of associated elementary groups. Thus, the connectivity of each elementary group of memory cell is independent of that of the other elementary groups. This implies an increase in the parallelism of the read and write operations in the data storage circuit.

[0083] In the illustrated embodiment, the unitary pattern 50 covers an elementary group 51 of memory cells comprising “M*6 columns*96 planes” CM ijk memory cells for 12 connection pads 31 to 36 and 31' to 36. The connection pads are wider than the vias (represented by hatching) passing through to the connectors.

[0084] The first connection pad 31 is connected to the connector BL 1 of the memory cells of the first column of the elementary group 51 and belonging to the first 4 memory planes P i1 to P i1+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the first column C 1 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 41.

[0085] The second connection pad 32 is connected to the connector SL 1 of the memory cells of the first column of the elementary group 51 and belonging to the 4 memory planes P i1+2x4 to P i1+2*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes SL of the aforementioned memory cells. The first input / output nodes SL of the memory cells belonging to the first column C 1 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 42.

[0086] The third connection pad 33 is connected to the connector BL 1b of the memory cells of the second column C 2 of the elementary group 51 and belonging to the 4 memory planes P i1+4x4 to P i1+4*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the second column C 2 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 43.

[0087] The fourth connection pad 34 is connected to the connector BL 2 of the memory cells of the third column C 3 of the elementary group 51 and belonging to the 4 memory planes P i1+6x4 to P i1+6*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the third column C 3 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 44.

[0088] The fifth connection pad 35 is connected to the connector SL 2 of the memory cells of the third column C 3 of the elementary group 51 and belonging to the 4 memory planes P i1+8x4 to P i1+8*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes SL of the aforementioned memory cells. The first input / output nodes SL of the memory cells belonging to the third column C 3 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 45.

[0089] The sixth connection pad 36 is connected to the connector BL 2b of the memory cells of the fourth column C 4 of the elementary group 51 and belonging to the 4 memory planes P i1+10x4 to P i1+10*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the fourth column C 4 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 46.

[0090] The seventh connection pad 31' is connected to the connector BL 3 of the memory cells of the fifth column C 5 of the elementary group 51 and belonging to the 4 memory planes P i1+12x4 to P i1+12*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the fifth column C 5 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 41'.

[0091] The eighth connection pad 32' is connected to the SL 3 connector of the memory cells of the fifth column C 5 of the elementary group 51 and belonging to the 4 memory planes P i1+14x4 to P i1+14*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the SL input / output nodes of the aforementioned memory cells. The first SL input / output nodes of the memory cells belonging to the fifth column C 5 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 42'.

[0092] The ninth connection pad 33' is connected to the BL connector 3b of the memory cells of the sixth column C 6 of the elementary group 51 and belonging to the 4 memory planes P i1+16x4 to P i1+16*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the BL input / output nodes of the aforementioned memory cells. The second BL input / output nodes of the memory cells belonging to the sixth column C 6 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 43'.

[0093] The tenth connection pad 34' is connected to the connector BL 4 of the memory cells of the seventh column C 7 of the elementary group 51 and belonging to the 4 memory planes P i1+18x4 to P i1+18*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the seventh column C 7 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 44'.

[0094] The eleventh connection pad 35' is connected to the SL 4 connector of the memory cells of the seventh column C 7 of the elementary group 51 and belonging to the 4 memory planes P i1+20x4 to P i1+20*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the SL input / output nodes of the aforementioned memory cells. The first SL input / output nodes of the memory cells belonging to the seventh column C 7 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 45'.

[0095] The twelfth connection pad 36' is connected to the connector BL 4b of the memory cells of the eighth column C 8 of the elementary group 51 and belonging to the 4 memory planes P i1+22x4 to P i1+22*4+3 of the elementary group 51. The connection is made by a via (hatched) crossing to the connectors of the input / output nodes BL of the aforementioned memory cells. The second input / output nodes BL of the memory cells belonging to the eighth column C 8 of the 96 memory planes of the elementary group 51 are interconnected via the metal track 46'.

[0096] The connection pads 31' to 36' are symmetrical to the connection pads 31 to 36 with respect to the center O of the unitary pattern 50. This is a central symmetry between two groups of pads, the two groups being identical in number and shape. This arrangement makes it possible to obtain a better spatial density of the connection pads.

[0097] Generally, along the z axis the connection pads are periodically repeated with a period equal to 2 times the number of memory planes covered by a connection pad. Let x1 be the number of ENS triplets k covered by the surface of a connection pad along the x axis. The connection pads are distributed over groups of 3*x1 pads. Each group of 3*x1 connection pads is aligned with the columns C k associated with the dedicated ENS sets k. In the illustrated case, 6 pads 31 to 36 are used to access the memory cells of 2 triplets ENS 1 and ENS 2 . The order between the connection pads belonging to the same group is presented here as an example. It is possible to interchange the positions along the Z axis of the connection pads of the same group.

[0098] There figure 5d illustrates a partial top view of the three-dimensional memory structure illustrating the dimensioning of a unitary pattern 50 of the distribution of the connection pads according to the invention. Diagram 501 illustrates the dimensions of a connection pad 31. We will describe the example of a rectangular connection pad but the dimensioning described remains valid for any possible shape of the connection pads. The connection pad has a first dimension ez (width) in a first direction Z and a second dimension ex in a second direction X (length). Along the Z axis, each pattern partially covers a predetermined number nb z of successive memory planes P 1 to P 4 , (here nb z =4). Along the X axis, each pattern covers a predetermined number nb x (here nb x=6) of connectors (BL,SL) per memory plane covered among P 1 to P 4 .

[0099] The optimal sizing of a unitary pattern 50 according to the invention depends on the parameters ez , ex , nb x . Diagram 501 illustrates the optimal sizing of a unitary pattern 50 according to the invention. The width sz of the unitary pattern 50 along the first direction Z is obtained by the following equation: s z = 2 ∗ 2 ∗ e z ∗ nb x

[0100] The length sx of the unit pattern 50 along the second direction X is obtained by the following equation: s x = 2 ∗ e x

[0101] There figure 5e illustrates an overall top view of the three-dimensional memory structure illustrating the distribution of the connection pads according to the second embodiment of the invention.

[0102] In order to connect all of the memory cells of the three-dimensional memory structure 10, the unit pattern 50 is repeated so as to cover the entire upper surface of said three-dimensional structure 10. The unit patterns covering the same memory planes (adjacent along the x axis) cover a three-dimensional sub-matrix 55 of memory cells. The adjacent unit patterns 50 covering the same columns C k (adjacent along the z axis) have distinct metal tracks 41 to 46 (and 41' to 46'). For each unit pattern 50, the metal track 41 is not connected to the metal track 41 of an adjacent unit pattern 50, the metal track 42 is not connected to the metal track 42 of an adjacent unit pattern 50, and so on. A plurality of three-dimensional sub-matrices 55 are thus obtained next to each other.Each three-dimensional sub-matrix 55 is independent of the others with respect to read and write operations (in SET and RESET). This makes it possible to improve the density of the memory structure while increasing the parallelism of the read and write operations (thanks to the independence of the three-dimensional sub-matrices 55).

[0103] There figure 6a illustrates a first example of a reading circuit 70 compatible with the invention. The data storage circuit further comprises, for each column C k of each memory plane P i , a reading circuit 70 produced on the second semiconductor substrate SUB2. Each reading circuit 70 comprises a comparator 71 for comparing a reading signal provided by the first input / output node SL of the memory cell to be read with a reference voltage VREF (or a reference current). The reading signal is propagated through the interconnection structure 30. In order to read the memory cell CM1, the control circuit 20 (not shown here) is configured to apply a positive electrical voltage V 1 to the second input / output node BL, and to maintain the first input / output node SL at electrical ground. The adjacent memory cell CM 2 shares the first input / output node SL with the memory cell CM 1 to be read.The second input / output node BL b of the memory cell CM 2 is kept at electrical ground. This induces a current flow I SL through the first input / output node SL. The comparator makes it possible to evaluate the resistive state of the memory cell CM 1 and therefore read the logic data stored in said memory cell.

[0104] Alternatively, the figure 6billustrates a second example of a reading circuit 70 compatible with the invention. The data storage circuit further comprises, for each column C k of each memory plane P i , a reading circuit 70 produced on the second semiconductor substrate SUB2. Each reading circuit 70 comprises an inverter 72 connected to the first input / output node SL of the memory cell CM 1 to be read. In order to read the memory cell CM 1 , the control circuit 20 (not shown here) is configured to apply a positive electrical voltage V 1 to the second input / output node BL. The adjacent memory cell CM 2 shares the first input / output node SL with the memory cell CM 1 to be read. The control circuit 20 is configured to apply a positive electrical voltage V 2 to the second input / output node BL b of the memory cell CM 2. The voltage V 2 is lower than the voltage V 1 .The difference between V 1 and V 2 is centered on the threshold (or switching) voltage of the inverter. If the memory cell CM 1 stores a logic data x=1 (low resistive state), the voltage V lect at the output of the inverter 71 is in the low logic state. If the memory cell CM 1 stores a logic data x=0 (high resistive state), the voltage V lect at the output of the inverter 71 is in the high logic state.

[0105] This embodiment allows reading to be performed with a less complex reading circuit, which simplifies the implementation and increases reading parallelism.

Claims

1. A data storage circuit (1) of NOR type comprising: - a three-dimensional memory structure (10), produced on a first semiconductor substrate (SUB1), and comprising a plurality of memory planes (Pi) of rank i ranging from 1 to N, with N a natural number greater than 1, each plane forming a two-dimensional array of non-volatile, resistive and programmable memory cells, each memory cell having a selection node (WL), a first input / output node (SL) and a second input / output node (BL); said array comprising M rows (Lj) of rank j ranging from 1 to M and K columns (Ck) of rank k ranging from 1 to K, with M and K two non-zero natural numbers; for each memory plane (Pi): the first input / output nodes (SL) of the memory cells belonging to one and the same column (Ck) are interconnected; and the second input / output nodes (BL) of the memory cells belonging to one and the same column (Ck) are interconnected; the three-dimensional memory structure (10) having an upper surface (Sur1) comprising a plurality of connectors (BLk, SLk, BLkb) distributed over said surface; each connector (BLk, SLk, BLkb) being connected to at least one among the first or second input / output nodes (SL, BL) of a given column (Ck); - a control circuit (20) configured to apply control voltages (VBL, VSL, VWL) to the nodes of each memory cell; and produced on a second semiconductor substrate (SUB2); the control circuit (20) is superposed on said upper surface (Sur1); - an interconnection structure (30) comprising: • a plurality of bonding pads (31, 32, 33) placed between the control circuit (20) and said upper surface (Sur1); each bonding pad (31, 32, 33) connects the control circuit (20) to a dedicated connector (BLk, SLk, BLkb); each bonding pad (31, 32, 33) being connected to an elementary group of memory cells belonging to separate memory planes (Pi), said plurality of bonding pads forming a periodic repetition of a unit pattern (50) in a plane (XZ) parallel to the upper surface (Sur1).

2. The data storage circuit (1) according to claim 1, wherein each bonding pad (31, 32, 33) has a first dimension (ez) in a first direction (Z) and a second dimension (ex) in a second direction (X); - the width (sz) in the first direction (Z) of the unit pattern (50) in the first direction (Z) being equal to the first dimension (ez) multiplied by 4*nbx, with nbx the number of connectors (BLk, SLk, BLkb) covered by the area of the bonding pad (31, 32, 33) belonging to one and the same memory plane (Pi) in the second direction (X); - the length (sx) is equal to twice the second dimension (ex) of said bonding pad (31, 32, 33) in the second direction (X).

3. The data storage circuit (1) according to any one of claim 1 or 2, wherein the interconnection structure further comprises for each elementary group (51): • a first connection track (40) for interconnecting the first input / output nodes (SL) of the memory cells (CM) belonging to columns (Ck) of one and the same rank k of a plurality of separate memory planes; • a second connection track (41) for interconnecting the second input / output nodes (SL) of the memory cells (CM) belonging to columns (Ck) of one and the same rank k of a plurality of separate memory planes.

4. The data storage circuit (1) according to any one of the preceding claims, further comprising a dielectric layer (60) encapsulating the three-dimensional memory structure (10) and bearing the plurality of bonding pads (31, 32, 33); and wherein the interconnection structure (30) further comprises a set of through-vias (38) passing through the dielectric layer (60), each via (38) among the set of vias being intended to connect one bonding pad (31, 32, 33) to one associated connector (BLk, SLk, BLkb).

5. The data storage circuit (1) according to any one of claims 1 to 4, further comprising at least one read circuit (70) produced on the second semiconductor substrate (SUB2).

6. The data storage circuit (1) according to claim 5, wherein each read circuit (70) comprises an inverter (72) able to carry out a differential read of two memory cells belonging to two adjacent columns and having a common first input / output node (SL) and having two second input / output nodes (BL1, BL1b) intended to receive complementary control signals (VBL1, VBL1b).

7. The data storage circuit (1) according to any one of the preceding claims, wherein each memory cell (CM) comprises: - a programmable resistive storage structure having: • an upper electrode (EL1) connected to the second input / output node (BL) of said memory cell (CM); • and a lower electrode (EL2); - a selection transistor (T1) having a gate connected to the selection node (WL) of said memory cell and connecting the lower electrode (EL2) to the first input / output node (SL) of said memory cell (CM).

8. The data storage circuit (1) according to claim 7, wherein each column (Ck) of memory cells (CM) comprises: - a stack of a plurality of selection transistors (T1) in a first direction (Δ); each selection transistor being of gate-all-around type and comprising, perpendicular to the first direction (Δ), a conduction channel (CC) made of a semiconductor material and having two ends; the first end of the channel corresponding to the source of the selection transistor and the second corresponding to the drain of the transistor; - in the first direction (Δ), a first metal pillar (BL1) connecting the sources of the various selection transistors; - a second dielectric layer (C'2) parallel to the first direction (Δ) and laterally covering the drains of the selection transistors; - at least one metal layer (C'3) parallel to the first direction and deposited on the dielectric layer; - in the first direction (Δ), a second metal pillar (BL1b) making lateral contact with the at least one metal layer; for each selection transistor, the assembly formed by the source, the dielectric layer (C'2) and the metal layer (C'3) forms an elementary resistive storage structure (S1).

9. The data storage circuit (1) according to any one of claims 1 to 8, wherein: - the surface area of a bonding pad is equal to the surface area of a region of the upper surface (Sur1) comprising a single connector (BL1, SL1, BL1b); - the unit pattern (50) comprises three bonding pads (31, 32, 33); - the unit pattern (50) covers an elementary group (51) of memory cells belonging to six successive separate memory planes (Pi).

10. The data storage circuit (1) according to any one of claims 1 to 8, wherein: - the surface area of a bonding pad is equal to the surface area of a region of the upper surface (Sur1) comprising at least six connectors (BL1, SL1, BL1b, BL2, SL2, BL2b); - the unit pattern (50) comprises at least six bonding pads (31, 32, 33, 34, 35, 36); - the unit pattern (50) covers an elementary group (51) of memory cells belonging to at least 96 successive separate memory planes (Pi).

11. The data storage circuit (1) according to any one of the preceding claims, wherein the unit pattern (50) comprises a first sub-group of bonding pads and a second sub-group of bonding pads, the sub-groups being symmetrical with respect to each other about a central point (O) of the unit pattern (50).

12. The data storage circuit (1) according to any one of the preceding claims, wherein the unit pattern (50) covers two groups of an equal number of one or more columns, each group of one or more columns being connected to one and the same number of bonding pads.