PIXEL DRIVER CIRCUIT, PIXEL CONTROL METHOD AND DISPLAY DEVICE

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and more particularly, to a pixel driving circuit, a pixel driving method and a display device.BACKGROUND

[0002] At present, a low temperature poly-silicon (LTPS) or oxide thin film transistor (TFT) driving technique is often used in an organic light-emitting diode (OLED) display. Generally, the brightness of an OLED mainly depends on the magnitude of a driving current thereof. The heavier the current, the higher the brightness. A threshold voltage for driving a TFT and a change in carrier mobility are both important factors influencing an OLED driving current. LTPS and oxide TFT devices may change in threshold voltage and carrier mobility thereof as they age over time, which will have influence on the display effect of the OLED and even result in poor display such as reduced contrast, residual image and flickering.

[0003] U.S. patent application published with No. US2017 / 061876 A1 on 2 March 2017 discloses a pixel, which includes an organic light emitting diode, a first transistor configured to control an amount of a current flowing from a first power to a second power via a second node and the organic light emitting diode in response to a voltage of a first node, a first capacitor between the first node and a third node, a second capacitor between the second node and the third node, a second transistor between the third node and a data line and including a gate electrode coupled to a scan line, and a third transistor between the first power and the second node and including a gate electrode coupled to a first emission control line.

[0004] U.S. patent application published with No. US 2014 / 152191 A1 on 5 June 2014 discloses a pixel driving circuit and a driving method thereof, an array substrate and a display apparatus, which is able to avoid an influence on a driving current of an active light emitting device caused by a drift in a threshold voltage of a driving transistor. The pixel driving circuit comprises a data line, a first scan line, a second scan line, a signal controlling line, a light emitting device, a storage capacitor, a driving transistor, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor and a fifth switch transistor. The embodiments of the present disclosure may be applied to a display manufacture.

[0005] Chinese patent application published with No. CN 111739470A on 2 October 2020 discloses a pixel driving circuit, a driving method and a display panel. The pixel driving circuit comprises a driving transistor, an energy storage capacitor, an initialization module,a data writing module, a charging module, a compensation module and a light emitting module, wherein a gate of the driving transistor is connected with the data writing module, a first electrode of the driving transistor is connected with the compensation module, and a second electrode of the driving transistor is connected with the light emitting module; the first pole of the energy storage capacitor is connected with the charging module, and the second pole of the energy storage capacitor is connected with the driving transistor; the initialization module writes the first voltage signal intothe positive electrode of the light emitting diode under the action of the first signal; the data writing module writes a data signal into a gate of the driving transistor under the action of the first signal; the charging module charges the energy storage capacitor under the action of the first signal; the compensation module enables the voltage of the gate and the first electrode of the drivingtransistor to change suddenly under the action of the first signal and the second signal; the light emitting module is connected with the driving transistor and the light emitting diode under the action of the third signal.SUMMARY

[0006] The present disclosure provides a pixel driving circuit, a pixel driving method and a display device, in accordance with the appended claims.

[0007] A first aspect of the present disclosure provides a pixel driving circuit according to claims 1-5.

[0008] A second aspect of the present disclosure provides a pixel driving method according to claims 6-9.

[0009] A third aspect of the present disclosure provides a display device including a display panel and a controller according to claims 10-12.

[0010] The pixel driving circuit, the pixel driving method and the display device of the solutions of the present disclosure can be used for realizing pixel compensation. The pixel driving circuit may include a light-emitting component, a driving transistor, a storage capacitor, a compensation capacitor, and first to third control units. The first to third control units may achieve a reset stage, a threshold voltage compensation stage, a mobility compensation stage and a light-emitting display stage of the pixel driving circuit in coordination with signals provided by a first control line, a second control line, a scan line, a data line, a power line and a ground line, and adverse factors such as a threshold voltage Vth and a power voltage (e.g., a voltage provided by the power line) can be eliminated. However, since a driving current may preferentially charge the compensation capacitor at the mobility compensation stage, a compensation voltage at the compensation capacitor can be derived. Thus, at the light-emitting display stage, a current flowing through the driving transistor is irrelevant to the threshold voltage of the driving transistor and the power voltage, but relevant to controllable parameter such as a data voltage provided by the data line and a duration of the mobility compensation stage. According to this solution, a compensation degree may be adjusted by adjusting the duration of the mobility compensation stage. In other words, the pixel driving circuit of this solution serves for compensating a threshold voltage Vth drift of the driving transistor and the carrier mobility, thereby reducing the influence of the threshold voltage and a leakage current on the driving current, improving the display effect and enhancing the display uniformity.

[0011] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description or partially learned from practicing the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are hereby incorporated in and constitute a part of the present description, illustrate embodiments of the present disclosure, and together with the description, serve to explain the principles of the present disclosure. FIG. 1 shows a schematic diagram of a pixel driving circuit according to embodiment 1 of the present disclosure. FIG. 2 shows a schematic diagram of timing of a pixel driving method according to embodiment 2 of the present disclosure. FIG. 3 shows a schematic diagram of a display device according to embodiment 3 of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The exemplary embodiments are described fully below with reference to the accompanying drawings.

[0014] Moreover, the terms "first" and "second" are merely used for the purpose of description and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, "a plurality of" means two or more, unless otherwise specifically defined.

[0015] Furthermore, the described features, structures or characteristic may be combined in one or more embodiments in any suitable manner. Many specific details are provided in the following description to provide a fully understanding of the embodiments of the present disclosure.Embodiment 1

[0016] This embodiment of the present disclosure provides a pixel driving circuit 10. With reference to FIG. 1, the pixel driving circuit 10 of the present disclosure may include a light-emitting component L, a driving transistor DT, a storage capacitor C1, a compensation capacitor C2, a first control unit K1, a second control unit K2 and a third control unit K3. Connections between these components will be set forth in detail below.

[0017] The light-emitting component L may be a current-driven light-emitting component, and is controlled by a current flowing through the driving transistor DT to emit light. For example, the light-emitting component L may be an organic light-emitting diode (OLED). In other words, the pixel driving circuit 10 may be applied to an OLED display product, and may be particularly applied to an active-matrix OLED (AMOLED) product for the advantages of AMOLED, such as self-illumination, low power consumption, wide viewing angle,high gamut, high contrast and fast response.

[0018] The driving transistor DT has a control terminal TG connected to a point G, a first terminal TS connected to a point S, and a second terminal TD connected to a point D. The control terminal TG of the driving transistor DT may be configured to control the first terminal TS and the second terminal TD of the driving transistor DT to be in an on state or an off state in response to a voltage at the point G, i.e., control the point S and the point D to be switched on or off and allow a current to flow through when the point S and the point D are switched on.

[0019] The control terminal TG of the driving transistor DT in this embodiment may be construed as a gate of the driving transistor DT, and one of the first terminal and the second terminal may be construed as a source of the driving transistor DT, while the other one may be construed as a drain of the driving transistor DT, depending on a type of the specific driving transistor DT and an access situation in a circuit, which will not be defined overmuch here.

[0020] For example, the driving transistor DT may be a P-type transistor. That is, the control terminal TG of the driving transistor DT may place the first terminal TS and the second terminal TD thereof in the on state in response to a low-level signal. But it is not limited thereto, the driving transistor DT may also be an N-type transistor. That is, the control terminal TG of the driving transistor DT may place the first terminal TS and the second terminal TD thereof in the on state in response to a high-level signal.

[0021] The first control unit K1 has a first response terminal K11 connected to a first control line L1, a receiving terminal K12 connected to a power line L8, and an output terminal K13 connected to the point S (it should be understood that as shown in FIG. 1, the output terminal K13 coincides with the point S). The first response terminal K11 may be configured to control an on-off state between the receiving terminal K12 and the output terminal K13 (point S) in response to a level signal provided by the first control line L1; and when the receiving terminal K12 and the output terminal K13 (point S) are switched on, a power voltage provided by the power line L8 to the receiving terminal K12 may be written to the point S. The power line L8 is connected to a supply power VDD.

[0022] The second control unit K2 has a second response terminal K21 connected to a scan line L2, a ground terminal K22 connected to a ground line L3, a data signal terminal K23 connected to a data line L4, a first connection terminal P1 connected to the point G, a second connection terminal P2 connected to a point Q, and a third connection terminal P3 connected to a first terminal 11 of the storage capacitor C1, with a second terminal 12 of the storage capacitor C1 being connected to the point S. The second response terminal K21 may be configured to control on-off states between the receiving terminal K22, the data signal terminal K23, the first connection terminal P1, the second connection terminal P2 and the third connection terminal P3 in response to level signals provided by the scan line L2. Specifically, the second response terminal K21 may be configured to, in response to level signals provided by the scan line L2, control the ground terminal K22 and the third connection terminal P3 to be in the on or off state, the first connection terminal P1 and the third connection terminal P3 to be in the on or off state, the data signal terminal K23 and the first connection terminal P1 to be in the on or off state, and the first connection terminal P1 and the second connection terminal P2 to be in the on or off state, so as to control states of the storage capacitor C1, the compensation capacitor C2, the driving transistor DT and the light-emitting component L at each stage.

[0023] The third control unit K3 has a third response terminal K31 connected to a second control line L5, a fourth connection terminal P4 connected to the point Q, a fifth connection terminal P5 connected to the point D, and a sixth connection terminal P6 connected to a positive electrode 38 of the light-emitting component L, with a negative electrode 39 of the light-emitting component being connected to the ground line L3. The third response terminal K31 may be configured to control on-off states between the fourth connection terminal P4, the fifth connection terminal P5 and the sixth connection terminal P6 in response to level signals provided by the second control line L5. Specifically, the third response terminal K31 may be configured to, in response to level signals provided by the second control line L5, control the fourth connection terminal P4 and the fifth connection terminal P5 to be in the on or off state, and the fifth connection terminal P5 and the sixth connection terminal P6 to be in the on or off state, so as to control states of the storage capacitor C1, the compensation capacitor C2, the driving transistor DT and the light-emitting component L at each stage. The ground line L3 is connected to a ground VSS .

[0024] A first terminal 13 of the compensation capacitor C2 is connected to the point G, while a second terminal 14 of the compensation capacitor C2 is connected to the point Q.

[0025] In this solution, the first control unit K1, the second control unit K2 and the third control unit K3 may achieve a reset stage, a threshold voltage compensation stage, a mobility compensation stage and a light-emitting display stage of the pixel driving circuit 10 in coordination with a control signal provided by the first control line L1, a control signal provided by the second control line L5, a scanning signal provided by the scan line L2, a data signal provided by the data line L4, a power signal provided by the power line L8, and a ground signal provided by the ground line L8, and adverse factors such as a threshold voltage Vth and a power voltage (e.g., a voltage provided by the power line) can be eliminated. However, since a driving current may preferentially charge the compensation capacitor C2 at the mobility compensation stage, a compensation voltage at the compensation capacitor C2 can be derived. Thus, at the light-emitting display stage, a current flowing through the driving transistor DT is irrelevant to the threshold voltage of the driving transistor DT and the power voltage, but relevant to controllable parameter such as a data voltage provided by the data line L4 and a duration of the mobility compensation stage. According to this solution, a compensation degree may be adjusted by adjusting the duration of the mobility compensation stage. In other words, the pixel driving circuit 10 of this solution serves for compensating a threshold voltage Vth drift of the driving transistor DT and the carrier mobility, thereby reducing the influence of the threshold voltage and a leakage current on the driving current, improving the display effect and enhancing the display uniformity.

[0026] For example, the first control line L1, the second control line L5 and the scan line L2 in this embodiment are independent of one another, allowing the first control unit K1, the second control unit K2 and the third control unit K3 to control independent of one another. Thus, the driving difficulty of the pixel driving circuit 10 of this solution can be reduced while the brightness of light emission is guaranteed.

[0027] In an alternative embodiment, the first control unit K1 further has a first transistor M1 having a control terminal 15 connected to the first response terminal K11, a first terminal 16 connected to the receiving terminal K12, and a second terminal 17 connected to the output terminal K13. It may be construed in another way that the first transistor M1 may be equivalent to the first control unit K1. That is, the control terminal 15 of the first transistor M1 is equivalent to the first response terminal K11, while the first terminal 16 of the first transistor M1 is equivalent to the receiving terminal K12 and the second terminal 17 of the first transistor M1 is equivalent to the output terminal K13. Thus, the structure of the first control unit K1 may be simplified while the control of the on-off state between the receiving terminal K12 and the output terminal K13 (point S) is facilitated. This helps reduce the space occupied by the pixel driving circuit 10, thereby facilitating the increase of the pixel density of a display product.

[0028] It should be understood that the control terminals 15,19,22,25,29,34,37 of the first transistor M1 mentioned in the present disclosure and second to seventh transistors M2-M7 mentioned below may be gates of the driving transistors, and one of the first terminal and the second terminal may be a source of a driving transistor, while the other one may be a drain of a driving transistor, depending on a type of each specific driving transistor and an access situation in a circuit, which will not be defined overmuch here.

[0029] For example, the first transistor M1 may be a P-type transistor. That is, the control terminal 15 of the first transistor M1 may place the first terminal 16 and the second terminal 17 thereof in the on state in response to a low-level signal received by the control terminal 15. Without limitation, the first transistor M1 may also be an N-type transistor.

[0030] In an alternative embodiment, the first transistor M1 is disposed adjacent to the driving transistor DT, and a type of the first transistor M1 is the same as that of the driving transistor DT. For example, when the driving transistor DT is a P-type transistor, the first transistor M1 may also be a P-type transistor; alternatively, the driving transistor DT and the first transistor M1 are both N-type transistors to reduce the doping difficulty and increase the product yield.

[0031] In an alternative embodiment, the second control unit K2 further has a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5.

[0032] Control terminals 19,22,25,29 of the second transistor M2, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 each are connected to the second response terminal K21. The second transistor M2 has a first terminal 18 connected to the ground terminal K22 and a second terminal 21 connected to the third connection terminal P3. The third transistor M3 has a first terminal 24 connected to the first connection terminal P1 and a second terminal 23 connected to the third connection terminal P3. The fourth transistor M4 has a first terminal 26 connected to the data signal terminal K23 and a second terminal 27 connected to the first connection terminal P1. The fifth transistor M5 has a first terminal 28 connected to the first connection terminal P1 and a second terminal 31 connected to the second connection terminal P2.

[0033] The second transistor M2, the fourth transistor M4 and the fifth transistor M5 each are first-type transistors; the third transistor M3 is a second-type transistor; and one of the first-type transistor and the second-type transistor is a P-type transistor, while the other one is an N-type transistor. In other words, at the same stage, when the second transistor M2, the fourth transistor M4 and the fifth transistor M5 are in the on state in response to signals provided by the second response terminal K21, the third transistor M3 is in the off state; alternatively, when the second transistor M2, the fourth transistor M4 and the fifth transistor M5 are in the on state in response to signals provided by the second response terminal K21, the third transistor M3 is in the on state.

[0034] The second control unit K2 in this embodiment is designed with four transistors so that the second response terminal K21, the ground terminal K22, the data signal terminal K23, the first connection terminal P1, the second connection terminal P2 and the third connection terminal P3 thereof can be connected, so as to control the on-off states between the ground terminal K22, the data signal terminal K23, the first connection terminal P1, the second connection terminal P2 and the third connection terminal P3 when the second response terminal K21 responses to the scanning signal provided by the scan line L2. Thus, when the working state at each stage is achieved in coordination with other control units, the number of control lines can be reduced. For example, the second control unit K2 only needs one scan line L2 for control so that an aperture ratio of a pixel can be increased.

[0035] In a specific embodiment, the third transistor M3 is disposed closer to the driving transistor DT than the second transistor M2, the fourth transistor M4 and the fifth transistor M5. To reduce the doping difficulty, the types of the third transistor M3 and the driving transistor DT may be set to be the same. For example, when the driving transistor DT is a P-type transistor, the third transistor M3 may also be a P-type transistor, and the second transistor M2, the fourth transistor M4 and the fifth transistor M5 each may be N-type transistors. Alternatively, the driving transistor DT and the third transistor M3 may be both N-type transistors, and the second transistor M2, the fourth transistor M4 and the fifth transistor M5 each may be P-type transistors.

[0036] In a specific embodiment, the third control unit K3 further includes a sixth transistor M6 and a seventh transistor M7.

[0037] Control terminals 34,37 of the sixth transistor M6 and the seventh transistor M7 are both connected to the third response terminal K31. The sixth transistor M6 has a first terminal 32 connected to the fourth connection terminal P4 and a second terminal 33 connected to the fifth connection terminal P5. The seventh transistor M7 has a first terminal 35 connected to the fifth connection terminal P5 and a second terminal 36 connected to the sixth connection terminal P6.

[0038] One of the sixth transistor M6 and the seventh transistor M7 is a P-type transistor, while the other one is an N-type transistor. In other words, at the same stage, when the sixth transistor M6 is in the on state in response to a signal provided by the third response terminal K31, the seventh transistor M7 is in the off state; alternatively, when the sixth transistor M6 is in the off state in response to a signal provided by the third response terminal K31, the seventh transistor M7 is in the on state.

[0039] The third control unit K3 in this embodiment is designed with two transistors so that the third response terminal K31, the fourth connection terminal P4, the fifth connection terminal P5 and the sixth connection terminal P6 thereof can be connected, so as to control the on-off states between the fourth connection terminal P4, the fifth connection terminal P5 and the sixth connection terminal P6 when the third response terminal K31 responses to the control signal provided by the second control line L5. Thus, when the working state at each stage is achieved in coordination with other control units, the number of control lines can be reduced. For example, the third control unit K3 only needs one second control line L5 for control so that an aperture ratio of a pixel can be increased.

[0040] In a specific embodiment, the sixth transistor M6 is disposed closer to the driving transistor DT than the seventh transistor M7. To reduce the doping difficulty, the types of the sixth transistor M6 and the driving transistor DT may be set to be the same. For example, when the driving transistor DT is a P-type transistor, the sixth transistor M6 may also be a P-type transistor, and the seventh transistor M7 may be an N-type transistor. Alternatively, the driving transistor DT and the sixth transistor M6 may be both N-type transistors, and the seventh transistor M7 may be a P-type transistor.

[0041] With reference to the pixel driving circuit shown in FIG. 1, the driving transistor DT, the first transistor M1, the third transistor M3 and the sixth transistor M6 each are P-type transistors, and the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 each are N-type transistors. Without limitation, like the pixel driving circuit 10, the driving transistor DT, the first transistor M1, the third transistor M3 and the sixth transistor M6 each are N-type transistors, and the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 each are P-type transistors, so long as high and low levels of each signal line in FIG. 3 at each stage are converted, which will not be specifically described here.

[0042] For example, the transistors, namely the driving transistor DT and the first to seventh transistors M7, mentioned in this embodiment, each may be LTPS or oxide TFTs to provide good stability and good carrier mobility.

[0043] Furthermore, each transistor may be of a bottom gate type. That is, the control terminal of the transistor is located below an active layer (on a side close to a glass substrate) so that the product can be thinned appropriately. Without limitation, each transistor may also be of a top gate type, depending on the specific circumstances.

[0044] Each transistor may be an enhanced transistor or a depleted transistor, which will not be specifically defined in the embodiment of the present disclosure.

[0045] On this basis, the pixel driving circuit 10 of the embodiment of the present disclosure uses an 8T2C (8 transistors and 2 capacitors) structure to realize the reset stage, the threshold voltage compensation stage, the mobility compensation stage and the light-emitting display stage. With such a design, the compensation degree may be adjusted by adjusting the duration of the mobility compensation stage while the influence of factors such as the threshold voltage Vth, OLED aging and a difference in power signal VDD on display is eliminated. Thus, the display effect can be improved, and the display uniformity can be enhanced. Furthermore, the design of a circuit structure is also simplified so that the occupied area thereof can be reduced, thereby being conducive to realize a high PPI (pixels per inch) display design.Embodiment 2

[0046] Embodiment 2 of the present disclosure further provides a pixel driving method for driving the pixel driving circuit 10 mentioned in any embodiment in embodiment 1. The pixel driving method of embodiment 2 may include a reset stage, a threshold voltage compensation stage, a mobility compensation stage and a light-emitting display stage, which are specifically described below with reference to FIG. 1 and FIG. 2.

[0047] At the reset stage: a first level signal is provided to the first response terminal K11 by the first control line L1 such that the receiving terminal K12 and the output terminal K13 of the first control unit K1 are switched on. A second level signal is provided to the second response terminal K21 by the scan line L2 such that the ground terminal K22 and the third connection terminal P3 of the second control terminal K2 are switched on, the first connection terminal P1 and the third connection terminal P3 are switched off, the data signal terminal K23 and the first connection terminal P1 are switched on, and the first connection terminal P1 and the second connection terminal P2 are switched on. A third level signal is provided to the third response terminal K31 by the second control line L5 such that the fourth connection terminal P4 and the fifth connection terminal P5 of the third control unit K3 are switched off, and the fifth connection terminal P5 and the sixth connection terminal P6 are switched on.

[0048] At the threshold voltage compensation stage: a fourth level signal is provided to the first response terminal K11 by the first control line L1 such that the receiving terminal K12 and the output terminal K13 of the first control unit K1 are switched off. A fifth level signal is provided to the second response terminal K21 by the scan line L2 such that the ground terminal K22 and the third connection terminal P3 of the second control terminal K2 are switched on, the first connection terminal P1 and the third connection terminal P3 are switched off, the data signal terminal K23 and the first connection terminal P1 are switched on, and the first connection terminal P1 and the second connection terminal P2 are switched on. A sixth level signal is provided to the third response terminal K31 by the second control line L5 such that the fourth connection terminal P4 and the fifth connection terminal P5 of the third control unit K3 are switched off, and the fifth connection terminal P5 and the sixth connection terminal P6 are switched on.

[0049] At the mobility compensation stage: a seventh level signal is provided to the first response terminal K11 by the first control line L1 such that the receiving terminal K12 and the output terminal K13 of the first control unit K1 are switched on. An eighth level signal is provided to the second response terminal K21 by the scan line L2 such that the ground terminal K22 and the third connection terminal P3 of the second control terminal K2 are switched off, the first connection terminal P1 and the third connection terminal P3 are switched on, the data signal terminal K23 and the first connection terminal P1 are switched off, and the first connection terminal P1 and the second connection terminal P2 are switched off. A ninth level signal is provided to the third response terminal K31 by the second control line L5 such that the fourth connection terminal P4 and the fifth connection terminal P5 of the third control unit K3 are switched on, and the fifth connection terminal P5 and the sixth connection terminal P6 are switched off.

[0050] At the light-emitting display stage: a tenth level signal is provided to the first response terminal K11 by the first control line L1 such that the receiving terminal K12 and the output terminal K13 of the first control unit K1 are switched on. An eleventh level signal is provided to the second response terminal K21 by the scan line L2 such that the ground terminal K22 and the third connection terminal P3 of the second control terminal K2 are switched off, the first connection terminal P1 and the third connection terminal P3 are switched on, the data signal terminal K23 and the first connection terminal P1 are switched off, and the first connection terminal P1 and the second connection terminal P2 are switched off. A twelfth level signal is provided to the third response terminal K31 by the second control line L5 such that the fourth connection terminal P4 and the fifth connection terminal P5 of the third control unit K3 are switched off, and the fifth connection terminal P5 and the sixth connection terminal P6 are switched on.

[0051] The pixel driving method corresponding to the pixel driving circuit 10 in FIG. 1 is described in detail below with reference to the working timing diagram of the pixel driving circuit shown in FIG. 2.

[0052] The working timing diagram of the pixel driving circuit 11 shown in FIG. 2 depicts level stages of a first control signal SEL1[n] received by the first response terminal K11, a scanning signal Scan[n] received by the second response terminal K21, a second control signal SEL2[n] received by the third response terminal K31, and a data signal Vdata received by the data signal terminal K23 at the reset stage T1, the threshold voltage compensation stage T2, the mobility compensation stage T3 and the light-emitting display stage T4.

[0053] At the reset stage T1: a low-level signal is provided by the first control line L1 to the first response terminal K11 such that the first transistor M1 is switched on; a high-level signal is provided by the scan line L2 to the second response terminal K21 such that the second transistor M2 is switched on, the third transistor M3 is switched off, the fourth transistor M4 is switched on, and the fifth transistor M5 is switched on; and a high-level signal is provided by the second control line L5 to the third response terminal K31 such that the sixth transistor M6 is switched off and the seventh transistor M7 is switched on.

[0054] At the reset stage T1, the storage capacitor C1 and the compensation capacitor C2 are mainly initialized, and the influence of charge of a previous frame is eliminated. At this time, the level signals provided by the scan line L2 and the second control line L5 are both high levels and the signal provided by the first control line L1 is a low level, and therefore, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 are switched on, while the third transistor M3 and the sixth transistor M6 are switched off. The voltage Vs at the first terminal (which may also be construed as the point S) and the voltage V C1 of the storage capacitor C1 are charged to the power voltage V DD provided by the power line L8, i.e., V S =V C1 =V DD . Two terminals of the compensation capacitor C2 are short-circuited by the fifth transistor M5 to empty the charge. Correspondingly, at the reset stage T1, the data voltage provided by the data line L4 is a high-level signal.

[0055] At the threshold voltage compensation stage T2, a high-level signal is provided by the first control line L1 to the first response terminal K11 such that the first transistor M1 is switched off; a high-level signal is provided by the scan line L2 to the second response terminal K21 such that the second transistor M2 is switched on, the third transistor M3 is switched off, the fourth transistor M4 is switched on, and the fifth transistor M5 is switched on; and a high-level signal is provided by the second control line L5 to the third response terminal K31 such that the sixth transistor M6 is switched off and the seventh transistor M7 is switched on. In other words, the threshold voltage V TH of the driving transistor DT is compensated at this stage. At the threshold voltage compensation stage T2 of the driving transistor DT, the signals provided by the first control line L1, the second control line L5 and the scan line L2 each are high-level signals, and therefore, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 are switched on, while the first transistor M1, the third transistor M3 and the sixth transistor M6 are switched off. Since the first transistor M1 is switched off and the storage capacitor C1 is connected to the ground, the charge at the point S is gradually released until V S =V DATA -V TH reaching a stable state, V C1 =V S =V DATA -V TH . At this stage, V TH is written in the storage capacitor C1, and two terminals 13,14 of the compensation capacitor C2 are short-circuited by the fifth transistor M5. It should be understood that V DATA is the data voltage provided by the data line L2.

[0056] At the mobility compensation stage T3, a high-level signal is provided by the first control line L1 to the first response terminal K11 such that the first transistor M1 is switched on; a low-level signal is provided by the scan line L2 to the second response terminal K21 such that the second transistor M2 is switched off, the third transistor M3 is switched on, the fourth transistor M4 is switched off, and the fifth transistor M5 is switched off; and a low-level signal is provided by the second control line L5 to the third response terminal K31 such that the sixth transistor M6 is switched on and the seventh transistor M7 is switched off. In other words, this stage is the carrier mobility compensation stage of the driving transistor. At the mobility compensation stage T3, the signals provided by the first control line L1, the second control line L5 and the scan line L2 each are low-level signals, and therefore, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 are switched off, while the first transistor M1, the third transistor M3 and the sixth transistor M6 are switched on. At this time, given the voltage of the point S V S =V DD and the voltage of the storage capacitor C1 V C1 = V DATA -V TH , the voltage of the point G is: V G =V TH -V DATA +V DD . The current flowing through the driving transistor DT may be expressed as: I OLED = 1 2 × μ × W L × C GI × V GS − V TH 2 = 1 2 × μ × W L × C GI × V TH − V DATA + V DD − V DD − V TH 2 = 1 2 × μ × W L × C GI × V DATA 2

[0057] It should be understood that in the above formula, µ represents the carrier mobility of the driving transistor DT, W represents a channel width of the driving transistor DT, L represents a channel length of the driving transistor DT, C GI represents the gate capacitance of the driving transistor DT, and V GS represents a difference between the voltage V G at the point G and the voltage V S at the point S.

[0058] Furthermore, as can be derived from the above expression formula, I OLED is irrelevant to the threshold voltage V TH of the driving transistor DT and the power voltage V DD provided by the power line L8, but the change of the carrier mobility µ may still affect the driving current.

[0059] When the second control line L5 is switched to a low level, the sixth transistor M6 is switched on and the point G and the point D are connected by the sixth transistor M6. Thus, the driving current may preferentially charge the compensation capacitor C2. Given a charging time t (the duration of the mobility compensation stage, or referring to the width of T3 in the figure), the compensation voltage may be derived according to a capacitor charging model as V µ =I OLED ×t÷C2. Thus, it can be derived that V µ is in direct proportion to I OLED . That is, smaller carrier mobility µ corresponds to lower V µ .

[0060] At the light-emitting display stage, a low-level signal is provided by the first control line L1 to the first response terminal K11 such that the first transistor M1 is switched on; a low-level signal is provided by the scan line L2 to the second response terminal K21 such that the second transistor M2 is switched off, the third transistor M3 is switched on, the fourth transistor M4 is switched off, and the fifth transistor M5 is switched off; and a high-level signal is provided by the second control line L5 to the third response terminal K31 such that the sixth transistor M6 is switched off and the seventh transistor M7 is switched on. At this stage, the current flowing through the driving transistor DT may be expressed as: I OLED = 1 2 × μ × W L × C GI × V DATA − V μ 2 . Thus, when the carrier mobility changes, there is corresponding V µ for compensating the driving current. The influence of the carrier mobility µ on the driving current is reduced, thereby improving the display effect of the OLED light-emitting component.

[0061] As a whole, at the four stages, the power line L8 is configured to provide a high-level direct current signal. The first level signal, the seventh level signal and the tenth level signal provided by the first control line L1 are all low-level signals. The fourth level signal provided by the first control line L1 is a high-level signal. The second level signal and the fifth level signal provided by the scan line L2 are both high-level signals. The eighth level signal and the eleventh level signal provided by the scan line L2 are both low-level signals. The third level signal, the sixth level signal and the twelfth level signal provided by the second control line L5 are all high-level signals. The ninth level signal provided by the second control line L5 is a low-level signal. Data signals provided by the data line L2 at the reset stage and the threshold voltage compensation stage are high-level signals; and data signals provided by the data line L2 at the mobility compensation stage and the light-emitting display stage are low-level signals.

[0062] Furthermore, the pixel driving method of this embodiment further includes adjusting a duration of the pixel driving circuit 10 being at the mobility compensation stage based on display parameter information.

[0063] For example, during detection of a product, a display picture of a display panel may be captured by using a product such as a charge coupled device (CCD). The captured display picture is then resolved to obtain display parameter information that may include brightness, tone and the like. Subsequently, when the display parameter information does not meet target information, the duration of the pixel driving circuit being at the mobility compensation stage may be adjusted so that the display picture meets requirements.Embodiment 3

[0064] Embodiment 3 provides a display device 100, which may be an OLED display device. As shown in FIG. 3, the display device 100 may include a display panel 1 and a controller 2, wherein the display panel 1 has the pixel driving circuit 10 of any implementation solution in embodiment 1, and the controller 2 is configured to carry out the pixel driving method of any implementation solution in embodiment 2.

[0065] The display device 100 of the embodiment of the present disclosure may be an active-matrix organic light-emitting diode (AMOLED) display which has many advantages such as slim body, power saving, bright color and high picture quality and has been widely used. The AMOLED display gradually plays a dominant role in the field of flat panel display, such as an OLED television, a mobile phone, a notebook computer.

Claims

1. A pixel driving circuit (10), comprising: a light-emitting component (L); a driving transistor (DT) having a control terminal (TG) connected to a point G, a first terminal (TS) connected to a point S, and a second terminal (TD) connected to a point D; a storage capacitor (C1); a first control unit (K1) having a first response terminal (K11) connected to a first control line (L1), a receiving terminal (K12) connected to a power line (L8), and an output terminal (K13) connected to the point S; wherein the first response terminal (K11) is configured to control an on-off state between the receiving terminal (K12) and the output terminal (K13) in response to a level signal provided by the first control line (L1); a second control unit (K2) having a second response terminal (K21) connected to a scan line (L2), a ground terminal (K22) connected to a ground line (L3), a data signal terminal (K23) connected to a data line (L4), a first connection terminal (P1) connected to the point G, a second connection terminal (P2) connected to a point Q, and a third connection terminal (P3) connected to a first terminal (11) of the storage capacitor (C1); wherein the second response terminal (K21) is configured to control on-off states between the ground terminal (K22), the data signal terminal (K23), the first connection terminal (P1), the second connection terminal (P2) and the third connection terminal (P3) in response to level signals provided by the scan line (L2), wherein a second terminal (12) of the storage capacitor (C1) is connected to the point S; a third control unit (K3) having a third response terminal (K31) connected to a second control line (L5), a fourth connection terminal (P4) connected to the point Q, a fifth connection terminal (P5) connected to the point D, and a sixth connection terminal (P6) connected to a positive electrode (38) of the light-emitting component (L), wherein the third response terminal (K31) is configured to control on-off states between the fourth connection terminal (P4), the fifth connection terminal (P5) and the sixth connection terminal (P6) in response to level signals provided by the second control line (L5), wherein a negative electrode (39) of the light-emitting component (L) is connected to the ground line (L3); and a compensation capacitor (C2) having a first terminal (13) connected to the point G, and a second terminal (14) connected to the point Q; wherein the second control unit (K2) further has a second transistor (M2), a third transistor (M3), a fourth transistor (M4) and a fifth transistor (M5), wherein control terminals (19,22,25,29) of the second transistor (M2), the third transistor (M3), the fourth transistor (M4) and the fifth transistor (M5) each are connected to the second response terminal (K21); wherein the second transistor (M2) has a first terminal (19) connected to the ground terminal (K22) and a second terminal (21) connected to the third connection terminal (P3); wherein the third transistor (M3) has a first terminal (24) connected to the first connection terminal (P1) and a second terminal (23) connected to the third connection terminal (P3); wherein the fourth transistor (M4) has a first terminal (26) connected to the data signal terminal (K23) and a second terminal (27) connected to the first connection terminal (P1); wherein the fifth transistor (M5) has a first terminal (28) connected to the first connection terminal (P1) and a second terminal (31) connected to the second connection terminal (P2); wherein the second transistor (M2), the fourth transistor (M4) and the fifth transistor (M5) each are N-type transistors, and the third transistor and the driving transistor (DT) are both P-type transistors; wherein the third control unit (K3) further comprises a sixth transistor (M6) and a seventh transistor (M7), wherein control terminals (34) of the sixth transistor (M6) and the seventh transistor (M7) are both connected to the third response terminal (K31); wherein the sixth transistor (M6) has a first terminal (32) connected to the fourth connection terminal (P4) and a second terminal (33) connected to the fifth connection terminal (P5); wherein the seventh transistor (M7) has a first terminal (35) connected to the fifth connection terminal (P5) and a second terminal (36) connected to the sixth connection terminal (P6); and wherein the sixth transistor (M6) and the driving transistor (DT) are both P-type transistors, and the seventh transistor (M7) is an N-type transistor.

2. The pixel driving circuit (10) according to claim 1, wherein the first control unit (K1) further has a first transistor (M1) having a control terminal (15) connected to the first response terminal (K11), a first terminal (16) connected to the receiving terminal (K12), and a second terminal (17) connected to the output terminal (K13).

3. The pixel driving circuit (10) according to claim 2, wherein the first transistor (M1) and the driving transistor (DT) are both P-type transistors.

4. The pixel driving circuit (10) according to claim 1, wherein the second transistor (M2), the fourth transistor (M4) and the fifth transistor (M5) each are N-type transistors, and the third transistor and the driving transistor (DT) are both P-type transistors.

5. The pixel driving circuit (10) according to claim 1, wherein the sixth transistor (M6) and the driving transistor (DT) are both P-type transistors, and the seventh transistor (M7) is an N-type transistor.

6. A pixel driving method for driving the pixel driving circuit (10) according to claim 1, the pixel driving method comprising: a reset stage, a threshold voltage compensation stage, a mobility compensation stage and a light-emitting display stage, wherein at the reset stage: providing a first level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched on; providing a second level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of a second control terminal (K2) are switched on, the first connection terminal (P1) and the third connection terminal (P3) are switched off, the data signal terminal (K23) and the first connection terminal (P1) are switched on, and the first connection terminal (P1) and the second connection terminal (P2) are switched on; and providing a third level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched off, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched on; at the threshold voltage compensation stage: providing a fourth level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched off; providing a fifth level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of the second control terminal (K2) are switched on, the first connection terminal (P1) and the third connection terminal (P3) are switched off, the data signal terminal (K23) and the first connection terminal (P1) are switched on, and the first connection terminal (P1) and the second connection terminal (P2) are switched on; and providing a sixth level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched off, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched on; at the mobility compensation stage: providing a seventh level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched on; providing an eighth level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of the second control terminal (L5) are switched off, the first connection terminal (P1) and the third connection terminal (P3) are switched on, the data signal terminal (K23) and the first connection terminal (P1) are switched off, and the first connection terminal (P1) and the second connection terminal (P2) are switched off; and providing a ninth level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched on, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched off; and at the light-emitting display stage: providing a tenth level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched on; providing an eleventh level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of the second control terminal (K2) are switched off, the first connection terminal (P1) and the third connection terminal (P3) are switched on, the data signal terminal (K23) and the first connection terminal (P1) are switched off, and the first connection terminal (P1) and the second connection terminal (P2) are switched off; and providing a twelfth level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched off, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched on.

7. The pixel driving method according to claim 6,further comprising: adjusting a duration of the pixel driving circuit (10) being at the mobility compensation stage based on display parameter information.

8. The pixel driving method according to claim 7, wherein the power line (L8) is configured to provide a high-level direct current signal, wherein the first level signal, the seventh level signal and the tenth level signal provided by the first control line (L1) each are low-level signals; the fourth level signal provided by the first control line (L1) is a high-level signal, wherein the second level signal and the fifth level signal provided by the scan line (L2) are both high-level signals, wherein the eighth level signal and the eleventh level signal provided by the scan line (L2) are both low-level signals, wherein the third level signal, the sixth level signal and the twelfth level signal provided by the second control line (L5) each arel high-level signals, wherein the ninth level signal provided by the second control line (L5) is a low-level signal, wherein data signals provided by the data line (L4) at the reset stage and the threshold voltage compensation stage are high-level signals; and data signals provided by the data line (L4) at the mobility compensation stage and the light-emitting display stage are low-level signals.

9. The pixel driving method according to claim 6, wherein the power line (L8) is configured to provide a high-level direct current signal, wherein the first level signal, the seventh level signal and the tenth level signal provided by the first control line (L1) each are low-level signals; the fourth level signal provided by the first control line (L1) is a high-level signal, wherein the second level signal and the fifth level signal provided by the scan line (L2) are both high-level signals, wherein the eighth level signal and the eleventh level signal provided by the scan line (L2) are both low-level signals, wherein the third level signal, the sixth level signal and the twelfth level signal provided by the second control line (L5) each arel high-level signals, wherein the ninth level signal provided by the second control line (L5) is a low-level signal, wherein data signals provided by the data line (L4) at the reset stage and the threshold voltage compensation stage are high-level signals; and data signals provided by the data line (L4) at the mobility compensation stage and the light-emitting display stage are low-level signals.

10. A display device (100) comprising a display panel (1) and a controller (2), wherein the display panel (1) has the pixel driving circuit (10) according to any one of claims 1 to 5.

11. The display device (100) according to claim 10, wherein the controller (2) is configured to carry out a pixel driving method, wherein the pixel driving method comprises: a reset stage, a threshold voltage compensation stage, a mobility compensation stage and a light-emitting display stage, wherein at the reset stage: providing a first level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched on; providing a second level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of a second control terminal (K2) are switched on, the first connection terminal (P1) and the third connection terminal (P3) are switched off, the data signal terminal (K23) and the first connection terminal (P1) are switched on, and the first connection terminal (P1) and the second connection terminal (P2) are switched on; and providing a third level signal to the third response terminal (K31) by the second control line (L2) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched off, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched on; at the threshold voltage compensation stage: providing a fourth level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched off; providing a fifth level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of the second control terminal are switched on, the first connection terminal (P1) and the third connection terminal (P2) are switched off, the data signal terminal (K23) and the first connection terminal (P1) are switched on, and the first connection terminal (P1) and the second connection terminal (P2) are switched on; and providing a sixth level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched off, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched on; at the mobility compensation stage: providing a seventh level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched on; providing an eighth level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of the second control terminal (K2) are switched off, the first connection terminal (P1) and the third connection terminal (P3) are switched on, the data signal terminal (K23) and the first connection terminal (P1) are switched off, and the first connection terminal (P1) and the second connection terminal (P2) are switched off; and providing a ninth level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched on, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched off; and at the light-emitting display stage: providing a tenth level signal to the first response terminal (K11) by the first control line (L1) such that the receiving terminal (K12) and the output terminal (K13) of the first control unit (K1) are switched on; providing an eleventh level signal to the second response terminal (K21) by the scan line (L2) such that the ground terminal (K22) and the third connection terminal (P3) of the second control terminal (K2) are switched off, the first connection terminal (P1) and the third connection terminal (P3) are switched on, the data signal terminal (K23) and the first connection terminal (P1) are switched off, and the first connection terminal (P1) and the second connection terminal (P2) are switched off; and providing a twelfth level signal to the third response terminal (K31) by the second control line (L5) such that the fourth connection terminal (P4) and the fifth connection terminal (P5) of the third control unit (K3) are switched off, and the fifth connection terminal (P5) and the sixth connection terminal (P6) are switched on.

12. The display device (100) according to claim 11, the pixel driving method comprises: adjusting a duration of the pixel driving circuit (10) being at the mobility compensation stage based on display parameter information.