METHOD FOR TRANSFERRING A LAYER FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATE

Description

[0001] The present application is based on, and claims priority from, French patent application 2204713 filed on May 18, 2022, entitled "Method for transferring a layer from a source substrate to a destination substrate" Domaine technique

[0002] This description generally concerns the manufacturing processes of microelectronic components based on semiconductor materials. More specifically, it focuses on a process for transferring a semiconductor layer from a source substrate to a destination substrate. Technique antérieure

[0003] In microelectronic component manufacturing processes, layer transfers are commonly used to transfer a relatively thin, high-crystalline-quality semiconductor layer onto a thicker, lower-crystalline-quality destination substrate or a less expensive material.

[0004] After the transfer, the transferred layer can serve as a basis for an epitaxial step. Microelectronic components can then be formed in and on the epitaxial layer.

[0005] It would be desirable to at least partially overcome certain drawbacks of known methods for transferring a semiconductor layer from a source substrate to a destination substrate. US patent 2007 / 023867 describes a method for transferring a layer from a source substrate to a destination substrate, comprising the following steps: forming a step opposite a peripheral portion of the bonding surface of said layer and / or the destination substrate, this operation involving mechanical or chemical etching; activating the bonding surface of said layer and the bonding surface of the destination substrate by ion etching and ion deposition of a bonding material; and bringing the bonding surface of said layer into contact with the bonding surface of the destination substrate.

[0006] We are particularly interested here in improving the quality of the edges of the transferred layer. Résumé de l'invention

[0007] One embodiment provides a method for transferring a layer from a source substrate to a destination substrate, comprising the following steps: a) place a masking disc on a central portion of a bonding surface of said layer and / or the destination substrate; b) perform ion etching to form a step opposite a peripheral portion, not covered by the masking disc, of the bonding surface of said layer and / or the destination substrate; c) remove the masking disc; d) activate the bonding surface of said layer and the bonding surface of the destination substrate by ion etching or ion deposition of a bonding material; and e) after step d), bring the bonding surface of said layer into contact with the bonding surface of the destination substrate. in which steps b) and d) are carried out successively in the same ion treatment chamber; and in which steps d) and e) are carried out under vacuum, without a break in vacuum between the two steps.

[0008] According to one embodiment, the destination substrate and / or the source substrate has beveled edges over a first width.

[0009] According to one embodiment, after step b), the step extends, from the edge of said layer and / or the edge of the destination substrate over a width greater than or equal to the first width.

[0010] According to one embodiment, the disk has a diameter smaller than the diameter of the source substrate and / or the diameter of the destination substrate.

[0011] According to one embodiment, the process includes, after step e), a step f) of removing the source substrate.

[0012] According to one embodiment, step f) includes an annealing step leading to fracturing the assembly obtained at the end of step e), in the plane of an implanted buried layer separating said layer from the source substrate.

[0013] According to one embodiment, said layer is a semiconductor layer.

[0014] According to one embodiment, the process comprises, after step f), an epitaxial step on and in contact with the face of said layer opposite the destination substrate.

[0015] According to one embodiment, after step b), the step extends to a depth, from the bonding surface of said layer and / or the bonding surface of the destination substrate, greater than 700 nm.

[0016] According to one embodiment, step d) consists of depositing a layer of adhesive on the adhesive surface of said layer and / or on the surface of the destination substrate.

[0017] According to one embodiment, the bonding layer has a thickness between 0.2 nm and 100 nm, for example between 1 nm and 20 nm. Brève description des dessins

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1A , there figure 1B , there figure 1C , there figure 1D , there figure 1E and the figure 1F are cross-sectional views, partially and schematically illustrating successive stages of an example of a process for transferring a semiconductor layer from a source substrate to a destination substrate according to a first embodiment; and the figure 2A , there figure 2B , there figure 2C , there figure 2D , there figure 2E and the figure 2F are cross-sectional views, partially and schematically illustrating successive steps of an example of a process for transferring a semiconductor layer from a source substrate to a destination substrate according to a second embodiment. Description des modes de réalisation

[0019] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0020] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, the fabrication processes for microelectronic components from the transferred semiconductor layers have not been detailed, as the described transfer processes are compatible with all or most common microelectronic component fabrication processes.

[0021] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0022] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean within 10%, preferably within 5%.

[0023] There figure 1A , there figure 1B , there figure 1C , there figure 1D , there figure 1E and the figure 1F are cross-sectional views, partially and schematically illustrating successive stages of an example of a process for transferring a semiconductor layer from a source substrate to a destination substrate according to a first embodiment.

[0024] There figure 1A represents, on the left, a structure 110 comprising a source substrate 13 and a semiconductor layer to be transferred 15, and, on the right, a destination substrate 17.

[0025] The semiconductor layer to be transferred 15 is disposed on the upper surface of the substrate 13 and, for example, in contact with it. The semiconductor layer 15 extends, for example, continuously and with a substantially uniform thickness over the entire upper surface of the substrate 13. The semiconductor layer 15 is, for example, a single-crystal layer. As an example, the semiconductor layer 15 is a silicon carbide (SiC) layer, for example, single-crystal, for example, of the 4H-SiC type. Alternatively, the semiconductor layer 15 is made of germanium (Ge), for example, single-crystal. The described embodiments are not limited to these particular examples.

[0026] The source substrate 13 is, for example, made of a semiconductor material. As an example, the source substrate 13 is made of the same material as the semiconductor layer 15. However, the embodiments described are not limited to this particular case.

[0027] The layer to be transferred 15 has, for example, a thickness between 100 nm and 10 µm, for example between 300 nm and 2 µm.

[0028] The source substrate 13 has, for example, a thickness between 100 µm and 1 mm, for example between 250 µm and 800 µm, for example on the order of 350 µm.

[0029] The destination substrate 17 can be made of a semiconductor material or a dielectric material. The destination substrate 17 is, for example, a semiconductor wafer, for example made of silicon or polycrystalline silicon carbide, for example of type 3C-SiC.

[0030] For example, the destination substrate 17 and the source substrate 13 have essentially the same shape and dimensions when viewed from above. For example, the destination substrate 17 and the source substrate 13 are both circular when viewed from above and have, for example, the same diameter.

[0031] To limit the risk of breakage, the destination substrate 17 and / or the source substrate 13 preferably have beveled or rounded edges and a drop-off zone, for example on a peripheral annular band with a width between 0.1 mm and 5 mm, or for example between 0.2 mm and 3 mm. In other words, the destination substrate 17 and / or the source substrate 13 have a decreasing thickness at their periphery as one moves away from the center of the substrate, for example on a peripheral annular band with a width between 0.1 mm and 5 mm, or for example between 0.2 mm and 3 mm.

[0032] During the bonding of the transfer layer 15 to the destination substrate 17, the transfer layer 15 is brought into contact, by its upper face in the orientation of the figure 1A , on the upper face of the destination substrate 17.

[0033] In practice, and particularly when the destination substrate 17 and / or the source substrate 13 have beveled edges, the bonding of layer 15 to the destination substrate 17 is incomplete at the periphery of the assembly. Indeed, during the bonding of layer 15 to substrate 17, while layer 15 and substrate 17 are well contacted at the center of the assembly, they are not, or only partially, in contact at the edges of the assembly, notably due to the peripheral bevel of the substrates and / or any flatness defects in the substrates.

[0034] Following a step of removing the source substrate 13, the peripheral parts of layer 15 that are not bonded or are poorly bonded to the destination substrate 17 detach. Thus, a peripheral annular band of the destination substrate 17 is not covered, or only partially covered, by layer 15.

[0035] Without special precautions, after the transfer, the edges of layer 15 at the periphery of the assembly are irregular. This is due to the irregular bond boundary between layer 15 and the destination substrate 17. This irregularity of the edges of layer 15 can lead to defects that may propagate towards the center of layer 15 during subsequent microelectronic component manufacturing steps, for example, during an epitaxial step from the top face of layer 15. In particular, the defects are likely to propagate into the layer epitaxially deposited on layer 15.

[0036] The aim here is to improve the regularity or sharpness of the edges of layer 15 after the transfer.

[0037] There figure 1B illustrates an etching step of a step 29 on the periphery of the top face, called the bonding surface of layer 15, and of a step 30, on the periphery of the top face, called the bonding surface of the destination substrate 17.

[0038] Step 29 extends, from the upper face of layer 15, for example into a part of layer 15. Alternatively, step 29 extends, from the upper face of layer 15 into layer 13 and, for example, into a part of substrate 13.

[0039] Steps 29 and 30 are produced by an ionic etching or abrasion process consisting of sending a beam of ions 19 or atoms, for example neutral ones, onto the areas to be etched. This step is carried out under vacuum, that is to say at a pressure lower than atmospheric pressure, for example under ultra-high vacuum, for example under a pressure less than 10⁻⁷ mbar, for example less than 10⁻⁸ mbar.

[0040] During the etching step, only the free parts of the upper faces of the destination substrate 17 and of layer 15, i.e. the parts of the upper face of layer 15 and of the destination substrate 17 which are not covered by a mask are etched.

[0041] In the example, of the figure 1B In order to form a step 29 only on the periphery of the bonding surface of layer 15 and a step 30 only on the periphery of the bonding surface of the destination substrate 17, the central portions of the bonding surfaces are each covered by a masking disc. Thus, during the etching step, a masking disc 31 covers a central portion of the bonding surface of layer 15 and a masking disc 33 covers a central portion of the bonding surface of the destination substrate 17.

[0042] For example, in vertical projection, the center of the masking disk 31 coincides with the center of the source substrate 13, and the center of the masking disk 33 coincides with the center of the destination substrate 17. For example, the diameter of the masking disk 31 is smaller than the diameter of the source substrate 13, and the diameter of the masking disk 33 is smaller than the diameter of the destination substrate 17. The difference between the diameter of the source substrate 13 and the diameter of the masking disk 31 is, for example, between 0.1 mm and 5 mm, for example, between 0.5 mm and 3 mm, for example, on the order of 1 mm. The difference between the diameter of the destination substrate 17 and the diameter of the masking disk 33 is, for example, between 0.1 mm and 5 mm, for example, between 0.5 mm and 3 mm, for example, on the order of 1 mm. As an example, masking discs 31 and 33 are identical, except for manufacturing variations.

[0043] The masking discs 31 and 33 are, for example, metallic and / or made of a semiconductor or insulating material. By way of example, during the etching step of steps 29 and 30, the masking disc 31 is placed on and in contact with the upper surface of the semiconductor layer 15, and the masking disc 33 is placed on and in contact with the upper surface of the destination substrate 17.

[0044] In the example shown, the engraving of step 29 in layer 15 and the engraving of step 30 in the destination substrate 17 are performed simultaneously. Alternatively, the engraving of step 29 in layer 15 and the engraving of step 30 in the destination substrate 17 are performed sequentially.

[0045] For example, step 29 has a depth, from the top face of layer 15, greater than approximately 700 nm, for example, greater than approximately 1 µm. For example, step 30 has a depth, from the top face of substrate 17, greater than approximately 700 nm, for example, greater than approximately 1 µm. For example, due to the different nature of layer 15 and substrate 17, steps 29 and 30 do not have the same depth.

[0046] At the end of this step, the masking discs 31 and 33 are removed.

[0047] There figure 1C illustrates an activation step of the bonding surfaces of layer 15 and the destination substrate 17.

[0048] The process used in this step is an ionic etching or abrasion process similar to the process used in the formation of steps 29 and 30. In particular, according to one aspect of the method of implementation of the figures 1A à 1F , the activation of the bonding surfaces by etching or ionic abrasion is carried out in the same ionic treatment chamber as the etching of steps 29, 30. The etching energy and / or etching time are however lower than the etching energy and / or etching time used during the formation of steps 29 and 30 so as to activate the exposed surfaces without etching a significant thickness of layer 15 and substrate 17.

[0049] During this step, the beam of ions 19 or atoms, for example neutral atoms, directed onto the surfaces to be activated removes, for example, any oxides present on the surface of the activated faces, leaving dangling bonds that will be used to form covalent bonds when the activated surfaces are brought into contact in a subsequent step. Such a bonding process is generally called surface-activated bonding or SAB. As an example, during this step, the material removed from the surfaces to be activated is less than a few nanometers, for example, less than 5 nm. In any case, the thickness of material removed during this activation step is less than the thickness removed during the formation of steps 29 and 30.

[0050] For example, during the step illustrated in figure 1C , the surface exposure time is, for example, reduced and / or the power of the ion beam 19 is, for example, reduced compared to the step illustrated in figure 1B .

[0051] In the example shown, the activation of the bonding surface of layer 15 and the activation of the bonding surface of the destination substrate 17 are performed simultaneously. The activation of the bonding surface of layer 15 and the activation of the bonding surface of the destination substrate 17 are performed successively without any gap interruption.

[0052] As an example, during this step, the entire surface of the substrate 17 bonding surface and the entire surface of the layer 15 bonding surface are activated.

[0053] There figure 1D illustrates structure 110 and destination substrate 17 after the activation step of the upper faces of destination substrate 17 and layer 15.

[0054] At this stage, a face 15' corresponding to the bonding surface of layer 15 which extends into step 29 and a face 17' corresponding to the bonding surface of the destination substrate 17 which extends into step 30 are activated in the same way as the central parts of layer 15 and substrate 17.

[0055] There figure 1E illustrates a step of bonding the structure 110 to the destination substrate 17. During this step, the bonding surface 15' of the layer 15 is brought into contact with the bonding surface 17' of the destination substrate 17. Due to the geometry of the structure 110 and the substrate 17, during this step, only a central area of ​​the bonding surface of the layer 15, delimited by the step 29, is brought into contact with a central area of ​​the bonding surface of the substrate 17, delimited by the step 30.

[0056] The dangling bonds formed on the bonding surface of layer 15 and the dangling bonds formed on the bonding surface of substrate 17 create, when they are brought into contact, covalent bonds ensuring the fixation of layer 15 on substrate 17. The depth of steps 29, 30 being sufficiently large, the dangling bonds formed at the periphery of layer 15, in step 29 and the dangling bonds formed at the periphery of substrate 15, in step 30, although they are placed opposite each other, do not form covalent bonds.

[0057] For example, the gluing step is carried out under a temperature between 10 °C and 400 °C, for example between 10 °C and 40 °C, for example at room temperature.

[0058] There figure 1F illustrates the structure obtained after a step of removing the source substrate 13 of the structure illustrated in figure 1E .

[0059] For example, the substrate 13 is made of the same semiconductor material as the layer 15, and a buried layer (not visible in the figures), implanted, for example, by hydrogen ions (H+), separates the layer 15 from the source substrate 13. For example, the structure 110 is initially a single-crystal semiconductor wafer, which is implanted from its upper face, for example by hydrogen ions, so as to create the buried implanted layer separating the transfer layer 15 from the source substrate 13. For example, the removal of the source substrate 13 may include a thermal annealing step leading to the fracturing of the structure 110 in the plane of the buried implanted layer, so as to allow the removal of the source substrate 13 and retain only the layer 15 on the destination substrate 17.

[0060] More generally, the removal of substrate 13 can be achieved by any other known method of removing a source substrate during a transfer of a semiconductor layer from a source substrate to a destination substrate, for example by grinding, or by a laser lift-off process.

[0061] During the removal of the source substrate 13, only the central area of ​​the layer to be transferred 15 located outside the opposite of the steps 29 and 31 remains attached to the destination substrate 17. The peripheral part of the destination substrate 17, located opposite the steps 29 and 30, remains free, that is to say not covered by the layer 15.

[0062] Thus, at the end of the process illustrated in figures 1A à 1F , the transferred layer 15 has a clear and regular edge corresponding substantially to the edge of the step 29 and / or 30.

[0063] The activation steps of the bonding surfaces ( figure 1C ) and gluing ( figure 1E ) are carried out without breaking the vacuum, for example within the same equipment, including, for example, an activation chamber in which the etching step of the figure 1B and the activation step of the figure 1C and a bonding chamber in which the bonding step of the figure 1E .

[0064] In practice, during the gluing stage ( figure 1E ), we seek to align the structures so as to make the central areas of the bonding surface of layer 15, delimited by step 29 and of the bonding surface of substrate 17, delimited by step 30 coincide. However, even if the alignment is not perfect, the proposed solution makes it possible to obtain a clean edge of the transferred layer, since only the portions of the bonding surfaces in contact adhere to each other.

[0065] In the example illustrated in figure 1B , the etching of layer 15 is carried out through a masking disc 31 so as to form a step 29 in layer 15 and the etching of the destination substrate 17 is carried out through a masking disc 33 so as to form a step 30 in the destination substrate 17. Alternatively, a masking disc may be provided only on layer 15 or only on the destination substrate 17 so as to form a step on only one of the two bonding surfaces.

[0066] There figure 2A , there figure 2B , there figure 2C , there figure 2D , there figure 2E and the figure 2F are cross-sectional views, partially and schematically illustrating successive steps of an example of a process for transferring a semiconductor layer from a source substrate to a destination substrate according to a second embodiment.

[0067] The second embodiment is similar to the first embodiment illustrated in figures 1A à 1F The difference being that, in the second embodiment, the activation of the bonding surfaces is achieved by depositing a thin layer of a bonding material that provides dangling bonds, which then allow covalent bonds to form when the activated surfaces are brought into contact. The common elements with the process of figures 1A à 1F will not be detailed again below. Only the differences with the process of figures 1A à 1F will be highlighted.

[0068] There figure 2A illustrious, in a similar way to the figure 1A , on the left side, structure 110 comprising the source substrate 13 and the semiconductor layer to be transferred 15, and, on the right side, the destination substrate 17.

[0069] There figure 2B illustrious, in a similar way to the figure 1B , an engraving step of step 30, on the periphery of the upper face of the destination substrate 17 and of step 29 on the periphery of the upper face of layer 15.

[0070] There figure 2C illustrates an activation step of the bonding surface, layer 15 and the bonding surface, of the destination substrate 17.

[0071] This activation step involves depositing a thin activation layer, also called a bonding layer, onto the surfaces to be activated. This creates dangling bonds that will form covalent bonds when the activated layers are brought into contact in a subsequent step. This bonding technique is called atomic diffusion bonding, or ADB.

[0072] For example, in this step, a beam of ions or atoms, for example of a neutral gas, such as argon, bombards a target 24 made of a material whose atoms 25 detach and are deposited uniformly in a thin layer on the surface(s) to be activated. For example, the target is metallic, for example, tungsten or titanium. Alternatively, the target 24 is made of a semiconductor material, for example, silicon, germanium, etc.

[0073] This step is carried out under vacuum, i.e. below atmospheric pressure, for example under ultra-high vacuum, for example under a pressure below 10⁻⁷ mbar, for example below 10⁻⁸ mbar.

[0074] In the implementation of figures 2A à 2F , the activation of the bonding surfaces by spraying a bonding material is carried out in the same ionic treatment chamber as the engraving of steps 29, 30.

[0075] In the example shown, the activation of the bonding surface of layer 15 and the activation of the bonding surface of the destination substrate 17 are performed simultaneously. Alternatively, the activation of the bonding surface of layer 15 and the activation of the bonding surface of the destination substrate 17 are performed sequentially without any gap interruption.

[0076] There figure 2D illustrates structure 110 and destination substrate 17 after the activation step of the bonding surfaces of destination substrate 17 and layer 15.

[0077] At this stage, the bonding surface of layer 15 and the bonding surface of the target substrate 17 are activated, i.e., covered by a layer 27 made of the target material 24. For example, the layers 27 each have a thickness greater than 0.2 nm, for example, less than 100 nm. Alternatively, the layer(s) 27 may have a thickness between 1 nm and 20 nm. In this embodiment, the layer 27 extends into the step 29 and the step 30; these areas are therefore activated in the same way as the central parts of layer 15 and the substrate 17.

[0078] There figure 2E illustrates a step in gluing structure 110 of the figure 2D on the destination substrate 17 of the figure 2C During this step, the central portion of the bonding surface of layer 15, delimited by step 29, is brought into contact with the central portion of the bonding surface of the destination substrate 17, delimited by step 30. More specifically, layer 27 formed on layer 15 and layer 27 formed on the destination substrate 17 are brought into contact. Due to the geometry of structure 110 and substrate 17, during this step, only a central area of ​​the bonding surface of layer 15, delimited by step 29, is brought into contact with a central area of ​​the bonding surface of substrate 17, delimited by step 30.

[0079] The dangling bonds of layer 27 deposited on layer 15 and those of layer 27 deposited on substrate 17 create, when they are brought into contact, covalent bonds ensuring the fixation of layer 15 on substrate 17. The depth of steps 29, 30 being sufficiently large, the dangling bonds formed at the periphery of layer 15, in step 29 and the dangling bonds formed at the periphery of substrate 15, in step 30, although they are placed opposite each other, do not form covalent bonds.

[0080] For example, the gluing step is carried out under a temperature between 10 °C and 400 °C, for example between 10 °C and 40 °C, for example at room temperature.

[0081] For example, the interface resistivity between layer 15 and the destination substrate 17 is less than 10⁻³ Ω.cm⁻², for example, less than 10⁻⁵ Ω.cm⁻². This allows the bond to be electrically transparent.

[0082] There figure 2F illustrates the structure obtained after a step of removing the source substrate 13 of the structure illustrated in figure 2E .

[0083] For example, the substrate 13 is made of the same semiconductor material as the layer 15, and a buried layer (not visible in the figures), implanted, for example, by hydrogen ions (H+), separates the layer 15 from the source substrate 13. For example, the structure 110 is initially a single-crystal semiconductor wafer, which is implanted from its upper face, for example by hydrogen ions, so as to create the buried implanted layer separating the transfer layer 15 from the source substrate 13. For example, the removal of the source substrate 13 may include a thermal annealing step leading to the fracturing of the structure 110 in the plane of the buried implanted layer, so as to allow the removal of the source substrate 13 and retain only the layer 15 on the destination substrate 17.

[0084] More generally, the removal of substrate 13 can be achieved by any other known method of removing a source substrate during a transfer of a semiconductor layer from a source substrate to a destination substrate, for example by grinding, or by a laser lift-off process.

[0085] As before, when removing the source substrate 13, only the central area of ​​the layer to be transferred 15 located outside the area opposite steps 29 and 30 remains attached to the destination substrate 17. The peripheral part of the destination substrate 17, located opposite steps 29 and 30, remains free, that is to say not covered by layer 15.

[0086] Thus, at the end of the process illustrated in figures 2A à 2F , the transferred layer 15 has a clear and regular edge corresponding substantially to the edge of the step 29 and / or 30.

[0087] The activation steps of the bonding surfaces ( figure 2C ) and gluing ( figure 2E ) are carried out without a vacuum interruption, within the same equipment, including for example an activation chamber in which the activation step of the figure 2C and a bonding chamber in which the bonding step of the figure 2E .

[0088] In the example illustrated in figure 2B , the etching of layer 15 is carried out through a masking disc 31 so as to form a step 29 in layer 15 and the etching of the destination substrate 17 is carried out through a masking disc 33 so as to form a step 30 in the destination substrate 17. Alternatively, a masking disc may be provided only on layer 15 or only on the destination substrate 17 so as to form a step on only one of the two bonding surfaces.

[0089] In practice, during the bonding stage, the aim is to align the structures so that the central areas of the layers 27 delimited by the steps 29 and 30 coincide. However, even if the alignment is not perfect, the proposed solution makes it possible to obtain a clean edge of the transferred layer, since only the portions of the layers 27 in contact adhere to each other.

[0090] One advantage of the process of figures 1A à 1F and figures 2A à 2F is that the engraving of steps 29 and / or 30 improves the sharpness of the boundary between the central glued area and the peripheral unglued area of ​​layer 15.

[0091] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, the embodiments described are not limited to the examples of materials and dimensions mentioned in this description.

[0092] Furthermore, embodiments have been described for circular source and destination substrates, however they may have a different shape.

[0093] Furthermore, although the proposed processes are advantageous for transferring a semiconductor layer from a source substrate to a destination substrate, they can also be implemented to transfer layers of different natures such as metallic layers or dielectric layers from a source substrate to a destination substrate.

[0094] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

1. Method of transferring a layer (15) from a source substrate (13) to a destination substrate (17), comprising the following steps: a) arranging a masking disk (31, 33) on a central portion of a bonding surface of said layer (15) and / or of the destination substrate (17); b) implementing an ion etching to form a step (29, 30) in front of a peripheral portion, not covered with the masking disk (31, 33), of the bonding surface of said layer (15) and / or of the destination substrate (17); c) removing the masking disk (31, 33); d) activating the bonding surface of said layer (15) and the bonding surface of the destination substrate (17) by ion etching or ion deposition of a bonding material; and e) after step d), placing into contact the bonding surface of said layer (15) with the bonding surface of the destination substrate (17), wherein steps b) and d) are successively implemented in a same ion treatment chamber; and wherein steps d) and e) are implemented under vacuum, with no rupture of vacuum between the two steps.

2. Method according to claim 1, wherein the destination substrate (17) and / or the source substrate (13) has tapered edges across a first width.

3. Method according to claim 2, wherein, after step b), the step (29, 30) extends, from the edge of said layer (15) and / or from the edge of the destination substrate (17) across a width greater than or equal to the first width.

4. Method according to any of claims 1 to 3, wherein the disk (31, 33) has a diameter smaller than the diameter of the source substrate (13) and / or than the diameter of the destination substrate (17).

5. Method according to any of claims 1 to 4, comprising, after step e), a step f) of removal of the source substrate (13).

6. Method according to claim 5, wherein step f) comprises an anneal step resulting in fracturing the assembly obtained at the end of step e), in the plane of an implanted buried layer separating said layer (15) from the source substrate (13).

7. Method according to any of claims 1 to 6, wherein said layer (15) is a semiconductor layer.

8. Method according to claim 7, comprising, after step f), a step of epitaxy on top of and in contact with the surface of said layer (15) opposite to the destination substrate (17).

9. Method according to any of claims 1 to 8, wherein, after step b), the step (31, 33) extends down to a depth, from the bonding surface of said layer (15) and / or the bonding surface of the destination substrate (17), greater than 700 nm.

10. Method according to any of claims 1 to 9, wherein step d) consists of the deposit of a bonding layer (27) onto the bonding surface of said layer (15) and / or onto the bonding surface of the destination substrate (17).

11. Method according to claim 10, wherein the bonding layer (27) has a thickness in the range from 0.2 nm to 100 nm, for example, in the range from 1 nm to 20 nm.