SOLAR CELL AND MANUFACTURING METHOD FOR IT

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Chinese patent application No. 202310975523.7, filed on August 4, 2023, and titled "SOLAR CELL AND PREPARATION METHOD THEREOF" .TECHNICAL FIELD

[0002] The present disclosure relates to a field of solar cell technology, and in particular, to a solar cell and a preparation method thereof.BACKGROUND

[0003] Compared to passivated emitter and rear cell (i.e., PERC cell) and heterojunction cells (i.e. HJT cell), interdigital back contact solar cell (i.e., IBC solar cell) does not have grid lines on a front side thereof, and positive electrode and negative electrode of the interdigital back contact solar cell are prepared in a cross arrangement on a back side of the interdigital back contact solar cell, which can avoid shading losses caused by an obstruction of front gate lines in the interdigital back contact solar cell. In a traditional IBC solar cell, staggered N-type doped semiconductor regions and P-type doped semiconductor regions are formed at interval by diffusion, and then holes are defined on a dielectric layer to achieve electrical contact connection between an electrode and an emission region. In such traditional IBC solar cell, poor electrical contact quality between the electrode and a semiconductor region limits further improvement of a photoelectric conversion efficiency of the IBC solar cell.

[0004] G. MASMITJÀ ET AL ("Interdigitated back-contacted crystalline silicon solar cells with low-temperature dopant-free selective contacts", JOURNAL OF MATERIALS CHEMISTRY A, vol. 6, no. 9, 26 January 2018, p.3977-3985) discloses an interdigitated back-contacted (IBC) silicon based solar cell that avoids the use of either thermal SiO 2 , or a-Si:H interlayers achieving a dopant-free, ITO-free and very low thermal budget fabrication process. MASMITJÀ GERARD ET AL ("Interdigitated back-contacted crystalline silicon solar cells fully manufactured with atomic layer deposited selective contacts", SOLAR ENERGY MATERIALS AND SOLAR CELLS, vol. 240, 2 April 2022) discloses carrier-selective contacts based on transition metal oxides deposited by atomic layer deposition (ALD) technique are applied to IBC c-Si(n) devices. In the first part of the study, they develop a hole-selective contact based on thin ALD vanadium oxide (V 2 O 5 ) layers without using an amorphous silicon interlayer. The ALD process has been optimised, i.e. number of ALD cycles and deposition temperature, as a trade-off between surface passivation and contact resistivity. Noticeable surface passivation with recombination current densities around 100 fA / cm 2< , as well as reasonable contact resistivity values below 250 mΩcm are reached using 200 ALD V 2 O 5 cycles deposited at a deposition temperature of 125 °C (~10 nm layer thickness). CN115995500 A discloses a solar cell and a preparation method thereof, belonging to the field of solar cell technology. The solar cell includes silicon substrates with first or second polarity including first and second opposing sides; a first passivation structure located on the first side of the silicon substrate , a part of the first passivation structure farthest from the silicon substrate has the first polarity; a location of the first passivation structure is the first electrode region; a second passivation structure located on the side of the first passivation structure away from the silicon substrate and at least in the second electrode region, wherein the portion of the second passivation structure farthest from the silicon substrate has a second polarity; a process temperature of the second passivation structure is lower than that of the first passivation structure; a first electrode is located on the side of the second passivation structure away from the silicon substrate and in the first electrode region, and a second electrode is located on the side of the second passivation structure away from the silicon substrate and in the second electrode region. CN105789342B discloses an oxide metal multilayer film back contact crystalline silicon solar cell, including a crystalline silicon wafer, wherein front and back surfaces of the crystalline silicon wafer are provided with passivation layers, and a back surface passivation layer is provided with an emitter, an emitter metal electrode, and a base metal electrode. The emitter includes a first oxide film, a metal film, and a second oxide film; the first oxide film or second oxide film is a WO 3 film, NiO film, or V 2 O 5 film, and the metal film is an Ag film, Au film, Pd film, Cu film, Ni film, Mo film, W film, or Al film. CN106024927B discloses a silicon-based solar cell including a sequentially stacked hole transport layer, a first passivation layer, and an n-type silicon wafer. The material of the hole transport layer is selected from the group consisting of cuprous iodide, cuprous chloride, cuprous bromide, nickel oxide, cobalt oxide, vanadium oxide, tungsten oxide, and molybdenum oxide. KR20210010728A discloses a preparation method of the back electrode charge selective complex solar cell, which is to oxidize the surface of the first conductive type silicon layer to form a back oxide layer formation stage, deposit a first transfer metal oxide in a partial area of the back oxide layer, form a first charge selective film formation stage through a tunnel to allow the first charge to pass through, and form a second selective film for the second selective charge through the second selective electrode when the first charge does not pass through the second selective film formed on the back oxide layer. The preparation method includes a stage of forming a selective film and a stage of forming first and second back transparent electrodes at the lower parts of the first and second charge selective films, as well as a stage of forming first and second back transparent electrodes at the first and second back surfaces, respectively. The lower part of the transparent electrode forms the first and second back metal electrodes, respectively. KR20190004952A discloses a solar cells including a semiconductor substrate; a first conductive type region located above the semiconductor substrate and composed of a first compound layer of metal and non-metal, which selectively extracts first charge carriers; a first insulating film located above the first conductive type region and compensating for the first recess; and a first electrode that runs through the first recess and is electrically connected to the first conductive type region. WANG YANHAO ET AL ("Dopant-free passivating contacts for crystalline silicon solar cells: Progress and prospects", ECOMAT, vol.5, no.2, 11 October 2022, p.1-29) discloses dopant-free passivating contacts, covering carrier transport mechanisms, material classification, and evaluation methods. It then focuses on advances in various strategies to enhance cell performance, including material property optimization, structural and interfacial engineering, and post-treatments. Finally, it discusses the challenges and future prospects of dopant-free passivating contact c-Si solar cells.SUMMARY

[0005] The invention is set out in the appended set of claims. According to various embodiments of the present disclosure, a solar cell and a preparation method thereof are provided.

[0006] On a first aspect, the present disclosure provides a solar cell. The solar cell includes a semiconductor substrate, a hole transport layer and an electronic transport layer, a first passivation layer, and a second passivation layer. The semiconductor substrate includes a first surface and a second surface opposite to each other. The hole transport layer and the electronic transport layer are disposed on the first surface of the semiconductor substrate at interval, a material of the hole transport layer includes a vanadium oxide, a material of the electronic transport layer includes a titanium oxide. The first passivation layer is located on a surface of the hole transport layer away from the semiconductor substrate. A surface of the first passivation layer away from the semiconductor substrate, a surface of the electronic transport layer away from the semiconductor substrate, and the first surface of the semiconductor substrate are all covered by the second passivation layer.

[0007] In some embodiments, a thickness of the hole transport layer is in a range of 20 nm to 30 nm.

[0008] In some embodiments, a thickness of the electronic transport layer is in a range of 45 nm to 55 nm.

[0009] In the present invention, a material of the first passivation layer includes aluminum oxide.

[0010] In the present invention, a material of the second passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0011] In some embodiments, the second surface of the semiconductor substrate is a textured surface.

[0012] In some embodiments, the solar cell further includes a third passivation layer and the third passivation layer is disposed on the second surface of the semiconductor substrate.

[0013] In some embodiments, the solar cell further includes a fourth passivation layer and the fourth passivation layer is disposed on a surface of the third passivation layer away from the semiconductor substrate, and a material of the fourth passivation layer is different from that of the third passivation layer.

[0014] On the second aspect, the present disclosure further provides a method for preparation the above solar cell, which includes following steps: providing the semiconductor substrate including the first surface and second surface opposite to each other. forming the hole transport layer and the electronic transport layer on the first surface of the semiconductor substrate at interval, wherein the material of the hole transport layer includes vanadium oxide, the material of the electronic transport layer comprises titanium oxide. forming the first passivation layer on the surface of the hole transport layer away from the semiconductor substrate; and forming the second passivation layer to cover the surface of the first passivation layer away from the semiconductor substrate, the surface of the electronic transport layer away from the semiconductor substrate, and the first surface of the semiconductor substrate.

[0015] In some embodiments, preparation the hole transport layer includes: forming the hole transport layer by an atomic layer deposition method at 120 °C to 130 °Cand using a vanadium source and a first oxidant, or forming the hole transport layer by a plasma enhanced chemical vapor deposition method at 380 °C to 420 °C and using a vanadium source and a second oxidant.

[0016] In some embodiments, preparation the electronic transport layer includes: forming the electronic transport layer by an atomic layer deposition method at 100 °C to 160 °C and using a titanium source and a first oxidant, or forming the electronic transport layer by a plasma enhanced chemical vapor deposition method at 380 °C to 420 °Cand using a titanium source and a second oxidant.

[0017] The details of one or more embodiments of this application are presented in the accompanying drawings and description below. The other features, purposes, and advantages of this application will become apparent from the description, drawings, and claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a better description and illustration of embodiments and / or examples of those disclosures disclosed herein, reference may be made to one or more attached drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed disclosures, currently described embodiments and / or examples, and currently understood best modes of these disclosures. FIG. 1 is a schematic diagram of preparation a hole transport layer and a first passivation layer on a surface of a semiconductor substrate of one or more embodiments in the present disclosure. FIG. 2 is a schematic diagram of forming a first mask layer and a second mask layer on a basis of a structure in FIG. 1. FIG. 3 is a schematic diagram of removing a part of the hole transport layer and a dielectric layer on a basis of a structure in FIG. 2. FIG. 4 is a schematic diagram of removing a first mask layer on a basis of a structure in FIG. 3. FIG. 5 is a schematic diagram of forming an electronic transport layer on a basis of a structure in FIG. 4. FIG. 6 is a schematic diagram of forming a first passivation layer on a basis of a structure in FIG. 5. FIG. 7 a schematic diagram of forming a third passivation layer and a fourth passivation layer on a basis of a structure in FIG. 6. FIG. 8 is a schematic diagram of forming a first electrode and a second electrode on the basis of the structure in FIG. 6.

[0019] Reference signs are as follows: 10 represents a semiconductor substrate; 21 represents a hole transport layer; 22 represents a first passivation layer; 31 represents a first mask layer; 32 represents a second mask layer; 40 represents an electronic transport layer; 50 represents a second passivation layer; 61 represents a third passivation layer; 62 represents a fourth passivation layer; 71 represents a first electrode; and 72 represents a second electrode.DETAILED DESCRIPTION

[0020] In order to make above objectives, features, and advantages of this disclosure more obvious and understandable, a detailed explanation of detail description of this disclosure will be provided below in conjunction with drawings. Many specific details are described in following description to facilitate a thorough understanding of this disclosure. However, this disclosure can be implemented in many ways different from the other described herein, and those skilled in the art can make similar improvements without violating content of this disclosure. Therefore, this disclosure is not limited by the specific examples disclosed below.

[0021] Unless otherwise defined, all technical and scientific terms used in this article have the same meanings as those commonly understood by those skilled in the art of this disclosure. The terms used in the specification of this disclosure are only for the purpose of describing specific examples and are not intended to limit this disclosure. The term "and / or" used in this article includes any and all combinations of one or more related listed items.

[0022] In one embodiment of the present disclosure, a solar cell is provided. The solar cell includes a semiconductor substrate 10, a hole transport layer 21 and an electronic transport layer 40, a first passivation layer 22, and a second passivation layer 50. The semiconductor substrate 10 includes a first surface and a second surface opposite to each other. The hole transport layer 21 and the electronic transport layer 40 are disposed on the first surface of the semiconductor substrate at interval. A material of the hole transport layer 21 includes a vanadium oxide, and a material of the electronic transport layer 40 includes a titanium oxide. The first passivation layer 22 is located on a surface of the hole transport layer 21 away from the semiconductor substrate 10. A surface of the first passivation layer 22 away from the semiconductor substrate 10, a surface of the electronic transport layer 40 away from the semiconductor substrate 10, and the first surface of the semiconductor substrate 10 are all covered by the second passivation layer 50.

[0023] In the solar cell, the material of the hole transport layer 21 includes a vanadium oxide, and the vanadium oxide is in a state of hole selectivity. The material of the electronic transport layer 40 includes titanium oxide, and titanium oxide is in a state of electronic selectivity. In the present disclosure, the hole transport layer 21 is cooperated with the electronic transport layer 40, and schottky barrier between the hole transport layer 21 and an electrode and schottky barrier between the electronic transport layer 40 and an electrode are relatively low, facilitating a relatively great transmission effect of photo-generated carriers. Meanwhile, the surface of the hole transport layer 21 is laminated and passivated with two different materials, which can effectively improve a surface contact effect between the passivated hole transport layer 21 and the electrode. In such solar cell, it can realize excellent electric contact effect between the electrode and the hole transport layer 21 and between the electrode and the electronic transport layer 40, thereby realizing a relatively high photoelectric conversion efficiency of the IBC solar cell.

[0024] In some embodiments, the material of the hole transport layer 21 is vanadium oxide.

[0025] In some embodiments, the material of the electronic transport layer 40 is titanium oxide.

[0026] In some embodiments, a thickness of the hole transport layer 21 is in a range of 20 nm to 30 nm. In such thickness range of the hole transport layer 21, film quality of the hole transport layer 21 is excellent, and the obtained cell has an excellent selective contact effect. Alternatively, the thickness of the hole transport layer 21 can be 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm or 30 nm.

[0027] In some embodiments, a thickness of an electronic transport layer 40 is in a range of 45 nm to 55 nm. In such thickness range of the electronic transport layer 40, film quality of the electronic transport layer 40 is excellent, and the obtained cell has an excellent selective contact effect. Alternatively, the thickness of the electronic transport layer 40 can be 45 nm, 46 nm, 47 nm, 48 nm, 49 nm, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm or 55 nm.

[0028] A material of the first passivation layer 22 includes aluminum oxide. A cooperation between aluminum oxide and an N-type semiconductor material is excellent, which can have a greatly passivate effect on the hole transport layer 21 to obtain a solar cell with an excellent contact effect.

[0029] In the present invention, the material of the first passivation layer 22 is aluminum oxide.

[0030] Furthermore, the material of the second passivation layer 50 includes at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0031] In some embodiments, the second surface of the semiconductor substrate is a textured surface. The textured surface can be a textured surface with different shapes. For example, the textured surface can be a pyramid textured surface.

[0032] In some embodiments, the third passivation layer 61 can be further disposed on the second surface of the semiconductor substrate 10. By depositing the third passivation layer 61 one the front side of the cell, it can further improve a photoelectric performance of the solar cell.

[0033] In some embodiments, the material of the third passivation layer 61 includes at least one of aluminium oxide, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0034] In some embodiments, a fourth passivation layer 62 is further disposed on a surface of the third passivation layer 61 away from the semiconductor substrate 10. A material of the fourth passivation layer 62 is different from that of the third passivation layer 61. By disposing the third passivation layer 61 and the fourth passivation layer 62 laminated on the front side of the cell, it can further improve the photoelectric performance of the solar cell.

[0035] In some embodiments, a material of the fourth passivation layer 62 includes at least one of aluminium oxide, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0036] In some embodiments, the material of the third passivation layer 61 is different from that of the fourth passivation layer 62.

[0037] In the present invention, a material of the semiconductor substrate 10 includes an N-type monocrystalline silicon wafer.

[0038] In some embodiments, the solar cell further includes a first electrode 71 and a second electrode 72. The first electrode 71 is located on a surface of the second passivation layer 50 configured for covering the first passivation layer 22 and away from the semiconductor substrate 10, and the second electrode 72 is located on a surface of the second passivation layer 50 configured for covering the electronic transport layer 40 and away from the semiconductor substrate 10.

[0039] In another embodiment of the present disclosure, a method for preparation the above solar cells is provided. The preparation method includes following steps: providing a semiconductor substrate 10 including a first surface and a second surface opposite to each other; forming a hole transport layer 21 and an electronic transport layer 40 on the first surface of the semiconductor substrate 10 at interval, wherein a material of the hole transport layer 21 includes vanadium oxide, and a material of the electronic transport layer 40 includes titanium oxide; forming a first passivation layer 22 on a surface of the hole transport layer 21 away from the semiconductor substrate 10; and forming a second passivation layer 50 to cover a surface of the first passivation layer 22 away from the semiconductor substrate 10, a surface of the electronic transport layer 40 away from the semiconductor substrate 10, and the first surface of the semiconductor substrate 10.

[0040] In some examples of such embodiment, the preparation method of the solar cell includes step 100 to step 500.

[0041] Step 100 includes providing a semiconductor substrate including a first surface and a second surface opposite to each other.

[0042] In some examples, step 100 further includes cleaning the semiconductor substrate 10 to remove an impurity on a surface of the semiconductor substrate 10.

[0043] In some examples, the step of cleaning the semiconductor substrate 10 includes cleaning the semiconductor substrate 10 by a mixed solution of potassium hydroxide solution and hydrogen peroxide solution.

[0044] In some examples, after cleaning the semiconductor substrate 10, it further includes texturing the cleaned semiconductor substrate 10 to form a textured surface on the cleaned semiconductor substrate 10.

[0045] In some examples, the step of texturing the cleaned semiconductor substrate 10 includes processing an anisotropic etching on the cleaned semiconductor substrate 10 by an etching solution to form a pyramid textured surface on the cleaned semiconductor substrate 10.

[0046] In some examples, the etching solution includes a potassium hydroxide solution.

[0047] Step 200 includes forming the hole transport layer 21 and the electronic transport layer 40 on the first surface of the semiconductor substrate 10 at interval. A material of the hole transport layer 21 includes vanadium oxide, and a material of the electronic transport layer 40 includes titanium oxide.

[0048] In some examples, the step of preparation the hole transport layer 21 includes: forming the hole transport layer 21 by an atomic layer deposition method at 120 °C to 130 °C and using a vanadium source and a first oxidant. In such temperature range of the atomic layer deposition method, the hole transport layer 21 with an excellent film-forming effect and sealing performance can be obtained. Meanwhile, a relatively low deposition temperature can reduce a damage of passivation stability of the hole transport layer 21 when under a relatively high temperature. For example, a temperature of the atomic layer deposition method can be 120 °C, 121 °C, 122 °C, 123 °C, 124 °C, 125 °C, 126 °C, 127 °C, 128 °C, 129 °C or 130 °C. For example, the vanadium source of the atomic layer deposition method includes tetra (ethyl methyl amino) vanadium (IV). For example, the first oxidant of the atomic layer deposition method includes deionized water.

[0049] In some examples, circulation number of the atomic layer deposition is in a range of 160 times to 240 times. In such circulation number of the atomic layer deposition, the hole transport layer 21 with an appropriate thickness can be obtained. For example, the circulation number of the atomic layer deposition can be 160 times, 170 times, 180 times, 190 times, 200 times, 210 times, 220 times, 230 times, or 240 times.

[0050] In some examples, the step of forming the hole transport layer 21 includes: forming the hole transport layer 21 by plasma enhanced chemical vapor deposition at 380°C to 420°C and using a vanadium source and a second oxidant . In such temperature range of the plasma enhanced chemical vapor deposition, the hole transport layer 21 with an excellent film-forming effect and sealing performance can be obtained, and meanwhile, a relatively low deposition temperature can reduce a damage for passivation stability of the hole transport layer 21 when under a relatively high temperature. For example, the temperature of the plasma enhanced chemical vapor deposition can be 380 °C, 385 °C, 390 °C, 395 °C, 400 °C, 405 °C, 410°C, 415 °C and 420 °C. Alternatively, the vanadium source of the plasma enhanced chemical vapor deposition includes tetra (ethyl methyl amino) vanadium (IV). The second oxidant of the plasma enhanced chemical vapor deposition includes N 2 O.

[0051] In some examples, the step of forming the electronic transport layer 40 includes: forming the electronic transport layer 40 using a titanium source and a first oxidant by atomic layer deposition at 100 °C to 160 °C .

[0052] In some examples, the step of forming the electronic transport layer 40 includes: forming the electronic transport layer 40 by plasma enhanced chemical vapor deposition at 380°C to 420 °C and using the titanium source and the second oxidant.

[0053] Step 300 includes forming the first passivation layer 22 on the surface of the hole transport layer 21 away from the semiconductor substrate 10.

[0054] In some examples, referring to FIGs. 1 to 5, FIG. 1 is a schematic diagram of forming a hole transport layer 21 and a first passivation layer 22 on a surface of a semiconductor substrate 10. FIG. 2 is a schematic diagram of forming a first mask layer 31 and a second mask layer 32 on a basis of a structure in FIG. 1. FIG. 3 is a schematic diagram of removing a part of the hole transport layer 21 and a dielectric layer on a basis of a structure in FIG. 2. FIG. 4 is a schematic diagram of removing a first mask layer 31 on a basis of a structure in FIG. 3. FIG. 5 is a schematic diagram of preparation an electronic transport layer 40 on a basis of a structure in FIG. 4. The hole transport layer 21, the electronic transport layer 40, and the first passivation layer 22 are prepared by following steps: forming the hole transport layer 21 and the first passivation layer 22 successively laminated on the semiconductor substrate 10; forming the first mask layer 31 and the second mask layer 32 on a surface of the first passivation layer 22, wherein the first mask layer 31 can not be removed by a developing solution, and the second mask layer 32 can be removed by the developing solution; removing the second mask layer 32 and etching the first passivation layer 22 and the hole transport layer 21 which are exposed; and removing the first mask layer 31 and forming the electronic transport layer 40on the surface of the semiconductor substrate 10.

[0055] In some examples, a material of the first mask layer 31 includes photosensitive polyimide. In some embodiments, a material of a second mask layer 32 includes photosensitive polyimide.

[0056] Step 400 includes: forming the second passivation layer 50 to cover a surface of the first passivation layer 22 away from the semiconductor substrate 10, a surface of the electronic transport layer 40 away from the semiconductor substrate 10, and the first surface of the semiconductor substrate 10.

[0057] FIG. 6 is a schematic diagram of forming the first passivation layer 22 on a basis structure in FIG. 5. Referring to FIG. 6, the surface of the first passivation layer 22 away from the semiconductor substrate 10, the surface of an electronic transport layer 40 away from the semiconductor substrate 10, and the first surface of the semiconductor substrate 10 are all covered by the second passivation layer 50.

[0058] Step 500 includes: forming the first electrode 71 and the second electrode 72. The first electrode 71 is located on a surface of the second passivation layer 50 covering the first passivation layer 22 and away from the semiconductor substrate 10, and the second electrode 72 is located on a surface of the second passivation 50 covering the electronic transport layer 40 and away from the semiconductor substrate 10.

[0059] FIG. 8 is a schematic diagram of forming the first electrode 71 and the second electrode 72 on a basis of a structure in FIG. 6. Referring to FIG. 8, the first electrode 71 is located on the surface of the second passivation layer 50 covering the first passivation layer 22 and away from the semiconductor substrate 10, and the second electronic 72 is located on a surface of the second passivation layer 50 covering the electronic transport layer 40 and away from the semiconductor substrate 10.

[0060] In some examples, the materials of the first electrode 71 and the second electrode 72 are individually selected from usable metal electrodes in the art. For example, the first electrode 71 is a silver electrode. For example, the material of the second electrode 72 includes nickel and aluminum.

[0061] In some examples, the method further includes: forming the third passivation layer 61 on the second surface of the semiconductor substrate 10.

[0062] In some examples, the method further includes: forming the fourth passivation layer 62 on a surface of the third passivation layer 61.

[0063] FIG. 7 is a schematic diagram of forming the third passivation layer 61 and the fourth passivation layer 62 on a basis in FIG. 6. Referring to FIG. 7, the third passivation layer 61 is disposed on the second surface of the semiconductor substrate 10, and the fourth passivation layer 62 is disposed on a surface of the third passivation layer 61 away from the semiconductor substrate 10.

[0064] Some specific examples are as below to explain the method and the solar cell.Example 1

[0065] Referring to FIGs. 1 to 8, a method for preparation the solar cell includes following steps. (1) At 70 °C, a mixture of potassium hydroxide solution and hydrogen peroxide solution was used to clean a semiconductor substrate 10 for about 90 s, so as to remove an impurity of a surface of a silicon wafer. (2) At 78 °C, the potassium hydroxide solution and an additive were used to texture a front side of the silicon surface in chain for about 450 s, so as to form a pyramid textured surface on a front surface of the silicon wafer as a trapping structure. (3) At 120 °C to 130 °C, an ALD device was used, tetra (ethyl methyl amino) vanadium (IV) and deionized water were used as a precursor and an oxidant, respectively, circulations were processed 160 times to 240 times, an vanadium oxide film with a thickness of 20 nm to 30 nm was prepared as a hole transport layer 21. (4) At 190 °C to 210 °C, the ALD device was used, trimethyl aluminum (TMA) and the deionized water were used as a precursor and an oxidant, respectively, circulations were processed 450 times to 550 times, an aluminum oxide film with a thickness of 45 nm to 55 nm was prepared as a first passivation layer 22. (5) Photosensitive polyimide was used to prepare a patterned mask layer. A first mask layer 31 and a second mask layer 32 were obtained by utilizing photochemical reactions. A part of the hole transport layer 21 and a part of the first passivation layer 22 covered by the second mask layer 32 were removed by dry etching. (6) The first mask layer 31 was removed. (7) At 100 °C to 200 °C, the ALD device was used, titanium tetraisopropanolate and the deionized water were used as a precursor and an oxidant, respectively, circulations were processed 225 times to 275 times, a titanium oxide film with a thickness of 22.5 nm to 27.5 nm was prepared as an electronic transport layer 40. (8) Silane and methane were used as silicon source and carbon source, H 2 was used as a carrier gas, a silicon carbide thin film with a thickness of 20 nm was prepared as a second passivation layer 50. (9) An aluminum oxide thin film was prepared on the front side of the silicon wafer as the third passivation layer 61 by using same condition of the step (4), and a silicon carbide thin film was prepared on the front side of the silicon wafer as a fourth passivation layer 62 by using same condition of the step (8). (10) An annealing treatment was processed at 380 °C to 420 °C for 10 min, so as to activate surface passivation of the silicon carbide thin film. (11) A silver first electrode 71 and a nickel aluminum second electrode 72 were prepared, respectively. Example 2

[0066] This example is substantially the same as example 1,except that: in step (3), at 400 °C, plasma enhanced chemical vapor deposition device was used, tetra (ethyl methyl amino) vanadium (IV) and N 2 O were used as a precursor and an oxidant, respectively, and a vanadium oxide film with a thickness of 20 nm to 30 nm was prepared as a hole transport layer 21; and in step (7), at 400 °C, ALD device and the plasma enhanced chemical vapor deposition device were used, titanium tetraisopropanolate and N 2 O were used as a precursor and an oxidant, respectively, and a titanium oxide thin film with the thickness of 22.5 nm to 27.5 nm was prepared as an electronic transport layer 40.Comparative example 1

[0067] In the comparative example 1, a method for preparation a solar cell includes following steps. (1) At 70 °C, a mixture of a potassium hydroxide solution and a hydrogen peroxide solution was used to clean a semiconductor substrate 10 for about 90 s, so as to remove an impurity of a surface of a silicon wafer. (2) At 78 °C, the potassium hydroxide solution and an additive were used to texture a front side of the silicon surface in chain for about 450 s, so as to form a pyramid textured surface on the front side of the silicon wafer as a trapping structure. (3) At 600 °C, an intrinsic amorphous silicon layer was deposited on a back side of the silicon wafer by low-pressure chemical vapor deposition. (4) Boron diffusion was processed at 1000 °C to form P-type polycrystalline silicon as P region, i.e., a hole transport layer 21. (5) Photosensitive polyimide was used to prepare a patterned mask layer, a first mask layer 31 and a second mask layer 32 were obtained by utilizing photochemical reactions, and a part of the hole transport layer 21 covered by the second mask layer 32 was removed by dry etching. (6) The first mask layer 31was removed. (7) Phosphorus diffusion was processed at 900 °C to form N-type polycrystalline silicon as N region, i.e., an electron transport layer 40. (8) Silane and methane were used as silicon and carbon sources, H 2 was used as a carrier gas, a silicon carbide thin film with a thickness of 20 nm was formed as a second passivation layer 50. (9) An aluminum oxide thin film was prepared on a front side of the silicon wafer as a third passivation layer 61 by using same condition of the step (4), and a silicon carbide thin film was prepared on the front side of the silicon wafer as a fourth passivation layer 62 by using same condition of the step (8). (10) An annealing treatment was processed at a temperature of 380 °C to 420 °C for 10 min, so as to activate surface passivation of the silicon carbide thin film. (11) A silver first electrode 71 and a nickel aluminum second electrode 72 were prepared, respectively.

[0068] The solar cells obtained from examples 1 to 2 and comparative example 1 were tested for the quality, including an open circuit voltage U oc , a short circuit current I sc , a fill factor FF, and a conversion efficiency E ta , and the test result were shown in Table. 1. Table 1NumberU oc (V)I sc (mA / cm 2< )FF(%)E ta (%)Yield(%)Comparative example 10.63340.075.619.290Example 10.65239.281.121.399.5Example 20.64539.280.920.999.4

[0069] It can be seen that, photoelectric conversion efficiency and open circuit voltage of solar cells of examples 1 to 2 are higher than that of a solar cell of comparative example 1. Yield of the solar cells of examples 1 to 2 are higher than that of the solar cell of comparative example 1, which means that high temperature will influence warpage of the silicon wafer, therefore, the yield of the comparative example 1 is relatively low. Furthermore, compares with that of example 1, open circuit voltage of the solar cell of example 2 is relatively low, due to that film formed by plasma enhanced chemical vapor deposition is not dense sufficiently, therefore, a passivation effect of a film prepared by atomic layer deposition in the example 1 is inferior to that in the example 2.

[0070] The various technical features of above example can be combined in any way. To make the description concise, all possible combinations of the various technical features in the above examples have not been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered within the scope of this specification.

[0071] The above examples only express several examples of the present disclosure, and their description is more specific and detailed, but cannot be understood as a limitation on the scope of the present disclosure. It should be pointed out that for ordinary skill in the art, several modifications and improvements can be made without departing from the concept of this disclosure, all of which fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent disclosure should be based on the attached claims, and the specification and drawings can be used to explain the content of the claims.

Claims

1. A solar cell comprising: a semiconductor substrate (10) comprising a first surface and a second surface opposite to each other; a hole transport layer (21) and an electronic transport layer (40), wherein the hole transport layer (21) and the electronic transport layer (40) are disposed on the first surface of the semiconductor substrate (10) at interval, a material of the hole transport layer (21) comprises vanadium oxide, a material of the electronic transport layer (40) comprises titanium oxide; a first passivation layer (22) located on a surface of the hole transport layer (21) away from the semiconductor substrate (10); and a second passivation layer (50), wherein a material of the second passivation layer (50) is different from that of the first passivation layer (22), a surface of the first passivation layer (22) away from the semiconductor substrate (10), a surface of the electronic transport layer (40) away from the semiconductor substrate (10), and the first surface of the semiconductor substrate (10) are all covered by the second passivation layer (50), wherein the material of the first passivation layer (22) comprises aluminum oxide; the material of the second passivation layer (50) comprises at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride; and a material of the semiconductor substrate (10) comprises an N-type monocrystalline silicon wafer.

2. The solar cell of claim 1, wherein a thickness of the hole transport layer (21) is in a range of 20 nm to 30 nm.

3. The solar cell of claim 1, wherein a thickness of the electronic transport layer (40) is in a range of 45 nm to 55 nm.

4. The solar cell of any one of claims 1 to 3, wherein the second surface of the semiconductor substrate (10) is a textured surface.

5. The solar cell of claim 4, further comprising a third passivation layer (61), wherein the third passivation layer (61) is disposed on the second surface of the semiconductor substrate (10).

6. The solar cell of claim 5, further comprising a fourth passivation layer (62), wherein the fourth passivation layer (62) is disposed on a surface of the third passivation layer (61) away from the semiconductor substrate (10), and a material of the fourth passivation layer (62) is different from that of the third passivation layer (61).

7. A method for preparation the solar cell of any one of claims 1 to 6, comprising: providing the semiconductor substrate (10) comprising the first surface and second surface opposite to each other; forming the hole transport layer (21) and the electronic transport layer (40) on the first surface of the semiconductor substrate (10) at interval, wherein the material of the hole transport layer (21) comprises vanadium oxide, the material of the electronic transport layer (40) comprises titanium oxide; forming the first passivation layer (22) on the surface of the hole transport layer (21) away from the semiconductor substrate (10); and forming the second passivation layer (50) to cover the surface of the first passivation layer (22) away from the semiconductor substrate (10), the surface of the electronic transport layer (40) away from the semiconductor substrate (10), and the first surface of the semiconductor substrate (10), wherein the material of the first passivation layer (22) comprises aluminum oxide; the material of the second passivation layer (50) comprises at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride; and a material of the semiconductor substrate (10) comprises an N-type monocrystalline silicon wafer.

8. The method of claim 7, wherein forming the hole transport layer (21) further comprises: forming the hole transport layer (21) by an atomic layer deposition method at 120 °C to 130 °C and using a vanadium source and a first oxidant; or forming the hole transport layer (21) by a plasma enhanced chemical vapor deposition method at 380 °C to 420 °C and using a vanadium source and a second oxidant.

9. The method of claim 7, wherein forming the electronic transport layer (40) comprises: forming the electronic transport layer (40) by an atomic layer deposition method at 100 °C to 160 °C and using a titanium source and a first oxidant; or forming the electronic transport layer (40) by a plasma enhanced chemical vapor deposition method at 380 °C to 420 °Cand using a titanium source and a second oxidant.

10. The method of claim 7, wherein a thickness of the hole transport layer (21) is in a range of 20 nm to 30 nm.

11. The method of claim 7, wherein a thickness of the electronic transport layer (40) is in a range of 45 nm to 55 nm.