SQUARE OSCILLATORS

Description

technical field

[0001] This description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, in these electronic circuits, to devices for generating two periodic radio frequency signals in quadrature with respect to each other. Previous technique

[0002] Many known electronic circuits, for example wireless transmitters and / or receivers, include devices known to generate periodic signals in quadrature with respect to each other.

[0003] Some of these known devices use a polyphase filter to generate the two signals in quadrature.

[0004] Other known devices use an oscillator providing a first periodic signal from which the two quadrature signals are generated by frequency division, the first signal then having a frequency twice as high as that targeted for the two quadrature signals.

[0005] Other known devices use two oscillators interconnected to provide both signals in quadrature; these two interconnected oscillators are said to be in quadrature. An example of such a quadrature oscillator device is described in relation to Figure 1(b) of the article "A 900MHz CMOS LC-Oscillator with Quadrature Outputs" by A. Rofougaran et al., published in 1996 in ISSCC.

[0006] However, the known devices described above have drawbacks. For example, these known devices do not allow the generation of quadrature signals with selectable (or adjustable) frequencies from several high values, for example, above 5 GHz, spanning a wide frequency range, for example, from 5 to 10 GHz. For example, these known devices are not suitable for implementation in an Ultra Wide Band (UWB) radio frequency transmit and / or receive circuit.

[0007] US7421052B2 discloses a system with two coupled oscillators. CN114978042 B discloses uncoupled LC oscillators with an inductance quality factor lower than the capacitance quality factor. US2006 / 091969 A1 discloses the quality factor reduction of an LC resonator for a single oscillator. Summary of the invention

[0008] There is a need to overcome all or part of the drawbacks of devices known to generate two signals in quadrature.

[0009] For example, there is a need for a device capable of generating two quadrature signals with a frequency greater than 5 GHz and selectable over a wide frequency band, for example from 5 GHz to 10 GHz.

[0010] One embodiment overcomes all or part of the drawbacks of known devices for generating two signals in quadrature.

[0011] One embodiment provides a device comprising two oscillators coupled to each other so as to operate in quadrature, each oscillator comprising an inductance and a capacitance with a value selectable from at least two values ​​each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductance is less than the quality factor of its capacitance.

[0012] According to one embodiment, in each oscillator: The inductance comprises identical first and second windings; the first winding has a first end coupled to a first node of application of a supply potential and a second end coupled to a second node of output of the oscillator; the second winding has a first end coupled to the first node and a second end coupled to a third node of output of the oscillator; and a first electrode of the capacitor is connected to the second node and a second electrode of the capacitor is connected to the third node.

[0013] According to one embodiment, in each oscillator, the inductance comprises a first resistance connected in series with the first winding between the first and second nodes, and a second resistance connected in series with the second winding between the first and third nodes, the first and second resistances having the same resistance value.

[0014] According to one embodiment, each of the first and second resistors has a resistance value between 0.5 and 5 ohms, said at least two values ​​of the capacitance being for example between 0.5 and 2.0 pF and the inductance having for example a value between 300 and 700 pH.

[0015] According to one embodiment, in each oscillator, each of the first and second resistances is implemented by at least one portion of polycrystalline silicon, preferably undoped.

[0016] According to one embodiment, each of the first and second resistors comprises: a first conductive portion of a first metal level of an interconnect structure, the first conductive portion corresponding to a first terminal of the resistor; a second conductive portion of the first metal level corresponding to a second terminal of the resistor; at least a third conductive portion of a second metal level of the interconnect structure; at least a fourth conductive portion of the second metal level; first conductive vias electrically coupling the first portion to said at least a third portion and the second portion to said at least a fourth portion; and second conductive vias electrically coupling said at least a polycrystalline silicon portion to said at least a third portion and to said at least a fourth portion.

[0017] According to one embodiment, in each of the oscillators, the capacitance comprises a plurality of capacitances associated with switches configured such that each of the at least two values ​​corresponds to a given combination of open and closed states of said switches.

[0018] According to one embodiment, in each of the oscillators, the selectable value capacitor further includes varactor diodes.

[0019] According to one embodiment, each of the oscillators further comprises: a first MOS transistor and a second MOS transistor each having a first conduction terminal connected to the second node and a second conduction terminal coupled to a fifth node for applying a reference potential, the first transistor having its gate coupled to the third node; a third MOS transistor and a fourth MOS transistor each having a first conduction terminal connected to the third node and a second conduction terminal coupled to the fifth node, the third transistor having its gate coupled to the second node.

[0020] According to one embodiment: The second transistor of the first of the two oscillators has its gate coupled to the second node of the second of the two oscillators; the fourth transistor of the first oscillator has its gate coupled to the third node of the second oscillator; the second transistor of the second oscillator has its gate coupled to the third node of the first oscillator; and the fourth transistor of the second oscillator has its gate coupled to the second node of the first oscillator.

[0021] According to one embodiment, each of the oscillators comprises: a first current source having a first terminal connected to the second conduction terminals of the first and third transistors of the oscillator, and a second terminal connected to the fifth node; and a second current source having a first terminal connected to the second conduction terminals of the second and fourth transistors of the oscillator, and a second terminal connected to the fifth node.

[0022] According to one embodiment, each operating frequency value belongs to a range from 5 GHz to 10 GHz.

[0023] According to one embodiment, the operating frequency values ​​include a first value between 5 and 6.5 GHz and a second value between 8.5 and 10 GHz.

[0024] According to one embodiment, each of the operating frequency values ​​is separated from the other operating frequency values ​​by at least 0.5 GHz. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which:

[0026] there figure 1 represents one embodiment of an oscillator;

[0027] there figure 2represents, in block form, an embodiment of a device comprising two quadrature oscillators identical to that of the figure 1 ;

[0028] there figure 3 represents, by means of a schematic top view, an example of an embodiment of a resistor for the oscillators of the figures 1 and 2 ;

[0029] there figure 4 represents a schematic cross-sectional view of the resistance of the figure 3 . Description of the implementation methods

[0030] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, common electronic circuits, such as integrated circuits, and common applications in which a device for generating two quadrature signals might be used have not been detailed, as the described embodiments are compatible with these common circuits and applications.

[0032] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0033] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0034] Unless otherwise specified, a parameter value is said to be selectable when the parameter value is controllable and can take each of those values ​​depending on its control signal. For example, a capacitance value is said to be selectable when the capacitance can take each of those values, for example, under the control of one or more control signals. As another example, an operating frequency value is said to be selectable when the frequency can take each of those values, for example, under the control of one or more control signals.

[0035] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean within 10%, preferably within 5%.

[0036] Among the known devices presented previously, quadrature oscillators can generate quadrature signals with frequencies above 1 GHz, for example, a frequency on the order of 5 GHz. However, quadrature oscillators can switch between two operating modes corresponding to two different frequency values ​​for the quadrature signals generated by the device. More specifically, in the first of the two operating modes, the operating frequency of the quadrature oscillators is higher than the operating frequency of these oscillators when not interconnected, and in the second of the two operating modes, the operating frequency of the quadrature oscillators is lower than the operating frequency of these oscillators when not interconnected.Forcing the device's oscillators to operate in only one of the two modes ensures that the quadrature signal frequency is indeed the desired one. To achieve this, it has been proposed to add phase shifters to the connections between the two quadrature oscillators. However, in a device with quadrature oscillators interconnected via phase shifters, the phase shifters are sized for a specific operating frequency, that is, a specific frequency of the quadrature signals provided by the device. Consequently, the switching between the two operating modes is not controlled across the entire operating range of the device, which poses a problem.For example, such a device is not suitable for generating quadrature signals having a frequency whose value is selectable from several values ​​within a range of 5 GHz to 10 GHz, for example a frequency whose value is selectable from at least a first frequency value between 5 and 6.5 GHz and a second frequency value between 8.5 and 10 GHz and / or a frequency whose value is selectable from several values ​​separated from each other by at least 0.5 GHz.

[0037] This document proposes a device comprising two quadrature oscillators, that is, two oscillators coupled to each other to operate in quadrature. Each oscillator includes a parallel LC load (or "tank") and is configured so that, at each selectable operating frequency of the device's oscillators, the quality factor of the inductance L of the LC load is lower than the quality factor of the capacitance C of the LC load. In practice, in such a device, the LC load comprises a capacitance with a selectable (or controllable) value from among several values, each of these selectable capacitance values ​​corresponding to a different operating frequency of the device.

[0038] Predicting an inductance L with a lower quality factor than the capacitance C leads to greater losses compared to the case where the inductance L has a higher quality factor, for example, higher than that of the capacitance C. This contradicts common practice, which consists of using an inductance L in the LC load of an oscillator with the highest possible quality factor, and therefore generally higher than that of the capacitance C of the LC load. Indeed, an LC load with an inductance L having the highest possible quality factor, and, in particular, higher than that of the capacitance C of the load, helps to limit power consumption and optimize (for example, reduce) phase noise.

[0039] However, the prediction, for each selectable value of operating frequency of the device, of an inductance L with a quality factor lower than that of the capacitance allows that, for each of these values ​​of operating frequency, the device is always in the same operating mode among the two operating modes between which quadrature oscillators can switch.

[0040] To ensure that, for each selectable operating frequency, the device remains in the same operating mode among the two modes between which quadrature oscillators can switch, one could have considered configuring the LC load so that, at each selectable operating frequency, the quality factor of the LC load's inductance L is higher than the quality factor of its capacitance C. However, the device would then be maintained in the operating mode where the frequency of the quadrature signals it provides is lower than the operating frequency of each of the oscillators not interconnected with each other.Conversely, when for each selectable value of device operating frequency, the quality factor of the inductance L of the LC load is lower than the quality factor of the capacitance C of the LC load, the device is maintained in the operating mode where the frequency of the quadrature signals it provides is higher than the operating frequency of the oscillators not interconnected with each other, which is advantageous when targeting operating frequencies above 5 GHz including, for example, an operating frequency between 8.5 and 10 GHz.

[0041] In one embodiment, to ensure that, for each selectable operating frequency, the quality factor of the inductance L is lower than that of the capacitance C, the inductance L of each oscillator includes at least one resistor, even though this resistor increases the losses in the inductance. For example, this resistor is configured to limit the increase in power consumption, phase noise, and capacitance resulting from its introduction, while ensuring that, for each selectable operating frequency of the device, the device remains in the same operating mode, namely, the mode where the quality factor of the inductance is lower than that of the capacitance. Preferably, the value of the resistor is chosen to be the smallest possible among the resistance values ​​that ensure the above-described operation.

[0042] In one embodiment, at least one resistance of the inductance L is implemented using a portion of intrinsic polycrystalline silicon (i.e., intentionally undoped), rather than a conductive portion of a metal layer in an interconnect structure of the device's integrated circuit. This is because polycrystalline silicon does not suffer from the electromigration problems that affect a portion of a metal layer in a metal layer.

[0043] Implementation methods and variants of such a device will now be described.

[0044] In the following description, by way of example, the described device is configured to have an operating frequency whose value is selectable from at least two values ​​within a frequency range from 5 GHz to 10 GHz, for example, from at least two values ​​comprising a first value between 5 and 6.5 GHz and a second value between 8.5 and 10 GHz. Preferably, each of the selectable frequency values ​​is separated from the other selectable frequency values ​​by at least 0.5 GHz. However, a person skilled in the art is able, based on the functional indications given in this description, to modify the frequency range to which the selectable frequency values ​​belong and / or the selectable frequency values ​​themselves.For example, a person skilled in the art can, based on this description, adjust the selectable values ​​of capacitance C so that all or part of the operating frequencies of the device's oscillators are below 5 GHz. Indeed, the device described here is suitable for providing quadrature signals at frequencies below 5 GHz, although it is, for example, particularly advantageous for operating frequencies above 5 GHz.

[0045] There figure 1 represents one embodiment of a LO oscillator, and the figure 2 represents, in block form, an embodiment of a device 2 comprising two LO oscillators in quadrature, that is to say interconnected to each other so as to operate in quadrature or, in other words, so as to provide two signals in quadrature.

[0046] As can be seen in figure 1The LO oscillator includes a parallel LC-type load 100 (or "tank"). Load 100 comprises a capacitance C and an inductance L. The capacitance C has a selectable (controllable) value from at least two values, each corresponding to an operating frequency of the LO oscillators in device 2.

[0047] In device 2, the two LO oscillators in quadrature, referenced respectively 200 and 202 in figure 2 , are each configured so that, for each operating frequency of the LO oscillators of device 2, the quality factor of the inductance L of the oscillator is less than that of its capacitance C.

[0048] According to one embodiment, to obtain this relationship between the quality factors of the inductance L and the controllable capacitance C of the LO oscillator, the capacitance C is optimized so that its quality factor is as high as possible, and the inductance L is chosen with a low quality factor that is lower than that of the capacitance C.

[0049] In one embodiment, the inductance L includes at least one resistance. This reduces the quality factor of the inductance L compared to the case where the resistance is omitted, so that the quality factor of the inductance L is lower than that of the capacitance C.

[0050] In each LO oscillator, the load 100 is connected between two output nodes A and B of the LO oscillator. For example, the inductor L is connected between the two nodes A and B, and the capacitor C is connected between the two nodes A and B, in parallel with the inductor L. More specifically, the capacitor C has one electrode connected to node A and one electrode connected to node B.

[0051] Although this is not represented in figure 1 In one embodiment, the capacitor C comprises a bank of selectable capacitors, that is, several capacitors and several switches associated with these capacitors and configured so that each selectable value of the capacitor C corresponds to a given combination of the open and closed states of these switches. In this case, the control signals of the switches are control signals of the capacitor C.

[0052] In one embodiment, the capacitor C further comprises varactor diodes, a varactor diode being a diode that behaves like a capacitor whose value varies with the reverse voltage applied across its terminals. In such an embodiment, the capacitor bank allows for coarse adjustment of the value of the capacitor C, and the varactor diodes allow for fine adjustment of the value of the capacitor C. In this case, the signal(s) used to select or control the value of the reverse voltage applied across each varactor diode are, in addition to the control signals for the switches in the capacitor bank, control signals for the capacitor C itself.

[0053] The implementation of capability C is within the reach of the person in the trade based on the functional indications given in this description.

[0054] According to one embodiment, the inductance L of each LO oscillator comprises a first winding L1 and a second winding L2 identical to winding L1. The windings are connected in series between nodes A and B of the LO oscillator. More specifically, winding L1 has one end 102 coupled, preferably connected, to a node 112 which is itself coupled to a node 104 configured to receive a supply potential VDD, and one end 106 coupled to node A. Winding L2 has one end 108 coupled, preferably connected, to node 112 and one end 110 coupled to node B. In the example of the figure 1 , the ends 102 and 108 of the respective windings L1 and L2 are connected to node 112. Furthermore, in the example of the figure 1 node 112 is connected to node 104.

[0055] In the example of the figure 1, the VDD potential is positive and referenced with respect to a reference potential GND, for example ground.

[0056] In an embodiment not shown, the inductance L has no resistance and consists only of windings, for example windings L1 and L2. In such an embodiment, the inductance L and the capacitance C are nevertheless configured so that, for each of the operating frequencies of the device 2, the quality factor of the inductance L is lower than that of the capacitance C.

[0057] However, depending on the number and / or values ​​of the operating frequencies of device 2, it is difficult or even impossible to have an inductance L whose quality factor is lower than that of the capacitance for each operating frequency of device 2.

[0058] Thus, according to another embodiment, as previously indicated, the inductance L includes at least one resistance so as to reduce its quality factor. More specifically, as illustrated in figure 1 The inductance L comprises a resistor R1 connected in series with the winding L1 between nodes 112 and A, and a resistor R2 connected in series with the winding L2 between nodes 112 and B. Resistors R1 and R2 have the same resistance value, for example, between 0.5 and 5 ohms. As an example, as shown in figure 1 , resistor R1 is connected between end 106 of winding L1 and node A, resistor R2 being connected between end 110 of winding L2 and node B.

[0059] In one embodiment, each resistor R1, R2 is implemented using at least one portion of undoped polycrystalline silicon, i.e., intentionally undoped. For example, in each resistor R1, R2, each portion of polycrystalline silicon rests on a semiconductor substrate. As an example, an insulating layer is placed between the polycrystalline silicon and the substrate to separate the polycrystalline silicon of the resistor from the semiconductor substrate, although in other examples this insulating layer may be omitted.For example, in each resistor R1, R2, each polycrystalline silicon portion of the resistor has one end (or side) electrically coupled to the same portion of conductive layer of a metal level of an interconnect structure resting on the substrate, this conductive portion corresponding, for example, to a first terminal of the resistor, and a second end electrically coupled to the same other portion of conductive layer of this metal level, this other conductive portion corresponding, for example, to a second terminal of the resistor.

[0060] In alternative embodiments, resistors R1 and R2 can each be implemented using a portion of a metallic conductive layer within a metal layer of an interconnect structure. However, this portion of the metallic conductive layer will be subject to electromigration phenomena, unlike polycrystalline silicon.

[0061] Each LO oscillator also includes transistors T1, T2, T3 and T4. Transistors T1 to T4 are MOS transistors (from the English "Metal Oxide Semiconductor").

[0062] Transistors T1 and T2 each have a first conduction terminal coupled, preferably connected, to node A, and a second conduction terminal coupled to a node 114 configured to receive the reference potential GND. Transistors T3 and T4 each have a first conduction terminal coupled, preferably connected, to node B, and a second conduction terminal coupled to node 114. The first conduction terminal of each transistor T1, T2, T3, T4 corresponds, for example, to the drain of that transistor, its second conduction terminal then corresponding to its source.

[0063] Transistor T1 has its gate coupled, for example connected, to node B, transistor T3 has its gate coupled, for example connected, to node A.

[0064] In the following description, in each LO oscillator, the gate of transistor T2 is referenced as G2 and the gate of transistor T4 is referenced as G4. In each LO oscillator, nodes A and B are, for example, outputs of the oscillator, and terminals G2 and G4 are inputs of the oscillator.

[0065] The interconnection of two quadrature oscillators is, for example, illustrated by figure numbered 1(d) of the article "A 900MHz CMOS LC-Oscillator with Quadrature Outputs", and applies to the two oscillators 200 and 202 of device 2.

[0066] More specifically, as can be seen in figure 2 where the LO 200 and 202 oscillators are each represented by a block comprising two outputs A and B and two inputs G2 and G4, in device 2: the input G2 of oscillator 200 is coupled, for example connected, to the output A of oscillator 202; the input G4 of oscillator 200 is coupled, for example connected, to the output B of oscillator 202; the input G2 of oscillator 202 is coupled, for example connected, to the output B of oscillator 200; and the input G4 of oscillator 202 is coupled, for example connected, to the output A of oscillator 200.

[0067] In the example of the figure 1 Where the VDD potential is positive with respect to the GND potential, transistors T1 through T4 are N-channel MOS transistors, or NMOS. In another, unshown example where the VDD potential is negative with respect to the GND potential, transistors T1 through T4 are P-channel MOS transistors, or PMOS.

[0068] For example, transistors T1 and T3 are identical to each other, and transistors T2 and T4 are identical to each other.

[0069] In some examples, all transistors T1 to T4 are identical, that is, they have the same dimensions.

[0070] In other examples, the ratio between the dimensions of identical transistors T1 and T3 and those of identical transistors T2 and T4 is determined by a target coupling coefficient between the two oscillators 200 and 202.

[0071] In one embodiment, node 112 is connected to node 104, with the ends 102 and 108 of the respective windings L1 and L2 then, for example, connected to node 104. Furthermore, the second conduction terminals of transistors T1 to T4 are coupled to node 114 by at least one current source. For example, in such an embodiment, in each LO oscillator, the gate of transistor T1 is connected to node B of the oscillator, and the gate of transistor T3 is connected to node A of the oscillator. As an example, in such an embodiment, the G2 input of oscillator 200 is connected to the output A of oscillator 202, the G4 input of oscillator 200 is connected to the output B of oscillator 202, the G2 input of oscillator 202 is connected to the output B of oscillator 200, and the G4 input of oscillator 202 is connected to the output A of oscillator 200.

[0072] For example, in an embodiment where the second conduction terminals of transistors T1 to T4 are coupled to node 114 by at least one current source, as illustrated in figure 1 In each LO oscillator, a current source 116 is connected between the second conduction terminals of transistors T1 and T3 and node 114, and another current source 118 is connected between the second conduction terminals of transistors T2 and T4 and node 114. Current source 116 has, for example, one terminal connected to the second conduction terminals of transistors T1 and T3 and another terminal connected to node 114, current source 118 having, for example, one terminal connected to the second conduction terminals of transistors T2 and T4 and another terminal connected to node 114.

[0073] The provision of two current sources 116 and 118 to bias transistors T1 and T3, and T2 and T4 respectively, allows the parameter gm of transistors T1 and T3 to be different from the parameter gm of transistors T2 and T4.

[0074] As an alternative example not shown, in an embodiment where the second conduction terminals of transistors T1 to T4 are coupled to node 114 by at least one current source, in each LO oscillator, only one current source is connected between the second conduction terminals of transistors T1 to T4 and node 114, this current source having, for example, one terminal connected to the second conduction terminal of each of transistors T1 to T4 and another conduction terminal connected to node 114.

[0075] In an alternative embodiment not shown, the second conduction terminals of transistors T1 to T4 are all connected to node 114 and node 112 is coupled to node 104 by a current source, the current source having, for example, one terminal connected to node 112 and one terminal connected to node 104. As an example, in such an alternative embodiment, in each LO oscillator, the gate of transistor T1 is connected to node B of the oscillator, the gate of transistor T3 being connected to node A of the oscillator. As another example, in such an embodiment, the G2 input of oscillator 200 is connected to the output A of oscillator 202, the G4 input of oscillator 200 is connected to the output B of oscillator 202, the G2 input of oscillator 202 is connected to the output B of oscillator 200, and the G4 input of oscillator 202 is connected to the output A of oscillator 200.

[0076] In another embodiment not shown, the second conduction terminals of transistors T1 to T4 are all connected to node 114, and node 112 is connected to node 104. For example, in such an embodiment, in each LO oscillator, the gate of transistor T1 is coupled to node B of the oscillator by a capacitor, the gate of transistor T3 is coupled to node A of the oscillator by a capacitor, the input G2 of oscillator 200 is coupled to the output A of oscillator 202 by a capacitor, the input G4 of oscillator 200 is coupled to the output B of oscillator 202 by a capacitor, the input G2 of oscillator 202 is coupled to the output B of oscillator 200 by a capacitor, and the input G4 of oscillator 202 is coupled to the output A of the oscillator. 200 by capacity.

[0077] Device 2, described above, provides a first periodic signal at output B of oscillator 200, a second periodic signal at output A of oscillator 200 (the second signal having the same frequency as the first but phase-shifted by 180°), a third periodic signal at output B of oscillator 202 (the third signal having the same frequency as the first but phase-shifted by 90°), and a fourth periodic signal at output A of oscillator 202 (the fourth signal having the same frequency as the first but phase-shifted by 270°). Thus, the signals at outputs A and B of oscillator 202 are in quadrature with the signals at outputs A and B of oscillator 200, respectively.

[0078] As an example, device 2 of the figure 2allows the generation of two periodic quadrature signals at a selectable frequency from five equal frequency values ​​of 6.4896 GHz; 7.1136 GHz; 7.7376 GHz; 8.3616 GHz and 8.9856 GHz respectively, keeping the oscillators in the same operating mode for each of these values, which was not possible with known quadrature oscillator devices.

[0079] Using the example above, the value of the resistances R1 and R2 is, for example, between 0.5 and 5 ohms, the value of the inductance L, that is to say of the set of the two windings L1 and L2, is, for example, between 300 and 700 pH (pico henry) and each of the values ​​that the capacitance C can take is, for example, between 0.5 and 2 pF (pico farad).

[0080] The person skilled in the art will be able, from the functional description given above, to predict other operating frequency values, and to adapt the values ​​of the inductance L and the variable capacitance C accordingly.

[0081] There figure 3 represents, by a schematic top view, an example of one embodiment of the resistors R1 and R2 of the oscillators of the figures 1 and 2 , there figure 4 being a cross-sectional view taken in plane AA of the figure 3 In figures 3 and 4 Only resistance R2 is shown, it being understood that resistance R1 is identical or similar to resistance R2. In this embodiment, resistance R2 is implemented by at least one portion of undoped polycrystalline silicon.

[0082] For example, in Figures 3 and 4Resistor R2 is implemented using two polycrystalline silicon components, 300 and 302. The use of two polycrystalline silicon components, 300 and 302, rather than one, may result, for example, from integrated circuit design constraints within a given manufacturing technology. However, each resistor, R1 and R2, can also be implemented using a single polycrystalline silicon component or more than two polycrystalline silicon components.

[0083] Each portion 300, 302 of polycrystalline silicon of the resistor R2 rests on a semiconductor substrate 304, for example of monocrystalline silicon.

[0084] In the example shown, the polycrystalline silicon of portions 300 and 302 rests directly on the substrate 304.

[0085] However, in other examples not shown, each portion 300, 302 is separated from the substrate 304 by an insulating layer disposed between the polycrystalline silicon and the substrate. For example, in this case, the insulating layer has a first face in contact with the substrate 304 and a second face in contact with the polycrystalline silicon, the second face being opposite the first face.

[0086] Each portion 300, 302 has an end or a side (at the top in figure 3 and to the right in figure 4 ) which is electrically coupled to the same portion 308 of a conductive layer of a metal level Mtop of an IT interconnection structure based on the substrate 304. Thus, in the example of the figures 3 and 4where the resistor R2 comprises two portions 300 and 302 of polycrystalline silicon, these two portions are electrically coupled to the portion 308 of the metal level Mtop. The portion 308 of the metal level Mtop corresponds, for example, to a first terminal of the resistor R2, for example connected to the end 110 of the winding L2 of the inductor L ( figure 1 ).

[0087] Symmetrically, each portion 300, 302 has another end or another side (at the bottom in figure 3 and on the left in figure 4 ) which is electrically coupled to the same portion 310 of a conductive layer of the metal level Mtop. Thus, in the example of the figures 3 and 4 where the resistor R2 comprises two portions 300 and 302 of polycrystalline silicon, these two portions are electrically coupled to the portion 310 of the metal level Mtop. The portion 310 of the metal level Mtop corresponds, for example, to a second terminal of the resistor R2, for example connected to node B ( figure 1 ).

[0088] As an example, each portion 300, 302 is electrically coupled to portion 308, respectively 310, of the metal level Mtop via conductive vias and, for example, one or more portions of conductive layers of one or more metal levels of the IT structure which are arranged between the polycrystalline silicon and the metal level Mtop.

[0089] Preferably, the Mtop level corresponds to the least resistive metal level of the IT structure, that is, for example, the metal level that is furthest from the substrate.

[0090] In the example of figures 3 and 4 , one end of each of portions 300 and 302 (at the top in figure 3 and to the right in figure 4) is coupled by conductive vias 312 to a corresponding portion 314, 316 of a metal level Mlow of the IT structure, this portion 314, 316 being coupled by conductive vias 318 to the portion 308 of the metal level Mtop. The metal level Mlow is disposed between the substrate 304 and the metal level Mtop. Furthermore, another end of each of the portions 300 and 302 (at the bottom in figure 3 and on the left in figure 4 ) is coupled by other conductive vias 312 to a corresponding portion 320, 322 of the metal level Mlow, this portion 320, 322 being coupled by conductive vias 318 to the portion 310 of the metal level Mtop.

[0091] Preferably, the Mlow metal level is the least resistive metal level in the IT structure from which 312 vias can extend to the polycrystalline silicon of the resistor, i.e., the polycrystalline silicon of portions 300 and 302 in this example. In other words, preferably, the Mlow metal level is the least resistive metal level among all the metal levels in the IT structure from which vias can be formed to the polycrystalline silicon of the resistor.

[0092] Furthermore, although this is not detailed in figures 3 and 4 The IT interconnection structure typically includes intermediate metal layers arranged between the Mtop and Mlow levels. Although this is not detailed in figures 3 and 4 , one or more metal levels may be provided between the Mlow level and the substrate.

[0093] For example, as illustrated in figures 3 and 4, vias 312 extend from one end of portion 300 to portion 314 of the Mlow metal level, other vias 312 extend from another end of portion 300 to portion 320 of the Mlow metal level, still other vias 312 extend from one end of portion 302 to portion 316 of the Mlow metal level and still other vias 312 extend from another end of portion 302 to portion 322 of the Mlow metal level. In addition, 318 vias extend from each of portions 314 and 316 of the Mlow metal level to portion 308 of the Mtop metal level, and other 318 vias extend from each of portions 320 and 322 of the Mlow metal level to portion 310 of the Mtop metal level.

[0094] One advantage of providing coupling of portions 300 and 302 with the Mtop metal level via vias 318, the Mlow metal level and vias 312 is that the integration density of vias 312 is greater than that of vias 318, which helps to reduce the resistance of the electrical connection between the Mtop metal level and the polycrystalline silicon.

[0095] Although in the example above, the polycrystalline silicon portion 300 is coupled by vias 112 to portions 314 and 320 of the Mlow metal layer, and the polycrystalline silicon portion 302 is coupled by vias 112 to portions 316 and 322 distinct from portions 314 and 320 respectively, this choice is, for example, related to integrated circuit design rules. Thus, in other examples not shown, the Mlow metal layer 314 and portion 318 form a single portion of this metal layer, and similarly, the Mlow metal layer 314 and portion 318 form a single portion of this metal layer.

[0096] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0097] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

1. Device (200) comprising two oscillators (LO; 200, 202) coupled to each other so as to operate in quadrature, each oscillator comprising an inductance (L) and a capacitive element (C) having a value selectable from among at least two values, each corresponding to an operating frequency value of the oscillators, characterized in that each oscillator is configured so that, for each operating frequency value of the oscillators, the quality factor of its inductance (L) is lower than the quality factor of its capacitive element (C).

2. Device according to claim 1 wherein, in each oscillator: the inductance (L) comprises first and second identical windings (L1, L2); the first winding (L1) has a first end (102) coupled to a first node (104) of application of a power supply potential (VDD) and a second end (106) coupled to a second output node (A) of the oscillator; the second winding (L2) has a first end (108) coupled to the first node (104) and a second end (110) coupled to a third output node (B) of the oscillator; and a first electrode of the capacitive element (C) is connected to the second node (A) and a second electrode of the capacitive element is connected to the third node (B).

3. Device according to claim 2, wherein, in each oscillator (200, 202), the inductance (L) comprises a first resistor (R1) series-connected to the first winding (L1) between the first and second nodes (104, A), and a second resistor (R2) series-connected to the second winding (L2) between the first and third nodes (104, B), the first and second resistors (R1, R2) having a same resistance value.

4. Device according to claim 3, wherein each of the first and second resistors (R1, R2) has a resistance value in the range from 0.5 to 5 ohms, said at least two values of the capacitance (C) being for example in the range from 0.5 to 2.0 pF and the inductance (L) for example having a value in the range from 300 to 700 pH.

5. Device according to claim 3 or 4, wherein, in each oscillator (200, 202), each of the first and second resistors (R1, R2) is implemented by at least one polysilicon portion (300, 302), preferably non-doped.

6. Device according to claim 5, wherein each of the first and second resistors (R1, R2) comprises: a first conductive portion (308) of a first metal level (Mtop) of an interconnection structure (IT), the first conductive portion (308) corresponding to a first terminal of the resistor; a second conductive portion (310) of the first metal level (Mtop) corresponding to a second terminal of the resistor; at least one third conductive portion (314, 316) of a second metal level (Mlow) of the interconnection structure (IT); at least one fourth conductive portion (320, 322) of the second metal level (Mlow); first conductive vias (318) electrically coupling the first portion (308) to said at least one third portion (314, 316) and the second portion (310) to said at least one fourth portion (320, 322); and second conductive vias (312) electrically coupling said at least one polysilicon portion (300, 302) to said at least one third portion (314, 316) and to said at least one fourth portion (320, 322).

7. Device according to any of claims 2 to 6, wherein, in each of the oscillators (200, 202), the capacitive element (C) comprises a plurality of capacitive elements associated with switches configured so that each of the at least two values corresponds to a given combination of off and on states of said switches.

8. Device according to claim 7, wherein, in each of the oscillators (200, 202), the capacitive element with a selectable value further comprises varicap diodes.

9. Device according to any of claims 2 to 8, wherein each of the oscillators further comprises: a first MOS transistor (T1) and a second MOS transistor (T2) each having a first conduction terminal connected to the second node (A) and a second conduction terminal coupled to a fifth node (114) of application of a reference potential (GND), the first transistor (T1) having its gate coupled to the third node (B); a third MOS transistor (T3) and a fourth MOS transistor (T4) each having a first conduction terminal connected to the third node (B) and a second conduction terminal coupled to the fifth node (114), the third transistor (T3) having its gate coupled to the second node (A).

10. Device according to claim 9, wherein: the second transistor (T2) of a first one (200) of the two oscillators (200, 202) has its gate coupled to the second node (A) of a second one (202) of the two oscillators (200, 202); the fourth transistor (T4) of the first oscillator (200) has its gate coupled to the third node (B) of the second oscillator (202); the second transistor (T2) of the second oscillator (202) has its gate coupled to the third node (B) of the first oscillator (200); and the fourth transistor (T4) of the second oscillator (202) has its gate coupled to the second node (A) of the first oscillator (200).

11. Device according to claim 9 or 10, wherein each of the oscillators comprises: a first current source (116) having a first terminal connected to the second conduction terminals of the first and third transistors (T1, T3) of the oscillator, and a second terminal connected to the fifth node (114); and a second current source (118) having a first terminal connected to the second conduction terminals of the second and fourth transistors (T2, T4) of the oscillator, and a second terminal connected to the fifth node (114).

12. Device according to any of claims 1 to 11, wherein each operating frequency value belongs to a range from 5 GHz to 10 GHz.

13. Device according to any of claims 1 to 12, wherein the operating frequency values comprise a first value in the range from 5 to 6.5 GHz and a second value in the range from 8.5 to 10 GHz.

14. Device according to any of claims 1 to 13, wherein each of the operating frequency values is separated from the other operating frequency values by at least 0.5 GHz.