OPTOELECTRONIC DEVICE WITH THREE ELECTRODE DIODES AND METHOD FOR THEIR MANUFACTURING

Description

Domaine technique

[0001] This description generally concerns the field of optoelectronic devices including light-emitting diodes (also called "LEDs" for "Light-Emitting Diodes" in English) used for example for the realization of any light-emitting device (screens, projectors, video walls, etc.), and / or photodiodes. Technique antérieure

[0002] US Patent 2022 / 0320367 A1 describes an optoelectronic device comprising at least two first and second light-emitting diodes (LEDs), each comprising: a first p-type doped semiconductor portion and a second n-type doped semiconductor portion; an active region comprising multi-quantum wells between the first and second semiconductor portions; a conductive layer, serving as an electrical gate during operation, covering the side walls of the active region and at least a portion of the first semiconductor portion; and an insulating layer interposed between the side walls of the active region and at least a portion of the conductive layer. The device includes means for controlling the conductive layer, serving as the gate, of the first LED independently of the conductive layer, also serving as the gate, of the second LED.

[0003] US document 2020 / 0052151 A1 describes a flip chip LED and a display device comprising several of these flip chip LEDs, as well as a method for their manufacture.The flipped chip diode comprises: an electroluminescent layer; an n-type semiconductor layer stratified on a lower portion of the electroluminescent layer; a p-type semiconductor layer stratified on a higher portion of the electroluminescent layer; a first electrode that is electrically connected to the n-type semiconductor layer via a first contact hole formed in the LED; a second electrode that is electrically connected to the p-type semiconductor layer, and is electrically isolated from the first electrode; a metallic layer disposed in a first zone, a second zone, and a third zone; a third electrode that is formed on the metallic layer in the third zone, that is electrically connected to the metallic layer, and that is electrically isolated from the first and second electrodes; and a plurality of insulating layers.

[0004] Document EP 2 960 951 A1 describes an optoelectronic device of the LED or photodiode type comprising, in addition to the two electrodes each connected to one of the semiconductors of a pn junction, a third electrode implemented as a grid or Schottky contact. This third electrode, by generating a lateral electric field that increases the EQE (external quantum efficiency), overcomes the problem of charge carrier deficiency in certain semiconductor materials due to excessively high activation energy of the dopants in these materials, such as, for example, in wide bandgap materials like diamond or AlGaN-based epitaxial structures used in particular for LEDs emitting in the UV range.When the device includes several LEDs and / or photodiodes, the third electrode of the LEDs and / or photodiodes is common and distributed for all of these LEDs and / or photodiodes, for example in the form of trenches formed around the pn junctions or through the pn junctions of the LEDs and / or photodiodes.

[0005] One drawback of such an optoelectronic device is that the electrical contact between the electrodes requires very precise alignment when the device is small. This contact can be facilitated by making the device larger, thus increasing its compactness.

[0006] Document WO 2019 / 141948 A1 describes a three-electrode LED or photodiode optoelectronic device in which the third electrode is electrically coupled to the cathode. This simplifies electrical contact because it eliminates the need for separate electrical access to the third electrode and the cathode. A drawback of this solution is that this architecture does not allow for independent control of the electrical potentials applied to the third electrodes from those applied to the cathodes. Summary of the invention

[0007] Therefore, there is a need to propose an optoelectronic device comprising three-electrode diodes that does not have the disadvantages of existing solutions.

[0008] The present invention overcomes all or part of the drawbacks of known solutions and proposes an optoelectronic device according to independent claim 1 in the appendix comprising at least: a plurality of diodes each comprising a portion of a stack of at least one first and a second semiconductor layer doped with opposite types of conductivity, a portion of the first semiconductor layer of each diode being electrically coupled to a first electrode disposed under said portion of the first semiconductor layer; trenches through the stack, separating the diodes from each other and from which second electrodes are electrically accessible; an electrically conductive layer disposed at least against lateral walls of the trenches, electrically insulated from the stack, electrically coupled to the second electrodes and interrupted in such a way that portions of the electrically conductive layer disposed around each of the diodes are electrically insulated from other portions of the electrically conductive layer disposed around the other diodes;electrically conductive portions arranged in the trenches, electrically insulated from the electrically conductive layer and electrically coupled to each other and to at least one third electrode; and in which the bottom walls of the trenches are at least partly formed by the second electrodes.

[0009] According to a particular embodiment, the electrically conductive layer is interrupted at the bottom walls of the trenches.

[0010] According to a particular embodiment, the electrically conductive portions are electrically coupled to the portions of the second semiconductor layer of at least a portion of the diodes corresponding to LEDs.

[0011] According to a particular embodiment, the electrically conductive portions are electrically coupled to the portions of the second semiconductor layer of the LEDs by at least one electrically conductive and optically transparent layer disposed on the stack and on the electrically conductive portions.

[0012] According to a particular embodiment, the electrically conductive and optically transparent layer is electrically isolated from the electrically conductive layer by dielectric portions arranged between the electrically conductive layer and the electrically conductive and optically transparent layer.

[0013] According to a particular embodiment, the electrically conductive portions are electrically isolated from the electrically conductive layer by at least one first dielectric layer disposed between the electrically conductive portions and the electrically conductive layer.

[0014] According to a particular embodiment, the third electrode is arranged at an edge of the optoelectronic device.

[0015] According to a particular embodiment: Each first electrode is arranged between two second electrodes to which are electrically coupled the parts of the electrically conductive layer located around the diode whose portion of the first semiconducting layer is electrically coupled to said first electrode, and the optoelectronic device comprises several third electrodes each electrically coupled to one of the electrically conductive portions and arranged between two second electrodes each electrically coupled to parts of the electrically conductive layer located around different diodes.

[0016] According to a particular embodiment, the device comprises several third electrodes, each electrically coupled to one of the electrically conductive portions, each of the first electrodes being disposed between one of the second electrodes and one of the third electrodes, and each of the third electrodes is disposed between one of the first electrodes and one of the second electrodes.

[0017] According to a particular embodiment, the parts of the electrically conductive layer arranged around at least a part of the diodes corresponding to photodiodes are electrically coupled to the portions of the second semiconducting layer of the photodiodes.

[0018] According to a particular embodiment, the parts of the electrically conductive layer arranged around the photodiodes are electrically coupled to the portions of the second semiconductive layer of the photodiodes by at least one electrically conductive and optically transparent layer disposed on the stack and on the parts of the electrically conductive layer disposed around the photodiodes.

[0019] According to a particular embodiment, the device further comprises a second dielectric layer disposed between the electrically conductive layer and the stack.

[0020] The present invention also proposes a method according to independent claim 13 in the appendix for implementing an optoelectronic device, comprising at least the steps of: realization of a stack of at least one first and a second semiconducting layers doped according to opposite types of conductivity; realization of trenches crossing the stack, separating from each other diodes each comprising a part of the stack and making accessible second electrodes such that bottom walls of the trenches are at least partly formed by the second electrodes, a portion of the first semiconducting layer of each diode being electrically coupled to a first electrode disposed under said portion of the first semiconducting layer;fabrication of an electrically conductive layer disposed at least against the lateral walls of the trenches, electrically insulated from the stack, electrically coupled to the second electrodes and which is interrupted such that parts of the electrically conductive layer disposed around each of the diodes are electrically insulated from the parts of the electrically conductive layer located around the other diodes; fabrication of electrically conductive portions disposed in the trenches, electrically insulated from the electrically conductive layer and electrically coupled to each other and to at least a third electrode. Brève description des dessins

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1 represents an example of an optoelectronic device according to a first embodiment; the figure 2 , there figure 3 , there figure 4 , there figure 5 , there figure 6 , there figure 7 , there figure 8 and the figure 9 represent steps in a process for manufacturing an optoelectronic device according to the first embodiment; the figure 10 represents an example of an optoelectronic device according to a second embodiment; the figure 11 , there figure 12 , there figure 13 and the figure 14 represent steps in a process for manufacturing an optoelectronic device according to the second embodiment; the figure 15 represents an example of an optoelectronic device according to a first embodiment variant; and the figure 16 represents an example of an optoelectronic device according to a second embodiment variant. Description des modes de réalisation

[0022] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0023] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various components of the device (e.g., the control integrated circuit) and various steps in the device fabrication process (deposition, photolithography, etching, etc.) are not detailed. Those skilled in the art will be able to fabricate these components and implement these steps in detail based on the description provided here.

[0024] Unless otherwise specified, when referring to two elements connected together, this means directly connected without any intermediate elements other than conductors, and when referring to two elements linked or coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0025] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", "on", "under", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal position of use.

[0026] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0027] Throughout the document, the term "diode" is used to refer to a light-emitting diode or a photodiode.

[0028] Throughout the document, the term "LED" refers to an LED or a micro-LED.

[0029] Throughout the document, the term "layer" is used to refer to a layer comprising a single material or several materials arranged against each other, i.e., a stack.

[0030] On the figures 1 à 14 , dotted lines are shown to illustrate that the elements of device 100 shown on either side of these dotted lines are not necessarily arranged directly next to each other.

[0031] An example of an optoelectronic device 100 according to a first embodiment is described below in connection with the figure 1 .

[0032] In the described embodiment, the device 100 includes a control integrated circuit 102 comprising at least, in a metallization level 104, first electrodes 106 and second electrodes 108. The circuit 102, which corresponds, for example, to an ASIC (Application-Specific Integrated Circuit), includes electronic components enabling, in particular, the implementation of various diode control functions of the device 100, these functions not being detailed here. On the figure 1 , only level 104 is represented, although circuit 102 may have several superimposed metallization levels making the electrical connections of the electronic components of circuit 102.

[0033] For example, the figure 1 The level 104 comprises a dielectric layer 110 in which electrodes 106 and 108 are arranged. This dielectric layer 110 comprises, for example, SiO2 and its thickness (dimension parallel to the Z-axis on the figure 1 ) is for example equal to 1 µm.

[0034] In the described embodiment, the first electrodes 106 correspond to the anodes of the diodes of device 100, and the second electrodes 108 correspond to electrodes to which grids surrounding the pn junctions of the diodes of device 100 are electrically coupled. On the figure 1 Only two first electrodes 106 and two second electrodes 108 are shown. The total number of first and second electrodes 106, 108 of the device 100 depends in particular on the number of diodes in the device 100. Alternatively, other configurations of the first and second electrodes 106, 108 are possible.

[0035] In the described embodiment, the circuit 102 also includes, in level 104, at least one third electrode 111 serving as the cathode for the diodes of device 100. In the example of the figure 1 The device 100 includes a third electrode 111 forming a common cathode for the diodes of the device 100. Moreover, in the described embodiment, the third electrode 111 is located on the periphery of the device 100, that is, at an edge of the device 100 and not within the set of diodes of the device 100.

[0036] Electrodes 106, 108, 111, for example, contain a metallic material such as aluminum or copper.

[0037] In the described embodiment, the device 100 further comprises several metallic layers stacked on the integrated circuit 102. In the example of the figure 1 These metallic layers correspond to: a first stack 112 of Ti / TiN, comprising for example a titanium thickness of 5 nm and a TiN thickness of 30 nm; a titanium layer 114 comprising for example a thickness of 500 nm; a second stack 116 of Ti / TiN, comprising for example a titanium thickness of 10 nm and a TiN thickness of 40 nm.

[0038] In this embodiment of device 100, these metallic layers 112, 114, 116 serve, in particular, to implement, during the fabrication of device 100, a direct metal-to-metal bond between, on one side, the first stack 112 and a portion of layer 114 fabricated on circuit 102, and on the other side, the second stack 116 and another portion of layer 114 fabricated on a stack of layers used to fabricate the diodes of device 100. Alternatively, these metallic layers could be different from those described in the example of the figure 1 , both in terms of number of layers, thicknesses, materials, etc.

[0039] In the described embodiment example, a layer of AlSi 118 is placed on the second stack 116, and has, for example, a thickness of 100 nm.

[0040] The device 100 further comprises a plurality of diodes 126, each comprising a portion of a stack of at least one first and a second semiconductor layer 120, 122 doped with opposing conductivity types. For example, the figure 1 The semiconductor in the first layer 120 is p-doped, and the semiconductor in the second layer 122 is n-doped. Furthermore, in this example, this semiconductor stack also includes an active region 124 located between layers 120 and 122, comprising one or more emissive or receptive (optically absorbing) layers, each forming a quantum well and each positioned between two barrier layers. All layers of the active region 124—that is, the emissive / receptive layer(s) and the barrier layers—contain intrinsic semiconductor materials, meaning they are not intentionally doped (for example, with a residual donor concentration nnid between approximately 1015 and 1018 donors / cm3). The semiconductor stack is arranged, for example, glued, on the 104 level (with, in the example of the figure 1 , layers 112 to 118 arranged between level 104 and the semiconductor stack) and forms here, for each diode 126, a pin junction.

[0041] The semiconductor materials in layers 120, 122, and 124 include, for example, gallium nitride and / or aluminum nitride and / or indium nitride. According to one embodiment, this semiconductor stack is such that it comprises: a first layer 120 comprising p-GaN and of thickness for example equal to 120 nm; a second layer 122 comprising n-GaN and of thickness for example equal to 500 nm; an active zone 124 comprising one or more emissive layers of InGaN and barrier layers of GaN, and whose thickness is for example between 50 nm and 80 nm.

[0042] According to another embodiment, the first and second layers 120, 122 may contain AlGaN and the layer(s) of the active zone 124 may contain GaN.

[0043] Alternatively, other families of semiconductor materials can be used for the production of layers 120, 122, 124, for example arsenide or phosphide type semiconductors.

[0044] In the first embodiment, all the diodes 126 of the device 100 correspond to LEDs.

[0045] For example, the figure 1 , two diodes 126 are shown, each comprising a part of the stack of layers 120, 122, 124. A portion of the first semiconducting layer 120 of each diode 126 is electrically coupled to one of the first electrodes 106 disposed under this portion of the first semiconducting layer 120, this electrical coupling being achieved by means of an electrically conductive via 128 formed between the first electrode 106 and the parts of the metal layers 112, 114, 116 disposed on this first electrode 106 and which are in contact with this portion of the first semiconducting layer 120.

[0046] Alternatively, it is possible that the interface between the circuit 102 and the semiconductor stack of diodes 126, or between the level 104 and the semiconductor stack of diodes 126, is formed by layers different from layers 112 to 118, depending in particular on the techniques implemented for the realization of the device 100.

[0047] The device 100 also includes trenches 130 passing through the semiconductor stack (i.e., layers 120, 122 and 124), surrounding and separating the diodes 126 from each other and whose bottom walls are at least partly formed by the second electrodes 108. In the described embodiment, these trenches 130 also pass through layers 112, 114, 116 and 118, as well as part of the dielectric layer 110 until they reach the second electrodes 108.

[0048] The trenches 130 are, for example, constructed in such a way that they form, through the different layers in which these trenches 130 are made, a grid delimiting the diodes 126 whose cross-section, in a plane parallel to the principal planes in which these different layers extend (plane parallel to the (X,Y) plane visible on the figure 1 ), is square, hexagonal, or rectangular in shape. The dimension of one of the trenches 130 between two adjacent diodes 126, that is, the width of each trench 130 (which corresponds to the dimension of the trench 130 parallel to the X-axis on the figure 1 ), is for example equal to approximately 1 µm.

[0049] In the described embodiment, another trench 131 passes through the semiconductor stack as well as the layers 112, 114, 116 and 118 and part of the dielectric layer 110. In this example, this trench 131 has a bottom wall opening onto the third electrode 111 and allows electrical contact with the third electrode 111.

[0050] In the described embodiment example, the side walls, or flanks, of the trenches 130, 131 are covered with a dielectric layer 132 serving as a passivation layer and comprising, for example, at least one of the following materials: alumina, AlN, SiO2, SiN.

[0051] In the described embodiment, the dielectric layer 132 is covered, at the lateral walls of the trenches 130, 131, by an electrically conductive layer 134. This electrically conductive layer 134 is also positioned against the bottom walls of the trenches 130, 131. In the example of the figure 1 The electrically conductive layer 134 is thus electrically isolated from the stack of layers present on the circuit 102 by the dielectric layer 132. Furthermore, the electrically conductive layer 134 is electrically coupled to the second electrodes 108 and is interrupted such that portions of this electrically conductive layer 134 arranged around each of the diodes 126 are electrically isolated from other portions of this electrically conductive layer 134 arranged around the other diodes 126. In the described embodiment, the electrically conductive layer 134 is interrupted at the bottom walls of the trenches 130. In the example of the figure 1 , the electrically conductive layer 134 is not interrupted in trench 131.

[0052] According to one embodiment, the electrically conductive layer 134 comprises at least one metal. This metal can, for example, allow light reflection, particularly in the visible range, which allows the light emitted laterally by the diodes 126 to be reflected off the electrically conductive layer 134 and thus avoid disturbing the neighboring diodes 126.

[0053] In the described embodiment, the electrically conductive layer 134 is covered by another dielectric layer 136 which also covers the parts of the dielectric layer 132 located at the interrupted parts of the electrically conductive layer 134 (at the bottom walls of the trenches 130 in the example of the figure 1 ). This other dielectric layer 136 contains, for example, SiO2 or alumina. For example, the figure 1 , the dielectric layer 136 is interrupted at the bottom wall of the trench 131 so that the electrically conductive layer 134 is electrically accessible from the bottom of the trench 131.

[0054] In the described embodiment, the remaining volume of the trenches 130 not occupied by layers 132, 134, and 136 is filled by electrically conductive portions 138 which are electrically insulated from the electrically conductive layer 134 by the dielectric layer 136. Although this is not visible on the figure 1 The electrically conductive portions 138 are electrically coupled to each other due to the grid-like shape of the trenches 130. In one embodiment, each of the electrically conductive portions 138 comprises a stack of several materials, for example, a stack of Ti / TiN and copper. In the trench 131, the electrically conductive portion 138 is electrically coupled to the electrically conductive layer 134, and therefore also to the third electrode 111.

[0055] In the described embodiment, the device 100 further comprises dielectric portions 140, including, for example, SiN, extending over the vertices of the portions of the electrically conductive layer 134. In addition, the device 100 comprises an electrically conductive and optically transparent layer 142 disposed on an upper face of the device 100, which electrically couples the electrically conductive portions 138 to each other and to the portions of the second semiconducting layer 122 of the diodes 126. This layer 142 is electrically isolated from the electrically conductive layer 134 by the dielectric portions 140. The electrically conductive and optically transparent layer 142 may include a transparent conductive oxide, for example, ITO, to allow light emission from the diodes 126 through it.Layer 142 also ensures the spreading of the current over the distance between the semiconductor of the second layer 122 and the electrically conductive portions 138.

[0056] In the described embodiment, the metallic filling of the trenches 130, 131 enables electrical coupling between portions of the second semiconductor layer 122 of the diodes 126 and the third electrode 111, which corresponds to the common cathode of the diodes 126. In the example shown on the figure 1 , device 100 also includes a connection pad 144 disposed on the electrically conductive portion 138 disposed in the trench 131, and serving as electrical access to the common cathode of the diodes 126.

[0057] Thus, the device 100 according to the first embodiment comprises diodes 126 that can be controlled independently of each other and addressed by control electrical potentials applied by the circuit 102 to the anodes corresponding to the first electrodes 106. In addition, the grids formed by the portions of the electrically conductive layer 134 around the semiconductor stacks of the diodes 126 can be controlled independently of each other and addressed by control electrical potentials applied by the circuit 102 to the second electrodes 108. Applying an electrical potential to these grids can modify the carrier distribution on the lateral sides of the P- or N-doped semiconductor (depending on the applied potential), thereby increasing the light emission efficiency of the diodes 126. When these electrical potentials are applied to these grids, no current flows through them.

[0058] Advantageously, the thickness of the dielectric layer 132 can be chosen to be sufficient to prevent breakdown when an electrical potential is applied to the gates of the diodes 126, but not so thick as to maximize the field effect applied through the gate of the diodes 126. For example, the thickness of this dielectric layer 132 is, for instance, between 10 nm and 60 nm, depending on the dielectric characteristics of the material(s) of this layer 132.

[0059] Advantageously, the thickness of the dielectric layer 136 can be chosen to be sufficient to prevent breakdown due to the electrical potentials applied to the gates of the diodes 126 and the reference electrical potential, for example, ground, applied to the cathode. For example, when the potential difference between the electrically conductive layer 134 and the electrically conductive portions 138 is on the order of 1 V, the dielectric layer 136 can contain alumina and have a thickness of approximately 10 nm.

[0060] The lateral sides of the trenches 130, 131 may be perpendicular to the surface of the circuit 102 to which the semiconductor stack is bonded, or they may form an angle such that the width of the trenches 130, 131 at the upper face of the device 100 (the face on which the dielectric portions 140 and the electrically conductive and optically transparent layer 142 are located) is greater than the width of these trenches 130, 131 at the level of the circuit 102, i.e., the dielectric layer 110 in the example of the figure 1 . Such a difference in width of trenches 130, 131 can facilitate the implementation of material deposits in trenches 130, 131.

[0061] The device 100 described therefore comprises a compact set of three-electrode diodes 126, of which the diodes 126 can be individually controlled thanks to the electrical independence of the anodes and gates of these diodes 126.

[0062] The structure of the device 100 can allow its realization by a monolithic integration, directly on the circuit 102, of the junctions forming the diodes 126 without critical alignment, thanks to the fact that the singularization of the diodes 126 (corresponding to the realization of the trenches 130) is carried out after the solidification of the semiconductor layers with the circuit 102.

[0063] An example of a method for implementing device 100 as previously described in connection with the figure 1 is described below in connection with the figures 2 à 9 .

[0064] The integrated circuit 102 is first made from a semiconductor substrate, for example by implementing classic microelectronic steps (deposition, lithography, etching, etc.) to form the electronic components of this integrated circuit 102 as well as the metallization levels (BEOL) including the metallization level 104. The first stack 112 and part of the layer 114 are also made on the level 104 in preparation for a future direct metal / metal bond with the semiconductor stack intended for the fabrication of the diodes 126.

[0065] In the described embodiment, the semiconductor stacking of layers 124, 122, and 120, as well as layer 118, the second stack 116, and part of layer 114, are carried out on a separate substrate (not shown). Layers 124, 122, and 120 are, for example, carried out by epitaxy. One or more buffer layers may be present on this separate substrate to facilitate the growth of layers 124, 122, and 120.

[0066] A direct metal-to-metal bond can then be used to join the two parts of layer 114 together, and the substrate used for the growth of layers 124, 122, and 120 can then be removed. Any buffer layer(s) interposed between the substrate and layer 124 can also be removed, for example, by thinning and etching.

[0067] Alternatively, other types of bonding can be implemented to bond the circuit 102 with the semiconductor stack from which the diodes 126 will be made.

[0068] In the described embodiment, a dielectric hard mask 146 is then produced, for example by deposition, on the semiconductor layer 122. In one example, the dielectric hard mask 146 may comprise SiO2 and / or SiN. The thickness of the dielectric hard mask 146 is chosen here to be sufficient to allow the trenches 130, 131 to be etched down to the electrodes 106, 108, 111. The structure obtained at this stage of the process is shown in the figure. figure 2 .

[0069] Trenches 130, 131 are then created through the semiconductor stack to electrodes 111, 106, and 108. In the described embodiment, lithography and etching can then be performed, using the dielectric hard mask 146, to form trenches 130, 131 through the layers present on electrodes 106, 108, and 111. The etching process can judiciously utilize a stop layer comprising, for example, TiN and / or SiN, present on the metallization layer of electrodes 106, 108, and 111. The use of such a stop layer ensures that any variations in the thickness of the etched materials do not affect the final depth of trenches 130, 131. This etching of trenches 130, 131 down to the metallization layer comprising the electrodes 106, 108, 111 then allow for the various re-establishments of contact. The structure obtained at this stage of the process is represented on the figure 3 .

[0070] In the described embodiment, the dielectric layer 132 is then deposited in the trenches 130, 131, covering the side and bottom walls of these trenches 130, 131, and also on the dielectric hard mask 146. Anisotropic etching can then be performed to remove the portions of the dielectric layer 132 located on the bottom walls of the trenches 130, 131, as well as those resting on the dielectric hard mask 146. The remaining portions of the dielectric layer 132 form dielectric spacers covering the sides of the diodes 126. The structure obtained at this stage of the process is shown in the figure. figure 4 .

[0071] The electrically conductive layer 134 is then deposited onto the structure, thus covering the bottom walls of the trenches 130, 131, the dielectric hard mask 146, and the remaining portions of the dielectric layer 132 positioned against the side walls of the trenches 130, 131. In the trenches 130, the electrically conductive layer 134 is in electrical contact with the second electrodes 108, i.e., those intended to form the grids of the diodes 126 in the example described. Prior to this deposition, one or more surface preparation steps may be carried out on the surfaces onto which the electrically conductive layer 134 is to be deposited, for example, to remove any native metal oxide present on these surfaces. The structure obtained at this stage of the process is shown in the figure 5 .

[0072] A localized etching step can then be implemented to remove certain portions of the electrically conductive layer 134 such that parts of the electrically conductive layer 134 arranged around each of the diodes 126 are electrically isolated from other parts of the electrically conductive layer 134 arranged around the other diodes 126. In other words, this etching can be implemented such that the remaining parts of the electrically conductive layer 134 are electrically isolated from one pixel to the next while maintaining electrical contact, for the remaining parts of the layer 134, around each diode 126, with one of the second electrodes 108. In the described embodiment, the etched parts of the electrically conductive layer 134 (designated by reference numeral 135 in the figure 6 ) are located on the bottom walls of the trenches 130. In the example described, this etching is carried out in such a way that the parts of the electrically conductive layer 134 located in the trench 131 are not etched and that electrical contact with the third electrode 111 is maintained. Alternatively, it is possible for the parts of the electrically conductive layer 134 located in the trench 131 to be etched. The structure obtained at this stage of the process is shown in the figure 6 .

[0073] In the described embodiment, the dielectric layer 136 is then deposited on the electrically conductive layer 134, and also on the portions of the trench bottom walls 130 that are no longer covered by the electrically conductive layer 134 (i.e., at the locations of the engraved portions 135). Localized engraving can then be performed to remove the portion of the dielectric layer 136 covering the bottom wall of the trench 131 so that the electrically conductive layer 134 remains electrically accessible from the bottom of the trench 131. The structure obtained at this stage of the process is shown in the figure. figure 7 .

[0074] In the described embodiment, the electrically conductive portions 138 are then formed so that they fill the remaining volume of the trenches 130, 131 not occupied by the other previously deposited layers. According to one embodiment, the formation of the portions 138 may involve the deposition of Ti / TiN / Cu layers from which electrochemical copper growth is subsequently carried out.

[0075] A planarization of the upper surface of the fabricated structure can then be carried out, stopping at the second semiconductor layer 122. This mechano-chemical polishing removes the dielectric hard mask 146, as well as portions of layers 134 and 136 and portions 138 located at the level of the dielectric hard mask 146. The structure obtained at this stage of the process is shown in the figure 8 .

[0076] In the described embodiment, a dielectric encapsulation layer 140 is then deposited on the upper face of the structure produced, this layer 140 being then etched locally in order to remove the parts of this layer covering the electrically conductive portions 138 and the second semiconducting layer 122. The remaining parts of this encapsulation layer form the dielectric portions 140.

[0077] In the described embodiment, the electrically conductive and optically transparent layer 142 is then deposited on the upper face of the fabricated structure, thus establishing electrical contacts between the portions of the second semiconducting layer 122 of the diodes 126 and the electrically conductive portions 138, and also with the electrically conductive portion 138 which is in contact with the third electrode 111 corresponding to the common cathode of the diodes 126. The structure obtained at this stage of the process is shown in the figure 9 .

[0078] Device 100 can then be completed by applying an electrical / chemical passivation coating and creating connection pads, including connection pad 144 which serves as the contact for the common cathode of device 100. The resulting device 100 corresponds to the one shown in the figure 1 Alternatively, other connection pads coupled to the anodes and / or the second electrodes 128 can also be made via routing in the metallization levels of the circuit.

[0079] In the example of the implementation of device 100 described previously in connection with the figure 1 All the diodes 126 in the device correspond to LEDs. Alternatively, it is possible that at least some of these diodes 126 correspond to photodiodes. In this case, the active area 124 may include one or more receiving layers, i.e., optically absorbing layers.

[0080] An example of an optoelectronic device 100 according to a second embodiment is described below in connection with the figure 10 .

[0081] In this second embodiment, the device 100 includes some diodes 126 corresponding to LEDs and other diodes 126 corresponding to photodiodes. On the figure 10 The diode designated by reference numeral 126a is an LED and is similar to the diodes 126 of device 100 according to the first embodiment described above. Thus, the portion of the second semiconductor layer 122 of this diode 126a is electrically coupled to one of the electrically conductive portions 138 adjacent to this portion of the second semiconductor layer 122 so that it is coupled to the common cathode of the LEDs of device 100. Furthermore, an electrical potential different from the electrical potentials applied to the anode and cathode of this diode 126a is intended to be applied to the gate of this diode 126a formed by the portions of the electrically conductive layer 134 arranged around the semiconductor stack of this diode 126a.

[0082] For example, the figure 10 The diode designated by reference numeral 126b is a photodiode that differs from diode 126a in that the electrical potential applied to the portion of the second semiconductor layer 122 of this photodiode 126b does not correspond to that of the common cathode, but rather to that applied to the grid of this diode 126b, which is formed by the portions of the electrically conductive layer 134 arranged around the semiconductor stack of this diode 126b. This configuration of diode 126b is achieved because the dielectric portion 140 formed next to this diode 126b covers the electrically conductive portion 138 and not one of the portions of the electrically conductive layer 134 arranged around the semiconductor stack of this diode 126b.Thus, the portion of the electrically conductive and optically transparent layer 142 formed above this diode 126b electrically couples the portion of the second semiconductor layer 122 of this diode 126b to one of the portions of the electrically conductive layer 134 arranged around the semiconductor stack of this diode 126b. Furthermore, in this configuration, the electrically conductive layer 142 is not continuous but is interrupted (interruption designated by reference 148 on the . figure 10 ) so that the parts of layer 134 providing electrical connections for the diodes corresponding to LEDs are not electrically connected to those providing electrical connections for the diodes corresponding to photodiodes.

[0083] In this second embodiment, the electrically conductive and optically transparent layer 142 allows the electrical potential applied to the portions of the second semiconductor layer 122 to be differentiated according to the nature of the diodes 126. Thus, for the diodes 126 corresponding to photodiodes, it is possible to apply the same electrical potential to the portions of the second semiconductor layer 122 of these photodiodes as that applied to the anodes of the diodes 126 corresponding to LEDs. Therefore, the circuit 102 does not need to supply opposing voltages to the LEDs and the photodiodes of the device 100, since the same voltage can be used for biasing both the LEDs and the photodiodes.

[0084] In a particular configuration, the device 100 may include a pixel matrix such that each pixel of the matrix comprises a first diode similar to diode 126a and corresponding to an LED, and a second diode similar to diode 126b and corresponding to a photodiode. Each pixel of such a matrix therefore fulfills both a light emission function and a light reception function.

[0085] An example of a method for implementing device 100 according to the second embodiment is described below in connection with the figures 11 à 14 .

[0086] The steps previously described in connection with the figures 2 à 8 are first implemented, with the difference, however, that the planarization of the upper face of the structure produced is implemented with a stop not on the second semiconductor layer 122 but on the hard dielectric mask 146. The structure obtained at this stage of the process is represented on the figure 11 .

[0087] The dielectric encapsulation layer is then deposited on the upper face of the structure produced. This layer is then etched locally, for example via photolithography, in order to remove, at the level of the diodes 126a intended to form LEDs, the parts of this layer covering the electrically conductive portions 138 and the dielectric hard mask 146, and to remove, at the level of the diodes 126b intended to form photodiodes, the parts of this layer covering the parts of the electrically conductive layer 134 and the dielectric hard mask 146.At the level of the diodes 126 intended to form photodiodes, a sufficiently large thickness of the dielectric layer 136, corresponding for example to a SiO2 layer with a thickness of approximately 200 nm, facilitates the implementation of this etching so as to etch the parts of the encapsulation layer located on the parts of the electrically conductive layer and to preserve those located on the electrically conductive portions 138. The remaining parts of this encapsulation layer form the dielectric portions 140. The structure obtained at this stage of the process is visible on the . figure 12 .

[0088] A second photolithography and etching step is then implemented to form openings 149 through the dielectric hard mask 146, allowing access to parts of the second semiconductor layer 122 of diodes 126a and 126b. The structure obtained at this stage of the process is shown in the figure 13 .

[0089] The electrically conductive and optically transparent layer 142 is then deposited on the upper surface of the fabricated structure, thus establishing electrical contacts between the portions of the second semiconductor layer 122 and the electrically conductive portions 138 for the diodes 126a corresponding to LEDs, and electrical contacts between the portions of the second semiconductor layer 122 and the portions of the electrically conductive layer 134 for the diodes 126b corresponding to photodiodes. Photolithography and etching steps of the electrically conductive layer 142 can then be implemented so that the electrically conductive layer 142 is interrupted, ensuring that the portions of this layer 142 providing electrical connections for the diodes corresponding to LEDs are not electrically connected to those providing electrical connections for the diodes corresponding to photodiodes.The structure obtained at this stage of the process is represented on the . figure 14 .

[0090] Device 100 can be completed as previously described for the first embodiment, the resulting device 100 corresponding to that shown in the figure 10 .

[0091] In the embodiments of device 100 described previously, the third electrode 111 forms a common cathode for all the diodes 126 corresponding to LEDs. Furthermore, in these examples, the third electrode 111 is located at an edge of device 100, for example, next to the diode array 126.

[0092] In a first variant applicable to the first or second embodiment described above, it is possible that each first electrode 106 is arranged between two second electrodes 108 to which are electrically coupled the parts of the electrically conductive layer 134 located around the diode 126, the portion of whose first semiconducting layer 120 is electrically coupled to said first electrode 106. In addition, in this first variant, the device 100 can comprise several third electrodes 111 arranged in the metallization level 104, each of the third electrodes 111 being electrically coupled to one of the electrically conductive portions 138 and arranged between two second electrodes 108, each electrically coupled to parts of the electrically conductive layer 134 located around different diodes 126.

[0093] An example of a part of a device 100 according to such a variant applied here to device 100 according to the first embodiment is shown on the figure 15 As can be seen in this figure, the parts of the electrically conductive layer 134 and the dielectric layer 136 located on the bottom walls of the trenches 130 and covering the third electrodes 111 are etched so that the electrically conductive portions 138 are in electrical contact with the third electrodes 111. In addition, the parts of the electrically conductive layer 134 arranged in the same trench are electrically coupled to second electrodes 108 different from each other.

[0094] This first variant can facilitate the realization of device 100, with the trade-off of a less compact device 100 thus produced compared to a device 100 comprising a single third electrode 111 located at the edge of device 100.

[0095] In a second variant that can be applied to the first or second embodiment described above, it is possible that the device 100 comprises several third electrodes 111 each electrically coupled to one of the electrically conductive portions 138 and arranged in the metallization level 104, each of the first electrodes 106 being arranged between one of the second electrodes 108 and one of the third electrodes 111, and each of the third electrodes 111 is arranged between one of the first electrodes 106 and one of the second electrodes 108.

[0096] An example of such a second variant, applied here to device 100 according to the first embodiment, is shown on the figure 16 As can be seen in this figure, the electrically conductive layer 134 and the dielectric layer 136 are etched such that one portion of the electrically conductive layer 134 is in electrical contact with the second electrode 108 located at the bottom of the trench 130, and the electrically conductive portion 138 is in contact with the third electrode 111 located at the bottom of the trench 130. Furthermore, in the example of the figure 16 , part of the electrically conductive layer 134 can be retained on the third electrode 111, the electrically conductive portion 134 being electrically coupled to the third electrode 111. Alternatively, this part of the electrically conductive layer 134 can be removed.

[0097] Like the first variant, this second variant makes it easier to produce device 100, but with the trade-off of less compactness than when device 100 has only one third electrode 111 located at the edge of device 100.

[0098] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0099] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

[0100] The scope of the present invention is defined by the following claims.

Claims

1. Optoelectronic device (100) comprising at least: - a plurality of diodes (126), each comprising a portion of a stack of at least a first and a second semiconductor layers (120, 122) doped according to opposite conductivity types, a portion of the first semiconductor layer (120) of each diode (126) being electrically coupled to a first electrode (106) arranged under said portion of the first semiconductor layer (120); - trenches (130) running through the stack, separating the diodes (126) from one another and from which second electrodes (108) are electrically accessible; - an electrically conductive layer (134) arranged at least against side walls of the trenches (130), electrically insulated from the stack, electrically coupled to the second electrodes (108) and which is interrupted in such a way that portions of the electrically conductive layer (134) arranged around each of the diodes (126) are electrically insulated from other portions of the electrically conductive layer (134) arranged around the other diodes (126); - electrically conductive portions (138) arranged in the trenches (130), electrically insulated from the electrically conductive layer (134) and electrically coupled to one another and to at least a third electrode (111); and characterized in that bottom walls of the trenches (130) are at least partly formed by the second electrodes (108).

2. Optoelectronic device (100) according to claim 1, wherein the electrically conductive layer (134) is interrupted at bottom walls of the trenches (130).

3. Optoelectronic device (100) according to one of the foregoing claims, wherein the electrically conductive portions (138) are electrically coupled to the portions of the second semiconductor layer (122) of at least part of the diodes (126) corresponding to light-emitting diodes, LEDs.

4. Optoelectronic device (100) according to claim 3, wherein the electrically conductive portions (138) are electrically coupled to the portions of the second semiconductor layer (122) of the LEDs by at least one electrically conductive and optically transparent layer (142) arranged on the stack and on the electrically conductive portions (138).

5. Electronic device (100) according to claim 4, wherein the electrically conductive and optically transparent layer (142) is electrically insulated from the electrically conductive layer (134) by dielectric portions (140) arranged between the electrically conductive layer (134) and the electrically conductive and optically transparent layer (142).

6. Optoelectronic device (100) according to one of the foregoing claims, wherein the electrically conductive portions (138) are electrically insulated from the electrically conductive layer (134) by at least a first dielectric layer (136) arranged between the electrically conductive portions (138) and the electrically conductive layer (134).

7. Optoelectronic device (100) according to one of the foregoing claims, wherein the third electrode (111) is arranged at an edge of the optoelectronic device (100).

8. Optoelectronic device (100) according to one of claims 1 to 6, wherein: - each first electrode (106) is arranged between two second electrodes (108) to which are electrically coupled the portions of the electrically conductive layer (134) located around the diode (126) having the portion of its first semiconductor layer (120) electrically coupled to said first electrode (106), and - the optoelectronic device (100) comprises a plurality of third electrodes (111), each electrically coupled to one of the electrically conductive portions (138) and arranged between two second electrodes (108), each electrically coupled to portions of the electrically conductive layer (134) located around different diodes (126).

9. Optoelectronic device (100) according to one of claims 1 to 6, comprising a plurality of third electrodes (111), each electrically coupled to one of the electrically conductive portions (138), each of the first electrodes (106) being arranged between one of the second electrodes (108) and one of the third electrodes (111), and each of the third electrodes (111) is arranged between one of the first electrodes (106) and one of the second electrodes (108).

10. Optoelectronic device (100) according to one of the foregoing claims, wherein the portions of the electrically conductive layer (134) arranged around at least part of the diodes (126) corresponding to photodiodes are electrically coupled to the portions of the second semiconductor layer (122) of the photodiodes.

11. Optoelectronic device (100) according to claim 10, wherein the portions of the electrically conductive layer (134) arranged around the photodiodes are electrically coupled to the portions of the second semiconductor layer (122) of the photodiodes by at least one electrically conductive and optically transparent layer (142) arranged on the stack and on the portions of the electrically conductive layer (134) arranged around the photodiodes.

12. Optoelectronic device (100) according to one of the foregoing claims, further comprising a passivation layer (132) arranged between the electrically conductive layer (134) and the stack.

13. Method of manufacturing an optoelectronic device (100), comprising at least the steps of: - forming of a stack of at least a first and a second semiconductor layers (120, 122) doped according to opposite conductivity types; - creation of trenches (130) running through the stack, separating from one another diodes (126), each comprising a portion of the stack and providing access to second electrodes (108) such that bottom walls of the trenches (130) are at least partly formed by the second electrodes (108), a portion of the first semiconductor layer (120) of each diode (126) being electrically coupled to a first electrode (106) arranged under said portion of the first semiconductor layer (120); - forming of an electrically conductive layer (134) arranged at least against side walls of the trenches (130), electrically insulated from the stack, electrically coupled to the second electrodes (108) and which is interrupted in such a way that portions of the electrically conductive layer (134) arranged around each of the diodes (126) are electrically insulated from the portions of the electrically conductive layer (134) located around the other diodes (126); - implementation of electrically conductive portions (138) arranged in the trenches (130), electrically insulated from the electrically conductive layer (134) and electrically coupled to one another and to at least a third electrode (111).