WAFER HANDLING ASSEMBLY

DE602024005607T2Active Publication Date: 2026-06-24ASM IP HLDG BV
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
ASM IP HLDG BV
Filing Date
2024-05-21
Publication Date
2026-06-24

AI Technical Summary

Technical Problem

Existing semiconductor processing technologies face challenges in handling warped substrates and large-sized wafers, leading to increased production costs and wafer breakage during batch processing.

Method used

A wafer handling assembly with a boat and end effector design that includes three supports per wafer, positioned to minimize movement and provide balanced support, allowing for improved handling of warped and large-sized wafers, reducing pitch and enhancing throughput.

Benefits of technology

The assembly enhances wafer handling reliability, reduces breakage and cracking, and lowers production costs by enabling higher wafer loads and efficient transfer, particularly for warped wafers.

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