Ac / dc power converter

Abstract

Provided an AC / DC power converter (300, 422). The AC / DC power converter (300, 422) includes a low-frequency half-bridge switching device circuit (Sa, Sb) (302), a high-frequencyhalf-bridge switching device (S1, S2) circuit (304) and a controller (308, 420). The controller (308, 420) includes a Power Factor Correction (PFC) stage with an outer loop configured forDC-bus voltage control (402) and an inner loop (404) for controlling the converter duty cycle.The controller (308, 420) is configured to generate a converter duty cycle. The controller (308, 420) is configured to saturate the converter duty cycle based on a converter gain. The controller (308, 420) is configured to maintain the converter gain after the converter duty cycle saturationaround the zero-crossing region by utilizing a zero-crossing compensation algorithm.

Description

[0001] AC / DC POWER CONVERTER

[0002] TECHNICAL FIELD

[0003] The disclosure relates to power converters, more particularly, the disclosure relates to an AC / DC power converter.

[0004] BACKGROUND

[0005] 5G provides advanced connectivity that enables convergence of everything across different scenarios and devices such as smartphones, tablets, and laptops with larger screens. The devices require more power, and the pressure on battery life and charging continues to increase. Hence there is an increasing demand for the next generation of AC / DC adapters to charge larger Lithium-ion batteries very quickly. The current trend for higher-end mobiles / smart devices is faster charging. Hence, AC / DC adapters with higher power, smaller size, and lightweight are needed. Earlier, the AC / DC adapters have a range of charging from 5 Watts to 50W. Recently, the charging of the AC / DC adapters has increased up to 120W or more on high-end, premium devices today. However, today’s laptops are already 50 - 60W with big, bulky chargers, and isolated single-stage power factor correction (PFC) AC / DC converters together with wide band gap semiconductor materials like Gallium Nitride (GaN) comes the opportunity to deliver the high-power fast-charging, in a dramatically smaller and lighter-weight form-factor.

[0006] FIGS. 1A-1C illustrate a bridge two-stage AC / DC converter, a bridge single-stage AC / DC converter, and a bridgeless single-stage AC / DC converter, in accordance with a prior art. The most popular AC / DC converter topology in PFC AC / DC converters is the bridge two-stage AC / DC converter as shown in FIG. 1A. The bridge two-stage AC / DC converter includes the first stage which provides PFC and a half-bridge LLC resonant converter that regulates the output voltage. The bridge two-stage AC / DC converter achieves high efficiency owing to an increased number of semiconductors, improved magnetic components designs, and reduced switching frequency. However, the power density of the bridge two-stage AC / DC converter decreases as the input energy is processed in two steps, thereby there is a limitation in efficiency. The components in the bridge two-stage AC / DC converters are more, thereby the cost for low power applications is higher. The control of the bridge two-stage AC / DC converter becomes complex.

[0007] Furthermore, the AC / DC converter topology as shown in FIG. IB is the bridge single-stage AC / DC converter. The bridge single-stage AC / DC converter integrates a diode bridge, boost inductor with a LLC resonant converter in other to provide PFC feature and output voltage regulation. The components in the bridge single-stage AC / DC converter are less, thereby the cost for low power applications is lower. Whereas, there is a limitation of device ratings being higher than the bridge two stage AC / DC converter. The issues relating to low-frequency ripples (100 Hertz) also arises. In the modulation control strategy, the degrees of freedom are limited in nature. The bridge single stage AC / DC converter is show in FIG. IB regulates the DC bus voltage with the asymmetric duty cycle control and pulse frequency modulation control for the output voltage regulation.

[0008] The bridgeless single-stage AC / DC converter as shown in FIG. 1C provides output voltage regulation using asymmetric duty cycle control with fixed frequency and no DC bus regulation. A point to note is operation in bridgeless configuration as seen in FIG. 1C requires the need for fast diode for the input diodes (£)1,£)2) and not low ohmic MOSFETs. This is because the input diodes are pulsating at the switching frequency and this behavior could make the input filter bigger leading to increased size and cost.

[0009] FIG. 2A is a graph illustrating duty cycle for various input voltages according to a prior art. The duty cycle depends on the magnitude of the input voltage as shown in Fig. 2a, during high input voltages, the duty cycle becomes quite small. The small duty cycle impact can be seen in FIG. 2B where at high input voltages low efficiency could be observed.

[0010] Duty dem

[0011] FIG. 2B is a graph illustrating efficiency for various input voltages according to a prior art. The smaller duty cycle as the magnitude of the input voltage increases, causes a lower efficiency in the bridge single-stage AC / DC converter. Thereby the efficiency becomes as low as approximately 90% in FIG. 2B. Furthermore, the operation is in discontinuous conduction mode (DCM) for the bridge single- stage AC / DC converter, and the bridgeless single-stage AC / DC converter. This DCM operation causes higher input current total harmonic distortion, high root mean square (RMS) current through the switches, and therefore another reason for low efficiency. As the cost of the fast diode is more, thereby the single-stage AC / DC converter becomes costlier.

[0012] Therefore, the present invention aims to overcome the outlined drawbacks of the single-stage AC / DC converters.

[0013] SUMMARY

[0014] It is an object of the disclosure to provide an AC / DC power converter to achieve benefit of wide input and wide output voltage regulation using a new control technique for single stage AC / DC resonant converter topologies. The new control technique uses ACM control technique to regulate the PFC stage and VFM control technique for the DC stage regulation (output voltage). With this control, zero voltage switching (ZVS) and Zero current switching (ZCS) is guaranteed for all the operating point while avoiding the disadvantages of prior art approaches.

[0015] This object is achieved by the features of the independent claims. Further implementations are apparent from the dependent claims, the description, and the figures.

[0016] It is another object of the disclosure to provide an AC / DC power converter.

[0017] According to a first aspect, there is provided an AC / DC power converter. The AC / DC power converter includes a low-frequency half-bridge switching device circuit (Sa, Sb), a high- frequency half-bridge switching device (SI, S2) circuit, and a controller. The controller includes a Power Factor Correction (PFC) control stage with an outer loop configured for DC- bus voltage control, and an inner loop for controlling the converter duty cycle. The controller is configured to generate a converter duty cycle. The controller is configured to saturate the converter duty cycle based on the converter gain. The controller is configured to maintain the converter gain after the converter duty cycle saturation around the zero-crossing region by utilizing a zero-crossing compensation algorithm.

[0018] The AC / DC power converter is appropriate for higher power levels due to high efficiency owing to guaranteed ZVS for all operating points in the converter which was also achieved in the case of this invention. The switching resonant stage operates below the resonant frequency by a large margin. The ZVS is still retained across the switches without incurring higher conduction losses in both the primary and the secondary sides of the ac / dc power converter. This is because of the advantage of designing the boost inductor such that the current of the boost inductor can go below zero or negative, hence plays a key role in still maintaining ZVS. This behavior of the switching resonant stage operating below the resonant frequency without a hard switch made it possible for the ac / dc power converter to have wide input (110 to 230Vac) and wide output (11 Vdc to 20Vdc) regulation and while maintaining high efficiency. The high efficiency and wide input / output voltage regulation ability of the ac / dc power converter is maintained due to the wide duty cycle variation (duty cycle independent of the magnitude of the input voltage) and operation of the switching resonant stage below and above the resonant frequency region without losing ZVS / ZCS through different combinations of input voltage to DC bus voltage control. More so, there is no need for additional circuits to cancel low-frequency ripple (100Hz) in the output due to the DC-bus capacitor acting as power decoupling.

[0019] The AC / DC power converter provides low THD (<10%), high PF (>96%), high power density, and high efficiency (>95%). The THD of the ac / dc power converter meets IEC Class D requirement.

[0020] Optionally, the AC / DC power controller is further configured to saturate the converter duty cycle between 0.2 and 0.8 based on the converter gain.

[0021] Optionally, the AC / DC power controller is further configured to turn off low-frequency halfbridge switching device circuit (Sa, Sb) to stop reverse power flow utilizing the zero crossing compensation algorithm near the zero crossing area.

[0022] Optionally, the AC / DC power controller is further configured to utilize continuous conduction (CCM) mode in the converter duty cycle before the duty cycle saturation and to utilize discontinuous conduction mode (DCM) mode in the converter duty cycle after the duty cycle saturation and in the zero crossing area.

[0023] Optionally, the AC / DC power controller is further configured to regulate the output voltage using Variable frequency modulation (VFM) thereby generating a switching frequency. Optionally, the controller is further configured to compare the switching frequency to the generated converter duty cycle to generate a high frequency (HF) PWM signal for the high- frequency half-bridge switching devices (SI, S2). Optionally, the AC / DC power controller is further configured to control the switches (S1,S2) of the high-frequency half-bridge switching device circuit and the switches (Sa, Sb) of the low- frequency half-bridge switching device circuit utilizing the PWM signal based on a grid frequency.

[0024] Optionally, the AC / DC power controller is further configured to set the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit to turn-off during the DCM mode and set to turn-on complementarily in each half-cycle of grid frequency (50Hz / 60Hz) during the CCM mode.

[0025] Optionally, the AC / DC power controller is further configured to, utilizing the zero-crossing algorithm, determine the clamping voltage (Vg ciamp) and the clamping angle (wt) for setting the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit to turn-off by: where V)>us, Vg Pk and Dciampare the bus voltage, peak of the input voltage and clamp duty respectively, and scaling down of the converter duty cycle in the DCM mode based on the equation: where Lb, fsw, and Pacare the boost inductor, switching frequency and input power respectively.

[0026] Optionally, the AC / DC power controller is further configured to run the PFC control in the DCM region to generate the converter duty cycle to be compared with the switching frequency to generate the HF PWM signal.

[0027] Optionally, the AC / DC power converter further includes a Bridgeless Rectifier stage including a boost inductor, and a DC-bus capacitor coupled with a switching resonant stage. Optionally, the switch resonant stage includes a resonant inductor, a resonant capacitor and a high frequency (HF) transformer connected to output synchronous rectification (SR) Switches (SR1-SR2).

[0028] Optionally, the switch resonant stage further includes two switches (S1,S2) of the high- frequency half-bridge Switching circuit and two switches (Sa, Sb) of the low-frequency halfbridge Switching circuit.

[0029] Optionally, the AC / DC power converter further includes a modulation controller for an integrated PFC+LLC stage.

[0030] Therefore, in contradistinction to the prior art, according to the method and the apparatus, of providing an application-level attestation for trusted applications with a higher level of trust guarantees and privacy.

[0031] These and other aspects of the disclosure will be apparent from the implementations described below.

[0032] BRIEF DESCRIPTION OF DRAWINGS

[0033] Implementations of the disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0034] FIGS. 1A-1C illustrate a bridge two stage AC / DC converter, a bridge single-stage AC / DC converter, and a bridgeless single stage AC / DC converter, in accordance with a prior art;

[0035] FIG. 2A is a graph illustrating a duty cycle for various input voltages according to a prior art;

[0036] FIG. 2B is a graph illustrating efficiency for various input voltages according to a prior art;

[0037] FIG. 3 is a circuit diagram of a single-stage AC / DC converter with a low-frequency half-bridge switching device circuit, and a high-frequency half-bridge switching device circuit, in accordance with an implementation of the disclosure;

[0038] FIG. 4 is a topological diagram of a single-stage AC / DC converter illustrating a control modulation strategy, in accordance with an implementation of the disclosure; FIG. 5 is a block diagram of control of high-frequency switches and a low-frequency switches, in accordance with an implementation of the disclosure;

[0039] FIGS. 6A-6D are graphical representations of operation of switches (Sa, Sb) of the low- frequency half-bridge switching device circuit in CCM mode and DCM mode using a zerocrossing compensation algorithm, in accordance with an implementation of the disclosure;

[0040] FIG. 7 is a graphical representation of gain curve for variation of a duty cycle of a single-stage AC / DC converter, in accordance with an implementation of the disclosure;

[0041] FIG. 8 is a graphical representation of power factor of a single stage AC / DC converter for variation of output power, in accordance with an implementation of the disclosure;

[0042] FIG. 9 is a graphical representation of efficiency of a single stage AC / DC converter for variation of output power, in accordance with an implementation of the disclosure; and

[0043] FIG. 10 is a graphical representation of total harmonic distortion of a single stage AC / DC converter, in accordance with an implementation of the disclosure.

[0044] DETAILED DESCRIPTION OF THE DRAWINGS

[0045] Implementations of the disclosure provide an AC / DC power converter with a benefit of wide input and wide output voltage regulation using the newly developed control technique which provides zero voltage switching (ZVS) for all operating points in the converter.

[0046] To make solutions of the disclosure more comprehensible for a person skilled in the art, the following implementations of the disclosure are described with reference to the accompanying drawings.

[0047] Terms such as "a first", "a second", "a third", and "a fourth" (if any) in the summary, claims, and foregoing accompanying drawings of the disclosure are used to distinguish between similar objects and are not necessarily used to describe a specific sequence or order. It should be understood that the terms so used are interchangeable under appropriate circumstances, so that the implementations of the disclosure described herein are, for example, capable of being implemented in sequences other than the sequences illustrated or described herein. Furthermore, the terms "include" and "have" and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, a method, a system, a product, or a device that includes a series of steps or units, is not necessarily limited to expressly listed steps or units but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or device.

[0048] FIG. 3 is a circuit diagram of an AC / DC power converter 300, in accordance with an implementation of the disclosure. The circuit diagram of the AC / DC power converter 300 includes a low-frequency half-bridge switching device circuit (Sa, Sb) 302, a high-frequency half-bridge switching device (SI, S2) circuit 304, and a controller 308. The controller 308 includes a Power Factor Correction (PFC), control stage with an outer loop configured for DC- bus voltage control and an inner loop for controlling the converter duty cycle. The controller 308 is configured to generate a converter duty cycle. The controller 308 is configured to saturate the converter duty cycle based on a converter gain. The controller 308 is configured to maintain the converter gain after the converter duty cycle saturation around the zero-crossing region by utilizing a zero-crossing compensation algorithm.

[0049] The circuit diagram of the AC / DC power converter 300 includes a switching resonant stage 306. The low-frequency half-bridge switching device circuit (Sa, Sb) 302 may include low- frequency MOSFETs. The high-frequency half-bridge switching device (SI, S2) circuit 304 may include gallium nitride (GaN) switches. The switching resonant stage 306 includes a resonant inductor Lr, a resonant capacitor Cr and a high frequency (HF) transformer connected to output synchronous rectification (SR) switches (SR1-SR2). The AC / DC power converter 300 receives an input power from an AC-source (Vac), through an input EMI filter 310. For example, the input filter can be realized as a single-stage or two stage common-mode (CM) filter and differential filter (DF). The first output terminal of the EMI filter 310 is connected to the input stage of the AC / DC power converter 300. The AC / DC power converter 300 includes a boost inductor Lb, connected to the switches (SI, S2) of the high-frequency half-bridge switching device circuit 304. One of the terminals of the resonant inductor Lr and the other terminals connects to the resonant capacitor Cr. The resonant capacitor Cr connects to the primary windings of the high frequency (HF) transformer and the secondary windings connect to the output synchronous rectification (SR) switches (SR1-SR2) before connection to the output capacitor Co which powers the load.

[0050] The AC / DC power converter 300 is appropriate for higher power levels due to high efficiency owing to guaranteed ZVS for all operating points in the AC / DC power converter 300. The switching resonant stage operates below the resonant frequency by a large margin. The ZVS is still retained across the switches without incurring higher conduction losses in both the primary and the secondary sides of the AC / DC power converter 300. This is because of the advantage of designing the boost inductor such that the current of the boost inductor can go below zero or negative plays a key role in still maintaining ZVS. This behavior of the switching resonant stage operating below the resonant frequency without hard switch made it possible for the AC / DC power converter 300 to have wide input (110 to 230 Vac) and wide output (I lVdc to 20Vdc) regulation and maintaining high efficiency. The high efficiency of the AC / DC power converter 300 is maintained due to wide a variation in the duty cycle as the magnitude of the input voltage is now independent of the duty cycle, operation of the switching resonant stage below and above the resonant frequency region without losing ZVS / ZCS through different combination of input voltage to DC bus voltage control, while still retaining ZVS. More so, there is no need for additional circuits to cancel low frequency ripple (100Hz) in the output due to the DC-bus capacitor acting as power decoupling.

[0051] The AC / DC power converter 300 provides low THD (<10%), high PF (>96%), high power density and high efficiency (>95%). The THD of the AC / DC power converter 300 meets IEC Class D requirement.

[0052] Optionally, the AC / DC power controller 308 is further configured to saturate the converter duty cycle between 0.2 and 0.8 based on the converter gain.

[0053] Optionally, the AC / DC power controller 308 is further configured to turn off low-frequency half-bridge switching device circuit (Sa, Sb) 302 to stop reverse power flow utilizing the zerocrossing compensation algorithm near the zero crossing area.

[0054] Optionally, the AC / DC power controller 308 is further configured to utilize continuous conduction (CCM) mode in the converter duty cycle before the duty cycle saturation and to utilize discontinuous conduction mode (DCM) mode in the converter duty cycle after the duty cycle saturation and in the zero-crossing area.

[0055] Optionally, the AC / DC power controller 308 is further configured to regulate the output voltage using Variable frequency modulation (VFM) thereby generating a switching frequency. Optionally, the controller is further configured to compare the switching frequency to the generated converter duty cycle to generate a high frequency (HF) PWM signal for the high- frequency half-bridge switching devices (SI, S2). Optionally, the AC / DC power controller 308 is further configured to control the switches (SI, S2) of the high-frequency half-bridge switching device circuit 304 and the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit 302 utilizing the PWM signal based on a grid frequency.

[0056] Optionally, the AC / DC power controller 308 is further configured to set the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit 302 to turn-off during the DCM mode and set to turn-on complementarily in each half-cycle of grid frequency (50Hz / 60Hz) during the CCM mode.

[0057] Optionally, the AC / DC power controller 308 is further configured to, utilizing the zerocrossing algorithm, determine the clamping voltage (Vg ciamp) and the clamping angle (wt) for setting the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit 302 to turn-off by: where V[,us, g pkand Dciamp are the bus voltage, peak of the input voltage and clamp duty respectively, and scaling down of the converter duty cycle in the DCM mode based on the equation: where Lb, fsw, and Pacare the boost inductor, switching frequency and input power respectively.

[0058] Optionally, the AC / DC power controller 308 is further configured to run the PFC control in the DCM region to generate the converter duty cycle to be compared with the switching frequency to generate the HF PWM signal.

[0059] Optionally, the AC / DC power converter further including a Bridgeless Rectifier stage including a boost inductor, and a DC-bus capacitor coupled with a switching resonant stage. Optionally, the switch resonant stage includes a resonant inductor, a resonant capacitor and a high frequency (HF) transformer connected to output synchronous rectification (SR) Switches (SR1-SR2).

[0060] Optionally, the switch resonant stage further includes two switches (SI, S2) of the high- frequency half-bridge Switching circuit 304 and two switches (Sa, Sb) of the low-frequency half-bridge Switching circuit 302.

[0061] Optionally, the converter further includes a modulation controller for an integrated PFC+LLC stage.

[0062] FIG. 4 is a topological diagram of a controller 420 of an AC / DC power converter 422 illustrating a control modulation strategy, in accordance with an implementation of the disclosure. The topological diagram of the controller 420 includes a high-frequency (HF) MOSFET control 400, a stage with an outer loop configured for DC-bus voltage control 402, an inner loop 404 for controlling the converter duty cycle, a zero-crossing operation 406, pulse width modulators (PWM) 408 A, 408B for generating PWM signals by comparing with the converter duty cycle, an output voltage loop (VFM) 410, and a low-frequency (LF) MOSFET control 412.

[0063] The HF MOSFET control 400 may include the switches (SI, S2) of the high-frequency halfbridge switching device circuit. The LF MOSFET control 412 may include the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit. The PWM modulators 408A, 408B may generate PWM signals by encoding an amplitude of a signal into a pulse width.

[0064] The control modulation strategy includes an average current mode control (ACM) technique and a variable frequency mode (VFM) control modulation. The ACM control technique provides PFC regulation and the VFM control technique regulate the output voltage and generate a switching frequency.

[0065] The PFC control stage with an outer loop configured for the DC-bus voltage control 402 compares DC bus voltage with a constant DC reference value to generate an error signal in a low bandwidth proportional-integral (PI) controller. The low bandwidth may be 8-10Hz. The output of the PI controller is divided by a square of root mean square of the input ac voltage (Vac) and then multiplied with a measured Vac to generate a reference current (lac ref). The inner loop 404 for controlling the converter duty cycle compares the reference current (lac ref) with a measured input AC (lac) to generate an error signal that is provided to the PI controller to generate a converter duty cycle. The converter duty cycle is saturated between 0.2 and 0.8 based on a converter gain. The converter duty cycle may be compensated for around the zerocrossing area using a zero-crossing algorithm. The zero-crossing compensation algorithm maintains the converter gain near zero crossing region and turns off the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit to stop reverse power flow. The converter duty cycle combines CCM and DCM mode duty cycles before and during the zero-crossing region respectively. The output voltage loop (VFM) 410 regulates the output voltage using VFM. The bandwidth may be greater than 2KHz. The output voltage is compared with the converter duty cycle to produce the PWM signals for the switches (SI, S2) of the high- frequency half-bridge switching device circuit. The PWM signals control the switches (SI, S2) of the high-frequency half-bridge switching device circuit and the switches (Sa, Sb) of the low- frequency half-bridge switching device circuit. The switches (SI, S2) of the high-frequency half-bridge switching device circuit and the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit is controlled based on the grid frequency (50Hz). The switches (Sa, Sb) of the low-frequency half-bridge switching device circuit are turned off during the DCM operation and turn on complementarily in each half-cycle of grid frequency (50Hz).

[0066] FIG. 5 is a block diagram of a control of high-frequency switches and a low-frequency switches, in accordance with an implementation of the disclosure. An outer loop 502 compares DC bus voltage with a constant DC reference value to generate an error signal in a low bandwidth proportional-integral (PI) controller. The low bandwidth may be 8-10Hz. The output of the PI controller is divided by a square of root mean square of the input ac voltage (Vac) and then multiplied with a measured Vac to generate a reference current (lac ref). An inner loop 504 that compares the reference current (lac ref) with a measured input AC (lac) to generate an error signal that is provided to a PI controller to generate a converter PFC duty cycle. The converter PFC duty cycle is saturated between 0.2 and 0.8 according to the converter gain. The PFC duty cycle is compensated for around the zero-crossing area using a new developed zero-crossing algorithm. The Zero crossing compensation algorithm maintains the converter gain near zero crossing region and turns off the LF switches to stop reverse power flow. The generated PFC duty cycle combines CCM and DCM mode duty cycles before and during the zero-crossing region respectively. The output voltage loop (Bandwidth>2KHz) regulates the output voltage using VFM and then compared with the unique converter duty cycle to produce the PWM signals for the HF switches (SI, S2). The PWM signals control the HF switches (SI, S2) and the LF switches (Sa, Sb) is controlled based on the grid frequency (50Hz). The LF switches (Sa, Sb) are turn-off during the DCM operation and turn on complementarity in each half-cycle of grid frequency (50Hz).

[0067] FIG. 6A is a graphical representation of operation of switches (Sa, Sb) of a low-frequency halfbridge switching device circuit in CCM mode and DCM mode, in accordance with an implementation of the disclosure. The graphical representation depicts the change of mode of the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit based on the grid frequency. The switches (Sa, Sb) of the low-frequency half-bridge switching device circuit are turned off in DCM mode and turned on complementarily for each half-cycle of the grid frequency 50 Hertz / 60 Hz during the CCM mode of the converter.

[0068] For example, the switch Sb is turned on initially and in the next half-cycle of the grid frequency, the switch Sa is turned on as shown in the figure.

[0069] FIG. 6B is a graphical representation of current spikes in zero-crossing region, in accordance with an implementation of the disclosure. The graphical representation depicts current spikes in zero-crossing region when the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit are not turned off.

[0070] FIG. 6C is a graphical representation of current spikes after zero crossing region, in accordance with an implementation of the disclosure. The graphical representation depicts current spikes after zero crossing region due to no change in duty cycle in the zero crossing area. The converter duty cycle is clamped and the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit are turned off in the zero-crossing region. If the switches of the low-frequency half-bridge switching device circuit are not turned off there is a huge reverse power flow around zero crossing area causing huge current spikes.

[0071] FIG. 6D is a graphical representation of depicting duty cycle scaled-down in zero crossing region, in accordance with an implementation of the disclosure. The graphical representation depicts the scaling down of the duty cycle in the zero-crossing region. The zero-crossing region is depicted using a zero-crossing algorithm. The zero-crossing algorithm determines the clamping voltage (Vg ciamp) and the clamping angle (wt) for setting the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit to turn-off by: where Vbus, Vg pkand Dciampare the bus voltage, peak of the input voltage, and clamp duty respectively, and scaling down of the converter duty cycle in the DCM mode based on the equation: where Lb, fsw, and Pacare the boost inductor, switching frequency and input power respectively. The change in the duty cycle at clamp region prevents the current spike, maintains the converter gain to regulate the main output voltage.

[0072] FIG. 7 is a graphical representation of gain curves for variation of a duty cycle of a single stage AC / DC converter, in accordance with an implementation of the disclosure. The graphical representation depicts various gain curves for the single-stage AC / DC converter when the duty cycle ranges from 0 to 1. When the duty cycle is lower than 0.2 or higher than 0.8, the voltage gain between the DC-bus voltage and output voltage drops very fast. The dropping of the output voltage initiates difficulty in the regulation of the output voltage. Thereby, the duty cycle of 0.3 to 0.7 is referred to as a working region of the single-stage AC / DC converter as the voltage gain remains flat.

[0073] FIG. 8 is a graphical representation of power factor of a single stage AC / DC converter for variation of output power, in accordance with an implementation of the disclosure. The graphical representation depicts the power factor greater than 96% at full power of 150W. The power factor is worse as the power goes lower at high input voltage of 230Vac rms. However, below 75 W power, power factor may not be needed as per class D requirement standard.

[0074] FIG. 9 is a graphical representation of efficiency of a single stage AC / DC converter for variation of output power, in accordance with an implementation of the disclosure. The graphical representation depicts efficiency curves for high input voltage 230 Volts (V) and low input voltage at full load of 150 W, 20V, and 75W, 1 IV respectively. The peak efficiencies of 95.44% and 95.18% are obtained for low and high input voltage respectively. FIG. 10 is a graphical representation of total harmonic distortion (THD) of a single stage AC / DC converter, in accordance with an implementation of the disclosure. The graphical representation depicts measured THD for each harmonic. The measured THD may be up to 39thharmonics meet the required IEC 61000-3-2 Class D requirement by a large margin at high input voltage.

[0075] It should be understood that the arrangement of components illustrated in the figures described are exemplary and that other arrangement may be possible. It should also be understood that the various system components (and means) defined by the claims, described below, and illustrated in the various block diagrams represent components in some systems configured according to the subject matter disclosed herein. For example, one or more of these system components (and means) may be realized, in whole or in part, by at least some of the components illustrated in the arrangements illustrated in the described figures.

[0076] In addition, while at least one of these components are implemented at least partially as an electronic hardware component, and therefore constitutes a machine, the other components may be implemented in software that when included in an execution environment constitutes a machine, hardware, or a combination of software and hardware.

[0077] Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

CLAIMS1. An AC / DC power converter (300, 422), the converter (300, 422) comprising a low- frequency half-bridge switching device circuit (Sa, Sb) (302), a high-frequency halfbridge switching device (SI, S2) circuit (304) and a controller (308, 420) comprising a Power Factor Correction (PFC), stage with an outer loop (402) configured for DC-bus voltage control (402) and an inner loop (404) for controlling the converter duty cycle, wherein the controller (308, 420) is configured to: generate a converter duty cycle; saturate the converter duty cycle based on a converter gain; and maintain the converter gain after the converter duty cycle saturation around the zero-crossing region by utilizing a zero-crossing compensation algorithm.

2. The AC / DC power converter (300, 422) according to claim 1, wherein the controller (308, 420) is further configured to saturate the converter duty cycle between 0.2 and 0.8 based on the converter gain.

3. The AC / DC power converter (300, 422) according to claim 1 or 2, wherein the controller (308, 420) is further configured to turn off low- frequency half-bridge switching device circuit (Sa, Sb) (302) to stop reverse power flow utilizing the zero-crossing compensation algorithm near the zero-crossing area.

4. The AC / DC power converter (300, 422) according to claim 1, 2 or 3, wherein the controller (308, 420) is further configured to utilize continuous conduction (CCM) mode in the converter duty cycle before the duty cycle saturation and to utilize discontinuous conduction mode (DCM) mode in the converter duty cycle after the duty cycle saturation and in the zerocrossing area.

5. The AC / DC power converter (300, 422) according to any preceding claim, wherein the controller (308, 420) is further configured to regulate the output voltage using Variable frequency modulation (VFM) thereby generating a switching frequency, and to compare the switching frequency to the generated converter duty cycle to generate a high frequency (HF) PWM signal for the high-frequency half-bridge switching devices (SI, S2) (304).

6. The AC / DC power converter (300, 422) according to claim 5, wherein the controller (308, 420) is further configured to control the switches (SI, S2) of the high-frequency halfbridge switching device circuit (304) and the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit (302) utilizing the PWM signal based on a grid frequency.

7. The AC / DC power converter (300, 422) according to claim 4 and 6, wherein the controller (308, 420) is further configured to set the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit (302) to turn-off during the DCM mode and set to turn-on complementarily in each half-cycle of grid frequency (50Hz / 60Hz) during the CCM mode.

8. The AC / DC power converter (300, 422) according to any preceding claim, wherein the controller is further configured to, utilizing the zero-crossing algorithm, determine the clamping voltage (Vg ciamp) and the clamping angle (wt) for setting the switches (Sa, Sb) of the low-frequency half-bridge switching device circuit (302) to turn-off by:where Vbus, Vg pkand Dciampare the bus voltage, peak of the input voltage and clamp duty respectively, and scaling down of the converter duty cycle in the DCM mode based on the equation:where Lb, fsw, and Pacare the boost inductor, switching frequency and input power respectively.

9. The AC / DC power converter (300, 422) according to claim 5 and 8, wherein the controller (308, 420) is further configured to run the PFC control in the DCM region to generate the converter duty cycle to be compared with the switching frequency to generate the HF PWM signal.

10. The AC / DC power converter (300, 422) according to any preceding claim, further comprising a Bridgeless Rectifier stage comprising a boost inductor, and a DC-bus capacitor coupled with a switching resonant stage (306).

11. The AC / DC power converter (300, 422) according to claim 10, wherein the switch resonant stage (306) comprises a resonant inductor, a resonant capacitor and a high frequency (HF) transformer connected to output synchronous rectification (SR) Switches (SR1-SR2).

12. The AC / DC power converter (300, 422) according to claim 10 or 11, wherein the switch resonant stage (306) further comprises two switches (SI, S2) of the high-frequency half-bridge Switching circuit and two switches (Sa, Sb) of the low-frequency half-bridge Switching circuit.

13. The AC / DC power converter (300, 422) according to any of claims 10 to 12, wherein the AC / DC power converter (300, 422) further comprises a modulation controller for an integrated PFC+LLC stage.

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