Reram device and production method therefor

Abstract

The invention relates to a ReRAM device (1) having an electrode (4) which is embedded in a passivation structure (3) and is in the form of a fin which has a first metal and extends parallel to a plane of a substrate (2), a counter electrode (5) in the form of a layer which has a second metal and extends parallel to the plane of the substrate, and a metal oxide part (6) which has the first metal in oxidised form and which is located between the electrode and counter electrode, wherein the passivation structure (3) connects the electrode (4) to the counter electrode (5) and is arranged to block oxygen diffusion with respect to the metal oxide part (6). The invention also relates to a corresponding method for producing the ReRAM device.

Description

[0001] Description

[0002] RERAM DEVICE AND MANUFACTURING METHOD THEREFOR

[0003] TECHNICAL FIELD

[0004] The invention relates to a resistive random access memory device (ReRAM device) having the features of the preamble of claim 1 and a method for producing a ReRAM device.

[0005] The following background is intended only to provide information necessary to understand the context of the inventive ideas and concepts disclosed herein. Therefore, this background section may contain patentable subject matter and should not be considered prior art per se.

[0006] BACKGROUND

[0007] Resistive switching uses the programming of different resistance values ​​in a memory cell (resistive switching cell) as information storage. Voltage pulses are applied to a metal-insulator-metal (MIM) structure, whereby the resistance of the insulator (usually an oxide) can be repeatedly set to a conducting state or reset to a higher resistance state. Resistive switching cells are integrated into non-volatile memory devices and neuromorphic circuits for their synaptic behavior.

[0008] Conventional scaling techniques for resistive switching cells mostly involve nanoscaling of the metal electrodes without special consideration of the insulator.

[0009] Thus, there remains a need to expand the nanoscaling of ReRAM devices. In particular, the invention is based on the task of further developing ReRAM devices in terms of reliability and integration.

[0010] SUMMARY

[0011] This summary is intended to introduce a selection of features and concepts of the invention that are explained further in the description. This summary is not intended to identify important or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0012] According to the invention, the above-mentioned object is achieved by the features of the independent claims.

[0013] Specifically, this problem is solved by a resistive random access memory (ReRAM) device. The ReRAM device has a substrate. The substrate can be semiconducting and comprise, for example, a material such as silicon or germanium. The substrate can usually be coated with a thin layer of a dielectric material, such as silicon oxide, silicon nitride, or hafnium oxide. Thus, the ReRAM device has a passivation structure. The passivation structure is present at least on the substrate.

[0014] The ReRAM device has an electrode. The electrode is arranged on the substrate. Directly between the electrodes is a substrate-based insulating layer (also known as the passivation structure). The electrode is embedded in the passivation structure. Thus, the passivation structure can enclose the electrode on the bottom and wall sides. On the top side, the electrode can be partially covered with the passivation structure (adjacent to the metal oxide part, see below).

[0015] The electrode is in the shape of a fin. Here, the term fin is to be understood as an elongated yet narrow structure whose length is greater than its width and height. It can also be understood that it is an elongated shape with a narrow width compared to its length. In the longitudinal direction, the electrode can have elevations at regular intervals on a top side of the electrode (see below in conjunction with the metal oxide section). A bottom side of the electrode can be flat, for example, parallel to a top side of the substrate. The electrode has a first metal. Thus, the electrode can form one conductive element of the MIM structure of the ReRAM device. The electrode extends parallel to a plane of the substrate. Preferably, the electrode can extend along a first direction (X-direction). The first direction can coincide with the longitudinal axis of the electrode.

[0016] The ReRAM device has a counter electrode. The counter electrode is formed in the form of a layer. The counter electrode comprises a second metal. The second metal may be different from the first metal. Thus, the counter electrode may form the other conductive element of the MIM structure of the ReRAM device. The counter electrode extends parallel to the plane of the substrate, preferably along a second direction (Y direction) that differs from the first direction (orthogonal).

[0017] The ReRAM device has a metal oxide portion. The metal oxide portion comprises the first metal in oxidized form. The metal oxide portion may, in particular, have been formed from the electrode by oxidation. Thus, the metal oxide portion may form the insulating element of the MIM structure of the ReRAM device.

[0018] The metal oxide part can be in the form of a disk or column, or can be disk-like or columnar. In this case, a lateral dimension of the metal oxide part can be larger than a vertical dimension of the metal oxide part. A dimension of the metal oxide part in the second direction can correspond to a dimension of the electrode in the second direction. A dimension of the metal oxide part in the first direction can be much smaller than a dimension of the electrode in the first direction, for example, less than 0.1 times (or 0.05 times or 0.01 times). A height or dimension of the metal oxide part in the vertical direction (Z direction) can be less than 0.25 times (or 0.1 times) a height or dimension of the electrode in the vertical direction. The vertical direction can correspond to a third direction, wherein the first, second and third directions are perpendicular to one another. A respective dimension of the metal oxide part in the first, second and third directionsthird direction may be less than twice as large as a dimension of the metal oxide part in a corresponding other of the first, second or third directions.

[0019] The metal oxide portion is located between the electrode and the counter electrode. The metal oxide portion can also be referred to as the switching oxide portion. The metal oxide portion, the electrode, and the counter electrode together form a (particularly single) memory cell of the ReRAM device. This enables resistive switching of the ReRAM device. The metal oxide portion, the electrode, and the counter electrode together can form the MIM structure of the ReRAM device.

[0020] The passivation structure connects the electrode to the counterelectrode, preferably in a non-conductive (insulating) manner. The passivation structure is arranged to block oxygen diffusion relative to the metal oxide part, preferably independently of operation and / or completely. In particular, oxygen diffusion from the metal oxide part into the immediate surroundings can be prevented. Thus, the passivation structure can be designed and arranged relative to the electrode, the counterelectrode, and the metal oxide part in such a way that oxygen diffusion is limited.

[0021] The invention has the advantage that reliability can be achieved with higher integration density.

[0022] Advantageous embodiments of the invention are specified in the subclaims.

[0023] The metal oxide portion can be laterally delimited by the passivation structure. For example, the metal oxide portion can be directly and completely surrounded or encapsulated laterally by the passivation structure. Preferably, the metal oxide portion is delimited on both sides and in the second direction by the passivation structure.

[0024] Furthermore, the metal oxide portion can be delimited in the first direction by the passivation structure. In the vertical direction, in particular perpendicular to the plane of the substrate, the metal oxide portion can be delimited by the electrode and the counterelectrode. The metal oxide portion can also form a vertical spacer between the electrode and the counterelectrode. The metal oxide portion can fill a space between the passivation structure.

[0025] This allows the ReRAM device, especially the metal oxide part, to be better scaled and thus have higher electrical reliability.

[0026] The metal oxide portion can be delimited, in particular directly and completely, in the vertical direction perpendicular to the plane of the substrate by the passivation structure and the counterelectrode. For example, the passivation structure and the counterelectrode can delimit the metal oxide portion in the vertical direction perpendicular to the plane of the substrate. The passivation structure can completely and directly enclose the electrode, except for the metal oxide portion.

[0027] This allows for better control of the electrical state of the ReRAM device and improved reliability.

[0028] The first metal can be a transition metal, for example, one with a high affinity for oxygen. Examples of the first metal can be tantalum, hafnium, zirconium, titanium, or tungsten. The second metal can be a noble metal. For example, the second metal can be platinum, iridium, ruthenium, or titanium. The counter electrode can also be titanium nitride (an electrically conductive ceramic). The metal oxide part can be the appropriately oxidized form of the first metal, preferably tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or tungsten oxide. The passivation structure can be a dielectric, for example, a high-k dielectric with high electrical resistivity and good barrier properties against oxygen diffusion, in particular silicon nitride.

[0029] These facilitate the formation of the ReRAM device through known electrical and dielectric properties in processes.

[0030] The passivation structure can be essentially divided into three different passivation sections. Thus, the passivation structure can have a first, second, and third passivation section. The metal oxide portion can fill the space between the parallel first and second passivation sections, which preferably extend in the second direction. Thus, the first and second passivation sections can be arranged adjacent to each other in the first direction (with only the metal oxide portion between them).

[0031] The third passivation section can extend in the first direction, viewed section by section (relative to the (one) electrode). The third passivation section can surround the electrode in a U-shape, preferably viewed in cross-section in the first direction. In this case, the third passivation layer together with the first and / or second passivation layer can form a closed shape and encircle the electrode. The U-shape can form one of the aforementioned sections. Thus, several U-shapes can arise section by section (row by row) in the second direction. The U-shapes can extend along respective entire rows. A number of U-shapes can correspond to a number of rows (word lines). Each U-shape can extend across all columns (bit lines).

[0032] All three passivation sections can be arranged to suppress oxygen diffusion from the environment into the metal oxide part and the electrode and / or out of the metal oxide part.

[0033] Undersides of the first and second passivation sections and the counter electrode can each be in contact with corresponding sections of a top side of the metal oxide part. The metal oxide part can be flush with the electrode or embedded flush with the electrode.

[0034] Viewed in the cross-section of the ReRAM device, top surfaces of the passivation structure or of the first and second passivation sections may each be at the same height as or above a top surface of the metal oxide part. Thus, the top surfaces of the passivation structure or of the first and second passivation sections may each be in the same plane as or higher than the top surface of the metal oxide part in the vertical direction from the substrate. The bottom surfaces of the passivation structure or of the first and second passivation sections may each be lower in the vertical direction from the substrate than a bottom surface of the metal oxide part. For example, the height of the metal oxide part in the vertical direction from the substrate may be less than 0.25 times (or 0.1 times) the height of the passivation structure or of the respective first and second passivation sections.The height of the passivation structure, in particular of the first and second passivation sections, may be greater than the height of the metal oxide part.

[0035] Viewed in the cross-section of the ReRAM device, the undersides of the passivation structure or of the first and second passivation sections can each be located below the underside of the metal oxide part. Viewed in the cross-section of the ReRAM device, the undersides of the first and second passivation sections can also each be at the same height as the top side of the metal oxide part.

[0036] The electrode can be located below the counterelectrode in cross-section. The counterelectrode can rest flat on the first and second passivation sections and the metal oxide part, in particular directly. Likewise, an electrode terminal connected to the electrode (to be understood as an electrode connection), which serves to tap or apply current to the electrode, can be at the same height as the counterelectrode in the cross-section of the ReRAM device. The electrode terminal can rest on an end piece (front side in the X direction) of the electrode.

[0037] Consequently, the integration of the ReRAM device can be simplified.

[0038] The substrate can be semiconducting, for example, silicon-based. The passivation structure can also be semiconductor-based and represent an electrical insulation structure located between the electrode and the substrate.

[0039] The above-mentioned object is also achieved by a method for producing a resistive random access memory (ReRAM) device. The method comprises providing a substrate. The method comprises providing an electrode in the form of a fin and comprising a first metal on the substrate. The electrode extends parallel to a plane of the substrate. The method comprises providing a passivation structure on the electrode. The method comprises providing a metal oxide part with an oxidized form of the first metal between the electrode and a counter electrode, such that the metal oxide part, the electrode, and the counter electrode together form a memory cell of the ReRAM device. The method comprises providing, on the metal oxide part and the passivation structure, the counter electrode in the form of a layer and extending parallel to the plane of the substrate, comprising a second metal.The passivation structure connects the electrode to the counter electrode. The passivation structure is arranged to block oxygen diffusion relative to the metal oxide portion, preferably independently of operation and / or completely. Lateral and / or vertical oxygen diffusion can be prevented.

[0040] This allows reliability to be achieved with higher integration density.

[0041] Preferably, after providing the substrate, a first partial passivation structure can be provided. Preferably, after providing the first partial passivation structure, a first photoresist can be provided on the first partial passivation structure. Preferably, after providing the first photoresist, the first partial passivation structure can be etched according to the specification of the first photoresist in order to form a recess in the first partial passivation structure in the form of a well with substantially straight sidewalls. A bottom of the well can be spaced from the substrate (i.e., higher in the vertical direction than the substrate). Preferably, after etching the first partial passivation structure, the first photoresist on the first partial passivation structure can be removed.

[0042] This allows the sidewall technique (see below) to be prepared easily and effectively for the formation of a fin electrode (herein also called electrode fin).

[0043] The provision of the electrode can preferably be carried out after the removal of the first photoresist. The provision of the electrode can comprise depositing a surface electrode along a contour of the recess or on a surface of the first partial passivation structure present after the etching of the first partial passivation structure or after the removal of the first photoresist, while maintaining a low oxygen content, in particular under vacuum conditions. The provision of the electrode can further comprise, preferably after the deposition of the surface electrode, providing a second partial passivation structure on the deposited surface electrode while maintaining the low oxygen content, in particular under vacuum conditions.Providing the electrode may further comprise, preferably after providing the second partial passivation structure, planarizing at least up to an upper surface of the first partial passivation structure in order to expose at least a fin-forming portion of the deposited surface electrode laterally between the first and second partial passivation structures, or an upper surface of the fin. The exposed portion of the deposited surface electrode, which forms at least the fin, may be understood as the electrode.

[0044] This sidewall technology allows an effectively narrow width of the fin electrode to be achieved.

[0045] For example, after providing the electrode, the method may comprise sequentially applying a first hard mask and a second photoresist to the provided electrode to define a hard mask etch pattern for the provided electrode. For example, after the hard mask has been applied over the entire surface, the second photoresist may be applied over the entire surface. The second photoresist may then be exposed and developed locally at specific locations. Developing the photoresist may dissolve exposed (or unexposed) areas of the second photoresist, thereby creating a pattern in the resist. The hard mask etch pattern may then be provided by etching the first hard mask according to the patterned resist.

[0046] For example, after providing the electrode, preferably after applying the first hard mask and the second photoresist or after patterning the second photoresist and providing the hard mask etching structure, the method may comprise etching the electrode to a predetermined depth under oxygen deprivation, in accordance with the hard mask etching structure. For example, after providing the electrode, preferably after etching the electrode under oxygen deprivation, the method may comprise applying a third partial passivation structure to cover the hard mask etching structure and the etched electrode while maintaining the oxygen deprivation. For example, after providing the electrode, preferably after applying the third partial passivation structure, the method may comprise planarizing a plane resulting from the third partial passivation structure and the electrode.Alternatively or additionally, the planarization may be carried out at least up to the upper surfaces of the etched electrode or the aforementioned elevations of the electrode in order to expose the upper surfaces of the etched electrode or upper surfaces of the elevations of the etched electrode and to remove the first hard mask or the (remaining) hard mask etching structure.

[0047] This allows the offset technique to be prepared efficiently after the sidewall technique.

[0048] For example, after providing the electrode, preferably after planarizing the plane, the method may comprise providing pads of a second hard mask on top of the electrode in the longitudinal direction of the electrode. The pads may extend in the second direction and be shifted relative to the previously present hard mask etching structure of the first hard mask, preferably in the first direction. For example, after providing the electrode, preferably after providing the pads, the method may comprise in-situ etching under oxygen deprivation according to the specification of the second hard mask to produce elevations of the electrode or recesses in the electrode corresponding to the shift. The width of the electrode elevation in the first direction along the fin resulting after etching may be determined by the previously specified overlap (shift of the first and second masks relative to one another).

[0049] With this offset technique, overlaps can be set which can be manufactured more precisely than line widths. For example, after the electrode has been provided, preferably after in-situ etching, the passivation structure can be provided while maintaining the oxygen deficiency. The provision of the passivation structure can comprise providing a fourth partial passivation structure in order to surround the elevations of the electrode or to fill recesses in the electrode. The provision of the passivation structure can further comprise, preferably after the fourth partial passivation structure has been provided, planarization, in particular without oxygen deficiency, at least up to the upper surfaces of the electrode or the elevations of the electrode in order to planarize the upper surfaces of the electrode orExposing the top surfaces of the electrode bumps and removing the second hard mask, thereby forming a flat plane between alternately arranged (first and second) passivation sections of the passivation structure and electrode sections of the electrode. The electrode sections may be the sections that are oxidized and then form corresponding metal oxide parts.

[0050] In this way, the bottom-up technique can be effectively prepared, thus avoiding other procedures.

[0051] After providing the passivation structure, preferably after planarization up to at least the upper surface of the electrode or the elevations of the electrode, the metal oxide part can be provided by growing the metal oxide part using a bottom-up technique, such as thermal oxidation, oxidation in oxygen plasma, or area-selective deposition, on the upper side of the electrode exposed to air. After providing the metal oxide part, the counterelectrode can be provided by depositing the counterelectrode, preferably as the last or final step of the method. In particular, the deposition of the counterelectrode may not take place simultaneously with an electrode terminal provided for the electrode, but may comprise the same material. For example, the electrode and the counterelectrode can be provided from different metal deposition layers.The deposition of the electrode terminal on the electrode may involve a prior (reduced / shorter) in-situ etching step to remove the electrode oxide formed in ambient air and ensure good contact. The deposition of the counter electrode may, in particular, be performed without a prior in-situ etching step in order to retain the metal oxide portion beneath the counter electrode for electrical switching.

[0052] The above-mentioned object is also achieved by a computer program. The computer program comprises instructions which, when the computer program is executed by a computer, cause the computer or one or more special devices to carry out or initiate the method described above or at least one of the steps thereof. The computer program can, for example, be a module for starting / operating one of the special devices used to manufacture the ReRAM device described herein, such as production and deposition systems. The production and deposition systems can comprise deposition chamber(s), vacuum chamber(s), etching system(s) and / or coating machine(s), such as physical vapor deposition (PVD) system(s), chemical vapor deposition (CVD) system(s), sputtering system(s) and / or lithography system(s).

[0053] The above-mentioned task is also achieved by a data storage medium. The computer program can be stored on a machine-, processor-, or computer-readable storage medium, such as a permanent or rewritable storage medium. This also includes the possibility of making the computer program available for download on a server or a cloud server, e.g., via a data network such as the Internet or a communications connection such as a wireless connection.

[0054] In other words, the invention relates to a novel method for fabricating confined nano-oxide ReRAM devices. Confined explicitly means that the nano-oxide in the ReRAM device is confined to a space in all spatial directions.

[0055] In other words, a volume of the switching insulator (here: switching oxide or metal oxide part) can be confined in all three dimensions. This nanopillar structure can be contacted by electrodes on the top and bottom, while being enclosed on the sides by the passivation structure (diffusion barrier). The process can involve a combination of a sidewall technique with excellent tunability of the fin width, an offset technique with separate patterning steps to circumvent lithographic resolution limits, and / or thermal oxidation of the electrodes as a bottom-up technique for self-aligned oxide growth.

[0056] The sidewall technology can be implemented using an oxidizable material (Ta, Hf, Zr, etc.) that acts as an ohmic electrode in the resistive switching cell. The critical dimension of the sidewall electrode (herein also referred to as the area electrode) is not limited by lithographic resolution limits, as it is controlled by the film thickness during deposition of the electrode material. The electrode material can cover the entire trench (herein also referred to as the recess or well). To achieve favorable electrical properties, sputter deposition can be used at an angle that leads to an asymmetric growth rate on vertical and horizontal surfaces. A thick electrode layer on the horizontal trench floor can increase conductivity, while a thin layer on the trench walls scales the lateral dimension of the memory cell.For example, the trench can be etched into silicon nitride as a passivation structure and filled with silicon nitride after electrode deposition to encapsulate the ohmic electrode fin with a passivating material. The oxidizable electrode is covered in situ (without breaking the vacuum) to prevent the growth of native oxide.

[0057] With the offset technique, silicon nitride passivation pads offset by a few predefined nanometers can be used with two separate exposures for a memory cell, thus circumventing the lithographic resolution limit. The size of the passivation pads can also be outside the nanoscale range in this process, yet still achieve a nanoscale gap through controlled offset of the aligned pads. This allows the resolution limitation to be shifted from linewidth scaling to line edge roughness and overlay performance. This can lead to better control over the dimensions.

[0058] The deposition of, for example, silicon nitride as passivation pads can be preceded by an in-situ etching step to remove the native oxide formation of the exposed electrode fin after the CMP process. These offset passivation pads with in-situ etching can form a nano-pillar and encapsulate it within the fin electrode, whereby the in-situ etch depth can define the height of the nano-pillar. The lateral dimensions of the oxide can thus be defined by the offset of the passivation pads in one dimension (X-direction) and by the thickness of the electrode fin(s) in the other dimension (Y-direction). Both processes are not restricted by lithographic resolution limits.

[0059] These process steps leave only a small nano-column of the oxidizable electrode exposed on the surface. A bottom-up technique such as thermal oxidation or oxygen plasma treatment can then be used for local, self-aligned oxide growth on the exposed nano-column. By varying process parameters such as temperature or heat treatment time, the Z-direction thickness and stoichiometry of the oxide are controlled, while the lateral dimensions of the nano-column can remain limited by the passivating silicon nitride as an example of the passivation structure. The resulting oxide can then be used for resistive switching without the need for subsequent or further detrimental etching processes that can lead to deoxidation.

[0060] The result of the combination of the above-mentioned process techniques can be a laterally confined nano-pillar with a controlled oxide volume for resistive switching, encapsulated by passivating silicon nitride.

[0061] The electrode can have a width of less than 20 nm (or 15 nm or 10 nm). This could result in improvements in the reliability, retention, and variability of the memory cells, which explicitly arise from the smaller scaling of the oxide volume in the nano-pillar structure of the switching insulator described here.

[0062] The process concept described here, for example, differs from previous approaches because it allows the switching oxide volume to be scaled laterally to approximate the filament size. The passivation structure, for example, encapsulates the oxide nanopillar to prevent oxygen diffusion into the memory cell.

[0063] The filament sizes can be smaller than known lithographic resolution limits. With the present method, the switching oxide volume of the ReRAM device, for example, can be unconstrained by the lithographic resolution limits of currently achievable linewidths. This can be achieved by leveraging knowledge of well-controllable layer thickness, low edge roughness, and good overlay performance to overcome the resolution limitation in linewidth scaling and achieve better dimensional control.

[0064] Locally increased oxygen vacancies can form a filament upon application of a voltage between the electrode and counter electrode, determining the resistive state of the oxide. This filament can be susceptible to oxygen diffusion due to recombination with the oxygen vacancies, resulting in a change in resistive state. Small changes in the local oxygen vacancy concentration can lead to large resistive state changes. By reducing the switching oxide to filament size, the filament environment consists of a passivation structure instead of more oxide volume. Defects in the larger surrounding oxide volume can cause harmful free oxygen to diffuse into the filament.The nano-pillar design of the switching oxide described herein can therefore lead to a more stable filament by directly encapsulating the filament with a passivation structure, thus reducing the reliability and retention issues in ReRAM devices.

[0065] Furthermore, rather than further increasing the filament diameter, geometrically confining filament growth can lead to higher oxygen vacancy concentrations being achieved for given resistance states. Higher oxygen vacancy concentrations correlate with lower variability of the programmed resistance state. The increased oxygen vacancy concentration in confined cells or in confined switching oxides can reduce the variability of the memory cells for a given resistance state compared to larger, unconfined filaments with lower oxygen vacancy concentrations.

[0066] Since high variability and low reliability (limited retention of a specific state) are among the major drawbacks of ReRAM devices, limiting their large-scale deployment, it is important to be able to control these effects. However, scaling the oxide volume to small filament sizes is beyond the limits of conventional lithographic resolution. These limitations can be circumvented with the measures mentioned above.

[0067] The cell size is traditionally defined by the electrode overlap, independent of the oxide dimensions. However, the above-mentioned measures allow not only scaling of the electrodes (electrode and counter electrode), but also scaling of the oxide, particularly laterally and vertically by the electrodes.

[0068] In general, lithography offers the greatest flexibility, but scaling the oxide to a filament size smaller than approximately 10nm in diameter is beyond the limits of optical lithography and electron beam lithography (EBL). The oxide beneath the top electrode (counter electrode) can be scaled in more than one dimension. Sidewall technology can be used for excellent scalability, as the removed layer thickness defines the lateral feature size, which can be easily controlled even in the low nm range. The oxide volume can then be nanostructured.

[0069] This may eliminate techniques such as pillar etching, via etching, and / or top-down technologies, which have poorer scalability than the methods mentioned above. Reducing oxide damage by etching the switching oxide and encapsulating it with a passivation structure may lead to more reliable resistive switching. Lateral passivation may be provided after the process for fabricating the ReRAM device to limit oxygen diffusion into the filament. Thus, a method for scaling the switching oxide volume to the filament size may be provided. The method may provide that the volume of the switching oxide is confined in all three dimensions. The scalability of this method may enable the production of oxide volumes on the order of a filament.This nano-pillar structure of the switching oxide can be contacted by electrodes on the top and bottom, while it is encapsulated on all four sides by a passivation structure.

[0070] The techniques described herein can achieve extreme scalability of the switching oxide volume by circumventing conventional lithographic resolution limits. The resulting nanopillar of switching oxide can be encapsulated by the passivation structure, which limits oxygen diffusion into the switching oxide filament. The switching oxide can be formed locally within the nanopillar using bottom-up techniques, without the need for subsequent damaging etching techniques. The encapsulation and geometric confinement of the filament within the nanopillar can offer advantages in terms of variability and reliability.

[0071] Although some of the aspects described above relate to the ReRAM device or the method of manufacturing the ReRAM device, these aspects may also apply to the other aspects thereof in a corresponding manner.

[0072] All technical and scientific terms used herein have the meaning commonly understood by those skilled in the art in the technical field of information storage technology. They are to be interpreted based on the definitions found in the dictionary or the technical jargon of that technical field. If technical terms are used incorrectly and thus do not express the technical spirit of the present invention, they shall be replaced by technical terms that convey a correct understanding to those skilled in the art.

[0073] The terms "first" and "second" are merely intended to distinguish components from one another. For example, a first component can be referred to as the second component, and a second component as the first component. It should be noted that these terms, as well as all numerical designations ("one," "two," etc.), are not intended to be exhaustive with regard to the scope of protection, but are also exhaustive with regard to the disclosure content. For example, the expression "two ABC" can mean either "exactly two ABC" or "two or more ABC."

[0074] If it is stated here that a component is "connected" to another component, this may mean, for the purposes of this disclosure, that these components may also be directly connected to each other or able to communicate. The terms "direct" or "immediate" indicate that no further component is present between them.

[0075] The process steps described herein should not be interpreted as requiring them to be performed in a particular order, unless expressly or implicitly stated otherwise, for example, if these process steps cannot be interchanged for technical reasons. The process steps may also be performed directly one after the other (without any further intervening steps) and / or continuously.

[0076] BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Further objects, features, advantages, and possible applications will become apparent from the following description of non-limiting embodiments with reference to the accompanying drawings. The same or similar elements in the drawings are always provided with the same or similar reference numerals. Detailed explanations of well-known functions and structures are omitted where they would detract from the scope of the invention.

[0078] The drawings show in:

[0079] Fig. 1 is a schematic diagram of a ReRAM device;

[0080] Fig. 2A-2B show cross-sectional views of memory cells of a ReRAM device; Fig. 3 shows a schematic representation of a method for manufacturing the ReRAM device according to Fig. 1 or Fig. 2A and 2B;

[0081] Fig. 4A-7D are schematic representations of process sequences according to the method of Fig. 3; and

[0082] Fig. 8 is a schematic representation of a computer for use in the method according to Fig. 3.

[0083] DETAILED DESCRIPTION

[0084] The ReRAM device 1 and the method 50 for manufacturing the ReRAM device 1 will now be described with reference to the embodiments. Without being limited thereto, specific details are explained to provide a deeper understanding of the invention.

[0085] In addition, spatially relative descriptors such as "below," "under," "beneath," "bottom," "above," "upper," "above," "top," "left," "right," "front," "back," and the like may be used herein to conveniently describe the relationship of elements illustrated in the drawings to one another. The spatially relative descriptors are intended to additionally encompass other orientations of the device in use or operation. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly. The correspondingly indicated X, Y, and Z directions correspond to first, second, and third directions, respectively, and are used mutatis mutandis in the drawings.

[0086] Fig. 1 shows a schematic representation of a ReRAM device 1. Here, the entire arrangement or an individual memory cell of this arrangement can be referred to as a ReRAM device 1. The ReRAM device 1 has a substrate 2 located beneath the passivation structure 3 (not shown in Fig. 1). Specifically, the substrate 2 can be considered the underside of the ReRAM device 1 and coated on one side such that the terms "top," "above," "upper surface," "higher," etc., are to be understood as the direction pointing away from the substrate 2. Located above the substrate 2 is the passivation structure 3, into which a plurality of fin-shaped, elongated electrodes 4 extending in the X direction are embedded. The part of the passivation structure 3 that embeds the electrodes 4 can be referred to as the third passivation section 3-3 (see Figs. 2A and 2B).The electrodes 4 extend parallel to one another in the X direction and are adjacent to one another in the Y direction at a first predetermined distance (e.g., in a range from 20 nm to 100 nm). The passivation structure 3 further has first and second passivation sections 3-1 and 3-2 extending in the Y direction and running parallel, which are each adjacent to one another at a second predetermined distance (e.g., in a range from 5 nm to 15 nm). The second predetermined distance can be determined by the metal oxide parts 6 formed therebetween on the respective electrode sections of the electrode 4. The surfaces of the metal oxide parts 6, the first, second, and / or third passivation sections 3-1, 3-2, 3-3, and the electrode 4 can be substantially planar. The first and second passivation sections 3-1 and 3-2 can be partially embedded in the electrode 4. On the, for example,The counterelectrodes 5 can be applied to a flat surface. The counterelectrodes 5 extend parallel to one another in the Y direction and are each spaced apart from one another by a third predetermined distance (e.g., in a range of 10 nm to 50 nm). Corresponding electrode terminals 7 can be applied to respective end pieces of the electrodes 4. In particular, the counterelectrode 5 and the electrode terminals 7 can be based on the same metal layer, for example, comprise the same material, but be manufactured in separate and / or sequentially performed process steps. Note that the distances between the corresponding (periodically arranged) elements, in particular the first, second, and / or third distances, are regular or uniform.

[0087] 2A and 2B show corresponding ReRAM devices 1, each comprising: a substrate 2, a passivation structure 3 comprising first, second, and third passivation sections 3-1, 3-2, and 3-3, an electrode 4, a counter electrode 5, a metal oxide part 6, and an electrode terminal 7. The structures and properties illustrated and described with reference to FIGS. 2A and 2B can, of course, also apply to the ReRAM device 1 of FIG. 1. Thus, the elements illustrated in detail can, of course, be implemented in the majority thereof according to FIG. 1, but are not limited to the majority thereof herein.

[0088] In Fig. 2A and 2B, a ReRAM device 1 is shown. In both cases of Fig. 2A and 2B, the ReRAM device 1 has a substrate, a

[0089] Passivation structure comprising a first, second and third

[0090] passivation section, an electrode 4, a counter electrode 5, a metal oxide part 6 and an electrode terminal 7.

[0091] In Fig. 2A and 2B, the underside of the ReRAM device 1 is formed by the substrate 2. The third passivation section 3-3 of the passivation structure 3 is located above the substrate 2. The electrode 4 is embedded in (the third passivation section 3-3) of the passivation structure 3. The electrode extends in the form of an elongated cuboid fin in the X direction. The cuboid shape can predetermine the U-shape of the passivation section 3-3. The first and second passivation sections 3-1 and 3-2 of the passivation structure 3 each extend in the form of elongated cuboid bars in the Y direction. The first, second, and third passivation sections can form a single, contiguous space.

[0092] The key difference between the ReRAM device 1 of Fig. 2A and 2B lies in the arrangement of the metal oxide 6 relative to the passivation sections 3-1 and 3-2. The different structures are described in layers below.

[0093] In Fig. 2A, the upper surface of the substrate 2 lies in a first plane, which coincides with the lower surface of the third passivation section 3-3. The lower surface of the electrode 4 lies in a second plane, above the first plane. An upper (intermediate) surface of the third passivation section 3-3, which is located between the uppermost surface and the lower surface of the third passivation section 3-3, also lies in the second plane. The uppermost surfaces of the first, second, and third passivation sections 3-1, 3-2, and 3-3 and the respective uppermost surfaces of the electrode 4 and the metal oxide 6 lie in a third plane, above the second plane. The lower surfaces of the counter electrode 5 and the electrode terminal 7 also lie in the third plane. The upper surfaces of the counter electrode 5 and the electrode terminal 7 may lie in a fourth plane, above the third plane.The lower surface of the metal oxide part 6 lies in a fifth plane, below the third plane. The lower surfaces of the first and second passivation sections 3-1 and 3-2 lie in a sixth plane, below the fifth plane and above the second plane.

[0094] In Fig. 2B, the upper surface of the substrate 2 lies in a first plane, which coincides with the lower surface of the third passivation section 3-3. The lower surface of the electrode 4 lies in a second plane, above the first plane. An upper (intermediate) surface of the third passivation section 3-3, which is located between the uppermost surface and the lower surface of the third passivation section 3-3, also lies in the second plane. The upper surface of the third passivation section 3-3, the upper surface of the electrode 4, and the upper surface of the metal oxide 6 lie in a third plane, above the second plane. The respective lower surfaces of the first and second passivation sections 3-1 and 3-2, the lower surface of the counter electrode 5, and the lower surface of the electrode terminal 7 also lie in the third plane.The upper surface of the electrode terminal 7 lies in a fourth plane, above the third plane. The respective upper surfaces of the first and second passivation sections 3-1 and 3-2 lie in a fifth plane, above the fourth plane. The upper surface of the counter electrode 5 lies in a sixth plane, above the fifth plane. The metal oxide part lies between the second plane and the third plane. In particular, a lowermost surface of the metal oxide part 6 lies in a seventh plane, below the third plane and above the second plane.

[0095] The manufacture of the ReRAM device 1 shown in Fig. 1 or Fig. 2A and 2B is shown in an abstracted and simplified manner in Fig. 3 and in a specific process sequence in Figs. 4A to 7D.

[0096] Fig. 3 shows a schematic representation of the method SO for producing the ReRAM device 1 in the sense of Fig. 1 or Fig. 2A and 2B. Expressed in abstract and simplified terms, the method SO comprises the method steps S1 to S5, for example, in exactly this order. In S1, the substrate 2 is provided. In S2, the fin-shaped electrode 4 is provided on the substrate 2, which electrode comprises the first metal and extends parallel to the substrate plane. In S3, the passivation structure 3 is provided on the electrode 4. A part of the final passivation structure 3 is of course already provided above the substrate before the provision S2 of the electrode.In S4, the metal oxide part 6 (oxidized form of the first metal) is provided between the electrode 4 and the counter electrode 5, so that the three structural elements—metal oxide part 6, electrode 4, and counter electrode 5—together form a common memory cell of the ReRAM device 1. In S5, the counter electrode 5, formed in a layered form and extending parallel to the plane of the substrate 2 and comprising the second metal, is provided on the metal oxide part 6 and on the passivation structure 3. The passivation structure 3 connects the electrode 4 to the counter electrode 5 and blocks oxygen diffusion relative to the metal oxide part 6, regardless of the operating mode of the ReRAM device 1.

[0097] The method steps illustrated as blocks of the block diagram in Fig. 3 may, for example, be substantially embodied in a machine-, processor-, or computer-readable medium and thus executed by a computer 10 or processor 11, as described below with reference to Fig. 8. Examples may further be or refer to a computer program containing program code for executing at least some of the method steps of Fig. 3 when the computer program is executed on the computer 10 or processor 11. An example may also include a volatile memory 12 or persistent memory 13, as also described below with reference to Fig. 8, which is machine-, processor-, or computer-readable and encodes machine-executable, processor-executable, or computer-executable programs with instructions that cause some or all of the method steps to be executed.

[0098] Figs. 4A-7D show schematic representations of the process sequences in the sense of the process 50 according to Fig. 3, but in a more specific form. Further below, it is described how the use of the computer 10 can be used in the manufacture of the ReRAM device 1.

[0099] Fig. 4A shows the intermediate step A1 of the process sequence. Here, an insulating and oxidation-resistant silicon nitride is applied as a partial passivation structure 3, in particular as a diffusion barrier for oxygen, to a silicon wafer as substrate 2. For example, 200 nm of silicon nitride is applied to a 4-inch, 8-inch, or 12-inch silicon wafer using plasma-enhanced chemical vapor deposition (PECVD).

[0100] The following process flow can be used for PECVD. First, the substrate 2 is cleaned to remove any contaminants that could interfere with the deposition process. The substrate 2 is then loaded into the deposition chamber, which is typically made of quartz or stainless steel. The substrate 2 is then heated to a temperature between 200-400°C to prepare it for deposition. A gas mixture containing silane (SiH4), ammonia (NH3), and / or nitrogen (N2) is introduced into the deposition chamber. The gas mixture is then ionized using a plasma source. The ionized gas reacts on the surface of the substrate 2, forming a thin film of silicon nitride. The deposited partial passivation structure 3 is then annealed at high temperature to improve its electrical and mechanical properties.

[0101] Next, an etching mask is applied using optical lithography—here, photoresist 8 with a gap of, for example, 2 μm—to etch a recess, well, or trench into the partial passivation structure 3. The gap can also be smaller than 300 nm (or 200 nm or 100 nm). For example, the gap can also be larger than 50 nm (or 75 nm or 100 nm). The etching mask is a type of photomask used for patterning processes such as etching and deposition. The etching mask is typically made of a material that is resistant to the etching process and can withstand the conditions during etching, such as high temperatures and harsh chemicals.

[0102] The following process flow can be used in optical lithography to provide the photoresist 8. A resist is applied to the partial passivation structure 3 using a coating machine. The coating machine typically uses turntable or spin coater technology to create a uniform layer of resist on the substrate. The entire structure can then be heated to a specific temperature for a short time (also called a soft bake) to dry and cure the resist. A photomask is projected onto the applied resist, altering exposed areas to create the desired pattern. The exposed parts of the resist can then be removed in a developer bath (in the case of positive resist) to leave the desired photoresist 8.The developed photoresist 8 may be further heated for a certain time at a higher temperature than the softbake (also called hardbake) to harden the photoresist 8 and improve its chemical and physical properties.

[0103] Fig. 4B shows intermediate step A2 of the process sequence. Here, the partial passivation structure 3 is etched anisotropically by reactive ion etching (RIE). RIE utilizes chemical reactions between a gas and the partial passivation structure 3 to etch it specifically according to the photoresist 8. The goal of this intermediate step A2 is to achieve a substantially vertical sidewall angle for the deposition of the surface electrode. In a specific example, the recess can have a depth in the range of 50 nm to 100 nm (e.g., 65 nm) and a width of 1 pm to 3 pm (e.g., 2 pm). The use of such recesses instead of pillars enables the use of the aforementioned sidewall technology, better visual depth control during planarization with chemical mechanical polishing (CMP - see below) within a few nm, and electrical isolation of the components from one another after CMP.

[0104] The following process flow can be used for RIE. The process begins with the placement of the Al structure in a vacuum chamber. A fluorine-based gas (e.g., Fluoroform CHF3) is introduced into the vacuum chamber and ionized to generate a plasma discharge. The ions are then directed at the material of the partial passivation structure 3, ablating the surface of the material. RIE differs from other etching methods in the use of reactive gases that react with the material (here, for example, SiN) to produce a specific etching behavior. The gas is typically selected to react only with the material to be etched and not with other nearby materials to ensure precise patterning.RLE has the advantage of being able to produce very precise and uniform etching patterns, and it is also very effective in etching materials that are difficult to process using other methods, such as dense silicon nitride layers or metallic layers. Fig. 4C shows the intermediate step A3 of the process sequence, in which the recess is filled with the surface electrode 4, and the recess covered by the surface electrode 4 is filled with a second partial passivation structure 3, for example, SiN.

[0105] Here, the recess is first sputtered with a thin layer of ohmic electrode material, for example tantalum (the surface electrode 4), onto the first etched partial passivation structure 3, which has a stepped shape due to the recess. During sputtering, a plasma discharge is used to release atoms or ions from a target material and transfer them to the first partial passivation structure 3. The target material is surrounded by a gas stream. The gas is ionized and forms a plasma that bombards the target material and releases the atoms. These atoms are then applied to the first partial passivation structure 3 in an oxygen-deficient environment, forming a thin layer. This has the advantage that a wide range of materials can be applied with high layer quality and density, as well as excellent adhesion between the ohmic electrode material and the first partial passivation structure 3.The final fin width of electrode 4 can be easily scaled by adjusting the sputtering time based on the layer thickness of the area electrode 4. This means there is no limitation imposed by the lithography resolution. The only major limitations are the layer continuity and the layer resistance of the area electrode 4.

[0106] After sputtering, the surface electrode 4 is covered with the second partial passivation structure 3, which is deposited in-situ to prevent oxidation of the surface electrode 4, while maintaining the oxygen deficiency. Similar to the method described above for Al, the second partial passivation structure 3 is again deposited, for example, using PECVD. In this case, at least the space of the recess is filled with the second partial passivation structure 3, in particular SiN.

[0107] 5A and 5B show the same intermediate step A4 of the process sequence in different views A4a and A4b. A first CMP planarization is used here. Here, an upper surface of the second partial passivation structure 3 is planarized until at least the electrode fin 4, with fin orientation in the Z direction and extension in the X direction, is at least superficially exposed. As a result of the first CMP planarization, an upper surface of the electrode fin 4 is planar with the first and second partial passivation structures 3. During the first CMP planarization, the wafer (here elements 2, 3 and 4) is placed on a polishing table. The polishing table supports the wafer and a polishing disk is pressed onto the wafer while rotating. A polishing fluid that has both chemical and mechanical properties is applied to the surface of the wafer (here second partial passivation structure 3) in order to evenly remove the material.During the first CMP planarization, the second partial passivation structure 3 is removed by a combination of chemical and mechanical forces. The polishing fluid contains abrasive materials such as silicon dioxide or aluminum oxide, which abrade the surface of the second partial passivation structure 3 (during the course of the first CMP planarization, also the surface electrode 4 and, for example, a small portion of the first partial passivation structure 3) and simultaneously remove material from it through possible chemical reactions with the surface. CMP planarization generally offers the advantage of creating surfaces with very low roughness, ensuring low variability of the switching elements and a smooth interface for subsequent processes. The result can be highly reproducible while simultaneously achieving high throughput.

[0108] Fig. 5C shows intermediate step A5 of the process sequence. A first hard mask 9, together with a second, particularly structured (to specify the etching structure), photoresist 8, is lithographically applied at least to the electrode fin 4 produced in intermediate step A4. In intermediate step A6, a pattern to be etched is etched into the first hard mask 9 according to the second photoresist 8 (see Fig. 5C), which pattern remains as the target hard mask 9 (see Fig. 6A). In intermediate step A7 (see Fig. 6B), recesses are created in the fin electrode 4 at predetermined intervals (pitches) according to the target hard mask 9 by etching under oxygen deprivation. These recesses are introduced regularly or periodically in the longitudinal direction of the electrode fin 4. In-situ, while maintaining the oxygen deficiency, a third partial passivation structure 3 is then applied by PECVD to the entire surface, at least in the recesses of the surface electrode 4 and on the target hard mask 9.In intermediate step A8 (see Fig. 6C), a second CMP planarization is performed. During this step, an upper surface of the third partial passivation structure 3 is planarized until at least the uppermost surfaces of the electrode fin 4 are at least superficially exposed. As a result of the second CMP planarization, the uppermost surfaces of the electrode fin 4 are flush with the third partial passivation structure 3. During the second CMP planarization, the wafer (here elements 2, 3, 4, and 9—shown without substrate 2 in Fig. 6B for simplicity) is placed on the polishing table. The polishing table supports the wafer, and the polishing disk is pressed onto the wafer while rotating. The polishing fluid is applied to the surface of the wafer (here third partial passivation structure 3) to evenly remove the material.During the second CMP planarization, the third partial passivation structure 3 is removed using the same combination of chemical and mechanical forces as during the first CMP planarization. The polishing fluid abrades the surface of the third partial passivation structure 3 (during the course of the second CMP planarization, also the target hard mask 9 and, for example, a small portion of the surface electrode 4) and simultaneously removes material from it through possible chemical reactions with the surface. What remains is a flat plane between the uppermost surfaces of the surface electrode 4 and sections of the third partial passivation structure 3 deposited in the recesses of the surface electrode 4.

[0109] Fig. 6D shows intermediate step A9 of the process sequence, in which the offset technique is applied. A second hard mask 9, offset from the first hard mask, is lithographically deposited as offset pads onto the planar surface provided in A8. Equal spacing can be used for the first and second hard masks 9, with the first and second hard masks 9 being offset relative to one another. Not only are the pads of the second hard mask extending in the Y direction offset from one another in the X direction, but their overlap with the elevations complementary to the recesses of the surface electrode 4 is also offset, so that the elevations can be etched away according to the specifications of the second hard mask 9.

[0110] Fig. 7A shows the intermediate step A10 of the process sequence. Here, etching was already performed according to the specifications of the second hard mask 9, and a fourth partial passivation structure 3 was applied in-situ under oxygen-deficient conditions over the entire surface, at least in the further etched recesses of the surface electrode 4 and on the second hard mask 9, using PECVD.

[0111] Fig. 7B shows the intermediate step A1 1 of the process sequence, in which a third CMP planarization was performed and the first and second passivation sections 3-1 and 3-2 of the passivation structure 3 described herein remain between narrowly etched elevations of the surface electrode 4. During the third CMP planarization, an upper surface of the fourth partial passivation structure 3 is planarized until at least the uppermost surfaces of the electrode fin 4 are again exposed, at least superficially. As a result of the third CMP planarization, the uppermost surfaces of the electrode fin 4 are flush with the third and fourth partial passivation structures 3. During the third CMP planarization, the wafer (here elements 2, 3, 4, and 9—shown without substrate 2 in Fig. 7A for the sake of simplicity) is placed on the polishing table. The polishing table supports the wafer, and the polishing disk is pressed onto the wafer while rotating.The polishing fluid is applied to the surface of the wafer (here, the third and fourth partial passivation structures 3) to evenly remove the material. During the third CMP planarization, the third and fourth partial passivation structures 3 are removed using the same combination of chemical and mechanical forces as during the first and second CMP planarization. The polishing fluid abrades the surface of the third and fourth partial passivation structures 3 (during the course of the third CMP planarization, also the second hard mask 9 and, for example, a small portion of the etched elevations of the surface electrode 4) and simultaneously removes material from it through possible chemical reactions with the surface. What remains is a flat plane between the uppermost surfaces of the etched elevations of the surface electrode 4 and the third and fourth partial passivation structures 3 remaining between these etched elevations.

[0112] Fig. 7C shows the intermediate step A12 of the process sequence, which illustrates the bottom-up technique. Here, an electrode oxide based on the material of the electrode fin 4 is formed on the wafer in air or with additional thermal and oxidative support. This electrode oxide then forms the final metal oxide part 6 on the uppermost surfaces of the final electrode 4. The uppermost surfaces of the remaining, periodically, regularly, and / or uniformly arranged passivation sections 3-1 and 3-2 can then be flush with the uppermost surfaces of the metal oxide parts 6, which are also periodically, regularly, and / or uniformly arranged in the longitudinal direction of the electrode 4.

[0113] Finally, a counterelectrode 5 is deposited on the metal oxide parts 6 (see intermediate step Al 3 in Fig. 7D). The deposition of the counterelectrode 5 can also be carried out by sputtering, as described above. The deposition of the electrode terminal 7 can be carried out before the deposition of the counterelectrode 5, in particular before the provision of the metal oxide part. This can prevent oxidation at the electrode 4. The counterelectrode 5 extends in the same direction as the first and second passivation sections 3-1 and 3-2 and is arranged offset therefrom in order to connect them as well as the metal oxide part 6.

[0114] This may be the final essential step in the production of a fully functioning ReR AM device 1. Computer-assisted methods and means may be used during production. Computer 10 from Fig. 8, which will be discussed below, is also used for this purpose.

[0115] Fig. 8 schematically shows a block diagram of a computer 10, which may, for example, be part of the production and deposition systems for manufacturing the ReRAM device 1. The computer 10 may describe one or more parts of the production and deposition systems, including deposition chamber(s), vacuum chamber(s), etching system(s), and / or coating machine(s), such as PVD system(s), CVD system(s), sputtering system(s), and / or lithography system(s).

[0116] The computer 10 implements one or more steps of the method SO, as shown in Fig. 3. In particular, the computer 10 provides functionality, such as computer software, that runs on the computer 10 and performs one or more steps of the method SO. In particular, the computer 10 can execute instructions related to circuit data that are contained in the computer program described herein and cause the computer 10 to perform the one or more steps of the method SO. The circuit data described herein can be compact input data and can specifically include one or more of the following, in particular time-resolved, data or information: materials, layer thicknesses, line widths, electric fields, geometry, temperatures, gas composition, pressures, exposure times, and etching methods. These elements are referred to below as compact data.

[0117] It is contemplated herein that computer 10 may take any suitable physical form. By way of example, computer 10 may be embodied at least in part as an embedded computer, system-on-chip (SOC), single-board computer (SBC), server, and / or user equipment (UE). Computer 10 may be unified or distributed; span one or more locations; span one or more machines or data centers; or be located in a cloud, which may include cloud components in a network. Computer 10 may perform one or more steps of method SO without substantial spatial or temporal limitation. By way of example, computer 10 may perform one or more steps of method SO in real time, in parallel, or in batch mode. Computer 10 may perform step(s) of method SO at different times or at different locations.

[0118] Computer 10 includes at least one or more of the following components: a processor 11, a volatile memory 12, a persistent memory 13, a bus 14, an arbiter 15, a communications interface 16, a main power supply 17, and an auxiliary power supply 18. The components of computer 10 may be implemented, at least partially, in hardware and / or software. The interconnection of the components of computer 10 is structured as shown in Fig. 8 merely for the sake of simplicity. In particular, the interconnection and connection may differ in implementation due to signal processing and signaling.

[0119] The processor 11 has means for executing instructions associated with the compact data, e.g., of the computer program described herein. For example, the processor 11 may load the instructions associated with the compact data contained in the computer program described herein, e.g., from the volatile memory 12 and / or the persistent memory 13, and then execute the instructions, which in turn causes the processor 11 to perform the one or more steps of the method 50, as illustrated, e.g., in Fig. 3. The processor 11 may have an internal register / cache for the compact data, for the instructions associated with the compact data, and / or for associated addresses. The processor 11 may have an FPGA, ASIC, DSP, microcontroller, a CPU, and / or GPU for accessing the internal register / cache.As an example, to execute instructions related to the compact data, processor 11 may fetch the compact data from processor 11's internal register / cache, volatile memory 12, or persistent storage 13; decrypt and execute the data; and then write a result to processor 11's internal register / cache, volatile memory 12, or persistent storage 13.

[0120] As an example, processor 11 may include an instruction cache, a data cache, and / or a translation buffer (TLB). The compact data-related instructions in the instruction cache may be copies of instructions in volatile memory 12 and / or persistent storage 13, and the instruction cache may accelerate the fetching of these compact data-related instructions by processor 11. The compact data in the data cache may be copies of data for the compact data-related instructions currently executing on processor 11 in volatile memory 12 and / or persistent storage 13. The results of previous compact data-related instructions executing on processor 11 may be scheduled for access by subsequent compact data-related instructions to be executed on processor 11, or for writing to volatile memory 12 and / or persistent storage 13.The data cache can accelerate the read or write operations of processor 11. The addresses associated with the compact data in the TLB can be address references to addresses in volatile memory 12 and / or persistent storage 13 to accelerate virtual address translation for processor 11.

[0121] The volatile memory 12 may be a dynamic RAM (DRAM) or a static RAM (SRAM). The volatile memory 12 may, in particular, be embodied as the data storage medium described herein, on which the computer program described herein may be at least temporarily stored. Furthermore, the volatile memory 12 may be a single-channel or multi-channel RAM. The volatile memory 12 may include a main memory for storing instructions related to the compact data for the processor 11, which then executes these instructions; or include the compact data for the processor 11, which the processor 11 uses to operate on it. For example, the computer 10 may load these instructions into the volatile memory 12 from the persistent memory 13 or another source (such as another computer, the network, or the cloud).Processor 11 can then load these instructions from volatile memory 12 into the internal register / cache of processor 11. To execute these instructions, processor 11 can retrieve and decrypt these instructions from the corresponding internal register / cache. During or after executing these instructions, processor 11 can write a result (which can be intermediate or final results) to the internal register / cache. Processor 11 can then write the result to volatile memory 12.

[0122] For example, processor 11 executes only instructions related to the compact data in processor 11's internal register / cache or volatile memory 12 (as opposed to persistent memory 13), and operates only on the compact data in processor 11's internal register / cache or volatile memory 12 (as opposed to persistent memory 13).

[0123] The persistent memory 13 has a mass storage device, e.g., a non-volatile mass storage device (NVM), for the compact data or the instructions associated with the compact data. The persistent memory 13 can, in particular, be embodied as the data storage device described herein, on which the computer program described herein can be stored. As an example, the persistent memory 13 can be a flash memory, in particular an SSD or eMMC. The persistent memory 13 can store the compact data in an erasable or non-erasable manner. The persistent memory 13 can be located in the computer 10, i.e., internally, or externally.

[0124] The processor 11 can be connected to the persistent memory 13 directly or indirectly, e.g., via the arbiter 15. The connection can be implemented via a clock bus, command bus, and data bus. This is shown only schematically using bus 14 in Fig. 8. The persistent memory 13 receives commands associated with the compact data and the compact data in conjunction with a clock signal provided by the processor 11 on the clock bus. The clock signal clocks the reception of the commands associated with the compact data and the compact data. The processor 11 sends a command associated with the compact data to the persistent memory 13 via the command bus. Furthermore, the processor 11 sends the compact data to the persistent memory 13 via the data bus in accordance with the command or receives the compact data from the persistent memory 13 via the data bus.

[0125] Bus 14 can be understood herein as a subsystem of computer 10 that transmits the compact data and / or electrical power between the components of computer 10. The (one) bus 14 can connect the components of computer 10 to one another via the same set of lines. Bus 14 can be configured for dedicated communication of the compact data between two or more of the components of computer 10. Bus 14 can be a system bus via which processor 11 is connected to the other components of computer 10. In this case, bus 14 can be synchronous—the compact data is transferred bidirectionally with a clock edge of a clock pulse of bus 14—and / or asynchronous—no clock pulse, but a handshake is used to transfer the compact data.In such a semi-synchronous system bus, the bus 14 is clocked, but control lines allow wait cycles to also use slow components, such as the persistent memory 13, via the bus 14.

[0126] Arbiter 15 can be provided for at least partial control over bus 14. Arbiter 15 can be considered a coprocessor subordinate to processor 11. Arbiter 15 regulates access to bus 14 related to the compact data based on a two-way handshake or three-way handshake. For this purpose, three signals are used: Bus Request (BREQ) for forwarding the compact data, Bus Grant (BGRT) for confirming and approving forwarding, and Bus Grant Acknowledge (BGA) for optional forwarding feedback. Arbiter 15 simultaneously receives multiple BREQs from different components of computer 10 via bus 14. Arbiter 15 sorts the BREQs by priority and forwards them sequentially—in a pipeline—to processor 11. Once the processor 11 has received the BREQ, the processor 11 sends the BGRT to the arbiter 15 or directly to the component of the computer 10 that sends the BREQ.A subordinate BREQ of the BREQs in the pipeline—e.g., from another component of computer 10—is forwarded to processor 11 in response to a BGRT sent by processor 11 relating to the BREQ with priority in the pipeline and related to at least a portion of the compact data. The BGRT related to the subordinate BREQ is sent from processor 11 to arbiter 15 after at least a portion of the compact data has been processed. Arbiter 15 can, for example, in turn, in response to the BGRT related to the subordinate BREQ, send a BREQ further down the pipeline—related, for example, to another portion of the compact data—to processor 11. Likewise, in response to each BGRT from processor 11, arbiter 15 can send a respective BGA related to it to processor 11. With the procedure described here, a BGA can be omitted entirely.This saves overhead in the communication between the components of computer 10. That is, instead of a three-way handshake, a two-way handshake is provided.

[0127] Bus 14 may also include a data bus, address bus, and control bus. The compact data is transferred bidirectionally between the components of computer 10 via the data bus. The address bus is operated solely by processor 11 and unidirectionally transfers memory addresses associated with the compact data. The control bus is controlled solely by arbiter 15, e.g., in the sense of a watchdog, and transfers control of it to the processor in the pipelined manner described above to control the transfer of the compact data.

[0128] The communication interface 16 enables the computer 10 to communicate with a network, preferably with a network of the production and deposition systems. Alternatively or additionally, a direct communication connection with the individual production and deposition systems can be established via the communication interface 16. For example, this can be an ad hoc network, a wireless personal area network (WPAN), e.g., a Bluetooth WPAN, a local area network (LAN), and / or a WLFI network of the production and deposition systems.

[0129] The communication interface 16 enables the computer 10 to communicate with a network, e.g., Bluetooth, WLAN, mobile radio, and / or at least part of the Internet.

[0130] The communication interface 16 may enable user interaction with the computer 10 in an environment of the computer 10 (for example, input of the compact data). The communication interface 16 may include a device and / or software driver that allows the processor 11 to

[0131] Communication interface 16 to control the production and

[0132] Deposition systems for controlling the SO procedure must be provided with an action instruction based on the compact data.

[0133] The computer 10 as an (NR) UE can be used in Narrow Band (NB) Internet of Things (IoT) applications where only occasional and small amounts of data are sent in the uplink (UL), such as compact data. For example, the compact data can be sent when the computer 10 is in a Radio Resource Control (RRC) CONNECTED state, which requires a significant amount of electrical power from the main power supply 17 or the auxiliary power supply 18. However, since the amount of NB-IoT data is small, the compact data can be sent less frequently and more efficiently. In particular, the different RRC states of the computer 10 consume different amounts of resources, and therefore, transitioning between the RRC states can efficiently reduce network resources. The computer 10 can be in one of the following states at any one time: (NR) RRC CONNECTED state, (NR) RRC INACTIVE state, and (NR) RRC IDLE state.

[0134] When the computer 10 is turned off (e.g., when no electrical power is being supplied from the main power supply 17 and / or the auxiliary power supply 18), the computer 10 is in a disconnected state and is not in any of the three RRC states. After the computer 10 is turned on, the computer 10 may initially transition to the RRC IDLE state. In the RRC IDLE state, the computer 10 may attempt to establish a wireless connection with a serving base station (e.g., gNB - not shown) and transition to the RRC CONNECTED state. After the computer 10 transitions, the computer 10 may also be released from the RRC CONNECTED state to return to the RRC IDLE state. However, after the initial transition to the RRC CONNECTED state, the computer 10 may transition to the RRC INACTIVE state to more efficiently utilize network resources.The RRC INACTIVE state of computer 10 can be released, resumed, or suspended to transition back to the RRC CONNECTED state. Furthermore, computer 10 can be released from the RRC INACTIVE state and transition back to the RRC IDLE state. The RRC INACTIVE state minimizes latency and reduces signaling load, thereby more efficiently utilizing network resources and reducing the power consumption of computer 10 during compact data transmission.

[0135] For example, computer 10 may be part of a 4-stage Random Access Channel (RACH) transmission procedure that includes the transmission of four messages (Msgl, Msg2, Msg3, and Msg4) prior to transmitting the compact data to the serving base station. Here, computer 10 may perform random access by sending a RACH preamble—e.g., Msgl—on a RACH resource. The serving base station may respond with a Random Access Response (RAR)—e.g., Msg2. Computer 10 may then send a Radio Resource Control (RRC) connection request—e.g., Msg3—on the Physical Uplink Shared Channel (PUSCH) (e.g., NR-PUSCH). The serving base station may then respond with an RRC Connection Setup—e.g., Msg4—that completes computer 10's initial access process.This RACH mode is an inefficient way of transmitting the compact data, since only after the four messages are the compact data transmitted between the computer 10 and the serving base station.

[0136] Another example: Computer 10 may be part of an Early Data Transmission (EDT) procedure that includes the transmission of two messages (Msg1 and Msg2) before transmitting the compact data to the serving base station. That is, in this EDT mode, computer 10 may send the compact data in message 3 (Msg3), and the serving base station may send the downlink (DL) data in message 4 (Msg4) of the (legacy) 4-step RACH mode. This type of compact data transmission is more efficient than the 4-step RACH mode. Computer 10 may continue to send / receive UL / DL data packets in EDT mode after Msg4 in the RRC IDLE state or RRC INACTIVE state.

[0137] Yet another example: Computer 10 may be part of a transmission scheme in which none of the Msg1 to Msg4 packets are transmitted prior to the transmission of the compact data. In this Preconfigured UL Resources (PUR) mode, computer 10 immediately sends the compact data to the serving base station using preconfigured resources. This type of transmission of UL data packets is more efficient than the two aforementioned RACH and EDT modes. This allows for the transmission of UL data packets in the RRC INACTIVE state. Accordingly, the compact data contained in the UL data packets can be sent periodically or sporadically.

[0138] As described further below, the (NR-)PUR parameters can be adjusted to transmit the compact data more efficiently to better accommodate changing radio conditions and traffic patterns and to provide the computer 10 with improved functionality of transmitting small UL data packets of the compact data in the RRC INACTIVE state.

[0139] The computer 10 transmits to the serving base station, e.g., via the communication interface 16, the UL data packets containing the compact data in the RRC INACTIVE state, based on an (initial) PUR configuration. The (initial) PUR configuration is defined according to a set of PUR parameters (e.g., in connection with 5G NR) that comprise one or more of the following elements: a control resource set configuration (CORESET) including an aggregate level and repetition types, a PUSCH configuration including a frequency hopping pattern, a UL narrow beam direction for frequency range 2 (FR2), or a transmit-receive point (TRP) assignment.

[0140] The CORESET configuration comprises a UE-specific CORESET configuration or a general CORESET configuration to enable the computer 10 to monitor and decode a Downlink Control Indicator (DCI) information received by the computer 10 (via the communication interface 16) from the serving base station in order to reconfigure the PUR configuration in the RRC INACTIVE state. At least one of the PUR parameters in the RRC INACTIVE state is updated, activated, or deactivated based on the received DCI information. The DCI information may include an acknowledgment (ACK) / negative ACK (NACK) of the PUR transmissions as well as the UL grant for a Hybrid Automatic Repeat Request (HARQ) retransmission in case of NACK. The ACK / NACK and the UL grant for the HARQ retransmission may be sent over a UE-specific or common search space.

[0141] Once the PUR is assigned, the PUR configurations can be used for a period of time. However, the radio channel and radio traffic can change constantly, so the (initial) PUR configurations may no longer be suitable for computer 10 after a certain period of time. Therefore, a reconfiguration mechanism for PUR can be considered. Reconfiguration can be performed via the PUR response message. The PUR response message can contain ACK / NACK of the PUR transmissions (if not included in DCI) and information for reconfiguring the PUR parameters. The PUR response message can be a UE-specific RRC signaling or a Broadcast System Information Block to reconfigure the (initial) PUR configuration and create a new PUR configuration.

[0142] The computer 10 may receive a message from the serving base station (via the communication interface 16) indicating that the (initial or newly created) PUR configuration may be released if no UL data packets intended to contain at least part of the compact data are sent for more than a predetermined number of continuous PUR transmissions.

[0143] Computer 10 may receive a message from the serving base station (via communications interface 16) indicating to computer 10 that computer 10 should fall back to EDT mode or RACH mode in the event of a UL transmission error. The occurrence of the UL transmission error may be determined based on at least one of the following: timing mismatch (TA), low transmit power, deep channel fading, or beam dropout. Computer 10 may receive a signal from the serving base station (via communications interface 16) to reconfigure computer 10 for transmission of the UL data packets containing at least a portion of the compact data in the RRC INACTIVE state based on one or more PUR parameters after computer 10 returns to EDT mode or RACH mode.The one or more PUR parameters may be reconfigured based on a request from the computer 10, a radio network load, or a radio link performance.

[0144] The main power supply 17 supplies at least one or more of the components of the computer 10 with electrical power, e.g., via the bus 14. In particular, the main power supply 17 charges the auxiliary power supply 18 with electrical power, e.g., from outside the computer 10, e.g., in the case that the main power supply 17 is connected to the power source outside the computer 10. Here, the main power supply 17 may represent a preferred component used to power the components of the computer 10 and may, for example, comprise an accumulator or a battery. The main power supply 17 may comprise further components such as voltage regulators, DC voltage stabilizers, series regulators, buck converters, and / or boost converters to meet the respective requirements of the components of the computer 10.The main power supply 17 can either have a dedicated fixed power supply connection to the external power source, such as a power grid, or a detachable power supply connection for charging the accumulator or battery of the main power supply 17. For this purpose, the main power supply 17 can have an inverter to provide a predetermined DC power supply from a connected AC power source as the external power source. The predetermined DC power supply can also already be provided by a connected DC power source as the external power source. The DC power supply can be regulated via the above-mentioned voltage regulators and supplied to the components of the computer 10 as set DC supplies. The auxiliary power supply 18 is connected to the volatile memory 12 and / or the persistent memory 13 via the bus 14.The auxiliary power supply 18 is charged by the electrical power of the main power supply 17. The auxiliary power supply 18 can be arranged inside or outside the computer 10, or inside or outside the volatile memory 12 and / or the permanent memory 13. For example, the auxiliary power supply 18 can be housed on a motherboard of the computer 10 to supply the volatile memory 12 and / or the permanent memory 13 with auxiliary power. The auxiliary power supply 18 can, in particular, be embodied in the form of a supercapacitor, an accumulator, and / or a battery. The power capacity / energy capacity of the main power supply 17 can be many times, for example, at least 10 times or 50 times greater than the power capacity / energy capacity of the auxiliary power supply 18.

[0145] The processor 11 monitors changes in the electrical power supplied by the main power supply 17. In the event of a sudden power failure, e.g., if the power source external to the computer 10 is disconnected from the main power supply 17 or the main power supply 17 degrades or fails for another reason, and the processor 11 determines that the electrical power supplied by the main power supply 17 to one or more of the components of the computer 10 has fallen below a threshold, e.g., 0.8 or 0.75 of an operating power of the main power supply 17, the processor 11 causes the auxiliary power supply 18 to assume a remaining supply power for a shutdown of the computer 10. The shutdown includes supplying at least the processor 11, the volatile memory 12, and / or the persistent memory 13 with electrical power for the duration of the shutdown.During the shutdown process, the compact data currently located in the volatile memory 12 and / or the compact data currently being processed in the processor 11, for example, in the register / cache of the processor 11, are transferred from the volatile memory 12 and / or the processor 11 to a meta-area of ​​the persistent memory 13. For this purpose, the meta-area of ​​the persistent memory 13 can be reserved specifically for the shutdown process.

[0146] When the computer 10 is booted and the main power supply 17 resumes operating power, the processor 11 loads the compact data from the meta-area of ​​the persistent memory 13 to enable faster data processing. The meta-area of ​​the persistent memory can be released after the boot process or successively during the boot process. It should be noted at this point that all of the above-described parts, viewed individually and in any combination, particularly the details shown in the drawings, are claimed as essential to the invention. Modifications to these are familiar to those skilled in the art.

[0147] LIST OF REFERENCE SYMBOLS

[0148] 1 ReRAM device

[0149] 2 Substrat

[0150] 3 Passivation structure

[0151] 3-1 first passivation section

[0152] 3-2 second passivation section

[0153] 3-3 third passivation section

[0154] 4 Electrode

[0155] 5 Counter electrode

[0156] 6 Metal oxide part

[0157] 7 Electrode terminal

[0158] 8 photoresist

[0159] 9 Hard mask

[0160] 10 computers

[0161] 11 processor

[0162] 12 Volatile memory

[0163] 13 Permanent storage

[0164] 14 buses

[0165] 15 arbiters

[0166] 16 Communication interface

[0167] 17 Main power supply

[0168] 18 Auxiliary power supply

[0169] X first direction

[0170] Y second direction

[0171] Z third direction

[0172] SO procedure

[0173] S1-S5 process steps

[0174] Al -Al 3 process sequence

Claims

Claims 1. A resistive random access memory, ReRAM, device (1) comprising: a substrate (2); a passivation structure (3) at least on the substrate (2); an electrode (4) embedded in the passivation structure (3), which is in the form of a fin and comprises a first metal and extends parallel to a plane of the substrate (2); a counter electrode (5) which is in the form of a layer and comprises a second metal and extends parallel to the plane of the substrate (2); and a metal oxide part (6) which comprises the first metal in oxidized form and is located between the electrode (4) and the counter electrode (5), wherein the metal oxide part (6), the electrode (4), and the counter electrode (5) together form a memory cell of the ReRAM device (1) and enable resistive switching of the ReRAM device (1);characterized in that the passivation structure (3) connects the electrode (4) to the counter electrode (5) and is arranged to block oxygen diffusion relative to the metal oxide part (6); 2. ReRAM device (1) according to claim 1, characterized in that the metal oxide part (6) is delimited laterally by the passivation structure (3) and is delimited in the vertical direction (Z) perpendicular to the plane of the substrate (2) by the electrode (4) and the counter electrode (5).

3. ReRAM device (1) according to one of the preceding claims, characterized in that, viewed in cross-section of the ReRAM device (1), all upper sides of the passivation structure (3) are located at least at the same height as a top side of the metal oxide part (6); and the electrode (4) is located below the counter electrode (5) in cross-section.

4. Method (SO) for producing a resistive random access memory, ReRAM, device (1), the method (SO) comprising the following method steps in the specified order S1 to S5: Providing (Sl) a substrate (2); Providing (S2) an electrode (4) in the form of a fin with a first metal on the substrate (2), which extends parallel to a plane of the substrate (2); Providing (S3) a passivation structure (3) on the electrode (4); Providing (S4) a metal oxide part (6) with an oxidized form of the first metal between the electrode (4) and a counter electrode (5), so that the metal oxide part (6), the electrode (4) and the counter electrode (5) together form a memory cell of the ReRAM device (1); and Providing (S5), on the metal oxide part (6) and the passivation structure (3), the counter electrode (5) formed in the form of a layer and extending parallel to the plane of the substrate (2) with a second metal; characterized in that the passivation structure (3) connects the electrode (4) to the counter electrode (5) and is arranged to block oxygen diffusion relative to the metal oxide part (6).

5. Method (SO) according to claim 4, characterized in that after the provision (Sl) of the substrate (2) the following steps are carried out: Providing a first partial passivation structure (3), Providing a first photoresist (8) on the first partial passivation structure (3), Etching the first partial passivation structure (3) according to the specification of the first photoresist (8) in order to form a recess in the first partial passivation structure (3) in the form of a trough with substantially straight side walls, and Removing the first photoresist (8) on the first partial passivation structure (3).

6. Method (SO) according to claim 4 or 5, characterized in that the provision (S2) of the electrode (4) comprises the following steps: Depositing a surface electrode (4) along a contour of the recess or on a surface of the first partial passivation structure (3) present after etching the first partial passivation structure (3) or after removing the first photoresist (8) while maintaining a low oxygen content, Providing a second partial passivation structure (3) on the deposited Surface electrode (4) while maintaining the oxygen deficiency, and Planarizing up to at least an upper surface of the first partial passivation structure (3) in order to expose at least a part of the deposited surface electrode (4) forming the fin laterally between the first and second partial passivation structures (3) or an upper surface of the fin.

7. Method (SO) according to one of claims 4 to 6, characterized in that after the provision (S2) of the electrode (4) the following steps are carried out: Successive application on the provided electrode (4) of a first hard mask (9) and a second photoresist (8) to specify a hard mask etching structure for the provided electrode (4), Etching the electrode (4) to a predetermined depth under oxygen deprivation, according to the specification of the hard mask etching structure, Applying a third partial passivation structure (3) while maintaining the oxygen deficiency to cover the hard mask etching structure and the etched electrode (4), and Planarizing at least to upper surfaces of the etched electrode (4) or the elevations of the etched electrode (4) in order to expose the upper surfaces of the etched electrode (4) or upper surfaces of the elevations of the etched electrode (4) and to remove the first hard mask.

8. Method (SO) according to one of claims 4 to 7, characterized in that at least after the provision (S2) of the electrode (4) the following steps are carried out: Providing, in the longitudinal direction of the electrode (4) on the top side of the electrode (4), pads of a second hard mask, wherein the pads are shifted relative to the previously existing hard mask etching structure of the first hard mask, in-situ etching under oxygen deficiency according to the specification of the second hard mask to produce elevations of the electrode (4) or recesses in the electrode (4) corresponding to the shift, and providing (S3) the passivation structure (3) comprising: Providing a fourth partial passivation structure (3) while maintaining the oxygen deficiency to surround the elevations of the electrode (4) or to fill recesses in the electrode (4), and Planarization up to at least upper surfaces of the electrode (4) or the elevations of the electrode (4) in order to expose the upper surfaces of the electrode (4) or upper sides of the elevations of the electrode (4) and to remove the second hard mask, so that a flat plane is formed between alternately arranged passivation sections (3-1, 3-2) of the passivation structure (3) and electrode sections of the electrode (3).

9. Method (SO) according to one of claims 4 to 8, characterized in that after the provision (S3) of the passivation structure (3), the provision (S4) of the metal oxide part (6) is carried out by growing the metal oxide part (6) using a bottom-up technology on the upper side of the electrode (4) exposed to air; and after the provision (S4) of the metal oxide part (6), the provision (S5) of the counterelectrode (5) is carried out by depositing the counterelectrode (5).

10. Computer program, characterized in that the computer program comprises instructions which, when the computer program is executed by a computer (10), cause the computer (10) to carry out the method (SO) according to one of claims 4 to 9 or at least one of the To carry out or initiate steps of this.

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