Vertical iii-v hall sensor
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-19
- Publication Date
- 2026-03-11
AI Technical Summary
The development of vertical III-V Hall sensors is hindered by the different material properties and technological requirements of III-V materials compared to silicon, making it challenging to manufacture sensors with high sensitivity using III-V materials, as doping by implantation is prohibited and thermal passivation methods like oxide growth are not possible.
A vertical III-V Hall sensor is designed with a substrate layer, insulation layers, and a III-V semiconductor layer produced through epitaxy processes, featuring n-doping and all-round insulation, allowing for the creation of high-sensitivity sensors using standard III-V processes, with the semiconductor layers grown monolithically and lattice-matched, and insulation layers composed of III-V materials.
This approach enables the reliable and cost-effective manufacturing of sensitive vertical III-V Hall sensors, overcoming the limitations of III-V material properties and process incompatibilities, allowing for the production of sensors with improved performance and efficiency.
Smart Images
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Abstract
Description
[0001] Vertical III-V Hall sensor
[0002] Vertical Hall sensors have long been known in silicon technology. However, due to the completely different III-V material properties and completely different technological requirements, and especially due to the manufacturing processes that are completely incompatible with silicon, such Hall sensors using III-V materials have not been known to date.
[0003] CN 102 520 376 A discloses various III-V Hall sensors for measuring the three components of a magnetic field. For measuring magnetic fields running parallel to a substrate surface, a columnar Hall sensor structure arranged perpendicularly to the substrate surface is disclosed. The columnar structure is contacted, among other things, at both end faces.
[0004] EP 3 216 057 Bl also discloses a III-V Hall sensor using a 2DEG quantum well structure.
[0005] Against this background, the object of the invention is to provide a device that further develops the state of the art.
[0006] The object is achieved by a vertical III-V Hall sensor having the features of patent claim 1. Advantageous embodiments of the invention are the subject of subclaims.
[0007] According to the subject matter of the invention, a vertical III-V Hall sensor is provided, comprising a substrate layer with a top side and a bottom side. A first insulating layer is formed on the substrate layer, a III-V semiconductor layer is formed on the insulating layer, and a second insulating layer is formed on the III-V semiconductor layer.
[0008] The second insulation layer is structured and has at least three openings formed as contact regions.
[0009] The III-V semiconductor layer has a length formed in the X direction and a width formed in the Y direction.
[0010] The at least three contact regions are arranged along a straight line on a top side of the III-V semiconductor layer, which is formed in the direction of the second insulation layer. The III-V semiconductor layer has an n-type doping.
[0011] It should be noted that the vertical III-V Hall sensor has a main extension surface parallel to the substrate surface.
[0012] Furthermore, the III-V semiconductor layer has a surrounding insulation.
[0013] It should be noted that the III-V semiconductor layers are generally produced by an epitaxial process using organometallic precursors, in particular by means of a MOVPE or an MBE system.
[0014] One advantage is that, surprisingly, vertical Hall sensors with high sensitivity can also be reliably manufactured using III-V materials. Until now, experts have assumed that the production of a vertical III-V Hall sensor is impossible due to the completely different technological requirements of III-V materials compared to silicon. One reason for this is that doping by implantation in III-V is not possible. Thermal passivation processes such as oxide growth are also not possible. Another advantage is that, due to the simple design, cost-effective vertical III-V Hall sensors can be manufactured using standard III-V processes.
[0015] In one embodiment, the aforementioned III-V semiconductor layers are grown monolithically and lattice-matched to one another. It should be noted that the term "monolithic" refers to a manufacturing process in which the III-V semiconductor layers are deposited using a continuous epitaxial process. In other words, the III-V semiconductor wafer is not removed from the epitaxial system during layer deposition. In particular, no semiconductor bond is formed between the III-V semiconductor layers.
[0016] In another embodiment, all layers are produced by vapor phase epitaxy in a MOVPE system, preferably lattice-matched.
[0017] In a further development, the semiconductor wafer, ie the substrate, has a diameter of 100 mm or a diameter of 150 mm or a larger diameter.
[0018] In one embodiment, the III-V semiconductor layer has a uniform thickness. In another embodiment, the III-V semiconductor layer has a uniform thickness across the entire region of the vertical III-V Hall sensor.
[0019] In one embodiment, the III-V semiconductor layer has a uniform thickness at least or exclusively in the region of the III-V Hall sensor. It is understood that the III-V semiconductor layer has a uniform thickness at least between the contact regions and including the contact regions.
[0020] In one embodiment, the first insulation layer and / or the second insulation layer consists of a III-V material. In an alternative embodiment, the first insulation layer and / or the second insulation layer comprises a III-V material. In a further development, the first insulation layer and / or the second insulation layer is undoped. It should be noted that the term exclusively refers to intentional doping. In this regard, it should be noted that when using organometallic precursors during the production of the III-V layers by means of vapor phase epitaxy in a MOVPE system, an unintentional doping, at least with carbon, generally occurs. It should be noted that the unintentional doping generally ranges between 1*10 14 N / cm 3 and l*10 15 N / cm 3 lies.
[0021] Furthermore, it should be noted that unintentional doping can also inevitably occur due to the choice of process parameters during epitaxy. It should be noted that the choice of process parameters can limit the amount of unintentional doping above an unintentional minimum carbon doping in a range of greater than l*10 14 N / cm 3 can be influenced.
[0022] In another embodiment, the band gap of the first insulation layer and / or the second insulation layer is each larger than the band gap of the III-V semiconductor layer. It is understood that the use of undoped high-band materials creates an insulating space charge zone at the interface with the III-V semiconductor layer.
[0023] In one embodiment, the thickness of the first insulation layer formed in a III-V material and / or the thickness of the second insulation layer formed in a III-V material is in a range between 2 nm and 100 nm. In another development, the thickness is in a range between 10 nm and 80 nm or in a range between 20 nm and 60 nm. In another embodiment, the thickness of the first insulation layer and / or the thickness of the second insulation layer is greater than 10 nm and less than 500 nm. In one embodiment, the first insulation layer and / or the second insulation layer comprises at least the elements InGaP. It is understood that the first insulation layer and / or the second insulation layer can comprise further III-V elements, in particular Al or P.
[0024] In another embodiment, the first insulation layer and / or the second insulation layer consists of InGaP.
[0025] In one embodiment, the second insulation layer comprises a silicon oxide and / or a silicon nitride.
[0026] In a further development, an n-doped structured InGaP layer is arranged as a metallically conductive layer on top of the III-V semiconductor layer and is bonded to the III-V semiconductor layer. The doping of the InGaP layer lies in a range between 1«10 18 cm' 3 to l«10 2 ° cm' 3 In another embodiment, the highly conductive InGaP layer is arranged exclusively beneath a metal contact formed in the contact opening.
[0027] In another embodiment, the doping is uniform or variable across the thickness of the III-V semiconductor layer. In one further development, the III-V semiconductor layer has a lower doping at the interface with the first insulation layer than in the direction toward the second insulation layer.
[0028] In a further development, the doping of the III-V semiconductor layer is in a range between l*10 14 1 / cm 3 and 5*10 17 1 / cm 3 or in a range between 5*10 14 1 / cm 3 and l*10 16 1 / cm 3 or in a range between l*10 15 1 / cm 3 and 5«10 15 1 / cm 3 . It is understood that in order to achieve the highest possible mobility, the doping of the III-V semiconductor layer should be in a range below 5*10 16 1 / cm 3In another embodiment, the III-V semiconductor layer has a thickness in a range between 0.5 pm and 50 pm or in a range between 1.0 pm and 20 pm or in a range between 3.0 pm and 10 pm.
[0029] In a further development, the ratio of length to width of the III-V semiconductor layer is greater than or equal to 1 or in a range between 1 and 50.
[0030] In a further development, the vertical III-V Hall sensor comprises or consists of a quadrilateral geometry. It is understood that with a length-to-width ratio of 1, the quadrilateral is formed as a square.
[0031] In another embodiment, the length is greater than the width, with the length being at least twice as large as the width.
[0032] In another embodiment, the vertical III-V Hall sensor comprises a geometry that is more than square. In particular, the vertical III-V Hall sensor has a hexagonal or octagonal geometry.
[0033] In another embodiment, the width of the III-V semiconductor layer is in a range between 1 pm and 20 pm or in a range between 3 pm and 10 pm.
[0034] If the length is twice the width, it is understood that the length is greater than or equal to 2 pm or greater than or equal to 6 pm or greater than or equal to 20 pm or greater than or equal to 40 pm.
[0035] In another embodiment, the length is less than 100 pm or less than 50 pm or less than 30 pm or less than 20 pm.
[0036] In one embodiment, the III-V semiconductor layer has a uniform stoichiometry. In a further development, the III-V semiconductor layer comprises GaAs or InGaAs, or the III-V semiconductor layer consists of GaAs, InGaAs, InSb, InAs, or GaSb.
[0037] In one embodiment, the III-V semiconductor layer of the vertical III-V Hall sensor has a surrounding region produced by means of a hydrogen implantation as insulation.
[0038] In a further development, the insulation produced by means of hydrogen implantation is designed such that the entire III-V semiconductor layer within the circumferential region is completely electrically insulated from the surrounding regions of the III-V semiconductor layer.
[0039] In another embodiment, the III-V semiconductor layer has a trench as insulation. The trench is preferably created by means of mesa etching. In another embodiment, the sidewalls, i.e., the vertical or nearly vertical walls of the III-V vertical Hall sensor, are passivated and / or covered with an insulating layer. It is understood that the term "circumferentially formed" refers to a closed, annular structure.
[0040] In one embodiment, the III-V semiconductor layer is completely severed by the trench. In other words, the first insulation layer is formed in the bottom region of the trench. This creates a first region in the III-V semiconductor layer that is electrically insulated from the other regions of the III-V semiconductor layer by forming the first insulation layer on the underside of the III-V semiconductor layer.
[0041] In one embodiment, the trench is filled with an insulating material, preferably a dielectric, for example, a PECVD oxide and / or a silicon nitride. In one embodiment, the distances between two immediately adjacent contact regions are either identical or different.
[0042] In a further development, the vertical III-V Hall sensor comprises exactly three contact areas, or exactly four, or exactly five, or exactly six, or exactly seven contact areas. The contact areas are preferably arranged along a straight line.
[0043] In another development, in the vertical Hall sensor with exactly five contact areas, all distances between two consecutive contact areas are exactly the same or the distances between the three contact areas in the middle are the same and the distances to the two outer contact areas are smaller or larger than the two distances in the middle.
[0044] The invention will be explained in more detail below with reference to the drawings. Similar parts are labeled with identical designations. The illustrated embodiments are highly schematic, ie the distances and the lateral and vertical extensions are not to scale and, unless otherwise stated, do not have any deducible geometric relationships to one another.
[0045] Figure 1 is a cross-sectional view of a vertical III-V Hall sensor,
[0046] Figure 2 shows the top view of an embodiment of Figure 1,
[0047] Figure 3a-f Top views of further different embodiments.
[0048] Figure 1 shows a cross-sectional view of a vertical III-V Hall sensor H1. The Hall sensor H1 comprises a substrate layer SUB with a top surface OS and a bottom surface US. A first insulation layer IS1 is arranged on the substrate layer SUB.
[0049] A III-V semiconductor layer HLS is formed on the first insulation layer IS1. A second insulation layer IS2 is arranged on the III-V semiconductor layer HLS.
[0050] In contrast to the first insulation layer IS1, the second insulation layer IS2 is structured. In particular, the second insulation layer IS2 has at least three openings formed as contact regions K1, K2, K3.
[0051] The at least three contact regions K1, K2, K3 are arranged along a straight line. It should be noted that the III-V semiconductor layer HLS has an n-type doping.
[0052] Furthermore, the III-V semiconductor layer HLS or the vertical III-V Hall sensor Hl has a circumferential insulation not shown.
[0053] Figure 2 shows a top view of an embodiment of Figure 1. Only the differences from the illustration in Figure 1 are explained below.
[0054] The vertical Hall sensor Hl features a rectangular, circumferential insulation ISR. The contacts K1, K2, and K3 arranged along the X-axis are completely within the X- and Y-direction.
[0055] It should be noted that for reasons of clarity, the outer rectangular insulation region ISR is not shown. A distance al exists between the first contact K1 and the second contact K2, and the distance al also exists between the second contact K2 and the third contact K3. In other words, two consecutive contacts K1, K2, or K2, K3, are arranged equidistant from each other.
[0056] The III-V semiconductor layer HLS or the second insulation layer IS2 has a length L in the X direction and a width B in the Y direction.
[0057] Figures 3a-f show further top views of different embodiments of a vertical Hall sensor H2. Only the differences from the previous figures are explained below.
[0058] In contrast to the rectangular embodiment of Figure 2, the embodiment of Figure 3a has a bow tie or butterfly-shaped extension in the X-direction with a circumferential outer edge. The outer edge is formed from a plurality of interconnected straight lines. In this case, the edge is formed from a total of twelve straight lines.
[0059] The III-V semiconductor region HLS has a smaller width in the region of the second contact K2 than in the region around the first contact K1 and the third contact K3. The width of the III-V semiconductor region at the first contact K1 corresponds to or is equal to the width of the III-V semiconductor region around the third contact K3. All three contacts K1, K2, K3 have a rectangular shape, with the width of the respective contacts K1, K2, K3 being greater than the length formed in the X direction.
[0060] It is understood that the edge regions of the contacts K1, K2, K3 in the illustrated embodiments are spaced from the edge of the III-V semiconductor region. In an embodiment not shown, the contacts are formed up to the edge of the III-V semiconductor region or beyond.
[0061] The first contact K1 and the third contact K3 are equally wide in the Y direction and significantly wider than the second contact K2. All three contacts K1, K2, and K3 have a rectangular extension in the illustrated plan view. The III-V Hall sensor region exhibits mirror symmetry with respect to a mirror axis running in the Y direction and passing through the center of the second contact.
[0062] The illustration in Figure 3b also shows a butterfly-shaped extension with two wings, with a mirror axis formed in the Y direction running through the center of the second contact K2.
[0063] The two wings are each crescent-shaped. In other words, the outer edge of the entire III-V semiconductor region does not have straight lines, but is formed by arcuate segments.
[0064] In contrast to the second contact K2, the first contact Kl and the third contact K3 are not rectangular but are designed as circular segments.
[0065] In contrast to the embodiment of the III-V semiconductor region of Figure 2, the embodiment of Figure 3c now comprises a total of five contacts K1-K5, which are also formed in a straight line along the X-direction.
[0066] The fourth contact K4 and the fifth contact K5 are formed as outer contacts at the two head ends of the III-V semiconductor region HLS. The distance a1 is formed between each of the contacts K1-K5. All five contacts K1-K5 are rectangular and arranged equidistant from one another. In contrast to the embodiment of the III-V semiconductor region in Figure 3c, in the embodiment in Figure 3d the two outer contacts K4 and K5 are arranged at a distance a2 from the immediately adjacent contacts K3 and K1, respectively. The distance a2 is greater than the distance a1. Although all five contacts K1-K5 are rectangular, the rectangle of the second contact K2 has the smallest length in the X direction of all five contacts K1-K5.
[0067] The two contacts K1 and K3 are of equal length, with the length of the two contacts K1 and K3 being greater than the length of the second contact K2. The length of the two outer contacts K4 and K5 is equal and each greater than the length of the first contact K1 and the third contact K3.
[0068] In the embodiment shown in connection with Figure 3e, a total of four individual III-V Hall sensors H1-H4, each with three contacts K1, K2, K3, are arranged along a straight line formed in the X direction and interconnected, whereby only the differences from the embodiment of Figure 2 are explained below. By means of the interconnection, it is achieved that the III-V Hall sensors H1 - H4 are designed as a single large four-contact Hall sensor HFS1.
[0069] The outer contacts Kl, K3 of each of the four III-V Hall sensors H1-H4 are connected to the outer contacts Kl, K3 of the adjacent III-V Hall sensors H1-H4 to form a ring. In other words, the first contact Kl of the first III-V Hall sensor H1 is connected to the third contact K3 of the fourth Hall sensor H4.
[0070] In the embodiment shown in connection with Figure 3f, four large four-contact Hall sensors HFS1, HFS2, HFS3, HFS4 are shown, each consisting of four ring-connected individual III-V Hall sensors H1-H4, each with three contacts K1, K2, K3 along a straight line formed in the X direction. Only the differences from the embodiment in Figure 3e are explained below. Overall, the four large four-contact III-V Hall sensors HFS1 - HFS4 are arranged in four rows. The middle contacts K1 are each connected to the middle contacts in an adjacent row. In other words, the four large four-contact Hall sensors are connected in parallel.
Claims
Patent claims 1. Vertical III-V Hall sensor (Hl), with - a substrate layer (SUB) with a top side (OS) and a bottom side (US), - a first insulation layer (IS1) formed on the substrate layer (SUB), - a III-V semiconductor layer (HLS) formed on the first insulation layer (IS1), - a second insulation layer (IS2) formed on the III-V semiconductor layer (HLS), wherein the second insulation layer (IS2) is structured and has at least three openings formed as contact regions (K1, K2, K3), - the III-V semiconductor layer (HLS) has a length (L) in the X direction and a width (B) in the Y direction, - the at least three contact areas (Kl, K2, K3) are arranged along a straight line, - the III-V semiconductor layer (HLS) has an n-doping, - the III-V semiconductor layer (HLS) has a circumferential insulation (ISR).
2. Vertical III-V Hall sensor according to claim 1, characterized in that the first insulation layer (IS1) and / or the second insulation layer (IS2) consists of a III-V material or comprises a III-V material and is in each case undoped.
3. Vertical III-V Hall sensor according to claim 1 or claim 2, characterized in that the band gap of the first insulation layer (IS1) and / or the second insulation layer (IS2) is each larger than the band gap of the III-V semiconductor layer (HLS).
4. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the thickness of the first insulation layer (IS1) formed in a III-V material and / or the thickness of the second insulation layer (IS2) formed in a III-V material is in a range between 2 nm and 100 nm.
5. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the first insulation layer (IS1) and / or the second insulation layer (IS2) comprises at least the elements In, Ga, and / or P or consists of InGaP.
6. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the second insulation layer (IS2) comprises a silicon oxide and / or a silicon nitride.
7. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the doping is uniform or different across the thickness of the III-V semiconductor layer (HLS).
8. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the doping of the III-V semiconductor layer (HLS) is in a range between l*10 14 1 / cm 3 and 5*10 17 1 / cm 3 or in a range between 5*10 14 1 / cm3 and l*10 16 1 / cm 3 or in a range between l*10 15 1 / cm 3 and 5*10 15 1 / cm 3 lies.
9. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the III-V semiconductor layer (HLS) has a thickness in a range between 0.5 pm and 50 pm or in a range between 1.0 pm and 20 pm or in a range between 3.0 pm and 10 pm.
10. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that in the III-V semiconductor layer (HLS) the length to width ratio is greater than or equal to 1 or in a range between 1 and 50.
11. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the width of the III-V semiconductor layer (HLS) is in a range between 1 m and 20 pm or in a range between 3 pm and 10 pm.
12. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the III-V semiconductor layer (HLS) has a uniform stoichiometry.
13. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the III-V semiconductor layer (HLS) comprises GaAs or InGaAs or consists of GaAs or InGaAs or of InSb or InAs or GaSb.
14. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the III-V semiconductor layer (HLS) has a trench as insulation (ISR).
15. Vertical III-V Hall sensor according to one of the preceding claims, characterized in that the distances between two immediately consecutive contact areas (Kl - K5) are the same or different.