Semiconductor structures

Abstract

A CAVET comprises: a drain terminal (110); a source terminal (170); and a current blocking layer (240), CBL, between the drain terminal and the source terminal, wherein the CBL comprises at least one porous region (244, 246) for blocking current between the source terminal and the drain terminal and a non-porous aperture region (242) for allowing current flow between the source terminal and the drain terminal.

Description

[0001] SEMICONDUCTOR STRUCTURES

[0002] Technical field

[0003] The present application relates to a current aperture vertical electron transistor (CAVET). The present application also relates to a semiconductor structure and method for forming a semiconductor structure.

[0004] Background

[0005] There is increasing interest in forming semiconductor devices such as transistors from Ill-N semiconductor materials. Ill-N semiconductor materials, such as GaN, possess desirable electronic properties, such as a high breakdown voltage and high critical electric field.

[0006] A popular semiconductor device formed from Ill-N semiconductor materials, such as GaN, is the high electron mobility transistor (HEMT). A HEMT comprises a two- dimensional electron gas (2DEG) for carrier flow between the source and the drain, which is attractive due to the high electron mobility of the 2DEG. A HEMT commonly has a lateral semiconductor device architecture where the source terminal and drain terminal are formed on the same side of a semiconductor wafer, either side of the gate terminal. Current flow thus occurs in a lateral direction from the source to the drain and is regulated by the gate terminal.

[0007] In some applications, a lateral HEMT architecture can suffer from drawbacks. For example, in high power applications, the gate-to-drain terminal spacing is relatively large, thus increasing the footprint of the device. It can therefore be desirable to form semiconductor devices with a vertical architecture with the source and drain terminal disposed on opposite sides of a semiconductor wafer.

[0008] One Ill-N based semiconductor device with a vertical architecture is the current aperture vertical electron transistor (CAVET).

[0009] In a CAVET, a source terminal and a drain terminal are formed on opposite sides of a semiconductor wafer. Current flow thus takes place in a vertical direction through the CAVET from the source terminal to the drain terminal. Figure 1 illustrates one example of a CAVET 100. CAVET 100 includes a drain terminal 110 fabricated on a n-type semiconductor layer 120, which is some examples may be termed a drain semiconductor layer. CAVET 100 further comprises a drift layer 130 over the n-type semiconductor layer 120 and a current blocking layer (CBL) 140 over the drift layer 130. The CBL 140 comprises an aperture 142 for allowing a flow of current and a first current blocking portion 144 and a second current blocking portion 146 for blocking current flow.

[0010] The CAVET 100 further comprises a channel layer 150 over the CBL 140 and a barrier layer 160 over the channel layer. A 2DEG 152 is formed within the channel layer 150. The CAVET 100 further comprises a first source terminal 170 and a second source terminal 180 fabricated on the channel layer 150. The CAVET 100 further comprises a gate terminal fabricated on the barrier layer 160.

[0011] In operation, a bias voltage applied to the gate terminal 190 may be controlled to prevent or allow current flow between the source terminals 170, 180 and the drain terminal 110. For example, in a depletion mode operation, removal of a bias voltage from the gate terminal 190 may allow charge carriers to flow from the source terminals 170, 180 to the drain terminal 110. In such examples, charge carriers travel along the 2DEG 152 in the channel layer 150 in a lateral direction under the gate terminal 190. Carriers can then drift towards the drain terminal 110 through the aperture 142 to allow current flow through the CAVET 100 in a vertical direction.

[0012] The CBL 140 and, in particular, the current blocking portions 144, 146, prevent carriers drifting from source terminals 170, 180 directly towards the drain terminal 110 through the drift layer 130. This effect by the current blocking portions 144, 146 maintains the formation of the 2DEG 152, enabling the high electron mobility of the CAVET 100. The first and second current blocking portions 144, 146 may thus comprise a material for blocking carrier flow. In some examples, the first and second current blocking portions 144, 146 may comprise epitaxially deposited SiN.

[0013] The architecture of the CAVET leads to many advantages over a lateral semiconductor device architecture, such as a reduced footprint, low voltage gate control, high critical electric field and high mobility. Whilst the CAVET has many advantages, it has not found wide spread use in many applications due to the fabrication process used to for a CAVET.

[0014] The fabrication of the CAVET 100 first involves epitaxially growing the drain semiconductor layer 120 and the drift layer 130 on a substrate. The semiconductor structure formed on the substrate may be termed a wafer from which many CAVETs may be fabricated.

[0015] Material to form the CBL 140 is then epitaxially grown on the drift layer 130. In such examples, the material may comprise SiN. The SiN material may then be masked to provision the regions where aperture 142 is to be formed. The SiN is subsequently etched to form the aperture 142. The remaining SiN thus forms the current blocking portions 144, 146 of the CBL 140. The channel layer 150 and the barrier layer 160 are subsequently epitaxially grown on the CBL 140. The drain terminal 110, source terminals 170, 180 and gate terminal 190 are subsequently fabricated on the semiconductor structure to form the CAVET 100.

[0016] Formation of the CAVET 100 thus first involves epitaxial growth of the drain semiconductor layer 120 and the drift layer 130. The etching step for the formation of the aperture 142 of the CBL 140 is performed using a lithography machine. The subsequent steps for forming the CBL 140, channel layer 150 and barrier layer 160 again involve epitaxial growth steps. The fabrication of the terminals 110, 170, 180, 190 is then performed using a semiconductor device fabrication machine.

[0017] The transfer of the semiconductor structure between epitaxial growth reactors and lithography machines for the formation of a CAVET is undesirable. Most semiconductor device fabrication facilities have lithography machines, but do not have epitaxial growth capabilities and vice versa most epitaxial growth facilities do not have lithography capabilities. The two processes involve different specialisms and the semiconductor device fabrication supply chain does not typically involve transfer of semiconductor structures between epitaxy facilities and lithography facilities in both directions. Typically, semiconductor device fabrication first involves epitaxial growth of a semiconductor structure, followed by transfer of the semiconductor structure to a lithography facility. Supply chains have evolved such that transfer does not take place from a lithography facility back to an epitaxial growth facility. Doing so reduces throughput and increases manufacturing costs. Thus, the CAVET has not found wide spread use in many applications due to the difficulties associated with its manufacturing process.

[0018] It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques.

[0019] According to a first aspect there is provided a CAVET that comprises: a drain terminal; a source terminal; and a current blocking layer (CBL) between the drain terminal and the source terminal, wherein the CBL comprises at least one porous region for blocking current between the source terminal and the drain terminal and a non-porous aperture region for allowing current flow between the source terminal and the drain terminal.

[0020] According to a second aspect there is provided a semiconductor structure that comprises: a substrate; and a plurality of semiconductor layers over the substrate comprising a first lll-N semiconductor layer comprising a porous region and a non-porous region.

[0021] According to a third aspect there is provided a method of forming a semiconductor structure comprising: forming a plurality of semiconductor layers over a substrate; and forming a porous region and a non-porous region in a first lll-N semiconductor layer of the plurality of semiconductor layers.

[0022] Brief description of the drawings

[0023] For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

[0024] Figure 1 is an example of a CAVET;

[0025] Figure 2 is another example of a CAVET ;

[0026] Figures 3a-d illustrate process steps in an example method for forming a semiconductor structure; Figures 4a-c illustrate aerial views of current blocking layers (CBLs);

[0027] Figure 5 is another example of a CAVET;

[0028] Figures 6a-d illustrate process steps in an example method for forming a semiconductor structure.

[0029] Detailed

[0030] Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition.

[0031] Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer.

[0032] A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1 :1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out- of-plane is used to mean perpendicular to the surface of the substrate.

[0033] Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), and gallium antimonide (GaSb).

[0034] Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type.

[0035] A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function.

[0036] A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided.

[0037] A fully depleted porous layer means a layer in which there are no charge carriers.

[0038] Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer.

[0039] Examples according to the present disclosure present a current aperture vertical electron transistor (CAVET), which comprises a current blocking layer (CBL) that includes a porous region for blocking current between a source terminal and a drain terminal. The CBL further comprises an aperture for allowing carriers to flow between the source terminal and the drain terminal. In one example, the porous region comprises a lll-N semiconductor material such as GaN. Porous GaN has been shown to exhibit highly resistive properties. As such, the porous region is able to block direct carrier flow between the source terminal and drain terminal and maintain the 2DEG within the channel layer of the CAVET. Carriers can thus travel along the 2DEG in the channel layer in a lateral direction and subsequently drift towards the drain terminal through the non-porous aperture.

[0040] As will be described in more detail below, the porous region of the current blocking layer can be formed following the full epitaxial growth of all of the semiconductor layers of the CAVET. As such, the formation of the CBL comprising the porous region does not involve transfer to and from an epitaxial growth facility and a lithography facility. The full device layer stack can be epitaxially grown and the porous current blocking portions of the CBL can be formed after the epitaxial growth. As such, a semiconductor structure including the semiconductor layers for forming a CAVET can be transferred to a lithography facility in a one-way manner, which improves the throughput for the fabrication of a CAVET and can be integrated with conventional semiconductor device fabrication supply chains.

[0041] Figure 2 illustrates a CAVET 200 according to examples of the present disclosure. CAVET 200 comprises elements in common with CAVET 100 described above with respect to Figure 1. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0042] CAVET 200 comprises a CBL 240 comprising a first porous region 244 and a second porous region 246 disposed either side of aperture 242. In some examples, CBL 240 may comprise a lll-N semiconductor material such as GaN. It has been observed that porous GaN is highly resistive. As such, first porous region 244 and a second porous region 246 may act to block direct current flow from the source terminals 170, 180 to the drain terminal 110 through the drift layer 130. The first porous region 244 and a second porous region 246 thus maintain the formation of the 2DEG 152. Carriers may thus travel laterally along the 2DEG 152 in the channel layer 150 underneath the gate terminal 190. The carriers may then drift towards the drain terminal 110 through the aperture 242 and drift layer 130.

[0043] In some examples, the first porous region 244 and the second porous region 246 may comprise a porosity of at least 20 %.

[0044] In some examples, the first porous region 244 and the second porous region 246 may be oxidized. As will be described in more detail below, the first porous region 244 and the second porous region 246 may be oxidized following the porous etch. For example, the first porous region 244 and the second porous region 246 may be heated in an environment containing oxygen, such as by baking the first porous region 244 and the second porous region 246. In some examples, oxidizing the first porous region 244 and the second porous region 246 enhances the insulating properties of the first porous region 244 and the second porous region 246. The oxidation process oxidizes the pore walls of the porous regions 244, 246, which enhances the insulating properties and thus the current blocking capability of the porous regions 244, 246. The oxidized first porous region 244 and the second porous region 246 may thus further block direct current flow from the source terminals 170, 180 to the drain terminal 110 through the drift layer 130, and further maintain the 2DEG 152.

[0045] In one example, the drain semiconductor layer 120, the drift layer 130, the CBL 140, the channel layer 150 and the barrier layer 160 may comprise lll-N semiconductor material. In one example, the drain semiconductor layer 120, the drift layer 130, the CBL 140 and the channel layer 150 may comprise GaN and the barrier layer 160 may comprise AIGaN. In some examples, the aperture 242 may be doped n-type. In some examples, the aperture 242 may be heavily doped (n+). In some examples the aperture 242 may comprise an n-type carrier concentration of at least 1 x 1018cm-3. As will be described in more detail below, formation of the first porous region 244 and the second porous region 246 may comprise heavily doping the CBL 240 n-type and subjecting the CBL to an electrochemical etch process. The electrochemical etch process is specific to the n+ material, such that portions of the CBL 240 are porosified, but leave all other layers substantially unaffected. The aperture 242 may be protected by a mask and may thus remain non-porous, but comprise the n+ doping profile following the porous etch.

[0046] In other examples, however, the aperture region 242 may be lightly doped with n-type dopants (n-), undoped, or even be doped with p-type dopants. In such examples, the first and second porous regions 244, 246 may thus comprise a greater concentration of n- type dopants than the aperture 242. As will be described in more detail below, in some examples, the process to dope regions of the CBL n+ to form the first and second porous regions 244, 246 may involve ion implantation. During the ion implantation process, the aperture region 242 may be masked to prevent the aperture region 242 being doped n+. During the epitaxial growth of the material for forming the CBL 240, the material may be doped n-, p-type or may be undoped. As such, when the aperture region 242 is masked during the ion implantation process to form the n+ regions for forming the first and second porous regions 244, 246, the aperture region 242 may remain n-, p-type or undoped. In such examples, the aperture region being doped n-, p-type or undoped may increase the vertical voltage through the CAVET 100 and increase conductivity. In some examples, the n- carrier concentration may refer to a n-type carrier concentration of between 1 x 1015cm'3to 1 x 1017cm'3.

[0047] Drain semiconductor layer 120 may comprise a n+ doping profile. The n+ doping profile may provide a convenient surface such that the drain terminal 110 may form an ohmic contact on the drain semiconductor layer 120. As will be described in more detail below, the electrochemical etching process to selectively form the first and second porous regions 244, 246 may not result in etching to the drain semiconductor layer 120.

[0048] In some examples, the drift layer 130 may be doped n-type. The drift layer 130 may be lightly doped (n-) relative to a n+ doping profile. In some examples the drift layer 130 may comprise an n-type carrier concentration of 1 x 1015cm'3to 1 x 1017cm'3. In some examples, the doping concentration and the thickness of the drift layer 130 may be adjusted depending on the application of the CAVET 200.

[0049] Figures 3a-d illustrate process steps in a method for forming a semiconductor structure for forming a CAVET according to examples of the present disclosure. Process steps 300a-d comprises elements in common with CAVETs 100, 200 described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0050] Figure 3a illustrates a first step comprising a semiconductor structure 300a. Semiconductor structure 300a comprises a plurality of semiconductor layers 320 comprising the drain semiconductor layer 120, the drift layer 130, the CBL 240, the channel layer 150 and the barrier layer 160 all formed on a substrate 310. In one example, the plurality of semiconductor layers 320 may be epitaxially grown on the substrate 310. As described above, the drain semiconductor layer 120, the drift layer 130, the CBL 240, the channel layer 150 and the barrier layer 160 may each comprise a lll-N semiconductor material. For example, the drain semiconductor layer 120, the drift layer 130, the CBL 240 and the channel layer 150 may comprise GaN and the barrier layer 160 may comprise AIGaN. Substrate 310 may thus comprise a substrate on which lll-N semiconductor material may be epitaxially grown. For example, the substrate 310 may comprise GaN, SiC or Si. In some examples, one or more buffer layers may be present between the substrate 310 and the plurality of semiconductor layers 320. In some examples, the one or buffer layers may provide a crystallographic or chemical transition between the substrate 310 and the plurality of semiconductor layers 320.

[0051] CBL 240 may be heavily doped (n+). In some examples, CBL 240 may comprise a n- type carrier concentration of at least 1 x 1018cm'3. As will be described in more detail below, the semiconductor structure 300a may be subjected to an electrochemical etch that is selective to the n+ material. As such, portions of the CBL 240 may be porosified during the etch, with the remaining layers of the semiconductor structure 300a being substantially unaffected during the etch.

[0052] In some examples, the CBL 240 may be doped n+ during epitaxial growth of the CBL 240. However, in other examples, the CBL 240 may be doped n+ following formation of the CBL 240, and the layers grown thereon, by ion implantation. For example, the semiconductor layers 320 may be grown on the substrate 310 in an epitaxial facility. The semiconductor structure 300a may be transferred to a semiconductor device fabrication facility for forming a CAVET from the semiconductor structure 300a. Semiconductor device fabrication facilities more commonly comprise machinery capable of ion implantation than epitaxial growth. Thus, the CBL 240 may be doped n+ by ion implantation at the semiconductor device fabrication facility. Doping the CBL 240 using ion implantation thus provides greater design freedom in the supply chain for forming a CAVET, as the stage at which the CBL 240 can be doped n+ can take place either at an epitaxial facility or at a semiconductor device fabrication facility.

[0053] As described above, drift layer 130 may be doped n- and drain semiconductor layer 120 may be doped n+. Drift layer 130 and semiconductor layer 120 may be doped during epitaxial growth of the layers or using ion implantation.

[0054] Figure 3b illustrates a second process step comprising a semiconductor structure 300b. Semiconductor structure 300b illustrates that a mask 390 is applied to the barrier layer 160. As will be described in more detail below, during the electrochemical etch process, mask 390 may enable the formation of a non-porous aperture in the CBL 240. Mask 390 may thus comprise a material that is unaffected by the electrochemical etch and can shield the aperture from the porosification process. In some examples, the mask 390 may comprise a photoresist or a hard mask such as SiN.

[0055] In some examples, mask 390 may comprise a specially designed mask that is applied to the barrier layer 160 and subsequently removed following the electrochemical etch. However, in other examples, the mask 390 may comprise an element that is maintained on the barrier layer 160 following the electrochemical etch and used in the processing of a CAVET according to examples of the present disclosure. In one example, the mask 390 may comprise a material used for forming a gate. In such examples, the mask 390 may comprise the gate terminal, which may not be affected by the electrochemical etch. In such examples, the mask 390 may comprise, for example, Pt which may not be affected by the electrochemical etch and may be used for forming a gate terminal of a CAVET.

[0056] In some examples, the mask 390 may mask regions of the CBL 240 during ion implantation to dope regions of the CBL 240 n+. As described above, in some examples, the CBL 240 may be doped n+ via an ion implantation process. In a further example, the semiconductor structure 300b may undergo the ion implantation process following application of mask 390. Mask 390 may prevent a region of the CBL 240 from being doped n+ during the ion implantation process. This region may further correspond to the non-porous aperture region for the CAVET. As such, following fabrication of a CAVET from semiconductor structure 300b, the aperture region may not be doped n+. For example, the aperture region may be undoped. In another example, the aperture region may be lightly doped with n-type dopants (n-) or even doped with p-type dopants. For example, during epitaxial growth of the CBL 240, the layer may be doped n-, p-type or undoped. The mask 390 may be applied to the semiconductor structure 300c, which is subjected to an ion implantation process to form n+ regions in the CBL 240. However, mask 390 masks the aperture region(s) of the semiconductor structure 300c, which remain n-, p-type or undoped. As will be described in more detail below, in such examples, where the aperture region is n-, p-type or undoped, the aperture region may be substantially unaffected by the porous etch to form the porous region(s) of the CBL 240. In such examples, the n-, p-type or undoped doping profile of the aperture region of the CBL 240 may increase the vertical voltage drop between the source terminals and drain terminal of a CAVET fabricated from semiconductor structure 300b, which increases conductivity of the CAVET.

[0057] Figure 3c illustrates a third process step comprising a semiconductor structure 300c. Semiconductor structure 300c illustrates that the CBL 240 has been subjected to an electrochemical etch to form the aperture 242, the first porous region 244 and the second porous region 246. The electrochemical etch process may involve submerging the semiconductor structure 300c in an electrolyte solution along with an electrode. The semiconductor structure 300c and the electrode are connected to an electrical source, such that the semiconductor structure 300c acts as the anode and the electrode acts as the cathode. An electrical potential is applied to the semiconductor structure 300c and the electrode to form pores in the CBL 240. The electrochemical reaction is selective to layers that are heavily doped n-type. Thus, during the electrochemical reaction, pores are formed in the CBL 240 to form the first porous region 244 and the second porous region 246.

[0058] As described above, drain semiconductor layer 120 may be heavily doped n+. However, semiconductor structure 300c may be orientated in the electrolyte solution with the electrode such that pores are formed in the CBL 240, but not the drain semiconductor layer 120 during the electrochemical etch. For example, the uppermost surface of the semiconductor structure 300c, as illustrated in Figure 3c, may face the electrode in the electrolyte. In this orientation, the formation of pores in the n+ layers may be formed in the direction X from the top of the semiconductor structure 300c towards the bottom of the semiconductor structure 300c. The pores form in the n+ layers in the direction X from the application of a current to the electrode and the semiconductor structure 300c in the electrolyte solution. The application of the current can thus be controlled to control the depth of the formation of the pores in the semiconductor structure 300c. The application of the current can therefore be controlled such that pores are formed in the CBL 240, but not in the drain semiconductor layer 120. For example, the current may be applied for a duration of time such that pores are formed in the CBL 240 and other portions of the semiconductor structure 300 are substantially unaffected.

[0059] The electrochemical etch thus provides a process where pores are formed in the CBL 240 and the other layers within the semiconductor structure 300c are substantially unaffected by the etching process.

[0060] As further illustrated in Figure 3c, the pores are formed in first porous region 244 and the second porous region 246 of the CBL 240, but the aperture 242 remains non-porous. The semiconductor structure 300c may thus be arranged in the electrolyte with the electrode in such a way that the mask 390 masks the aperture 242 from the applied electric potential to prevent pores from forming in the aperture 242. For example, the uppermost surface of the mask 390, as illustrated in Figure 3c may face the electrode in the electrolyte.

[0061] In some examples, as illustrated in Figure 3c, the mask 390 may substantially align with aperture 242 such that edges of the mask 390 may substantially align with edges of the aperture 242. However, in other examples, the mask 390 may overlie the aperture 242 such that the mask 390 is wider than the aperture 242 and the edges of the mask 390 extend laterally across the semiconductor structure 300c to a greater extent than the edges of the aperture 242. In such examples, the electrochemical porous etch may undercut the mask 390 such that pores are formed in at least some of the area under the mask 390. Thus, in some examples, the mask 390 may overlie at least a portion of the first porous region 244 and the second porous region 246. For example, referring briefly to Figure 2, gate terminal 190 overlies at least a portion of the first porous region 244 and the second porous region 246. Thus, in examples, where the mask 390 comprises the gate terminal 190, the mask 390 may overlie at least a portion of the first porous region 244 and the second porous region 246, as well as the aperture 242. Referring again to Figure 3c, in examples according to the present disclosure, the electrochemical etch may thus be tailored to form an aperture 242 of the desired size. For example, the voltage applied during the electrochemical etch and / or the time of the electrochemical etch may be adjusted to form an aperture 242 of the desired size.

[0062] As described above, in some examples, the aperture 242 may be undoped, or may be doped n- or p-type during the epitaxial growth of the CBL 240. In such examples, mask 390 may be removed from the semiconductor structure 300c prior to the electrochemical etch process. As the aperture 242 is not doped N+, pores may not form in the aperture 242 during the electrochemical etch process. In such examples, mask 390 may not be used to protect the aperture 242 during the electrochemical etch process.

[0063] Figure 3d illustrates a fourth process step comprising a semiconductor structure 300d. Semiconductor structure 300d illustrates that the mask 390 has been removed. In some examples, once the aperture 242, first porous region 244 and second porous region 246 have been formed in the CBL 240, the mask 390 may be removed. The semiconductor structure 300d may thus subsequently be processed into a CAVET, such as CAVET 200 described above. For example, source and gate terminals may be formed through the barrier layer 160 and the substrate 310 may be removed and a drain terminal may be formed on the drain semiconductor layer 120.

[0064] As described above, in other examples, mask 390 may be maintained on the barrier layer 160 following the electrochemical etch process. For example, the mask 390 may comprise a gate dielectric or a gate terminal. The mask 390 may thus be used in the formation of a CAVET according to examples of the present disclosure.

[0065] It will be appreciated that the process steps illustrated in Figures 3a-d may illustrate a portion of a semiconductor structure forming a CAVET. For example, the process steps illustrated in Figures 3a-d may illustrate a portion of a semiconductor wafer from which many CAVET devices may be formed. As such, mask 390 may illustrate one of a plurality of masks that may be applied to a semiconductor structure and aperture 242 may illustrate one of a plurality of apertures formed in the CBL 240 across the semiconductor wafer. In such examples, it will therefore be appreciated that whilst CBL 240 is illustrated as comprising a first porous region 244 and a second porous region 246, the first porous region 244 and the second porous region 246 may be part of the same porous region across the CBL 240, with a plurality of apertures formed in the porous region due to the plurality of masks. For example, Figure 4a illustrates an aerial view of a CBL 240a of a semiconductor structure for forming a CAVET. The CBL 240a comprises a plurality of apertures 242a-d formed in a porous region 244. Semiconductor structure 400 may thus be processed into four CAVETs, each one comprising one of the plurality of apertures 242a-d. In one example, as illustrated in Figure 4b, each CAVET may comprise a CBL 240b comprising a first porous region 244 and a second porous region 246 separated by aperture 242. However, in other examples, such as illustrated in Figure 4c, each CAVET may comprise a CBL 240c comprising a porous region 244 and an aperture 242 formed in the porous region 242. One skilled in the art will understand that Figure 4a-c are examples and that an aperture may be formed in a CBL according to examples of the present disclosure in a variety of manners.

[0066] Examples according to the present disclosure thus present a CAVET where the CBL may be formed from porous semiconductor material. The porous semiconductor material, such as porous GaN, may be highly resistive and thus may effectively block current between a source terminal and drain terminal and maintain the 2DEG in a CAVET. The current blocking regions of the CBL may be substantially porous throughout. However, in other examples the current blocking regions of the CBL may comprise a superlattice formed of porous and non-porous sub-regions.

[0067] Figure 5 illustrates a CAVET 500 according to examples of the present disclosure. CAVET 500 comprises elements in common with CAVETs 100, 200 described above with respect to Figures 1 and 2. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0068] CAVET 500 comprises a first porous region 344 comprising a first porous sub-region 345a, a second porous sub-region 345b and a third porous sub-region 345c. First porous region 344 further comprises a first non-porous region 347a and a second non-porous sub-region 347b. First porous region 344 thus comprises a first plurality of porous subregions 345a-c separated by a plurality of non-porous sub-regions 347a-b.

[0069] CAVET 500 further comprises a second porous region 346 comprising a fourth porous sub-region 348a, a fifth porous sub-region 348b and a sixth porous sub-region 348c. Second porous region 346 further comprises the first non-porous region 347a and the second non-porous sub-region 347b. First porous region 344 thus comprises a second plurality of porous sub-regions 348a-c separated by the plurality of non-porous subregions 347a-b.

[0070] CAVET 500 further comprises aperture 342. Aperture 342 comprises a first sub-region 349a, a second sub-region 349b and a third sub-region 349c. Aperture 342 further comprises the first non-porous region 347a and the second non-porous sub-region 347b. Aperture 342 thus comprises a plurality of sub-regions 349a-c separated by the plurality of non-porous sub-regions 347a-b. In some examples, the plurality of sub-regions 349a- c are heavily doped n+.

[0071] First porous region 344 and second region 346 may thus each comprise a superlattice formed by a plurality porous sub-regions 345a-c, 348a-c, separated by a plurality of non- porous regions 347a-b. As will be described in more detail below, the superlattice of the first porous region 344 and the second porous region 346 may be formed by depositing a plurality of semiconductor layers to form the CBL 240 on the drift layer 130. The plurality of semiconductor layers may be alternately doped n+, where the intervening layers are undoped or unintentionally doped. The CBL 240 may be subjected to an electrochemical etch to porosify the n+ layers to form the plurality porous sub-regions 345a-c, 348a-c. As the etch is selective to the n+ semiconductor layers, the non-porous regions 347a-b may be unaffected by the porous etch.

[0072] Aperture 342 additionally comprises a superlattice formed by the plurality of sub-regions 349a-c, separated by the non-porous regions 347a-b. The plurality of sub-regions 349a- c may thus comprise part of the n+ semiconductor layers for forming the plurality porous sub-regions 345a-c, 348a-c. In a similar manner to that described above, during the porous etch, the aperture 342 may be masked such that the n-type semiconductor regions 349a-c are not porosified during the porous etch. The plurality of sub- regions 349a-c may thus be doped n+ and are separated by undoped or unintentionally doped regions 347a-b. The difference in charge between the n+ semiconductor regions 349a- c and the undoped or unintentionally doped regions 347a-b may thus grade the electric potential through the aperture 342 and provide a voltage drop across the aperture 342. The grading and voltage drop may improve the drain bias control and reliability of the CAVET 500. In other examples, the aperture 342 may not comprise the plurality of sub-regions 349a- c, separated by the non-porous regions 347a-b and may instead comprise a non-porous bulk material. The bulk material may be doped n-, p-type or undoped. In a similar manner to that described above, in some examples, the n+ regions for forming the plurality porous sub-regions 345a-c, 348a-c may be formed by ion implantation. In such examples, a bulk material may be epitaxially deposited on the drift layer 130, which is doped n-, p-type or undoped. The aperture region 343 may be masked and ions implanted into the bulk material to form the n+ regions for the formation of the plurality porous sub-regions 345a-c, 348a-c. The ion implantation process can be controlled to form a plurality of n+ layers at the appropriate depth into the CBL 240. The n-, p-type or undoped bulk material of the aperture 343 may thus be unaffected by the electrochemical etch to form the plurality porous sub-regions 345a-c, 348a-c.

[0073] Figures 6a-d illustrate process steps in a method for forming a semiconductor structure for forming a CAVET according to examples of the present disclosure. Process steps 600a-d comprises elements in common with CAVETs 100, 200, 500 and semiconductor structures 300a-d described above. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0074] Figure 6a illustrates a first step comprising a semiconductor structure 600a. Semiconductor structure 600a comprises a plurality of semiconductor layers 320 formed on the substrate 310. As described above, the plurality of semiconductor layers 320 may comprise lll-N semiconductor material.

[0075] CBL 240 comprises a plurality of n-type semiconductor sub-layers 640a-c separated by a plurality of undoped semiconductor layers 347a-b. The n-type semiconductor sublayers 640a-c may comprise a heavily doped (n+) doping profile. In some examples, the n-type semiconductor sub-layers 640a-c may comprise a doping concentration of at least 1 x 1018cm'3. As similarly described above, the n-type semiconductor sub-layers 640a- c may be doped n-type during the epitaxial growth of the n-type semiconductor sublayers 640a-c. Alternatively, the n-type semiconductor sub-layers 640a-c may be doped n-type following their epitaxial growth by ion implantation. In some examples, the undoped semiconductor layers 347a-b may in fact be unintentionally doped and comprise a relatively low concentration of n-type dopants. During epitaxial growth of the n-type semiconductor sub-layers 640a-c, dopants may drift into the semiconductor layers 347a-b where the semiconductor layers 347a-b may thus be unintentionally doped.

[0076] CBL 240 thus comprises a plurality of n-type semiconductor sub-layers 640a-c separated by a plurality of undoped semiconductor layers 347a-b. As will be described in more detail below, semiconductor structure 600a may subjected to an electrochemical etching process, which is selective to the n-type semiconductor sub-layers 640a-c to form porous regions within the n-type semiconductor sub-layers 640a-c. As the etch is selective to n+ semiconductor layers, the layers of the semiconductor structure which are not n+ may be substantially unaffected by the electrochemical etch.

[0077] Figure 6b illustrates a process step comprising semiconductor structure 600b. Semiconductor structure 600b comprises a mask 390 applied to the semiconductor structure 600b. In a similar manner to that described above in relation to semiconductor structure 300b, mask 390 may prevent pores being formed across a region of the CBL 240 to form an aperture through the CBL 240.

[0078] Figure 6c illustrates a process step comprising semiconductor structure 600c. Semiconductor structure 600c illustrates that aperture 342, first porous region 344 and second porous region 346 are formed in CBL 240. In a similar manner to that described above for process step 300c, semiconductor structure 600c may be subjected to an electrochemical etch to form first porous region 344 and second porous region 346. The electrochemical etch may thus form pores within the n-type semiconductor layers 640a- c to form the first plurality of porous sub-regions 345a-c and the second plurality of porous sub-regions 347a-c.

[0079] The mask 390 may be arranged such that a plurality of non-porous n-type portions 349a- c are formed in the CBL 240 to form part of the aperture 342. The mask 390 masks the n-type portions 349a-c from the porous etch, such that, pores are not formed in the non- porous n-type portions 349a-c. The non-porous n-type portions 349a-c may thus not comprise highly resistive material and may allow carriers to drift through the aperture 342.

[0080] In a similar manner to that described above, in some examples, the first porous region 344 and the second porous region 346 may undercut the mask 390. Thus, in some examples, the mask 390 may at least partly overlie the first plurality of porous subregions 345a-c and the second plurality of porous sub-regions 348a-c.

[0081] Figure 6d illustrates a process step comprising semiconductor structure 600d. Semiconductor structure 600d illustrates that mask 390 may be removed from the semiconductor structure 600d following the electrochemical etch. In a similar manner to that described above for semiconductor structure 300d, semiconductor structure 600d may be processed to form a CAVET. For example, source and gate terminals may be formed on barrier layer 160 and substrate 310 may be removed and a drain terminal may be formed on drain semiconductor layer 120.

[0082] As similarly described above, in some examples, mask 390 may be maintained on the semiconductor structure 600d and form part of a CAVET. For example, the mask 390 may comprise a gate terminal.

[0083] As similarly described above, in some examples, the aperture 342 may not comprise a plurality of sub-regions and may instead comprise a non-porous bulk material. The bulk material may be doped n-, p-type or undoped. For example, a bulk semiconductor material for forming the CBL may be deposited on the drift layer 130. The bulk semiconductor material may be n-, p-type or undoped. The n+ regions for the formation of the first plurality of porous sub-regions 345a-c and the second plurality of porous subregions 348a-c may be formed by ion implantation. Prior to the ion implantation process a mask 390 may be applied to mask the aperture 342 from the ion implantation process. The aperture may thus not be doped during the ion implantation process and remain n-, p-type or undoped. The mask 390 may be removed and the semiconductor structure may be subjected to the electrochemical etch to form the first plurality of porous subregions 345a-c and the second plurality of porous sub-regions 348a-c. As the aperture 342 is not doped n+, it is left substantially unaffected following the porous etch process.

[0084] The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for managing or transferring power. In some examples the semiconductor device may comprise one of: a high electron mobility transistor (HEMT) or a CAVET. In some examples, the semiconductor device may comprise a device with a vertical architecture. The present disclosure further provides a power management device comprising a semiconductor device according to examples of the present disclosure.

[0085] In some examples the power management device may manage or transfer power within a vehicle, industrial machine or power infrastructure equipment. In some examples the power management device may comprise a power supply or power converter, such as a DC-DC converter, an AC-DC converter, a DC-AC converter or similar. In some examples the power management device may comprise a device for converting electrical energy to kinetic energy, such as a traction inverter or similar. In some examples the power management device may comprise a device for charging a battery, such as an onboard charger (OBC), a wireless charging device, or similar. In some examples the power management device may comprise a motor or a motor drive. In some examples the power management device may comprise a device for use in an energy storage system (ESS), such as a fuel cell inverter, ESS DC-DC converter or similar. In some examples the power management device may comprise a device for inputting power to, or outputting power from the grid, such as a three-phase inverter, three-phase rectifier, or similar.

[0086] The present disclosure thus further provides a vehicle comprising a power management device according to examples of the present disclosure. In some examples the vehicle may comprise an automotive vehicle such as a car, a van, a heavy goods vehicle (HGV), a bus, a motorbike, or similar. In some examples the vehicle may comprise an aviation vehicle, such as an aeroplane, helicopter, or similar. In some examples the vehicle may comprise an aeronautical vehicle, such as a boat, ship or similar.

[0087] In some examples the power management device according to examples of the present disclosure may manage or transfer power for an electronic device for user operation, for example a mobile phone, cell phone, smart phone, tablet computer, wearable computer such as a watch, or similar. In some examples the power management device may comprise a charging device such as a charger, an adapter, a wireless charger, or similar for charging a battery or on-board power source of an electronic device. In some examples the power management device may comprise a power supply housed in an electronic device for user operation, such as a power converter, for example a DC-DC converter, an AC-DC converter, a DC-AC converter or similar. The present disclosure thus further provides an electronic device comprising a power management device according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console, or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar.

[0088] It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A CAVET comprising: a drain terminal; a source terminal; and a current blocking layer, CBL between the drain terminal and the source terminal, wherein the CBL comprises at least one porous region for blocking current between the source terminal and the drain terminal and a non-porous aperture region for allowing current flow between the source terminal and the drain terminal.

2. The CAVET according to claim 1 wherein the at least one porous region comprises a first porous region and a second porous region disposed either side of the aperture region.

3. The CAVET according to claim 2 comprising a first source terminal and a second source terminal; and wherein the first source terminal is over the first porous region and the second source terminal is over the second porous region.

4. The CAVET according to any preceding claim wherein the at least one porous region comprises a plurality of porous sub-regions separated from each other by a plurality of non-porous sub-regions.

5. The CAVET according to claim 4 wherein the aperture region comprises a plurality of second sub-regions separated by the plurality of non-porous subregions.

6. The CAVET according to any preceding claim further comprising a gate terminal over the CBL; and wherein edges of the gate terminal overlap with edges of the aperture region.

7. The CAVET according to any preceding claim wherein the at least one porous region comprises an oxidized porous region.

8. The CAVET according to any preceding claim further comprising a plurality of III- N semiconductor layers comprising the CBL.

9. The CAVET according to any preceding claim wherein the at least one porous region comprises a greater concentration of n-type dopants than the non-porous aperture region.

10. A semiconductor structure comprising: a substrate; and a plurality of semiconductor layers over the substrate comprising a first III- N semiconductor layer comprising a porous region and a non-porous region.

11. The semiconductor structure according to claim 10 wherein the porous region comprises a plurality of porous sub-regions separated from each other by a plurality of non-porous sub-regions.

12. The semiconductor structure according to claim 10 or 11 wherein the non-porous region comprises a plurality of second sub-regions separated by the plurality of non-porous sub-regions.

13. The semiconductor structure according to any of claims 10-12 wherein the at least one porous region comprises a greater concentration of n-type dopants than the non-porous region.

14. The semiconductor structure according to any of claims 10-13 wherein the porous region comprises an oxidized porous region.

15. The semiconductor structure according to any of claims 10-14 wherein the first semiconductor layer comprises a current blocking layer, CBL, and wherein the plurality of semiconductor layers comprise: a drain semiconductor layer; a drift layer over the drain semiconductor layer; the CBL over the drain semiconductor layer, a channel layer over the CBL; and a barrier layer over the channel layer.

16. The semiconductor structure according to claim 15 wherein the plurality of semiconductor layers comprise lll-N semiconductor material.

17. A semiconductor device comprising the semiconductor structure according to any of claims 10-16.

18. A power management device comprising the semiconductor device according to claim 17 or the CAVET according to any of claims 1-9.

19. An electronic device comprising the power management device according to claim 18.

20. A vehicle comprising the power management device according to claim 18.

21. A method of forming a semiconductor structure comprising: forming a plurality of semiconductor layers over a substrate; and forming a porous region and a non-porous region in a first lll-N semiconductor layer of the plurality of semiconductor layers.

22. The method of claim 21 further comprising doping the first semiconductor layer n-type and wherein forming the at least one porous region comprises electrochemically etching the first semiconductor layer.

23. The method according to claim 22 wherein forming the plurality of semiconductor layers comprises forming a second semiconductor layer over the first semiconductor layer; and wherein doping the first semiconductor layer comprises implanting ions into the first semiconductor layer after forming the second semiconductor layer.

24. The method according to any of claims 21-23 further comprising forming a plurality of non-porous regions in the porous region of the first semiconductor layer.

25. The method according to any of claims 21-24 further comprising applying a mask over the plurality of semiconductor layers, and responsive to applying the mask, porosifying at least one region of the first semiconductor layer to form the porous region and the non-porous region.

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