Super junction semiconductor device

Abstract

The disclosure relates to a super junction semiconductor device 100 with monolithically integrated trench-gate and planar-gate. The super junction semiconductor device comprises: a substrate (1); a drift layer (3) formed above the substrate (1); a vertical channel section (4, 7, 8, 9) formed above the drift layer (3), the vertical channel section (4, 7, 8, 9) comprising a current spreading layer (4), a body-body separation region (7), a mesa body region (8) and a mesa source region (9); a planar channel section (4, 5, 6) formed above the drift layer (3) and below a trench (111) that is formed on both sides of the vertical channel section (4, 7, 8, 9), the planar channel section (4, 5, 6) comprising a layer stack of the current spreading layer (4), a trench body region (5) and a trench source region (6); and a pillar region (11) formed in the drift layer (3) below the trench body region (5), the pillar region (11) and the drift layer (3) forming a super junction (120).

Description

[0001] SUPER JUNCTION SEMICONDUCTOR DEVICE

[0002] TECHNICAL FIELD

[0003] The disclosure relates to the field of Power Semiconductor Technologies such as Silicon, Silicon Carbide, Gallium Nitride, etc. The disclosure relates to a super junction semiconductor device and a method for manufacturing such super junction semiconductor device.

[0004] BACKGROUND

[0005] The Super Junction (SJ) concept is widely used in many power semiconductor technologies such as Si, SiC, GaN, etc. The realization of a SJ power device is relying on the formation of two regions (called pillars) of opposite doping along a specific distance. The formation of the pillars is a technological challenge. Pillars may be formed by implantation including multi epitaxy and multi-implant or by trench re-fill including trench etch and epi regrowth. To be able to use a SJ power semiconductor switching device, the SJ feature needs to be connected to a gate to form a power device. All concepts of Super junction devices are structures containing a gate and a drift region. A main disadvantage of existing super junction devices seems the nonoptimized gate resistivity, i.e., current conduction. The main focus of existing solutions is to reduce the resistivity of the drift region by the SJ concept; however, this approach is not optimal since the current will also be limited by the resistivity of the gate region.

[0006] SUMMARY

[0007] This disclosure provides a solution for overcoming the above limitations in super junction devices due to non-optimal resistivity of drift region and gate region.

[0008] This disclosure provides a solution for optimizing the full power device resistivity of a super junction device. Furthermore, a Silicon Carbide (SiC) super junction device with integrated trench and planar MOSFET gates is disclosed. The foregoing and other objectives are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0009] Embodiments of the disclosure present a solution to optimize the full power device resistivity by associating the SJ drift region with a gate region that has a better conduction performance (thus lower resistivity) due to the use of multiple conducting channels.

[0010] The solution presented in this disclosure is a new Super Junction device formed by a monolithic integration of a Spacer based Gate, containing a vertical channel and a planar channel, in which the super junction is formed in the drift region below the body of the planar MOSFET.

[0011] The solution described hereinafter is applicable to any power conversion system or architecture using semiconductor power devices. The solution is applicable when high blocking voltage, high current density and high switching frequency are required. The solution is applicable in inductively switching circuits. The solution is applicable to all power electronic systems targeting energy loss, application size and total application cost reduction.

[0012] The products in which the disclosed solution can be applied are all power electronics products, particularly DC and AC converters used in photovoltaics, electric vehicles, chargers and onboard chargers, data centers, railway, telecom, servers and others.

[0013] In order to describe the disclosure in detail, the following terms and notations will be used.

[0014] MOS Metal Oxide Semiconductor

[0015] FET Field Effect Transistor

[0016] MOSFET Metal Oxide Semiconductor Field Effect Transistor

[0017] IGBT Insulated Gate Bipolar Junction Transistor

[0018] SiC Silicon Carbide

[0019] CSL Current Spreading Layer

[0020] JFET Junction Field Effect Transistor

[0021] SBD Schottky Barrier Diode JSBD Junction Schottky Barrier Diode

[0022] SSF Shockley Stacking Faults

[0023] BPD Basal Plane Dislocations

[0024] SJ Super Junction

[0025] Device active area - area which conducts a forward electric current; it is smaller than a device total area

[0026] Device total area - can be understood as a chip (die) area; consists of the active area and all peripheries, e.g., an edge termination, scribe lines (dicing streets), contact pads (e.g. a gate contact) and others

[0027] Forward electric current - a main electric current flowing through a device during its on-state

[0028] Edge termination - a region extending outside of the active area whose function is to reduce an electric field in outer part of a device

[0029] Source - a region in MOSFET which injects majority carriers during the on-state

[0030] Drain - a region in MOSFET which collects majority carriers during the on-state

[0031] Emitter - a region in IGBT which injects majority carriers during the on-state

[0032] Collector - a region in IGBT which collects majority carriers and injects minority carriers during the on-state

[0033] Majority carriers - electric carriers (electrons or holes) which dominate in the forward electric current conduction; their density is much bigger higher than the density of minority carriers

[0034] Minority carriers - electric carriers (electrons or holes) whose density is much lower than the density of the majority carriers Gate - a voltage-controlled region in MOSFET or IGBT which switches a device between the on- state and the off- state

[0035] Drift layer - a region in MOSFET or IGBT which conducts the electric current in the on-state and sustains the largest portion of an applied voltage (blocking voltage) in the off-state (blocking state)

[0036] Channel - a region in a body region of MOSFET or in a base region of IGBT to which the electric carriers are injected from the source or from the emitter, respectively, and whose conduction is controlled by the gate

[0037] Body region - a region in MOSFET of an opposite doping type to the doping type of the source and drift layer, which contains the channel and which creates a pn-junction with the drift layer

[0038] Base region - a region in IGBT of an opposite doping type to the doping type of the source and drift layer, which contains the channel and which creates a pn-junction with the drift layer

[0039] JFET region - a region between the body regions or base regions of MOSFET or IGBT, respectively

[0040] CSL - a region below the JFET region whose function is to spread the electric current in order to reduce an on-state resistance

[0041] SJ - The main idea of super junction is to enhance a two-dimensional (2D) depletion of a drift region (instead of ID). As a result, there is a significant increase in the voltage capability (breakdown voltage) or an increase in the current capability (a decrease in Rdson) or a reduction of the Epi thickness (epitaxy cost).

[0042] Super junction devices are structures including a gate, e.g., MOSFETs, IGBTs, etc. in planar, trench or groove trench implementations, JFETs with JFET gate, or diodes without gate; and a drift region, e.g., vertical or lateral devices containing alternating Ptype and Ntype regions (pillars). According to a first aspect, the disclosure relates to a super junction semiconductor device with monolithically integrated trench-gate and planar-gate, the super junction semiconductor device comprising: a substrate being arranged at a bottom surface of the super junction semiconductor device; a drift layer formed above the substrate; a buffer layer placed on top of the substrate and below the drift layer; a vertical channel section formed above the drift layer, the vertical channel section comprising a current spreading layer, a body-body separation region, a mesa body region and a mesa source region; a planar channel section formed above the drift layer and below a trench that is formed on both sides of the vertical channel section, the planar channel section comprising a layer stack of the current spreading layer, a trench body region and a trench source region; and a pillar region formed in the drift layer below the trench body region, the pillar region and the drift layer forming a super junction.

[0043] Such a semiconductor device represents a new Super Junction device formed by a monolithic integration of a Spacer based Gate, containing a vertical channel and a planar channel, in which the super junction is formed in the drift region below the trench body region.

[0044] This allows maximizing the current capability of the device by reducing at the same time the resistance of the drift region (via the use of the SJ) and the channel resistance (via the use of the spacer-based-Gate module providing multiple channels).

[0045] In an exemplary implementation of the semiconductor device, the pillar region is placed side- by-side with the drift layer; and the pillar region is vertically extending from the trench body region into the drift layer. Accordingly, the pillar regions can help depletion of the drift region.

[0046] In an exemplary implementation of the semiconductor device, the pillar region electrically contacts the current spreading layer and the trench body region. Accordingly, the pillar region allows to enhance 2D depletion of the drift region.

[0047] The above implementations are further described below with respect to Figure 1.

[0048] In an exemplary implementation of the semiconductor device, the trench is formed next to the vertical channel section above the buffer layer along a first direction; wherein the trench comprises a trench bottom and at least one trench side wall, the semiconductor device comprising: a body contact region formed in the planar channel section and in the vertical channel section along a second direction parallel to the bottom surface, the body contact region configured to electrically connect the trench body region of the planar channel section with the mesa body region of the vertical channel section by a metallization. This improves integration of trench-gate with planar gate together with a super junction.

[0049] The above implementation is further described below without reference to any specific Figure. The metallization is not shown in the Figures.

[0050] In an exemplary implementation of the semiconductor device, the body contact region comprises a first part formed in the planar channel section and a second part formed in the vertical channel section; wherein the first part of the body contact region is separated from the second part of the body contact region. Accordingly, the body contact region may be separately implemented in both channel sections, the vertical and the planar channel sections. The body contact region may also be formed in the third dimension.

[0051] The above implementations are further described below with respect to Figures 2a, 2b, 3a and 3b.

[0052] In an exemplary implementation of the semiconductor device, the first part of the body contact region is implanted self-aligned through a spacer on the trench body region. These self-aligned processing steps provide precise control of the body and are independent towards unwanted misalignments which results in improvement of the device performance and less variability of the performance over the dies of a wafer.

[0053] The above implementations are further described below with respect to Figures 2a, 2b, 3a and 3b.

[0054] In an exemplary implementation of the semiconductor device, the first part of the body contact region extends to the at least one trench side wall. Accordingly, an improved contact between the trench side wall and the first part of the body contact region can be provided. The above implementation is further described below without reference to a specific Figure.

[0055] In an exemplary implementation of the semiconductor device, the first part of the body contact region is spaced from the at least one trench side wall. Accordingly, the trench body region may be filled in the space between the first part of the body contact region and the at least one trench side wall and different designs of such trench body region can be implemented.

[0056] The above implementation is further described below with respect to Figure 2a.

[0057] In an exemplary implementation of the semiconductor device, the first part of the body contact region extends to an edge of the trench source region. This provides design flexibility for implementing the body contact region.

[0058] The above implementation is further described below with respect to Figure 2b.

[0059] In an exemplary implementation of the semiconductor device, the first part of the body contact region is spaced from an edge of the trench source region. This also provides design flexibility for implementing the body contact region.

[0060] The above implementation is further described below with respect to Figures 3a and 3b.

[0061] In an exemplary implementation of the semiconductor device, the first part of the body contact region is separating the trench source region in at least two parts. This provides design flexibility for implementing the body contact region.

[0062] The above implementation is further described below with respect to Figure 3a.

[0063] In an exemplary implementation of the semiconductor device, the first part of the body contact region forms a stripe along the first direction in parallel to the trench source region. This also provides design flexibility for implementing the body contact region. The above implementation is further described below with respect to Figures 4 and 5a.

[0064] In an exemplary implementation of the semiconductor device, the first part of the body contact region is formed in a discontinuous way along the first direction. Accordingly, different patterns can be formed by the body contact region.

[0065] The above implementation is further described below with respect to Figure 5b.

[0066] In an exemplary implementation of the semiconductor device, the pillar region is implanted self-aligned through a spacer in the drift layer. These self-aligned processing steps provide precise control of the body and are independent towards unwanted misalignments which results in improvement of the device performance and less variability of the performance over the dies of a wafer.

[0067] The above implementation is further described below with respect to Figure 6 corresponding to Embodiment 3.

[0068] In an exemplary implementation of the semiconductor device, the pillar region penetrates the drift layer with or without reaching the buffer layer; or wherein the pillar region penetrates the drift layer and the buffer layer with or without reaching the substrate. This allows design flexibility. The pillar region can be formed according to design requirements. The size of the super junction section can be designed by design of the pillar regions.

[0069] The above implementation corresponds to Embodiment 4.

[0070] In an exemplary implementation of the semiconductor device, a width of the pillar region is designed to vary along a vertical direction of the semiconductor device, wherein the vertical direction is defined from a top surface to the bottom surface of the semiconductor device. The implementation may be designed in such a way that the width of the pillar in the top part is larger than its width at the bottom part or vice versa. In an exemplary implementation of the semiconductor device, the pillar region is formed by a plurality of successive self-aligned implantations through corresponding spacers in the drift layer.

[0071] The above implementation is further described below with respect to Figure 7 corresponding to Embodiment 3.

[0072] According to a second aspect, the disclosure relates to a method for manufacturing a super junction semiconductor device, the method comprising: forming a mask in a die layer, the mask comprising a trench, the trench comprising a trench bottom and trench side walls; implanting a dopant to the trench to form a first dopant implantation region below the trench bottom; forming a spacer at the trench sidewalls; and implanting a dopant to the trench which trench sidewalls are covered by the spacer to form a second dopant implantation region below the first dopant implantation region; wherein a thickness of the spacer is designed to match a width of a second dopant diffusion region in a lateral direction to a width of a first dopant diffusion layer in the lateral direction, wherein the second dopant diffusion layer is formed by a diffusion or scattering of the second dopant implantation region in the lateral direction; and wherein the first dopant diffusion layer is formed by a diffusion or scattering of the first dopant implantation region in the lateral direction; wherein the first dopant implantation region and the second dopant implantation region together with the first dopant diffusion layer and the second dopant diffusion layer form a pillar region of the semiconductor device, wherein the pillar region and a drift layer formed in the die layer are forming a super junction.

[0073] By such a method a semiconductor device representing a new Super Junction device can be manufactured which can be formed by a monolithic integration of a Spacer based Gate, containing a vertical channel and a planar channel, in which the super junction is formed in the drift region below the trench body region.

[0074] Note that dopant diffusion can also happen in the vertical direction (not discussed further since it is not further relevant to this disclosure). The term “matched” means here not only alignment in the sense that both dopant diffusion regions laterally extend such that their lateral surfaces are positioned on the same plane but also designs where the first diffusion layer has a pre-defined width relation to the second diffusion layer, i.e., the lateral surface of the first diffusion layer is in a pre-defined distance to the lateral surface of the second diffusion layer. In the embodiments shown below, designing this width relation is an important aspect.

[0075] The matching of the extension of the second dopant diffusion region in the lateral direction with the extension of the first dopant diffusion layer in the lateral direction can be efficiently performed by using an appropriate spacer. By such implantation steps and diffusion / scattering steps together with the spacer, the width of the diffusion layers can be optimally controlled or designed.

[0076] As mentioned above, dopant diffusion can also happen in the vertical direction which is not discussed further since it is not further relevant to this disclosure. It is to be understood that this vertical diffusion is also covered by this disclosure.

[0077] In an exemplary implementation of the method, the first dopant implantation region is formed by another spacer. Different spacer processes may be applied to improve formation of the super junction.

[0078] In an exemplary implementation of the method, the first dopant implantation region is formed by a first self-aligned implantation to the trench; and the second dopant implantation region is formed by a second self-aligned implantation to the trench which trench sidewalls are covered by the spacer.

[0079] As described above, these self-aligned implantations provide precise control of the body and are independent towards unwanted misalignments which results in improvement of the device performance and less variability of the performance over the dies of a wafer.

[0080] In an exemplary implementation of the method, the method comprises: removing the mask and the spacer and forming another die layer on top of the first dopant implantation region; forming a further mask in the second die layer, the further mask comprising a trench, the trench comprising a trench bottom and trench side walls; implanting a dopant to the trench to form a further first dopant implantation region below the trench bottom; forming a further spacer at the trench sidewalls; and implanting a dopant to the trench which trench sidewalls are covered by the further spacer to form a further second dopant implantation region below the further first dopant implantation region; wherein a thickness of the further spacer is designed to match a width of a further second dopant diffusion region in a lateral direction to a width of a further first dopant diffusion layer in the lateral direction, wherein the further second dopant diffusion layer is formed by a diffusion or scattering of the further second dopant implantation region in the lateral direction; and wherein the further first dopant diffusion layer is formed by a diffusion or scattering of the further first dopant implantation region in the lateral direction; wherein the further first dopant implantation region and the further second dopant implantation region together with the further first dopant diffusion layer and the further second dopant diffusion layer forms a further part of the pillar region of the semiconductor device.

[0081] The above implementation is further described below with respect to Figure 6 corresponding to Embodiment 3.

[0082] BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Further embodiments of the disclosure will be described with respect to the following figures, in which:

[0084] Figure 1 shows a schematic cross section of a super junction semiconductor device 100 according to a first embodiment;

[0085] Figure 2a shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a first variant of the body contact region 51;

[0086] Figure 2b shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a second variant of the body contact region 51; Figure 3a shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a third variant of the body contact region 51;

[0087] Figure 3b shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a fourth variant of the body contact region 51;

[0088] Figure 4 shows a schematic cross section of a super junction semiconductor device 100 according to a second embodiment;

[0089] Figure 5a shows a 3D view of the super junction semiconductor device 100 according to the second embodiment with a first variant of the body contact region 51;

[0090] Figure 5b shows a 3D view of the super junction semiconductor device 100 according to the second embodiment with a second variant of the body contact region 51;

[0091] Figure 6 shows schematic cross sections representing steps of a method for manufacturing a super junction semiconductor device 100 according to a third embodiment; and

[0092] Figure 7 shows schematic cross sections representing implantations of a method for manufacturing a super junction semiconductor device 100 according to the third embodiment.

[0093] DETAILED DESCRIPTION OF EMBODIMENTS

[0094] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims. It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0095] Figure 1 shows a schematic cross section of a super junction semiconductor device 100 according to a first embodiment.

[0096] The super junction semiconductor device 100 is a device with monolithically integrated trenchgate and planar-gate.

[0097] The super junction semiconductor device 100 comprises: a substrate 1 being arranged at a bottom surface 101 of the super junction semiconductor device 100; a drift layer 3 formed above the substrate 1; a buffer layer 2 placed on top of the substrate 1 and below the drift layer 3; a vertical channel section 4, 7, 8, 9 formed above the drift layer 3; a planar channel section 4, 5, 6 formed above the drift layer 3 and below a trench 111 that is formed on both sides of the vertical channel section 4, 7, 8, 9; and a pillar region 11.

[0098] The vertical channel section 4, 7, 8, 9 comprises a current spreading layer 4, a body-body separation region 7, a mesa body region 8 and a mesa source region 9.

[0099] The planar channel section 4, 5, 6 comprises a layer stack of the current spreading layer 4, a trench body region 5 and a trench source region 6.

[0100] The pillar region 11 is formed in the drift layer 3 below the trench body region 5. The pillar region 11 and the drift layer 3 are forming a super junction 120.

[0101] The pillar region 11 may be placed side-by-side with the drift layer 3. The pillar region 11 is vertically extending from the trench body region 5 into the drift layer 3 as shown in Figure 1. The pillar region 11 electrically contacts the current spreading layer 4 and the trench body region 5.

[0102] The trench 111 may be formed next to the vertical channel section 4, 7, 8, 9 above the buffer layer 2 along a first direction 104. The trench 111 comprises a trench bottom I l la and at least one trench side wall 11 lb.

[0103] A spacer gate region 10 may be formed in the trench 111 above the trench body region 5 and part of the trench source region 6.

[0104] This first embodiment represents a vertical device.

[0105] The substrate 1, the buffer layer 2, the drift layer 3, the current spreading layer 4, the trench source region 6, the body-body separation region 7 and the mesa source region 9 can be of a first semiconductor doping type.

[0106] The trench body region 5 and the mesa body region 8 can be of a second semiconductor doping type.

[0107] The connection between the mesa body region 8 to the trench body region 5 can be performed in the third dimension through a body contact region 51 (not shown in the Figures).

[0108] In all implementations, this body contact region 51 is as deep as (or deeper than) trench source region 6 to realize contact to trench body region 5.

[0109] The connection of the mesa body region 8 and the connection of the trench body region 5 can also be realized separately and made in the third dimension (not shown in the Figures) where mesa body region 8 can be connected through a second part of body contact region 52 and trench body region 5 can be connected through a first part of body contact region 51. In this case region 52 needs to be as deep as (or deeper than) mesa source region 9. The connection of the trench body region 5 (by body contact region 51) can be realized in the third dimension as represented in Figures 2a, 2b, 3a and 3b where body contact region 51 can be implanted or regrown. This body contact region 51 can be self-aligned to the trench edge or spaced with a distance that can be between 0 and the width of the trench region. This body contact region 51 can be distributed in z-direction 104 (forming multiple regions), where Figures 2a, 2b, 3a and 3b show only one region of such multiple regions in z-direction 104. The drawing of only one region in the Figures is for simplicity.

[0110] The shape of body contact region 51 is also arbitrarily. Any other closed shape (circles, hexagons, triangles, rectangles, etc.) or any combination thereof can be implemented as well.

[0111] In all cases, body contact regions 51 and 52 can be electrically contacted by metallization (not shown in the Figures for clarity).

[0112] The pillar region 11 of such SJ semiconductor device 100 may be implanted self-aligned through a spacer in the drift layer 3, e.g., as shown in Figure 6. The pillar region 11 may penetrate the drift layer 3 with or without reaching the buffer layer 2 as shown in Figure 1. Alternatively, the pillar region 11 may penetrate the drift layer 3 and the buffer layer 2 with or without reaching the substrate 1 (not shown in the Figures).

[0113] A width of the pillar region 11 may be designed to vary along a vertical direction of the semiconductor device 100, wherein the vertical direction is defined from a top surface to the bottom surface of the semiconductor device 100.

[0114] The vertical direction may be sloped in such a way that the width of the pillar in the top part is larger than its width at the bottom part or vice versa.

[0115] The pillar region 11 may be formed by a plurality of successive self-aligned implantations through corresponding spacers in the drift layer 3, e.g., as shown in Figure 7. Figure 2a shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a first variant of the body contact region 51. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1.

[0116] The semiconductor device 100 comprises a body contact region 51 as described above with respect to Figure 1 formed in the planar channel section 4, 5, 6 and in the vertical channel section 4, 7, 8, 9, e.g., along a second direction 107 parallel to the bottom surface 101. The body contact region 51 may be configured to electrically connect the trench body region 5 of the planar channel section 4, 5, 6 with the mesa body region 8 of the vertical channel section 4, 7, 8, 9 by a metallization (not shown in the Figures).

[0117] The body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 as can be seen in Figure 2a.

[0118] The first part 51 of the body contact region 51 may be implanted self-aligned through a spacer on the trench body region 5, e.g., as described below with respect to Figures 6 and 7.

[0119] The first part 51 of the body contact region 51 is spaced from the at least one trench side wall 111b. In an alternate implementation (not shown in the Figures), the first part 51 of the body contact region 51 may extend to the at least one trench side wall 111b.

[0120] Figure 2b shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a second variant of the body contact region 51. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1.

[0121] As described above with respect to Figure 2a, the body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 as can be seen in Figure 2b. In this second variant, the first part 51 of the body contact region 51 extends to an edge of the trench source region 6 and the first part 51 of the body contact region 51 is separating the trench source region 6 in at least two parts.

[0122] Figure 3a shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a third variant of the body contact region 51. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1.

[0123] As described above with respect to Figure 2a, the body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 as can be seen in Figure 3a.

[0124] In this third variant, the first part 51 of the body contact region 51 is spaced from an edge of the trench source region 6 but the first part 51 of the body contact region 51 is separating the trench source region 6 in at least two parts.

[0125] Figure 3b shows a 3D view of the super junction semiconductor device 100 according to the first embodiment with a fourth variant of the body contact region 51. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1.

[0126] As described above with respect to Figure 2a, the body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 as can be seen in Figure 3b.

[0127] In this fourth variant, the first part 51 of the body contact region 51 is spaced from an edge of the trench source region 6 and the trench source region 6 is not separated by the first part 51 of the body contact region 51 in two or more parts.

[0128] Figure 4 shows a schematic cross section of a super junction semiconductor device 100 according to a second embodiment. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1 but the connection to the trench body region 5 is differently shaped, in particular as a stripe parallel to the trench source region 6.

[0129] As described above with respect to Figure 2a, the body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 (can be seen in Figures 5a and 5b).

[0130] Figure 5a shows a 3D view of the super junction semiconductor device 100 according to the second embodiment with a first variant of the body contact region 51. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1.

[0131] As described above with respect to Figure 2a, the body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 as can be seen in Figure 5a.

[0132] The first part 51 of the body contact region 51 forms a stripe along the first direction 104 in parallel to the trench source region 6. A depth of the first part of the body contact region 51 is greater than a depth of the trench source region 6 but less than a depth of the trench body region 5.

[0133] The first part 51 of the body contact region 51 is formed in a continuous way along the first direction 104.

[0134] Figure 5b shows a 3D view of the super junction semiconductor device 100 according to the second embodiment with a second variant of the body contact region 51. The semiconductor device 100 corresponds to the semiconductor device 100 shown in Figure 1.

[0135] As described above with respect to Figure 2a, the body contact region 51 comprises a first part 51 formed in the planar channel section 4, 5, 6 and a second part 52 formed in the vertical channel section 4, 7, 8, 9. The first part 51 of the body contact region 51 is separated from the second part 52 of the body contact region 51 as can be seen in Figure 5b.

[0136] The first part 51 of the body contact region 51 forms a discontinuously shaped stripe along the first direction 104 in parallel to the trench source region 6. As described above with respect to Figure 5a, a depth of the first part of the body contact region 51 is greater than a depth of the trench source region 6 but less than a depth of the trench body region 5.

[0137] Figure 6 shows schematic cross sections representing steps of a method for manufacturing a super junction semiconductor device 100 according to a third embodiment.

[0138] The method may manufacture a super junction semiconductor device 100 as described above with respect to Figures 1 to 5b.

[0139] The method comprises the following steps with respect to 1st epi layer: forming 601a a mask in a die layer 610, the mask comprising a trench 111, the trench 111 comprising a trench bottom I l la and trench side walls 11 lb; implanting 602a a dopant to the trench 111 to form a first dopant implantation region 5a below the trench bottom I l la; forming 603a a deposited layer; forming 604a a spacer at the trench sidewalls 11 lb; and implanting 604a a dopant to the trench 111 which trench sidewalls 111b are covered by the spacer to form a second dopant implantation region 5b below the first dopant implantation region 5a.

[0140] A thickness of the spacer is designed to match a width of a second dopant diffusion region 5 c in a lateral direction to a width of a first dopant diffusion layer 5d in the lateral direction, wherein the second dopant diffusion layer 5c is formed by a diffusion or scattering of the second dopant implantation region 5b in the lateral direction; and wherein the first dopant diffusion layer 5d is formed by a diffusion or scattering of the first dopant implantation region 5a in the lateral direction.

[0141] The first dopant implantation region 5a and the second dopant implantation region 5b together with the first dopant diffusion layer 5d and the second dopant diffusion layer 5c form a pillar region 11 of the semiconductor device 100 as shown in Figure 1, for example, wherein the pillar region 11 and a drift layer 3 formed in the die layer 610 are forming a super junction 120 as shown in Figure 1, for example.

[0142] Note that dopant diffusion can also happen in the vertical direction (not discussed further since it is not further relevant to this disclosure).

[0143] The first dopant implantation region 5a may be formed by another spacer.

[0144] The first dopant implantation region 5a may be formed by a first self-aligned implantation to the trench 111; and the second dopant implantation region 5b may be formed by a second selfaligned implantation to the trench 111 which trench sidewalls 111b are covered by the spacer.

[0145] The method may comprise the following further steps with respect to 2ndepi layer: removing the mask and the spacer and forming another die layer 611 on top of the first dopant implantation region 5a; forming 601b a further mask in the second die layer 611, the further mask comprising a trench 111, the trench 111 comprising a trench bottom I l la and trench side walls 11 lb as shown in Figure 1, for example; implanting 602b a dopant to the trench 111 to form a further first dopant implantation region 5 a below the trench bottom I l la; forming 603b a further deposited layer; forming 604b a spacer at the trench sidewalls 11 lb; and implanting 604b a dopant to the trench 111 which trench sidewalls 111b are covered by the further spacer to form a further second dopant implantation region 5b below the further first dopant implantation region 5a.

[0146] A thickness of the further spacer is designed to match a width of a further second dopant diffusion region 5c in a lateral direction to a width of a further first dopant diffusion layer 5d in the lateral direction, wherein the further second dopant diffusion layer 5c is formed by a diffusion or scattering of the further second dopant implantation region 5b in the lateral direction; and wherein the further first dopant diffusion layer 5d is formed by a diffusion or scattering of the further first dopant implantation region 5a in the lateral direction.

[0147] The further first dopant implantation region 5a and the further second dopant implantation region 5b together with the further first dopant diffusion layer 5d and the further second dopant diffusion layer 5c forms a further part of the pillar region 11 of the semiconductor device 100 shown in Figure 1, for example.

[0148] In all previous embodiments, the pillar region 11 can be realized by any manufacturing technique such as (but not limited to): multi-implantation and multi epitaxy, trench etch and filling, trench etch and sidewall implantation or a combination of any of them.

[0149] In particular, a novel way of fabrication of the pillars is presented in this disclosure. It is based on epitaxy and implantation through spacers:

[0150] In a first epitaxy growth (shown in the top part of Figure 6), a first thickness of epitaxy is grown, comprising the following steps:

[0151] Step 1 (Lithography) 601a: In this step, a photolithography mask is applied and developed to form openings on top of the semiconductor surface at regions where the future SJ will be formed;

[0152] Step 2 (Implantation 1) 602a: the first layers of the SJ are implanted with one or more different doses and energies. The use of several implants can be performed. Step 3 (Layer deposition) 603a: a layer is deposited in a conformal way. It can be of any material that can be blocking implanted species. Examples of such layer are dielectrics (such as oxide, nitride, . . . ), metals, alloys, . . .

[0153] Step 4. a (Layer etching) 604a: by an anisotropic etching (or combination of anisotropic and isotropic etching) of the deposited layer, a spacer is formed at the sidewalls of the trench

[0154] Step 4.b. (Implantation 2), 604a: A deeper part of the SJ layers is implanted self-aligned to the spacer (the spacer acts as a mask). The use of several implants can be performed.

[0155] In a second epitaxy growth (shown in the bottom part of Figure 6), a second thickness of epitaxy is grown, comprising the following steps:

[0156] Step 1 (Lithography), 601b: Same as Step 1 of first epitaxy. The opening of the photolithography mask is used as a parameter to determine the shape of the SJ. In the example shown in Figure 6, the mask opening is slightly widened (in view of forming a sloped SJ pillar). Note that this is only given as an example (other shapes of the pillar can be designed).

[0157] Step 2 (Implantation 3), 602b: the second layers of the SJ are implanted with one or more different doses and energies. The use of several implants can be performed.

[0158] Step 3 (Layer deposition), 603b: a layer is deposited in a conformal way. It can be of any material that can be blocking implanted species. Examples of such layer are dielectrics (such as oxide, nitride,...), metals, alloys, ... the thickness is tuned to form the shape of the pillar desired (the shape and size of the implants in Figure 6 are just exemplary).

[0159] Step 4. a (Layer etching), 604b: by an anisotropic etching (or combination of anisotropic and isotropic etching) of the deposited layer, a spacer is formed at the sidewalls of the trench

[0160] Step 4.b. (Implantation 4), 604b: A deeper part of the SJ layers is implanted self-aligned to the spacer (the spacer acts as a mask). The use of several implants can be performed.

[0161] Note that the thickness of the second epitaxy layer is tuned in such a way to have the implants formed after the second epitaxy touching the ones formed after the first epitaxy (to form the pillar).

[0162] Note that in Figure 6 (and associated text), it was chosen not to represent the changes of the width of the implanted layers forming the pillar of the SJ (for simplicity, and to avoid confusion). It has to be understood that during the process flow, the implanted layers become wider due to scattering effect (like in SiC) or diffusion (like in Si). The opening of the masks and the thicknesses of the spacers are designed to take this into account for the desired pillar shape.

[0163] Note that in the example given here, it was arbitrarily chosen to show two epitaxies with two implants each (in which one is performed through the mask and the other through a spacer). It has to be understood that this is just for illustration purposes: the number of epitaxies, the number of implantations, the energies and doses of each implant, the number of spacers are design parameters that can be chosen depending on the pillar shape to realize.

[0164] A few examples are given below with respect to Figure 7. An extreme high number of implants results in sloped pillar shape like those shown in Figure 7.

[0165] Figure 7 shows schematic cross sections representing implantations of a method for manufacturing a super junction semiconductor device 100 according to the third embodiment.

[0166] Figure 7 shows forming multiple epi layers according to the steps described above with respect to Figure 6 for the first 610 and second 611 epi layers.

[0167] After succeeding application of the method steps described above with respect to Figure 6, different shapes can be formed in the epi layer.

[0168] For example, the first diagram 701 in Figure 7 shows multiple dopant implantation regions forming a pyramid for which the top of the pyramid is upside down, i.e., directed towards the bottom side of the semiconductor device. There are three epi layers, in the first epi layer two dopant implantation regions are formed, in the second epi layer two dopant implantation regions are formed and in the third epi layer three dopant implantation regions are formed.

[0169] The second diagram 702 in Figure 7 shows multiple dopant implantation regions forming a pyramid for which the top of the pyramid is directed towards the top side of the semiconductor device. There are three epi layers, in the first epi layer two dopant implantation regions are formed, in the second epi layer two dopant implantation regions are formed and in the third epi layer three dopant implantation regions are formed.

[0170] The third diagram 703 in Figure 7 shows multiple dopant implantation regions forming two pyramid which tops are facing each other. There are three epi layers, in the first epi layer two dopant implantation regions are formed, in the second epi layer two dopant implantation regions are formed and in the third epi layer three dopant implantation regions are formed.

[0171] The fourth diagram 704 in Figure 7 shows multiple dopant implantation regions forming a pyramid for which the top of the pyramid is upside down. In contrast to the first diagram 701, there are an exemplary number of eleven epi layers, in which the dopant implantation regions are formed.

[0172] The fifth diagram 705 in Figure 7 shows multiple dopant implantation regions forming a pyramid for which the top of the pyramid is directed towards the top side of the semiconductor device. In contrast to the second diagram 702, there are an exemplary number of eleven epi layers, in which the dopant implantation regions are formed.

[0173] The sixth diagram 706 in Figure 7 shows multiple dopant implantation regions forming a cuboid. There are three epi layers, in the first epi layer two dopant implantation regions are formed, in the second epi layer two dopant implantation regions are formed and in the third epi layer three dopant implantation regions are formed.

[0174] In the following, further embodiments are described. According to a fourth embodiment, the pillar region 11 of all super junction semiconductor devices described above can be deep enough to reach the buffer layer 2, or penetrate it, or reach the substrate 1, or penetrate it.

[0175] According to a fifth embodiment, the pillar region 11 of all super junction semiconductor devices described above can be of a variable width from top to bottom. For example, the pillar region 11 can be sloped in such a way that the width of the pillar in the top part is larger than its width at the bottom (or opposite).

[0176] According to a sixth embodiment, the super junction semiconductor device is a vertical device for which the doping type of the substrate 1 is of opposite doping type to the doping type of the drift layer 3. The device forms an IGBT structure.

[0177] According to a seventh embodiment, the super junction semiconductor device is a complementary vertical device for which all semiconductor regions of embodiments described above are of a reversed doping type.

[0178] According to an eighth embodiment, the implantation of the SJ pillar layers can be performed through any number of spacers (not limited to 2). Each implantation through one spacer can be a sequence of many sub-implants with different energies and / or doses.

[0179] According to a ninth embodiment, all previous embodiments can be related to Silicon, SiC, GaN or Ga2O3.

[0180] According to a tenth embodiment, all previous embodiments can be related to devices where the current spreading layer 4 is less deep than the trench body region 5 or the trench source region 6.

[0181] In embodiments of the disclosure described above, the SJ is incorporated in a unique Gate module, i.e., a planar and trench gate. This allows maximizing the current capability of the device by reducing at the same time the resistance of the drift region (via the use of the SJ) and the channel resistance (via the use of the spacer-based-Gate module providing multiple channels).

[0182] In embodiments of the disclosure described above, the pillar extends below a body region of a planar MOSFET which is inside a trench region. This allows direct and short paths for collection of carriers during harsh events, for example: impact ionization.

[0183] In embodiments of the disclosure described above, the pillar connection to the ground is naturally made through the body and contact of the planar MOSFET body. This allows to have ground potential forced to the pillar and hence to avoid multiple ground regions with potential differences.

[0184] In embodiments of the disclosure described above, the SJ pillars are formed by use of multiple implants through spacers combined with multiple epitaxies. This allows better control of the shape of the pillar (e.g., straight, sloped, etc.).

[0185] In embodiments of the disclosure described above, the space below the body of the planar MOSFET is used to implement the SJ. Such design results in no area increase.

[0186] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0187] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0188] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1. A super junction semiconductor device (100) with monolithically integrated trenchgate and planar-gate, the super junction semiconductor device (100) comprising: a substrate (1) being arranged at a bottom surface (101) of the super junction semiconductor device (100); a drift layer (3) formed above the substrate (1); a buffer layer (2) placed on top of the substrate (1) and below the drift layer (3); a vertical channel section (4, 7, 8, 9) formed above the drift layer (3), the vertical channel section (4, 7, 8, 9) comprising a current spreading layer (4), a body-body separation region (7), a mesa body region (8) and a mesa source region (9); a planar channel section (4, 5, 6) formed above the drift layer (3) and below a trench (111) that is formed on both sides of the vertical channel section (4, 7, 8, 9), the planar channel section (4, 5, 6) comprising a layer stack of the current spreading layer (4), a trench body region (5) and a trench source region (6); and a pillar region (11) formed in the drift layer (3) below the trench body region (5), the pillar region (11) and the drift layer (3) forming a super junction (120).

2. The semiconductor device (100) of claim 1, wherein the pillar region (11) is placed side-by-side with the drift layer (3); and wherein the pillar region (11) is vertically extending from the trench body region (5) into the drift layer (3).

3. The semiconductor device (100) of claim 1 or 2, wherein the pillar region (11) electrically contacts the current spreading layer (4) and the trench body region (5).

4. The semiconductor device (100) of any of the preceding claims, wherein the trench (111) is formed next to the vertical channel section (4, 7, 8, 9) above the buffer layer (2) along a first direction (104); wherein the trench (111) comprises a trench bottom (1 I la) and at least one trench side wall (111b), the semiconductor device (100) comprising: a body contact region (51) formed in the planar channel section (4, 5, 6) and in the vertical channel section (4, 7, 8, 9) along a second direction (107) parallel to the bottom surface (101), the body contact region (51) configured to electrically connect the trench body region (5) of the planar channel section (4, 5, 6) with the mesa body region (8) of the vertical channel section (4, 7, 8, 9) by a metallization.

5. The semiconductor device (100) of claim 4, wherein the body contact region (51) comprises a first part (51) formed in the planar channel section (4, 5, 6) and a second part (52) formed in the vertical channel section (4, 7, 8, 9); wherein the first part (51) of the body contact region (51) is separated from the second part (52) of the body contact region (51).

6. The semiconductor device (100) of claim 5, wherein the first part (51) of the body contact region (51) is implanted self-aligned through a spacer on the trench body region (5).

7. The semiconductor device (100) of claim 5 or 6, wherein the first part (51) of the body contact region (51) extends to the at least one trench side wall (11 lb).

8. The semiconductor device (100) of claim 5 or 6, wherein the first part (51) of the body contact region (51) is spaced from the at least one trench side wall (11 lb).

9. The semiconductor device (100) of any of claims 5, 6 or 7, wherein the first part (51) of the body contact region (51) extends to an edge of the trench source region (6).

10. The semiconductor device (100) of any of claims 5, 6 or 7, wherein the first part (51) of the body contact region (51) is spaced from an edge of the trench source region (6).

11. The semiconductor device (100) of any of claims 5, 6, 8 or 10, wherein the first part (51) of the body contact region (51) is separating the trench source region (6) in at least two parts.

12. The semiconductor device (100) of claim 5 or 6, wherein the first part (51) of the body contact region (51) forms a stripe along the first direction (104) in parallel to the trench source region (6).

13. The semiconductor device (100) of claim 5 or 6, wherein the first part (51) of the body contact region (51) is formed in a discontinuous way along the first direction (104).

14. The semiconductor device (100) of any of the preceding claims, wherein the pillar region (11) is implanted self-aligned through a spacer in the drift layer (3).

15. The semiconductor device (100) of any of the preceding claims, wherein the pillar region (11) penetrates the drift layer (3) with or without reaching the buffer layer (2); or wherein the pillar region (11) penetrates the drift layer (3) and the buffer layer (2) with or without reaching the substrate (1).

16. The semiconductor device (100) of any of the preceding claims, wherein a width of the pillar region (11) is designed to vary along a vertical direction of the semiconductor device (100), wherein the vertical direction is defined from a top surface to the bottom surface of the semiconductor device (100).

17. The semiconductor device (100) of any of the preceding claims, wherein the pillar region (11) is formed by a plurality of successive self-aligned implantations through corresponding spacers in the drift layer (3).

18. A method for manufacturing a super junction semiconductor device (100), the method comprising: forming a mask in a die layer (610), the mask comprising a trench (111), the trench (111) comprising a trench bottom (1 I la) and trench side walls (11 lb); implanting a dopant to the trench (111) to form a first dopant implantation region (5a) below the trench bottom (I l la); forming a deposited layer; forming a spacer at the trench sidewalls (11 lb); and implanting a dopant to the trench (111) which trench sidewalls (11 lb) are covered by the spacer to form a second dopant implantation region (5b) below the first dopant implantation region (5a); wherein a thickness of the spacer is designed to match a width of a second dopant diffusion region (5c) in a lateral direction to a width of a first dopant diffusion layer (5d) in the lateral direction, wherein the second dopant diffusion layer (5c) is formed by a diffusion or scattering of the second dopant implantation region (5b) in the lateral direction; and wherein the first dopant diffusion layer (5d) is formed by a diffusion or scattering of the first dopant implantation region (5a) in the lateral direction; wherein the first dopant implantation region (5a) and the second dopant implantation region (5b) together with the first dopant diffusion layer (5d) and the second dopant diffusionlayer (5c) form a pillar region (11) of the semiconductor device (100), wherein the pillar region (11) and a drift layer (3) formed in the die layer (610) are forming a super junction (120).

19. The method of claim 18, wherein the first dopant implantation region (5a) is formed by another spacer.

20. The method of claim 18 or 19, wherein the first dopant implantation region (5a) is formed by a first self-aligned implantation to the trench (111); and wherein the second dopant implantation region (5b) is formed by a second self-aligned implantation to the trench (111) which trench sidewalls (11 lb) are covered by the spacer.

21. The method of any of claims 18 to 20, comprising: removing the mask and the spacer and forming another die layer (611) on top of the first dopant implantation region (5a); forming a further mask in the second die layer (611), the further mask comprising a trench (111), the trench (111) comprising a trench bottom (1 I la) and trench side walls (U lb); implanting a dopant to the trench (111) to form a further first dopant implantation region (5a) below the trench bottom (1 I la); forming a further deposited layer; forming a further spacer at the trench sidewalls (11 lb); and implanting a dopant to the trench (111) which trench sidewalls (11 lb) are covered by the further spacer to form a further second dopant implantation region (5b) below the further first dopant implantation region (5a);wherein a thickness of the further spacer is designed to match a width of a further second dopant diffusion region (5c) in a lateral direction to a width of a further first dopant diffusion layer (5d) in the lateral direction, wherein the further second dopant diffusion layer (5c) is formed by a diffusion or scattering of the further second dopant implantation region (5b) in the lateral direction; and wherein the further first dopant diffusion layer (5d) is formed by a diffusion or scattering of the further first dopant implantation region (5a) in the lateral direction; wherein the further first dopant implantation region (5a) and the further second dopant implantation region (5b) together with the further first dopant diffusion layer (5d) and the further second dopant diffusion layer (5c) forms a further part of the pillar region (11) of the semiconductor device (100).

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