Mosfet with self-adjusted widening region
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- ROBERT BOSCH GMBH
- Filing Date
- 2024-07-19
- Publication Date
- 2026-06-17
Smart Images
Figure EP2024070545_20022025_PF_FP_ABST
Abstract
Description
[0001] MOSFET WITH SELF-ALIGNED WIDESPREAD REGION
[0002] State of the art
[0003] FIG. 1 and FIG. 2 show schematic cross-sectional views of the cell in the active region of a SiC trench-gate power MOSFET as a comparative example of a semiconductor component 1. The semiconductor component 1 comprises: an n+-doped substrate 6, an n+-doped buffer layer 7, an n-doped drift region 8 with a first doping level, a p-doped diode region 9, an n-doped widening region 10 with a second doping level that is greater than the first doping level; a p-doped channel region 11, an n+-doped source region 16, a trench gate 4 (also referred to as gate electrode, trench electrode, or trench gate electrode), for example, made of polysilicon, a gate oxide 5, a drain metal 3, and a source metal 2.
[0004] A challenge with silicon carbide (SiC) trench-gate power MOSFETs is to achieve good conduction characteristics, such as a low area-specific (A) minimum contact resistance (also referred to as RDS(on) or RDSon) of a field-effect transistor, i.e., a low RDSon*A. A low RDSon*A generally requires high doping and thus low resistance of the current-carrying layers, including the drift region 8.
[0005] Another challenge with SiC trench-gate power MOSFETs is keeping the blocking voltage as high as possible above the threshold voltage. However, achieving a high blocking voltage requires low doping of the drift region 8.
[0006] A further challenge with SiC trench-gate power MOSFETs is to limit the maximum field strength in the trench oxide at high reverse voltage for reliability reasons and to achieve the best possible short-circuit strength. To limit the field strength in the gate oxide 5 and achieve good short-circuit strength, low doping levels, combined with a short distance between the diode region 9 and the trench gate 4 and the next diode region 9, are advantageous.
[0007] One way to make the tradeoff between these opposing requirements more favorable is to dope the area between the trench gate 4 and the diode region 9 more highly than the area below the trench gate 4. This area is referred to as the spreading region 10 (also known as the current spreading layer).
[0008] However, the widened region 10 has a disadvantageous width. The widened region 10, the trench gate 4, and the diode regions 9 are typically created through a sequence of lithography and implantation processes. The distance of the widened region 10 to the trench gate 4 or the diode regions 9 is subject to offset due to manufacturing-related fluctuations (cf. distance to the axis of symmetry 20 in FIG. 1 and FIG. 2). In this case, the current flow in the on-state condition is unevenly distributed between the two sides of the trench gate 4, and the RDSon*A is increased. To ensure that specifications are met while taking all fluctuations into account, the advantages of the widened region 10 cannot be fully utilized, and the tradeoff is not optimal.
[0009] Disclosure of the invention
[0010] Advantages of the invention
[0011] The vertical semiconductor component according to the invention with the features according to claim 1 has the advantage that the current flow in the on-state case is divided more evenly between the two sides of the trench gate and therefore the proportional RDSon*A is divided more evenly between the two sides of the trench gate. This makes it possible to comply with specifications while taking all process variations into account. This allows better use of the advantages of the widening region and an improved trade-off to be achieved. This is made possible by a self-aligned widening region, which is arranged symmetrically (with equidistant spacings) around the trench gate and the distance between the widening region and diode regions is constant. The semiconductor component can be designed such that the RDSon*A is particularly low for a specified blocking voltage, field strength and short-circuit strength.This leads to lower costs of a component with a given RDSon*A or a low Rdson*A for a given chip area.
[0012] Further developments of the aspects and advantageous embodiments of the vertical semiconductor component are described in the dependent claims and the description.
[0013] drawing
[0014] Embodiments of the invention are illustrated in the figures and explained in more detail below. They show:
[0015] FIG. 1 is a schematic cross-sectional view of a MOSFET as a comparative example;
[0016] FIG. 2 is a schematic cross-sectional view of a MOSFET as a comparative example;
[0017] FIG. 3 shows a schematic cross-sectional view of a semiconductor device according to various embodiments;
[0018] FIG.4 shows a flowchart of a method for manufacturing a semiconductor device according to various embodiments; and
[0019] FIG.5A to FIG.5G illustrate schematic cross-sectional views of a substrate in a method of manufacturing a semiconductor device.
[0020] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It is to be understood that the features of the various embodiments described herein may be combined with one another unless specifically indicated otherwise. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. In the figures, identical or similar elements are designated by identical reference numerals where appropriate.
[0021] Illustratively, the vertical semiconductor component has a self-aligned expansion region, which is, for example, n-doped, and extends laterally to both sides of the trench gate, optionally at least partially enclosing it on the underside. The n-doped expansion region is located below the p-doped channel region and can optionally also be located in the channel region. In the latter case, the channel region can be more heavily overdoped, resulting in an overall p-doping in the channel region. Optionally, the n-doped expansion region can extend to the semiconductor surface. The distance of the self-aligned expansion region to the diode regions located on both sides of the trench gate is constant and can be greater than zero (doping the diode regions). Optionally, the self-aligned expansion region can touch these diode regions, penetrate them, and even overdope them in edge regions.The use of the invention is not limited to strip-shaped cells in the active region, but can also be used with cells of other geometries. Furthermore, the use of the self-aligned expansion region is not limited to SiC (silicon carbide) as the material of the semiconductor substrate, but it can also be used with other semiconductor materials, e.g. GaN, Si, Ge and the like.
[0022] Description of the embodiments
[0023] FIG. 3 shows a schematic cross-sectional view of a semiconductor device according to various embodiments. In the following description, various aspects and embodiments of a vertical semiconductor device 100 are described using an n-channel SiC trench-gate power MOSFET as an example. However, the self-aligned widening region can also be applied to semiconductor devices with reverse doping, e.g., a p-channel MOSFET. In this case, the dopings of the other regions and structures mentioned are complementary, for example, n-doped diode regions. Furthermore, instead of a gate oxide, another insulator, e.g., a "high-k" material, or a stack of an oxide and another insulator, e.g., a "MISFET," can be used.It is also understood that the use of the self-aligned expansion region is not limited to a MOSFET, so that in principle any vertical semiconductor components can be manufactured using this technology, such as Schottky diodes, pn diodes, vertical diffusion MOSFETS (VDMOS), current-aperture vertical electron transistors (CAVETs), vGroove vertical high electron mobility transistors (vHEMTs) or fin field-effect transistors (FinFETs).
[0024] The semiconductor component 100 illustrated in FIG. 3 comprises, for example: an n+-doped substrate 106, an n+-doped buffer layer 107, an n-doped drift region 108 with a first doping level, a p-doped diode region 109, an n-doped widening region 115 with a second doping level that is greater than the first doping level; a p-doped channel region 111, an n+-doped source region 116, a trench gate 104, for example made of polysilicon, a gate oxide 105 (also referred to as gate dielectric), a drain metal 103 (also referred to as drain contact or first contact), a source metal 102 (also referred to as source contact or second contact).
[0025] The vertical semiconductor component 100 includes, among other things, a drift region 108, at least a first diode region 109 and a second diode region 109 laterally adjacent to one another; and a trench gate 104 arranged laterally between the first diode region 109 and the second diode region 109. The trench gate 104 may have a first doping. A widening region 115 may be arranged between the trench gate 104 and the drift region 108. The widening region 115 may be arranged laterally between the trench gate 104 and the first diode region 109 and the second diode region 109. The widening region 115 may be configured as a contiguous region.
[0026] The lateral distance 112 between the widening region 115 and the first diode region 109 may be substantially equal to the lateral distance between the widening region 115 and the second diode region 109.
[0027] A respective portion of the drift region 108 may be arranged between the widening region 115 and the first diode region 109 and the second diode region 109. In other words, the lateral distance 112 may be greater than zero.
[0028] The widening area 115 can be designed in such a way that the widening area
[0029] 115 is laterally spaced from the first diode region 109 and the second diode region 109, respectively. Alternatively or additionally, the widening region 115 may contact, overlap, or overdope at least one of the first diode region 109 and the second diode region 109.
[0030] The semiconductor device 100 may be formed on a substrate 106, wherein the substrate 106 comprises or is formed from at least one of: silicon carbide, gallium nitride, silicon, germanium.
[0031] The semiconductor device 100 may include a buffer layer 107 disposed between the substrate 106 and the drift region 108.
[0032] A source contact 102 may be arranged on or above at least one of the first diode region 109 and the second diode region 109. The source contact 102 may contact the first diode region 109 and / or the second diode region 109.
[0033] A gate dielectric 105 may be disposed between the trench gate 104 and the expansion region 115.
[0034] The drift region 108 may be arranged on or above the drain contact 103.
[0035] A channel region 111 may be arranged at least partially on or above the widening region 115 and may be arranged laterally adjacent to the trench gate 104.
[0036] A source region 116 may be arranged at least partially on or above the extension region 115 and may be arranged laterally adjacent to the trench gate 104. The source region 116 may be arranged on or above the channel region 111. At least a portion of the extension region 115 may be arranged in the channel region 111. The source region 116 may be arranged between a channel region 111 and a source contact 102.
[0037] FIG. 4 shows a flowchart of a method for manufacturing a semiconductor device according to various embodiments. The method 400 for manufacturing a vertical semiconductor device may include: forming a drift region; forming 402 at least a first diode region and a second diode region laterally adjacent to one another; forming 404 a trench gate laterally between the first diode region and the second diode region, wherein the trench gate has a first doping; and forming 406 an extension region, which may be arranged between the trench gate and the drift region and laterally between the trench gate and the first diode region and the second diode region. The extension region may be configured as a contiguous region.
[0038] The widening region can thus be precisely arranged laterally between the first diode region and the second diode region, for example, symmetrically (see symmetry axis 120 in FIG. 3). For example, the lateral distance between the widening region and the first diode region can be substantially equal to the lateral distance between the widening region and the second diode region.
[0039] The first diode region and the second diode region may be formed using a first mask. The widening region may be formed using a second mask. The second mask may have a structure inverted to the first mask. For example, the first mask may have openings through which the first diode region and the second diode region, respectively, are formed. The second mask may be formed at least partially in the openings of the first mask before the first mask is removed. This enables the second mask to have a structure inverted to the first mask. As a result, the display region may have improved alignment between the first diode region and the second diode region. Furthermore, the widening region may thereby have a structure contiguous between the first diode region and the second diode region. The trench gate may be formed in the widening region.A portion of the expansion region can be located between the trench gate and the drift region. This allows the on-resistance to be reduced.
[0040] The method can be carried out in the aforementioned order. In various embodiments, the method can have further features, for example, one or more intermediate steps before, after, or between the aforementioned method steps.
[0041] FIG.5A to FIG.5G illustrates schematic cross-sectional views of a
[0042] Substrates in a method for producing a semiconductor component. FIGS. 5A to 5G merely illustrate the production of the expansion region of a semiconductor component. It is understood that the semiconductor component may have further structures (see, for example, FIG. 3), the production of which is not illustrated in FIGS. 5A to 5G, for example, to the left of the first diode region and to the right of the second diode region.
[0043] FIG. 5A illustrates the provision of a drift region 108. This can be a lightly n-doped active region, formed, for example, by homoepitaxy of SiC on highly n-doped SiC substrates. Optionally, a buffer layer can have been previously grown on the SiC substrate.
[0044] Optionally, the drift region 108 can be formed from a plurality of layers that are doped to different degrees.
[0045] FIG. 5B illustrates the formation of the diode regions 109. For this purpose, a first hard mask 520 (for example, the first mask) can be applied to the drift region 108. The first hard mask 520 can be formed, for example, from silicon oxide, silicon nitride, polycrystalline silicon (poly-Si), or a combination of several of these layers. The first hard mask 520 can be patterned photolithographically and by means of an etching process, so that the first hard mask 520 has openings (also referred to as transmissive regions) above the drift region 108, below which the diode regions 109 are to be formed. The diode regions 109 can be created as p-doped diode regions, for example, by ion implantation 522 through the openings of the first hard mask 520. The dopants do not penetrate into the area of the drift region 108 on which the first hard mask 520 is applied (in FIG.5B as arrow 524; also referred to as opaque regions). In other words, the first diode region 109 and the second diode region 109 may be formed using a first mask 520. The first mask 520 may include transmissive regions through which the first diode region 109 and the second diode region 109 are formed, respectively, as illustrated in FIG. 5B.
[0046] The method may further comprise forming an inverted hard mask 532 (also referred to as a second mask), as illustrated in FIG. 5C to FIG. 5E. The inverted hard mask 532 has a structure inverted to the first hard mask 520, as illustrated in FIG. 5E. The widening region 115 may be formed using the second mask 532. The second mask 532 may have at least one transmissive region through which the widening region 115 is formed, as illustrated in FIG. 5E and FIG. 5F. A transmissive region may, for example, be an opening in a hard mask, and an opaque region may be a portion of the hard mask.
[0047] The second mask 532 may have a structure comprising transmissive regions and opaque regions that is at least partially complementary to the first mask 520 (see, for example, FIG. 5B to FIG. 5E). The complementary structure may also be referred to as an inverted structure. For example, the at least one transmissive region of the second mask 532 may be formed by removing a portion of an opaque region 530 of the second mask, which is arranged on or above the first mask 520, before or with the removal of the first mask 520 (see, for example, FIG. 5C to FIG. 5E). Alternatively or additionally, at least one opaque region of the second mask 532 may be formed in transmissive regions of the first mask 520 on or above the first diode region 109 and the second diode region 109 (see, for example, FIG. 5C and FIG. 5D).The at least one opaque region of the second mask 532 may be formed in transmissive regions of the first mask 520 before the first mask 520 is removed, see, for example, FIG. 5C and FIG. 5D. This enables precise alignment of the transmissive region of the second mask—and thus of the further formed expansion region—with respect to the first diode region 109 and the second diode region 109.
[0048] The second hard mask 530 may be conformally formed on the first hard mask 520 and the diode regions 109 (illustrated as region 532 in FIG. 5C). The second hard mask 530 may be formed, for example, from silicon oxide, silicon nitride, polycrystalline silicon (poly-Si), or a combination of several of these layers.
[0049] The second hard mask 530 can be removed to the level of the first hard mask 520, such that the second hard mask 530 remains in the openings (region 532) in the first hard mask 520, for example, by means of recess etching, as illustrated in FIG. 5D. In other words, the second hard mask 530 is exposed in the openings of the first hard mask 520, which is laterally surrounded by the first hard mask 520.
[0050] The method may further include removing the first hard mask 520 from the drift region
[0051] 108, so that only the second hard mask 530 remains over the diode regions 109, as illustrated in FIG.5E
[0052] The widening region 115 can be created by ion implantation in the drift region 108 symmetrically (illustrated in FIG. 5F by the symmetry axis 120) between the diode regions 109. FIG. 5F and FIG. 5G illustrate the widening region for only one transistor cell.
[0053] Lateral contact of the widened region 115 with the diode regions 109, overlap of the widened region 115 with the diode regions 109, or overdoping of the diode region 109 by the widened region 115 can be formed by lateral scattering of the implantation during the formation of the widened region 115. The lateral scattering can be characterized by the effective doping changing as a function of depth, for example, "retrograde," or remaining constant, for example, as a "box profile."
[0054] The second hard mask 532 may be removed after the formation of the expansion region 115, as illustrated in FIG. 5G. The further structures of the semiconductor device 100, which are illustrated, inter alia, in FIG. 3, may be formed in a conventional manner.
[0055] The embodiments described and shown in the figures are chosen only as examples. Different embodiments can be combined with one another entirely or with regard to individual features. An embodiment can also be supplemented by features of another embodiment. Furthermore, described method steps can be repeated and performed in a different order than the one described. In particular, the invention is not limited to the specified method.
Claims
Claims 1. A vertical semiconductor component (100) comprising: a drift region (108), at least a first diode region (109) and a second diode region (109) laterally adjacent to one another; a trench gate (104) arranged laterally between the first diode region (109) and the second diode region (109), wherein the trench gate (104) has a first doping; and a widening region (115) arranged between the trench gate (104) and the drift region (108) and arranged laterally between the trench gate (104) and the first diode region (109) and the second diode region (109), wherein the widening region (115) is configured as a contiguous region.
2. Vertical semiconductor component (100) according to claim 1, wherein the widening region (115) is arranged such that the widening region (115) is surrounded by the first diode region (109) and the second diode region (109) is laterally spaced.
3. Vertical semiconductor device (100) according to claim 1, wherein the widening region (115) contacts, overlaps or overdopes at least one of the first diode region (109) and the second diode region (109).
4. The vertical semiconductor device (100) according to claim 1, further comprising a source contact (102) arranged on or above at least one of the first diode region (109) and the second diode region (109), wherein the source contact (102) contacts the first diode region (109) and / or the second diode region (109), and a gate dielectric (105) arranged between the trench gate (104) and the semiconductor, at least the widening region (115), and a Drain contact (103), wherein the drift region (108) is arranged on or above the drain contact (103).
5. A method (400) for manufacturing a vertical semiconductor device (100), the method comprising: Formation of a drift area (108), Forming (402) at least one first diode region (109) and one second diode region (109) laterally adjacent to one another; Forming (404) a trench gate (104) laterally between the first diode region (109) and the second diode region (109), and Forming (406) an expansion region (115) which is arranged between the trench gate (104) and the drift region (108) and is arranged laterally between the trench gate (104) and the first diode region (109) and the second diode region (109), wherein the expansion region (115) is configured as a continuous region.
6. The method (400) according to claim 5, further comprising: wherein the first diode region (109) and the second diode region (109) are formed by means of a first mask (520), and wherein the widening region (115) is formed by means of a second mask (532), wherein the second mask (532) has a structure of transmissive and opaque regions that is at least partially complementary to the first mask (520).
7. The method according to claim 6, wherein the first mask (520) has transmissive regions through which the first diode region (109) and the second diode region (109) are formed, respectively, and wherein the second mask (532) has at least one transmissive region through which the widening region (115) is formed.
8. The method of claim 7, wherein the at least one transmissive region of the second mask (532) is formed by removing a portion of an opaque region (530) of the second mask disposed on or above the first mask (520) with removal of the first mask (520).
9. The method according to any one of claims 6 to 8, wherein at least one opaque region of the second mask (532) is formed in transmissive regions of the first mask (520) on or above the first diode region (109) and the second diode region (109).
10. The method of claim 9, wherein the at least one opaque region of the second mask (532) is formed in transmissive regions of the first mask (520) before the first mask (520) is removed.