Layout-based systematic defect determinations through design uniqueness and repeater overlap

Abstract

Systems and methods are presented for determination of layout-based systematic defect candidates based on design uniqueness and repeater overlap. A method may include accessing diagnosis reports (220) generated for physical circuits and identifying multiple repeater sets (230) from the diagnosis reports (220). The method may also include extracting layout patterns (250) from the diagnosis reports (220) and determining (608) a layout-based systematic defect candidate (510) from among the layout patterns (250) based on a design uniqueness factor and a repeater overlap factor. The design uniqueness factor may be based on a degree to which other layout patterns similar to a given layout pattern do not otherwise occur among layout patterns (320) for the circuit design (310). The repeater overlap factor may be based on a degree to which other layout patterns similar to the given layout pattern occur among layout patterns for other repeater sets of the multiple repeater sets (230).

Description

LAYOUT-BASED SYSTEMATIC DEFECT DETERMINATIONS THROUGH DESIGN UNIQUENESS AND REPEATER OVERLAPBACKGROUND

[0001] Electronic circuits, such as integrated circuits, are used in nearly every facet of modern society, from automobiles to microwaves to personal computers and more. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to fabrication and analysis of circuits after fabrication. EDA applications may implement various procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Certain examples are described in the following detailed description and in reference to the drawings.

[0003] Figure 1 shows an example of a computing system that supports layout-based systematic defect determinations through design uniqueness and repeater overlap.

[0004] Figure 2 shows an example extraction of layout patterns from repeater sets identified for manufactured physical circuits according to the present disclosure.

[0005] Figure 3 shows an example evaluation of a design uniqueness factor for layout patterns for a repeater set according to the present disclosure.

[0006] Figure 4 shows an example evaluation of a repeater overlap factor for layout patterns for a repeater set according to the present disclosure.

[0007] Figure 5 shows an example determination of a layout-based systematic defect candidate from layout patterns for a repeater set based on a design uniqueness factor and a repeater overlap factor.

[0008] Figure 6 shows an example of logic that a system may implement to support layout-based systematic defect determinations through design uniqueness and repeater overlap.

[0009] Figure 7 shows an example of a computing system that supports layout-based systematic defect determinations through design uniqueness and repeater overlap.DETAILED DESCRIPTION

[0010] Modern integrated circuits (ICs) have become increasingly complex. At some technology nodes, feature sizes have shrunk to a few atoms wide. Transistors and corresponding transistor connections are designed with increasingly complicated structures with additional layers, and often require additional process steps to manufacture. Increased circuit complexities and increased number of process steps can result in defects in IC manufacture, particularly as printing the exact physical layout of a circuit design on a silicon substrate becomes increasingly challenging. Consequently, silicon defects are becoming increasingly prevalent, limiting the manufacturing yield of ICs. IC manufacture at high volumes with high yield is an increasingly difficult challenge for chip designers and foundries, and accurately identifying yieldlimiting root causes can improve IC manufacture yields.

[0011] Defects in manufactured circuits can be characterized in multiple ways based on the cause of the defect. Example defect characterizations include random defects, which may randomly occur in circuits during fabrication, and may be based on process parameters of the fabrication process. Systematic defects are another form of defect characterization, which can be caused by specific characteristics of a physical layout of a circuit design. The characteristics of the physical layout (or a specific portion thereof) may be particularly susceptible or defect-prone, causing defects duringfabrication of physical chips in a systematic manner due to the problematic layout or sub-portions thereof.

[0012] As used herein, a layout pattern may refer to any physical layout portion of a circuit or circuit design. Layout patterns may be apportioned at any configurable size to capture or represent a specific portion of a circuit layout. Today, in even relatively simple circuit designs, billions of layout patterns can be extracted to characterize specific layout windows of the circuit design for defect analysis. Certain layout patterns may cause defects due to the design of a layout pattern itself, e.g., specific polygon positioning or geometric features that may be particularly difficult to print for a given fabrication process. In that way, a specific layout pattern may be a root cause of defects observed in physically manufactured chips.

[0013] Silicon defects caused by a physical design may be referred to as layout-based systematic defects. Such layout-based systematic defects may be caused by a polygon configuration, design characteristics, or other aspects of a specific layout pattern, which may in turn cause defects to occur in printed physical chips. For such systematic defects caused by layout patterns, other identical or similar layout patterns at other locations of a chip design may likewise be susceptible to the same systematic defect. Detection of layoutbased systematic defects can allow for flagging or re-design of problematic layout patterns that cause these defects, which can in turn increase IC yield and improve manufacturing efficiencies.

[0014] Scan tests provide a mechanism to test digital logic in manufactured ICs. Scan diagnosis procedures (also called volume diagnosis when performed over a population of failing ICs) may utilize scan test failure data obtained for failed ICs as well as circuit design information in order to identify candidate defect locations that cause a manufactured IC to fail. However, diagnosis results may contain inherent ambiguity. Different defects can be logically equivalent under applied scan test patterns and a diagnosis tool’s defect models. As such, more than one defect location (and thus multiple corresponding layout patterns that surround the multiple defect locations) can produce the same failure signature for the scan test. A diagnosis report maythus include multiple candidate defect locations for a single scan test failure, as the scan test is unable to pinpoint the exact defect location of a physical circuit at which the defect occurs. Diagnosis reports can thus include multiple sets of failure signatures, each with multiple candidate defect locations.

[0015] In order to determine exact causes of defects detected through scan tests, physical failure analyses can be performed. Physical failure analysis (PFA), also referred to as a failure analysis, can involve physically dissecting a manufactured chip and examining the candidate defect locations specified in diagnosis reports. Through such physical dissection, exact locations of defects can be determined, though at a high cost. PFA processes can be costly and prohibitive, especially for a large number of candidate defect locations included in diagnosis reports, many of which are not the actual root cause of systematic defects. By its nature, PFA can be time-consuming, expensive, and require significant manual efforts, and performing failure analyses for each candidate defect location in generated diagnosis reports is not practically feasible to determine layout-based defects caused by problematic layout patterns of a circuit design. PFA is also a destructive process, in that an analyzed physical circuit can check a single candidate location for a physical chip, but not others due to the physical tear down. Thus, it would be impractical (and perhaps impossible to perform PFA on all candidate defect locations specified in diagnosis reports).

[0016] The disclosure herein may provide systems, methods, devices, and logic in support of layout-based systematic defect determinations through design uniqueness and repeater overlap. The layout-based systematic defect determination technology described herein may provide automated, data- driven, and intelligent analyses of diagnosis reports to determine specific candidate defect locations and corresponding layout patterns that are increasingly likely to cause systematic defects. Such processing may include determining repeater sets among the diagnosis reports with identical candidate defect locations and evaluating the layout patterns for these repeater sets (e.g., the identical candidate defect locations thereof) based on a design uniqueness factor and a repeater overlap factor.

[0017] The design uniqueness factor can indicate a degree to which similar layout patterns occur in a full chip design. Thus, for a given layout pattern, the design uniqueness factor can be based on a degree to which other layout patterns similar to a given layout pattern do not otherwise occur among layout patterns of the full chip design. The repeater overlap factor can indicate a degree to which similar layout patterns occur in other repeater sets. As such, the repeater overlap factor can be based on a degree to which other layout patterns similar to a given layout pattern occur among layout patterns for other repeater sets of multiple repeater sets identified from volume diagnosis data. In combination, these factors may allow for the determination of layout patterns which are relatively unique in the full chip design, yet occur relatively frequently among repeater sets identified from diagnosis reports. In such a manner, guided selection of layout-based systematic defect candidates can be accomplished.

[0018] In some implementations, the design uniqueness and repeater overlap factors may provide criteria by which to filter the candidate defect locations and corresponding layout patterns contained in diagnosis reports to determine layout-based systematic defect candidates. Put another way, the design uniqueness factor and repeater overlap factor can provide a mechanism to discard or remove non-defective layout patterns from identified defect candidate locations. Through intelligent identification of layout patterns with high design uniqueness and high repeater overlap, layout-based systematic defect candidates can be detected and analyzed.

[0019] Through a filtered set of layout patterns, which are identified as layout-based systematic defect candidates through design uniqueness and repeater overlap evaluations, the number of layout patterns to analyze can be reduced, often times significantly so. Accordingly, failure analysis processes can be performed with increased efficiency as compared to conventional brute force analyses, since a lesser number of candidate defect locations are examined. Failure analyses times can thus be reduced or, in some instances, PFA can be skipped altogether. Layout patterns detected as systematic defect candidates can also be flagged and identified in other circuit designsas a potential defect root cause. In a similar manner, diagnosis reports can be annotated with determined layout-based systematic defect candidates, allowing for quick and efficient recognition of problematic layout patterns. The layout-based systematic defect determination technology of the present disclosure may thus provide intelligent analysis capabilities that can improve circuit design processes and result in improved IC yield through detection of systematic defect root causes with increased efficiency.

[0020] These and other layout-based systematic defect determination features and technical benefits according to the present disclosure are described in greater detail herein.

[0021] Figure 1 shows an example of a computing system 100 that supports layout-based systematic defect determinations through design uniqueness and repeater overlap. The computing system 100 may take the form of a single or multiple computing devices such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 may be an EDA system that implements, supports, or hosts an EDA application or other EDA-based capabilities. In that regard, the computing system 100 may support determination of layout-based systematic defect candidates in any of the ways described herein.

[0022] As an example implementation to support any combination of the layout-based systematic defect determination features described herein, the computing system 100 shown in Figure 1 includes a systematic defect determination engine 1 10. The computing system 100 may implement the systematic defect determination engine 1 10 (including components thereof) in various ways, for example as hardware and programming. The programming for the systematic defect determination engine 1 10 may take the form of processor-executable instructions stored on a non-transitory machine- readable storage medium. The hardware for the systematic defect determination engine 1 10 may include a processor to execute those instructions. A processor may take the form of single processor or multiprocessor systems, and in some examples, the computing system 100implements multiple engines using the same computing system features or hardware components (e.g., a common processor or a common storage medium).

[0023] In operation, the systematic defect determination engine 1 10 may access diagnosis reports generated for physical circuits manufactured for a circuit design. Each diagnosis report may specify candidate defect locations determined for a physical circuit. The systematic defect determination engine 1 10 may identify multiple repeater sets from the diagnosis reports, and a given repeater set includes diagnosis reports with candidate defect locations that are identical to one another. Then, the systematic defect determination engine 110 may extract layout patterns, for the given repeater set, from the candidate defect locations that are identical to one another in the diagnosis reports of the given repeater set and may determine a layout-based systematic defect candidate from among the layout patterns of the given repeater set based on a design uniqueness factor and a repeater overlap factor assessed for the layout patterns of the given repeater set.

[0024] For a given layout pattern of the given repeater set, the design uniqueness factor may be based on a degree to which other layout patterns similar to the given layout pattern, as measured within a design similarity threshold, do not otherwise occur among layout patterns for the circuit design. The repeater overlap factor may be based on a degree to which other layout patterns similar to the given layout pattern, as measured within a repeater similarity threshold, occur among layout patterns for other repeater sets of the multiple repeater sets.

[0025] These and other features of the layout-based systematic defect determination technology of the present disclosure are described in greater detail next.

[0026] Figure 2 shows an example extraction of layout patterns from repeater sets identified for manufactured physical circuits according to the present disclosure. As described herein, volume diagnosis processes can assess a population of manufactured circuits for defective manufacture, for example through scan tests. Volume diagnoses can be performed for a wafer,lot, or any population of physically manufactured circuits in order to identify defective chips.

[0027] An example of manufactured chips is shown in Figure 2 as the physical circuits 210, and the physical circuits 210 may be manufactured with the same circuit design. The physical circuits 210 (sometimes referred to as die or chips) may thus be a population of manufactured chips with the same circuit design. Any volume diagnosis, scan test, or suitable validation process may be performed on the physical circuits 210 to generate diagnosis reports 220 for the physical circuits 210. A respective diagnosis report may be generated for each physical circuit, and a given diagnosis report may specify candidate defect locations determined for a given physical circuit through a scan test and failing scan signatures that indicate defective chip operation.

[0028] The systematic defect determination engine 110 may access diagnosis reports 220 generated for the physical circuits 210, doing so in any suitable manner. For example, the systematic defect determination engine 1 10 may load the diagnosis reports 220 from a shared memory or receive the diagnosis reports 220 over a communication network. In some implementations, the systematic defect determination engine 1 10 may itself generate the diagnosis reports 220 for the physical circuits 210. Accordingly, the systematic defect determination engine 1 10 may implement or perform any suitable volume diagnosis processes to analyze physical circuits, perform scan tests, or otherwise assess scan signature data for the physical circuits 210.

[0029] From the diagnosis reports 220, the systematic defect determination engine 110 may identify repeater sets. As used herein, a repeater set may refer to any set of diagnosis reports, corresponding data for the diagnosis reports, or combinations of both, that are grouped together, e.g., by the systematic defect determination engine 1 10. In many of the examples presented here, a repeater set may be grouped as a set of diagnosis reports (or corresponding data for the diagnosis reports) that have identical candidate defect locations. However, repeater sets determined by the systematic defect determination engine 110 may be grouped in any suitable manner, technique,process, or according to any configurable criteria. A repeater set may be understood as a set of diagnosis reports (or corresponding data of the diagnosis reports, such as candidate defect locations, extracted layout patterns, etc.) that form candidates for systematic defects that can be further assessed based on design uniqueness, repeater overlap, or combinations of both.

[0030] A candidate defect location may refer to any indicator of a possible defect, such as defect coordinates, suspect polygons, points-of-interest, or any other suitable indicator for a point or section of a circuit design. The diagnosis reports 220 accessed by the systematic defect determination engine 110 may specify or determine candidate defect locations in various manners. Scan diagnosis may support verification of logic of a circuit design, and volume diagnosis processes may correlate digital logic errors or failing scan signatures to physical layout portions of a circuit design at which such failures could have occurred. As such, candidate defect locations may indicate portions of a physical design (e.g., layout polygons, points, etc.) at which defects could have occurred to cause a failing scan signature.

[0031] Since the physical circuits 210 are manufactured according to the same circuit design, identical candidate defect locations may indicate that two (or more) of the physical circuits are defective in an identical manner. In that regard, a repeater set may, through corresponding diagnosis reports, identify a subset of the physical circuits 210 that have failed identically. Identically failing chips can be further analyzed to assess whether a common root cause (e.g., a common layout pattern) has caused these chips to fail identically. Accordingly, identification of repeater sets may be a useful mechanism to help guide detection of layout-based systematic root causes in a circuit design.

[0032] Any configurable parameters may guide the identification of repeater sets by the systematic defect determination engine 110. In some implementations, the systematic defect determination engine 1 10 may identify a repeater set comprised of at least two (2) diagnosis reports with identical candidate defect locations, through any configurable numerical threshold is contemplated herein (e.g., at least three (3) diagnosis reports, at least five (5)diagnosis reports, or any other numerical threshold for the number of diagnosis reports required to form a repeater set).

[0033] In some examples, the systematic defect determination engine 1 10 may require an exact match of candidate defect locations in order for two diagnosis reports to form a repeater set. An exact match may refer to exactly identical locations (e.g., circuit coordinates) for the candidate defect locations specified in respective diagnosis reports. Additionally or alternatively, the systematic defect determination engine 1 10 may determine candidate defect locations as identical based on relative location of candidate defects. Relative location may refer to a location (e.g., coordinates) within a circuit design element (e.g., design core, block, design unit, etc.).

[0034] To explain further, modern circuit design often involve hierarchical designs formed of levels of circuit design elements. Circuit design elements (e.g., of a particular hierarchy level) are often re-used and different instances of the same circuit design element may occur at different locations within a circuit design. As an illustrative example, a circuit design may include four (4) instances of an arithmetic logic unit (ALU). A particular diagnosis report for a particular physical circuit may specify a set of candidate defect locations within a first instance of the ALU in the circuit design, e.g., as a set of coordinates within the ALU. Another diagnosis report for a different physical circuit may specify a set of candidate defect locations, with the same coordinates within the ALU as the particular diagnosis report, but for a fourth instance of the ALU in the circuit design instead.

[0035] In this example, the exact location of the candidate defect locations within the physical circuits may differ, as the first instance ALU and the fourth instance of the ALU are located at different physical locations in the chip. However, the systematic defect determination engine 1 10 may nonetheless determine the diagnosis reports as part of the same repeater set since the relative location of the candidate defect locations are identical within the ALU design unit (e.g., the coordinates of the candidate defect locations within the ALU are identical). Put another way, the relative location of these candidate defects may be identical as they occur in the same location within a commoncircuit design unit. As such, the systematic defect determination engine 1 10 may determine that multiple diagnosis reports specify identical candidate defect locations relative to a given circuit design element even though instances of the given circuit design element may be at different chip locations for the multiple diagnosis reports.

[0036] As another example parameter, the systematic defect determination engine 110 may require diagnosis reports of a repeater set specify only the candidate defect locations identical to one another (whether exactly identical or relatively identical). That is, the systematic defect determination engine 1 10 may require a complete correlation of all specified defect candidate locations for different diagnosis reports. To illustrate, a first diagnosis report may specify candidate defect locationsi-5 and a second diagnosis report may identically specifies candidate defect locationsi-5, but also specify candidate defect locatione. In this example, the systematic defect determination engine 1 10 may determine these diagnosis reports as not specifying identical candidate defect locations since the second diagnosis report specifies an additional candidate defect location, and thus not part of the same repeater set. In this illustration, the systematic defect determination engine 1 10 may determine that a third diagnosis report that specifies only candidate defect locationsi-5 (e.g., locations relative to circuit design elements) can form a repeater set with the first diagnosis report.

[0037] Accordingly, the systematic defect determination engine 1 10 may apply any suitable parameters, configurations, or definitions to identify diagnosis reports that specify identical candidate defect locations and thus determine repeater sets among diagnosis reports generated for a population of physical circuits.

[0038] The systematic defect determination engine 110 may identify repeater sets through any suitable parsing of the diagnosis reports 220, which can vary based on the specific format that the diagnosis reports 220 are produced. For examples, diagnosis reports may identify candidate defect locations as coordinates, and the systematic defect determination engine 1 10 may identify identical candidate defect locations through identical coordinatesspecified in multiple diagnosis reports. In some implementations, the diagnosis reports 220 may specify candidate defect locations as relative locations within circuit design elements of a physical circuits (e.g., as the coordinates within an ALU instance of the circuit design instead of coordinates within the physical circuit). In such formats, the systematic defect determination engine 110 may determine identical candidate locations based solely on the specific candidate defect locations specified in a relative location format. As another example, diagnosis reports may specify candidate defect locations in the form of (or as including) polygons-of-interest or suspect polygon, and the systematic defect determination engine 1 10 may compare diagnosis reports to identify identical candidate defect locations through identical polygons.

[0039] Regardless of the format in which diagnosis reports are generated, the systematic defect determination engine 1 10 may identify a repeater set as diagnosis reports that specify identically occurring candidate defects for two or more physical circuits manufactured with the same circuit design. As such, another example of repeater set determination may be through detection of identical scan signature data, which may likewise indicate that two different physical circuits are failing identically. Through any available technique, processing, or analysis by which identically failing physical circuits can be identified, the systematic defect determination engine 110 may employ or implement such technology to determine repeater sets.

[0040] In the example of Figure 2, the systematic defect determination engine 110 identifies multiple repeater sets 230 from the diagnosis reports 220. As used herein, multiple repeater sets may refer to two or more repeater sets, and each repeater set may itself include multiple diagnosis reports grouped together, e.g., with identical candidate defect locations. In the example of Figure 2, the multiple repeater sets 230 includes a repeater set labeled as repeater setA that includes multiple diagnosis reports that specify identical candidate defect locations to one another. The example of Figure also includes another repeater set labeled as repeater sets, which includes multiple diagnosis reports that specify identical candidate defect locations toone another. The candidate defect locations specified by repeater setA may be different from the candidate defect locations specified by repeater sets. In that regard, each repeater set of the multiple repeater sets 230 may identify a different subset of physical circuits, and each different subset may fail identically with one another, but in a different manner as other subsets (at least according to candidate defect locations).

[0041] Repeater sets may comprise strong candidates for root cause detection of systematic defects, as a given repeater set is indicative of multiple physical circuits that have failed identically. However, even though these physical circuits have identical failing scan signatures and failure causes in diagnosis reports, the candidate defect locations specified in the diagnosis reports of a repeater set will likely include non-defective locations. This may be the case as scan tests cannot comprehensively test every single possible defect location in a circuit design, and failure signature data may be in the form of digital data indicative that particular logic instances of a circuit are defective. Thus, defects in multiple different locations of a circuit design can produce in the same failure signature.

[0042] To illustrate, a failure signature of a scan test may indicate that a defect occurred on a wire between two different points in the circuit design. However, there may be multiple points along the wire at which the defect could have occurred, each of which would cause the same failure signature in a scan test. These multiple points may be referred to as points-of-interest, and various methods of point-of-interest identification are supported by EDA technologies. Volume diagnosis processes and diagnosis reports may report each of these points-of-interest as a candidate defect location, as each point- of-interest is located along the wire between the two different points that caused the failure signature in the scan test. Point-of-interest determination may be supported by various EDA technologies, and any suitable schemes, mechanisms, procedures, or technology is contemplated herein for point-of- interest determinations in circuit designs for defect detection (and, as described herein, layout pattern extraction).

[0043] It is unlikely that every point-of-interest determined through volume diagnosis from failing scan signatures is defective in the physical circuit. Thus it is unlikely that every candidate defect location specified in a diagnosis report is a root cause of the determined defect. For consistent reasons, the candidate defect locations specified in the multiple repeater sets 230 almost certainly include non-defective locations. Performing failure analysis at each of the specified candidate defect locations in the multiple repeater sets 230 can be inefficient, cost-intensive, and immensely time-consuming.

[0044] The layout-based systematic defect determination technology of the present disclosure may support intelligent identification of root cause candidates from repeater sets. The systematic defect determination engine 1 10 may further analyze the multiple repeater sets 230 in order to determine layout-based systematic defect candidates from the defect candidate locations specified in the multiple repeater sets 230. In doing so, the systematic defect determination engine 1 10 may deterministically identify particular candidate defect locations (or corresponding layout patterns for the particular candidate defect locations) with increased likelihood of being a root cause of a systematic defect. As described herein, the systematic defect determination engine 110 may do so through evaluating layout patterns based on a design uniqueness factor and a repeater overlap factor.

[0045] In support of such evaluation, the systematic defect determination engine 110 may extract layout patterns from a circuit design. In particular, the systematic defect determination engine 110 may extract layout patterns for individual repeater sets of the multiple repeater sets 230. Extraction of layout patterns may include process, technique, or functionality by which the systematic defect determination engine 1 10 accesses layout patterns. As such, the systematic defect determination engine 110 may access layout patterns for the multiple repeater sets 230 by accessing layout patterns that surround (e.g., are centered at) the candidate defect locations specified in each of the diagnosis reports of the multiple repeater sets 230.

[0046] The way in which the systematic defect determination engine 1 10 extracts layout patterns can vary, and any suitable extraction technique iscontemplated herein. For example, the systematic defect determination engine 110 may load the layout patterns for the candidate defect locations of the multiple repeater sets 230 from a memory or receive the layout patterns over a communication network. In some implementations, the systematic defect determination engine 1 10 itself extracts the layout patterns, for example doing so by accessing a layout file for the circuit design and extracting out a layout pattern that surrounds each of the candidate defect locations specified in the diagnosis reports of the multiple repeater sets 230. Layout patterns extracted for a particular repeater set may be considered part of the repeater set, e.g., as corresponding data of the repeater set.

[0047] The systematic defect determination engine 1 10 may extract layout patterns with extraction windows of a predetermined or configurable size. The extraction window may vary by circuit layer or by layout characteristics surrounding the candidate defect locations. Example layout characteristics may include polygon characteristics, current circuit layer, pitch width, and more. The systematic defect determination engine 1 10 may configure extraction windows to ensure sufficient layout data is captured surrounding the candidate defect locations, doing so in any suitable manner.

[0048] In the example of Figure 2, an illustrative example is depicted in which the systematic defect determination engine 1 10 extracts layout patterns for repeater setA of the multiple repeater sets 230. Repeater setA may comprise diagnosis reports that specify candidate defect locations 240, and the systematic defect determination engine 1 10 may extract a layout pattern for each of the candidate defect locations 240. In Figure 2, the systematic defect determination engine 1 10 extracts (e.g., loads) the layout patterns 250 for repeater setA and may similarly do so for repeater sets and other repeater sets of the multiple repeater sets.

[0049] The systematic defect determination engine 1 10 may then evaluate the extracted layout patterns for the multiple repeater sets 230 based on design uniqueness and repeater overlap factors. Example features of such evaluations are described in greater detail next with reference to Figures 3and 4 through a continuing example of extracted layout patterns for repeater setA.

[0050] Figure 3 shows an example evaluation of a design uniqueness factor for layout patterns for a repeater set according to the present disclosure. The systematic defect determination engine 1 10 may evaluate individual layout patterns for design uniqueness, particularly layout patterns extracted for a repeater set. In the example of Figure 3, the layout patterns 250 for repeater setA are illustrated to include three (3) layout patterns labeled as layout patternAi, layout patterns, and layout patternA3. The systematic defect determination engine 110 may evaluate each for design uniqueness.

[0051] As described herein, a design uniqueness factor may assess a degree to which a given layout pattern is unique with a circuit design. Uniqueness may be measured by infrequency of occurrence, as described herein. Thus, design uniqueness may assess a degree to which a given layout pattern does not otherwise occur in a circuit design. In some implementations, design uniqueness (and repeater overlap, as described herein) may be assessed based on exactly identical layout patterns, similar layout patterns, or a combination of both. As used herein, similarity between layout patterns may refer to any quantifiable metric by which differences between the layout patterns can be measured. In some implementations, similarity between layout patterns is measured based on the geometrical features of the layout patterns, polygon positioning and size, polygon vertex locations, or any other aspect that characterize layout patterns. Any suitable method to measure similarity between layout patterns can be implemented or performed by the systematic defect determination engine 110. Examples of similarity determinations that the systematic defect determination engine 110 may employ may include fuzzy pattern matching, overlap percentages, bitmap overlay and comparisons, and the like.

[0052] The design uniqueness factor may assess a degree to which the given layout pattern, as well as layout patterns similar to the given layout pattern, are unique (e.g., do not otherwise occur) within the circuit design. To measure design uniqueness, the systematic defect determination engine 1 10may quantify a degree to which a given layout pattern, and similar layout patterns, occur in a full chip design for manufactured physical circuits. The systematic defect determination engine 110 may do so by extracting layout patterns for a full chip design, which may include layout patterns extracted for each point-of-interest in an entire circuit design.

[0053] To illustrate through Figure 3, a circuit design 310 is shown that represents the full-chip design used to manufacture the physical circuits 210 in Figure 2. The systematic defect determination engine 110 may extract layout patterns for the circuit design 310, whether by accessing the layout patterns from a local memory or remote server or by itself performing the extraction from a layout file for the circuit design 310. In the example of Figure 3, the systematic defect determination engine 1 10 extracts the layout patterns 320 for the circuit design 310, which may comprise layout patterns extracted for the entire full circuit design.

[0054] The layout patterns 320 for the circuit design 310 may be extracted by the systematic defect determination engine 1 10 in a consistent manner as the layout patterns extracted for the multiple repeater sets 230, or vice versa. For example, the systematic defect determination engine 1 10 may utilize the same point-of-interest scheme to extract layout patterns for the entire circuit design and for the repeater sets. The particular point-of-interest mechanism employed by the systematic defect determination engine 1 10 may be any suitable technique, and consistent extraction for the full chip design and candidate defect locations of repeater sets can support a reliable comparison for design uniqueness evaluations.

[0055] In some implementations, the systematic defect determination engine 1 10 extracts the layout patterns 320 for the circuit design 310 prior to layout pattern extraction for the multiple repeater sets 230. In this way, the systematic defect determination engine 1 10 may obtain layout patterns for the entire chip design, which will include any potential candidate defect locations since the points-of-interest for a full chip will necessarily include any candidate defect locations also identified through the same point-of-interest scheme. The systematic defect determination engine 110 may then extract the layoutpatterns for the multiple repeater sets 230 by identifying and accessing the particular layout patterns among the full-chip layout patterns that correspond to failing scan signature through which the candidate defect locations specified in the diagnosis reports of the multiple repeater sets 230 are determined.

[0056] To evaluate the design uniqueness of a given layout pattern, the systematic defect determination engine 1 10 may determine a degree to which the given layout pattern and any similar layout patterns occur in the layout patterns for the full circuit design. As similarity may be a quantifiable comparison technique performed by the systematic defect determination engine 1 10, a similarity threshold can be used to assess whether two layout patterns are similar to one another or not. For design uniqueness evaluations, the systematic defect determination engine 1 10 may apply a design similarity threshold. For example, the systematic defect determination engine 1 10 may compare layout patterns for similarity through pattern overlap, and the design similarity threshold may be specified as a threshold overlap percentage between compared layout patterns (e.g., 98.5% or 99%)

[0057] To illustrate through Figure 3, the systematic defect determination engine 1 10 may evaluate the design uniqueness factor for the layout patterns 250 extracted for repeater setA. For layout patternAi , the systematic defect determination engine 110 may perform a similarity comparison between layout patternAi and each of the layout patterns 320 extracted for the full-chip layout of the circuit design 310, for example doing so via a design similarity threshold set at an overlap percentage of 98.5% and higher. In such examples, the systematic defect determination engine 110 may quantitatively determine a number of other layout patterns (including identical layout patterns) similar to a given layout pattern that occur in the full circuit layout patterns 320, such as for the layout patternAi.

[0058] In a similar manner, the systematic defect determination engine 1 10 may determine a number of similar layout patterns that occur in the layout patterns 320 for other layout patterns of repeater setA, including layout patternA2 and layout patternA3. As an illustrative example, the systematicdefect determination engine 1 10 may identify occurrence of multiple similar layout patterns for layout patternA2, including the specific layout patterns with bolded frames among the layout patterns 320 in Figure 3. While only a few example similar layout patterns are shown in Figure 3, the systematic defect determination engine 1 10 may compare each of the layout patterns 250 of repeater setA with the entire layout patterns for the full chip design in order to assess design uniqueness.

[0059] Design uniqueness may be determined by the systematic defect determination engine 110 as a function of the number of similar layout patterns that occur in a circuit design, or any equivalent measure. The higher the number of similar layout patterns that occur in the circuit design 310, the less unique the given layout pattern is in the circuit design 310 and the lesser the design uniqueness. The lower the number of similar layout patterns that occur in the circuit design 310, the more unique the given layout pattern is in the circuit design and the higher the design uniqueness. In some examples, the systematic defect determination engine 1 10 computes a design uniqueness value for the given layout pattern as a function of a number of the other layout patterns in the circuit design 310 that are similar to a given layout pattern, as measured within the design similarity threshold. Any suitable function is contemplated herein, and the systematic defect determination engine 1 10 may utilize, as examples, any suitable statistical algorithm, normalized definition, or weighted function to quantitatively determine a design uniqueness value that is based on the number of other similar layout patterns that occur in a circuit design (e.g., among layout patterns thereof).

[0060] In support of layout-based systematic defect candidate determinations, the systematic defect determination engine 110 may particularly identify layout patterns of repeater sets with high design uniqueness. As a circuit design can easily include billions of layout patterns (often times more), a particular layout pattern of a repeater set that is relatively unique may indicate that the layout pattern is more likely to cause a systematic defect. This may be the case since, if the particular layout pattern were not relatively unique in the circuit design 310, then the other instances of theparticular layout pattern would have also been part of the repeater set. Understood in another way, if instances of the particular layout pattern (or similar layout patterns) frequently occur in the circuit design 310 outside of the repeater set, then additional defects likely would have occurred due these other instances. If such defects to not systematically occur for a layout pattern with high occurrences within a circuit design, then it is unlikely that such a layout pattern is a root cause of systematic defects. Accordingly, the systematic defect determination engine 110 may particularly identify layout patterns of repeater sets with high design uniqueness as stronger candidates as the cause of systematic defects within a circuit design.

[0061] In the example of Figure 3, the systematic defect determination engine 1 10 evaluates the layout patterns 250 for design uniqueness. Classification of design uniqueness may be supported by the systematic defect determination engine 1 10 according to any metric or classification scheme. Example classifications may be “high”, “medium”, or “low”, which the systematic defect determination engine 110 can classify through ranges of design uniqueness values. In the example of Figure 3, the systematic defect determination engine 110 classifies layout patternAi and layout patternA3 with “high” design uniqueness and layout patternA2 with “low” design uniqueness.

[0062] In any of the ways described herein, the systematic defect determination engine 110 may evaluate design uniqueness for layout patterns of multiple repeater sets. As another feature, the systematic defect determination engine 1 10 may evaluate repeater overlap for layout patterns of the multiple repeater steps, example features of which are described next with reference to Figure 4.

[0063] Figure 4 shows an example evaluation of a repeater overlap factor for layout patterns for a repeater set according to the present disclosure. The systematic defect determination engine 1 10 may evaluate individual layout patterns for repeater overlap, including layout patterns extracted for a repeater set. In Figure 4, the layout patterns 250 for repeater setA are illustrated to include three (3) layout patterns labeled as layout patternAi, layout pattens,and layout patteiriA3, each of which the systematic defect determination engine 110 may evaluate for repeater overlap.

[0064] As described herein, a repeater overlap factor may assess a degree to which a given layout pattern or similar layout patterns occur among other different repeater sets. Thus, the repeater overlap factor may assess a degree to which a given layout pattern, as well as layout patterns similar to the given layout pattern, occur within other repeater sets. To measure repeater overlap, the systematic defect determination engine 110 may quantify a degree to which a given layout pattern, and similar layout patterns, occur in the other repeater sets determined for manufactured physical circuits of the same circuit design. The systematic defect determination engine 1 10 may do so by comparing a given layout pattern with the layout patterns extracted for other repeater sets.

[0065] To illustrate through Figure 4, the systematic defect determination engine 110 may assess repeater overlap for each of the layout patterns 250 of repeater setA. For layout patternAi , the systematic defect determination engine 110 may perform a similarity comparison between layout patternAi and each of the layout patterns extracted for other repeater sets, such as repeater sets and repeater setc shown in Figure 4. In Figure 4, the layout patterns extracted for repeater sets are labeled as the layout patterns 410 and the layout patterns extracted for repeater setc are labeled as the layout patterns 420.

[0066] In comparing layout patterns, the systematic defect determination engine 110 may implement or perform similarity functionality in a consistent manner as with the evaluation of design uniqueness as described herein. However, the systematic defect determination engine 1 10 may apply any differentiated or configurable parameters for the similarity comparisons in support of repeater overlap comparisons. For instance, the systematic defect determination engine 110 may measure similarity for repeater overlap comparisons through a repeater similarity threshold. The systematic defect determination engine 1 10 may configure the repeater similarity threshold to be the same or to be different from the design similarity threshold applied fordesign uniqueness evaluations. As an illustrative example, the systematic defect determination engine 1 10 may perform similarity comparisons for layout patterns via a repeater similarity threshold set at an overlap percentage of 98.5% and higher, which may be the same or different as the design similarity threshold applied for design uniqueness evaluations.

[0067] In Figure 4, the systematic defect determination engine 1 10 may perform similarity comparisons between layout patternAi of repeater setA and layout patterns extracted for other repeater sets different from repeater setA. In doing so, the systematic defect determination engine 110 may quantitatively determine a number of other layout patterns that are similar to layout patternAi (including identical layout patterns) that occur among layout patterns extracted for other different repeater sets. Such a repeater overlap evaluation can include similarity comparisons among the layout patterns 410 and 420 extracted for repeater sets and repeater setc. In a similar manner, the systematic defect determination engine 1 10 may determine a number of similar layout patterns that occur in layout patterns extracted for repeater sets for layout patternA2 and layout patternA3 of repeater setA.

[0068] As an illustrative example, the systematic defect determination engine 1 10 may identify occurrence of multiple similar layout patterns for layout patternA3 among the layout patterns 410 for repeater sets and the layout patterns for repeater setc, including the specific layout patterns in Figure 4 with bolded frames. While only a few example similar layout patterns are shown in Figure 4, the systematic defect determination engine 1 10 may compare each of the layout patterns 250 of repeater setA with each of the layout patterns extracted for other repeater sets in order to assess repeater overlap. The systematic defect determination engine 110 may likewise assess repeater overlap for the layout patterns 410 of repeater sets and the layout patterns 420 of repeater setc as well.

[0069] In some implementations, the systematic defect determination engine 1 10 assesses repeater overlap for only a subset of the extracted layout patterns of a repeater set. In particular, the systematic defect determination engine 1 10 may assess repeater overlap only for extracted layout patterns ofa repeater set determined to have high design uniqueness (e.g., above a threshold for computed design uniqueness values). For example, the systematic defect determination engine 110 may first assess a repeater set for design uniqueness and filter layout patterns extracted for a repeater set to include only those with high design uniqueness. Or, as another example, the systematic defect determination engine 110 may remove layout patterns classified with low design uniqueness. Then, the systematic defect determination engine 1 10 may assess repeater overlap for the filtered set of layout patterns. As an illustrative example, the systematic defect determination engine 110 may determine that layout pattern A2 has “low” design uniqueness and filter out layout patternA2 to form a filtered set of layout patterns for repeater setA that includes only layout patternAi and layout patternA3. Then, the systematic defect determination engine 1 10 may assess design uniqueness on this filtered set of layout patterns, e.g., for layout patternAi and layout patternA3 (and not layout pattern A2).

[0070] Repeater overlap may be determined by the systematic defect determination engine 110 as a function of the number of similar layout patterns that occur in other repeater sets different from the repeater set of a given layout pattern, or any equivalent measure. The higher the number of similar layout patterns that occur, the greater the overlap of a given layout pattern with other layout patterns determined as repeaters, and the greater the repeater overlap assessed by the systematic defect determination engine 110. The lower the number of similar layout patterns that occur, the lesser the overlap of the given layout pattern with other layout patterns determined as repeaters, and the lower the repeater overlap as assessed by the systematic defect determination engine 1 10. In some examples, the systematic defect determination engine 1 10 computes a repeater overlap value for a given layout pattern as a function of a number of the other layout patterns in the other repeater sets that are similar to the given layout pattern, as measured within the repeater similarity threshold. Any suitable function is contemplated herein, which may be different, similar, or the same as the function applied for design uniqueness evaluations. The systematic defect determination engine1 10 may utilize, as examples, any suitable statistical algorithm, normalized definition, or weighted function to quantitatively determine a repeater overlap value for a given layout pattern that is based on the number of other similar layout patterns that occur in other repeater sets different from the repeater set that the given layout pattern is part of.

[0071] In support of layout-based systematic defect candidate determinations, the systematic defect determination engine 110 may particularly identify layout patterns of repeater sets with high repeater overlap. Multiple similar layout patterns causing different sets of physical circuits to fail identically can indicate that a common geometric feature among the layout patterns is causing a systematic defect. As such, repeater overlap may be indicative of a common issue among repeater sets that causes systematic defects to occur in manufactured circuits. The systematic defect determination engine 1 10 may thus particularly identify layout patterns of repeater sets with high repeater overlap as stronger candidates as the cause of systematic defects within a circuit design.

[0072] In the example of Figure 4, the systematic defect determination engine 1 10 evaluates the layout patterns 250 for repeater overlap. Classification of design uniqueness may be supported by the systematic defect determination engine 1 10 according to any metric or classification scheme. Example classifications may be “high”, “medium”, or “low”, which the systematic defect determination engine 110 can classify through ranges of repeater overlap values. In the example of Figure 4, the systematic defect determination engine 110 classifies layout patternAi and layout patternA2 with “low” repeater overlap and layout patternA3 with “high” repeater overlap.

[0073] Accordingly, the systematic defect determination engine 1 10 may evaluate repeater overlap for layout patterns of multiple repeater sets. Through a combination of the design uniqueness and repeater overlap factors, the systematic defect determination engine 1 10 may determine layout-based systematic defect candidates, example features of which are described next with reference to Figure 5.

[0074] Figure 5 shows an example determination of a layout-based systematic defect candidate from layout patterns for a repeater set based on a design uniqueness factor and a repeater overlap factor. In the example of Figure 5, the systematic defect determination engine 110 assesses the layout patterns 250 extracted for repeater setA for both design uniqueness and repeater overlap in order to determine a layout-based systematic defect candidate.

[0075] Continuing the examples described herein, the systematic defect determination engine 1 10 may evaluate each of the layout patterns 250 for design uniqueness and repeater overlap. The systematic defect determination engine 110 may classify each individual layout pattern for these factors, e.g., do so based on computed design uniqueness and repeater overlap values and corresponding classification ranges. In the example of Figure 5, the systematic defect determination engine 1 10 classifies layout patternAi with high design uniqueness and low repeater overlap, layout patternA2 with low design uniqueness and low repeater overlap, and layout patternA3 with high design uniqueness and high repeater overlap.

[0076] The systematic defect determination engine 110 may identify layoutbased systematic defect candidates as layout patterns with (relatively) high design uniqueness and high repeater overlap. Such layout patterns may be part of repeater sets, and thus occur in multiple circuits that have failed identically. With high design uniqueness, such layout patterns occur in the repeater set(s) but not elsewhere in the circuit design and with high repeater overlap, such layout patterns are increasingly prevalent among repeater sets of identically failing die. High design uniqueness and high repeater overlap may guide the systematic defect determination engine 1 10 to select such layout patterns as strong candidates as root causes for systematic defects. In the example of Figure 5, the systematic defect determination engine 1 10 identifies layout patternA3 (with high design uniqueness and high repeater overlap) as a layout-based systematic defect candidate 510.

[0077] Note that the systematic defect determination engine 110 may identify layout patterns as layout-based systematic defect candidates basedon design uniqueness, repeater overlap, or a combination of both. In the example of Figure 5, the layout-based systematic defect candidate 510 determined for repeater setA may be one of multiple layout-based systematic defect candidates determined by the systematic defect determination engine 1 10. The systematic defect determination engine 1 10 may evaluate layout patterns from different repeater sets, and thus the determined layout-based systematic defect candidates may include layout patterns from different repeater sets.

[0078] In some implementations, the systematic defect determination engine 1 10 may normalize design uniqueness values and repeater overlap values computed for layout patterns of repeater sets, e.g., both on a normalized scale of 0-10 or 0-1 . As such, the systematic defect determination engine 1 10 may compare design uniqueness and repeater overlap on a common scale, and classify “high” design uniqueness and “high” repeater overlap along a common, normalized range of values. In some implementations, the systematic defect determination engine 1 10 may plot evaluated layout patterns on a grid, with one axis for design uniqueness and one axis for repeater overlap. In such a manner, visualization of the layout pattern analyses of repeater sets can be readily consumed and easily understood.

[0079] In some implementations, the systematic defect determination engine 1 10 may identify, as layout-based systematic defect candidates, layout patterns with low repeater overlap, but high design uniqueness. This may be indicative of a situation in which repeating defects in physical circuits are occurring, but are unlike other defects in other repeater sets. As such, the systematic defect determination engine 1 10 may identify such layout patterns as layout-based systematic defect candidates for further investigation. The degree, parameters, or process by which the systematic defect determination engine 110 determines layout patterns of a given repeater set with high design uniqueness layout-based as systematic defect candidates may be configurable. Any number of thresholds may be set or configured by the systematic defect determination engine 1 10 to support such determinations, though the systematic defect determination engine 1 10 may prioritize layoutpatterns of repeater sets with high design uniqueness and high repeater overlap as stronger layout-based systematic defect candidates.

[0080] The systematic defect determination engine 110 may provide any determined layout-based systematic defect candidates for failure analysis. Such layout patterns (and corresponding candidate defect locations) may be strong candidates as root causes of systematic defects. However, the systematic defect determination engine 110 need not send the other layout patterns not determined as layout-based systematic defect candidates for failure analysis. Such layout patterns have been determined to be not unique within a circuit design, not overlapping with other repeater sets, or both. By doing so, the systematic defect determination engine 110 may improve the efficiency of systematic defect determinations by supporting PFA performance on an intelligently selected subset of layout patterns, instead of all of the layout patterns found in repeater sets. Such efficiencies may provide tangible technical effects, as a lesser number of failure analyses can be performed as compared to conventional brute force PFA processes for volume diagnosis data.

[0081] As yet another example, the systematic defect determination engine 1 10 may flag determined layout-based systematic defect candidates as potential root causes for systematic defects. Flagging may include any specific display marker, metadata, or other suitable indicator that specifies a layout pattern or candidate defect location is a systematic defect candidate (or root cause thereof). For instance, the systematic defect determination engine 1 10 may annotate any diagnosis reports that include the determined layoutbased systematic defect candidates (e.g., include the same layout pattern or the candidate defect location / polygon information). Such annotation may be useful for diagnosis reports generated for different circuit designs, providing a knowledge-base and detection capabilities for problematic layout patterns that can cause systematic design issues.

[0082] Determination of layout-based systematic defect candidates may also support circuit redesigns or manufacturing process changes to address problematic layout patterns. In such examples, the systematic defectdetermination engine 1 10 may itself implement a circuit re-design of the problematic layout patterns (e.g., aided via user input) or adjust one or more manufacturing process parameters to improve the fabrication of the layout pattern. While some example features are presented herein, any suitable application, use, or subsequent effect based on determined layout-based systematic defect candidates is contemplated herein.

[0083] Many of the examples described herein are provided in the context of repeater sets determined through identical defect candidate locations. However, the layout-based systematic defect determination technology of the present disclosure is not so limited. The systematic defect determination engine 110 may identify repeater sets according to any suitable parameter, configuration, process, or criteria. As one example, the systematic defect determination engine 1 10 may determine diagnosis reports are part of the same repeater set with overlapping candidate defect locations, e.g., a first diagnosis report specifying defect candidate locationsi-5 and a second diagnosis report specifying defect candidate locationsi-6 determined to be part of the same repeater set due to overlapping candidate defect locations). In that regard, the systematic defect determination engine 1 10 need not require completely identical candidate defect locations for repeater set determinations. Candidate defect location overlap may require a threshold percentage to be part of the same repeater set (e.g., 90%+ overlap of identical candidate defect locations between diagnosis reports), which may be configurable.

[0084] Any suitable mechanism is contemplated herein by which the systematic defect determination engine 1 10 can group diagnosis reports into repeater sets, including without requiring any overlapping or identical defect candidate locations. For example, the systematic defect determination engine 1 10 may randomly select diagnosis reports to form a first repeater set, randomly select other diagnosis reports to form a second repeater set, and so forth. As yet another example, the systematic defect determination engine 1 10 may group diagnosis reports into repeater sets based on, at least in part, lot number or wafer location at which physical circuits are generated. In thatregard, a repeater set may represent any group of diagnosis reports (and can include corresponding data) that the systematic defect determination engine 1 10 groups together. The required overlap degree of identical defect candidate locations for repeater set grouping can be customizable and configured by the systematic defect determination engine 1 10.

[0085] For a given repeater set that includes diagnosis reports with nonidentical candidate defect locations, the systematic defect determination engine 1 10 may extract layout patterns for each candidate defect location specified in the given repeater set as a whole (e.g., not just the overlapping candidate defect locations in a repeater set). In other examples, the systematic defect determination engine 110 may limit layout patterns for a given repeater set to only the layout patterns of overlapping (e.g., identical) candidate defect locations in the repeater set (e.g., identically specified in two or more diagnosis reports). As such, the systematic defect determination engine 110 may employ multiple techniques, processes, or configurations in extracting layout patterns for a given repeater set. Then, the systematic defect determination engine 110 may evaluate layout patterns of repeater sets based on design uniqueness and repeater overlap factors in order to determine systematic defect candidates.

[0086] Many layout-based systematic defect determination features have been described herein through illustrative examples presented through various figures. The systematic defect determination engine 110 may implement any of the layout-based systematic defect determination features described herein, including individually and in combination. As yet another example feature, the systematic defect determination engine 110 may perform any combination of the layout-based systematic defect determination technology described herein on a layer-by-layer basis, and each layer may be customized with different parameters or configurations. Example per-layer configurations can include extraction window sizes for layout patterns, similarity thresholds (whether design similarity, repeater similarity, or both), any of the evaluation operations for design uniqueness and repeater overlap, and more.

[0087] Figure 6 shows an example of logic 600 that a system may implement to support layout-based systematic defect determinations through design uniqueness and repeater overlap. For example, the computing system 100 may implement the logic 600 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 600 via the systematic defect determination engine 1 10, through which the computing system 100 may perform or execute the logic 600 as a method to support layout-based systematic defect determinations through design uniqueness and repeater overlap. The following description of the logic 600 is provided using the systematic defect determination engine 1 10 as an example implementation. However, various other implementation options by systems are possible.

[0088] In implementing the logic 600, the systematic defect determination engine 1 10 may access diagnosis reports generated for physical circuits manufactured for a circuit design (602) and identify multiple repeater sets from the diagnosis reports (604), doing so in any of the ways described herein. Then, the systematic defect determination engine 1 10 may extract layout patterns, for the given repeater set, from the candidate defect locations that are identical to one another in the diagnosis reports of the given repeater set (606) and determine a layout-based systematic defect candidate from among the layout patterns of the given repeater set based on a design uniqueness factor and a repeater overlap factor assessed for the layout patterns of the given repeater set (608), e.g., as described herein.

[0089] The logic 600 shown in Figure 6 provides an illustrative example by which a computing system 100 may support, implement, or provide layoutbased systematic defect determinations through design uniqueness and repeater overlap. Additional or alternative steps in the logic 600 are contemplated herein, including according to any of the layout-based systematic defect determination technology described herein.

[0090] Figure 7 shows an example of a computing system 700 that supports layout-based systematic defect determinations through design uniqueness and repeater overlap. The computing system 700 may include a processor710, which may take the form of a single or multiple processors. The processor(s) 710 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 700 may include a machine-readable medium 720. The machine-readable medium 720 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the systematic defect determination instructions 722 shown in Figure 7. As such, the machine-readable medium 720 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0091] The computing system 700 may execute instructions stored on the machine-readable medium 720 through the processor 710. Executing the instructions (e.g., the systematic defect determination instructions 722) may cause the computing system 700 to perform any combination of the layoutbased systematic defect determination features described herein, including according to any of the features of the systematic defect determination engine 1 10.

[0092] For example, execution of the systematic defect determination instructions 722 by the processor 710 may cause the computing system 700 to access diagnosis reports generated for physical circuits manufactured for a circuit design and identify multiple repeater sets from the diagnosis reports, doing so in any of the ways described herein. Execution of the systematic defect determination instructions 722 by the processor 710 may also cause the computing system 700 to extract layout patterns, for the given repeater set, from the candidate defect locations that are identical to one another in the diagnosis reports of the given repeater set and determine a layout-based systematic defect candidate from among the layout patterns of the given repeater set based on a design uniqueness factor and a repeater overlap factor assessed for the layout patterns of the given repeater set, e.g., as described herein.

[0093] Any additional or alternative layout-based systematic defect determination features as described herein may be implemented via the systematic defect determination instructions 722.

[0094] The systems, methods, devices, and logic described above, including the systematic defect determination engine 1 10, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the systematic defect determination engine 1 10 may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the description above, including according to any features of the systematic defect determination engine 1 10.

[0095] The processing capability of the systems, devices, and engines described herein, including the systematic defect determination engine 110, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).

[0096] While various examples have been described above, many more implementations are possible.

Claims

CLAIMS1 . A method comprising: by a computing system (100, 700): accessing (602) diagnosis reports (220) generated for physical circuits manufactured for a circuit design (310), wherein each diagnosis report specifies candidate defect locations (240) determined for a physical circuit; identifying (604) multiple repeater sets (230) from the diagnosis reports (220), wherein a given repeater set includes diagnosis reports (220) with candidate defect locations (240) that are identical to one another; extracting (606) layout patterns (250), for the given repeater set, from the candidate defect locations (240) that are identical to one another in the diagnosis reports (220) of the given repeater set; determining (608) a layout-based systematic defect candidate (510) from among the layout patterns (250) of the given repeater set based on a design uniqueness factor and a repeater overlap factor assessed for the layout patterns of the given repeater set, wherein, for a given layout pattern of the given repeater set: the design uniqueness factor is based on a degree to which other layout patterns similar to the given layout pattern, as measured within a design similarity threshold, do not otherwise occur among layout patterns (320) for the circuit design (310); and the repeater overlap factor is based on a degree to which other layout patterns similar to the given layout pattern, as measured within a repeater similarity threshold, occur among layout patterns (410, 420) for other repeater sets of the multiple repeater sets (230).

2. The method of claim 1 , further comprising providing the layout-based systematic defect candidate (510) for physical failure analysis without providing other layout patterns for the given repeater set not determined tobe the layout-based systematic defect candidate for the physical failure analysis.

3. The method of claim 1 or 2, further comprising, for the given layout pattern of the given repeater set: computing a design uniqueness value for the given layout pattern as a function of a number of the other layout patterns in the circuit design (310) that are similar to the given layout pattern, as measured within the design similarity threshold.

4. The method of any of claims 1 -3, further comprising, for the given layout pattern of the given repeater set: computing a repeater overlap value for the given layout pattern as a function of a number of the other layout patterns in the other repeater sets that are similar to the given layout pattern, as measured within the repeater similarity threshold.

5. The method of any of claims 1 -4, further comprising annotating diagnosis reports (220) generated for physical circuits manufactured for a different circuit design indicating any defect candidate locations for the different circuit design that include the layout-based systematic defect candidate.

6. The method of any of claims 1 -5, wherein the design similarity threshold is specified as an overlap percentage between compared layout patterns, the repeater similarity threshold is specified as an overlap percentage between compared layout patterns, or a combination of both.

7. The method of any of claims 1 -6, wherein the design similarity threshold and the repeater similarity threshold are different.

8. A system (700) comprising: a processor (710); and a non-transitory machine-readable medium (720) comprising instructions (720) that, when executed by the processor (710), cause a computing system (100, 700) to: access diagnosis reports (220) generated for physical circuits manufactured for a circuit design (310), wherein each diagnosis report specifies candidate defect locations (240) determined for a physical circuit; identify multiple repeater sets (230) from the diagnosis reports (220), wherein a given repeater set includes diagnosis reports (220) with candidate defect locations (240) that are identical to one another; extract layout patterns (250), for the given repeater set, from the candidate defect locations (240) that are identical to one another in the diagnosis reports (220) of the given repeater set; determine a layout-based systematic defect candidate (510) from among the layout patterns (250) of the given repeater set based on a design uniqueness factor and a repeater overlap factor assessed for the layout patterns of the given repeater set, wherein, for a given layout pattern of the given repeater set: the design uniqueness factor is based on a degree to which other layout patterns similar to the given layout pattern, as measured within a design similarity threshold, do not otherwise occur among layout patterns (320) for the circuit design (310); and the repeater overlap factor is based on a degree to which other layout patterns similar to the given layout pattern, as measured within a repeater similarity threshold, occur among layout patterns (410, 420) for other repeater sets of the multiple repeater sets (230).

9. The system of claim 8, wherein the instructions (710), when executed, further cause the computing system (700) to provide the layout-based systematic defect candidate (510) for physical failure analysis without providing other layout patterns for the given repeater set not determined to be the determined layout-based systematic defect candidate for the physical failure analysis.

10. The system of claim 8 or 9, wherein the instructions (710), when executed, further cause the computing system (700) to, for the given layout pattern of the given repeater set: compute a design uniqueness value for the given layout pattern as a function of a number of the other layout patterns in the circuit design (310) that are similar to the given layout pattern, as measured within the design similarity threshold.11 . The system of any of claims 8-10, wherein the instructions (710), when executed, further cause the computing system (700) to, for the given layout pattern of the given repeater set: compute a repeater overlap value for the given layout pattern as a function of a number of the other layout patterns in the other repeater sets that are similar to the given layout pattern, as measured within the repeater similarity threshold.

12. The system of any of claims 8-11 , wherein the instructions (710), when executed, further cause the computing system (700) to annotate diagnosis reports (220) generated for physical circuits manufactured for a different circuit design indicating any defect candidate locations for the different circuit design that include the layout-based systematic defect candidate.

13. The system of any of claims 8-12, wherein the design similarity threshold is specified as an overlap percentage between compared layout patterns, the repeater similarity threshold is specified as an overlap percentage between compared layout patterns, or a combination of both.

14. The system of any of claims 8-13, wherein the design similarity threshold and the repeater similarity threshold are different.

15. A non-transitory machine-readable medium (720) comprising instructions (722) that, when executed by a processor (710), cause a computing system (100, 700) to a perform a method according to any of claims 1 -7.

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