Quantum error correction

Abstract

The present disclosure describes a method that involves receiving a description of a logical quantum circuit to be executed on a quantum computing system, determining a property of the logical quantum circuit and selecting a quantum error correction code from two or more candidate QECCs based on the determined property of the logical quantum circuit, in which the two or more candidate QECCs are capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system.

Description

Quantum Error CorrectionBACKGROUND1. Cross-Reference to Related Application

[0001] This application claims priority from US application No. 63 / 535480 filed 30 August 2023 and entitled QUANTUM ERROR CORRECTION which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No. 63 / 535480 filed 30 August 2023 and entitled QUANTUM ERROR CORRECTION which is hereby incorporated herein by reference for all purposes.2. Technical Field

[0002] This disclosure relates generally to quantum computing and, more particularly, to the selection of quantum error correction codes to implement logical quantum circuits.3. Description of Related Art

[0003] Quantum computing is computing based on quantum mechanical phenomena.Quantum computing is implemented by having quantum computers execute quantum circuits that represent the problem of interest. When a user wants to execute a quantum circuit using a quantum computer, they provide a logical representation of the program that they wish to run to the provider of the quantum computer. This logical representation is referred to as a logical quantum circuit and includes one or more logical quantum gates (logical operations, also referred to herein as logic gates, logical gates, or logic operations) to be performed on logical qubits. The provider transforms the logical quantum circuit into a physical quantum circuit that can be performed on their quantum computer hardware.

[0004] However, current quantum computing systems are noisy and imperfect. If a logical quantum circuit using k logical qubits is implemented as a physical quantum circuitusing k physical qubits, the execution of the physical quantum circuit on the imperfect quantum computing system may lead to erroneous results.SUMMARY

[0005] In one aspect, a method is provided. The method involves receiving a description of a logical quantum circuit to be executed on a quantum computing system, determining a property of the logical quantum circuit based on the description of the logical quantum circuit, and selecting a first quantum error correction code (QECC) from two or more candidate QECCs based on the determined property of the logical quantum circuit. The two or more candidate QECCs are capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system.

[0006] The logical quantum circuit may include logical quantum gates to be executed on logical qubits. The method may also involve generating a first physical quantum circuit executable by the quantum computing system by using the first QECC to map the logical quantum circuit to the first physical quantum circuit. The first physical quantum circuit may include physical quantum gates to be executed on physical qubits of the quantum computing system. The first physical quantum circuit, when executed by the quantum computing system, may implement the logical quantum circuit.

[0007] The method may also involve causing the first physical quantum circuit to be executed by the quantum computing system. Causing the first physical quantum circuit to be executed by the quantum computing system may involve executing the first physical quantum circuit by the quantum computing system. Causing the first physical quantum circuit to be executed by the quantum computing system may comprise transmitting the first physical quantum circuit to the quantum computing system for execution.

[0008] Selecting the first QECC may also involve determining that a number of physical qubits to implement the first physical quantum circuit is equal to or smaller than a number of available physical qubits of the quantum computing system.

[0009] The first QECC may be selected according to the fidelities of the quantum computing system executing particular physical quantum gates and the physical quantum gates of the first physical quantum circuit.

[0010] Selecting the first QECC may be based on a simulation of the first physical quantum circuit. That is, selecting the first QECC may be based on a simulation of a first physical quantum circuit generated by using the first QECC to map the logical quantum circuit to the first physical quantum circuit. The method may also involve selecting a second QECC from the candidate QECCs and generating, using the second QECC, a second physical quantum circuit executable by the quantum computing system, by using the second QECC to map the logical quantum circuit to the second physical quantum circuit. The second QECC may be different than the first QECC. The method may also involve determining the first physical quantum circuit has an improved performance metric value relative to the second physical quantum circuit. The method may also involve transmitting the first physical quantum circuit to the quantum computing system for execution.

[0011] Determining the first physical quantum circuit has the improved performance metric value relative to the second physical quantum circuit may involve determining a first value of the performance metric for the first physical quantum circuit based on a simulation of the first physical quantum circuit, determining a second value of the performance metric for the second physical quantum circuit based on a simulation of the second physical quantum circuit, and comparing the first value of the performance metricfor the first physical quantum circuit to the second value of the performance metric for the second physical quantum circuit.

[0012] The determined property of the logical quantum circuit may include at least one of: a gate type of each logical quantum gate in the logical quantum circuit; a count of logical quantum gates of each gate type in the logical quantum circuit; a most common logical quantum gate type of the logical quantum circuit; a sequence of logical quantum gates in the logical quantum circuit; a depth of the logical quantum circuit; a metric value indicating an amount of quantum entanglement resulting from implementing the logical quantum circuit; or a property of a partition of the logical quantum circuit.

[0013] The method may also involve determining a property for the two or more candidate QECCs. The determined property for the two or more candidate QECCs may relate to one or more logical quantum gates from the logical quantum circuit in the two or more candidate QECCs. The determined property of the candidate QECCs may be based on at least one of: a predicted execution time of one or more logical quantum gates from the logical quantum circuit in the candidate QECCs; a count of magic states to implement one or more logical quantum gates from the logical quantum circuit in the candidate QECCs; a count of Bell pairs to implement one or more logical quantum gates from the logical quantum circuit in the candidate QECCs; a fidelity of implementing one or more logical quantum gates from the logical quantum circuit in the candidate QECCs; a code distance of the candidate QECCs; a number of physical qubits accommodated by the candidate QECCs; a distance value of the candidate QECCs; a pseudo-threshold value of the candidate QECCs; an error spread value for a physical quantum gate of the candidate QECCs; or a decoder performance value of a decoder for the candidate QECCs.

[0014] The determined property of the logical quantum circuit may include the most common logical gate type of the logical quantum circuit. The first QECC may be selectedbased on a performance metric value of the first QECC for implementing the most common logical gate type in a physical quantum circuit.

[0015] The method may also involve, for each candidate QECC, determining a predicted execution time to implement the logical quantum circuit using the candidate QECC. The first QECC may be selected based on the predicted execution time. The predicted execution time may be based on the count of gates of each gate type in the logical quantum circuit.

[0016] The first QECC may also be selected according to a property of the quantum computing system. The property of the quantum computing system may be a qubit connectivity of the quantum computing system, and the first QECC may be selected according to the number of SWAP operations to be used to implement the logical quantum circuit using the first QECC.

[0017] The property of the quantum computing system may be a native gate set of the quantum computing system, and the first QECC may be selected according to a number of resources to implement the logical quantum circuit using quantum gates of the native gate set.

[0018] The property of the quantum computing system may include fidelities of the quantum computing system executing particular physical quantum gates. The first QECC may be selected according to the fidelities and the physical quantum gates of the first physical quantum circuit to be generated using the first QECC.

[0019] The property of the quantum computing system may include reliability values for implementing measurement protocols, and the first QECC may be selected according to the reliability values and a measurement protocol of the first QECC.

[0020] The property of the quantum computing system may include whether or not the quantum computing system implements 2-qubit gates using teleportation.

[0021] The method may also involve determining a second logical quantum circuit that is equivalent to the received logical quantum circuit, and determining second properties of the second logical quantum circuit. The first QECC may be selected according to the determined properties of the received logical quantum circuit and the determined second properties of the second logical quantum circuit. Determining the second logical quantum circuit may involve replacing a logical quantum gate of the logical quantum circuit with one or more logical quantum gates equivalent to the replaced logical quantum gate.

[0022] Selecting the first QECC may involve: selecting a first subset of the candidate QECCs according to the determined properties of the candidate QECCs and the determined properties of the received logical quantum circuit, and selecting a second subset of the candidate QECCs according to the determined properties of the candidate QECCs and the determined second properties of the second logical quantum circuit. The first QECC may be part of the first subset or the second subset. Selecting the first QECC may also involve selecting the first QECC based on a comparison of the first subset and the second subset.

[0023] The first QECC may be selected due to the first QECC allowing a logical gate of the logical quantum circuit to be implemented at least in part by a classically computable operation. Selecting the first QECC may also involve determining the most common gate type of the logical quantum circuit, and selecting the first QECC based on a determination that the first QECC allows the most common gate type of the logical quantum circuit to be implemented at least in part by a classically computable operation.

[0024] Selecting the first QECC may also involve, for the candidate QECCs, determining a total number of logical quantum gates of the logical quantum circuit that can be implemented at least in part with classically computable operations using theQECC, and selecting the first QECC based on the determined total numbers of logical quantum gates that can be implemented at least in part by classically computable operations.

[0025] Selecting the first QECC may also involve determining a most computationally expensive logical quantum gate of the logical quantum circuit, and selecting the first QECC based on a determination that the first QECC allows the most computationally expensive logical quantum gate to be implemented at least in part by a classically computable operation.

[0026] Selecting the first QECC from two or more candidate QECCs may comprise jointly selecting the first QECC and a basis for the selected first QECC.

[0027] In another aspect, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium may include stored instructions which, when executed by a computing system, cause the computing system to perform any of the methods described above.

[0028] In another aspect, a computing system including a quantum computing system or a classical computing system is provided. The computing system may be configured to perform any of the methods described above.

[0029] In another aspect, a computing system is provided. The computing system includes a classical computing system and a quantum computing system. The classical computing system may be configured to perform operations that include receiving a description of a logical quantum circuit to be executed on a quantum computing system, determining properties of the logical quantum circuit based on the description of the logical quantum circuit, and determining properties for two or more candidate QECCs capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system. The operations may further includeselecting a first QECC from two or more candidate QECCs based on the determined properties of the candidate QECCs, and generating a description of a first physical quantum circuit executable by the quantum computing system. The description of the first physical quantum circuit may be generated by using the first QECC to map the logical quantum circuit to the first physical quantum circuit. The two or more candidate QECCs may be capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system. The quantum computing system may be configured to perform operations that include receiving the description of the first physical quantum circuit, and executing the first physical quantum circuit on physical qubits of the quantum computing system.

[0030] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable mediums, and other technologies related to any of the above.BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Embodiments of the disclosure have other advantages and features which will be more readily apparent from the following detailed description and the appended claims, when taken in conjunction with the examples in the accompanying drawings, in which:

[0032] Fig. 1A is a block diagram of a quantum error correction code (QECC) selector system, in accordance with some embodiments of the present disclosure.

[0033] Fig. IB is a flow diagram showing operation of a QECC selector system, in accordance with some embodiments of the present disclosure.

[0034] Fig. 2 shows an example of implementing a logical H(l) gate using an [[8, 3, 2]] QECC, in accordance with some embodiments of the present disclosure.

[0035] Figs. 3A-3E show examples of circuit implementation using quantum computers of different qubit connectivity, in accordance with some embodiments of the present disclosure.

[0036] Figs. 4A-4B show examples of gate rewrite rules, in accordance with some embodiments of the present disclosure.

[0037] Fig. 5 shows two equivalent circuits, in accordance with some embodiments of the present disclosure.

[0038] Fig. 6 shows a transversal implementation of the Hadamard gate H on a 5- qubit code, in accordance with some embodiments of the present disclosure.

[0039] Figs. 7A and 7B show implementation of a logical quantum circuit using rewrite rules and classically-implementable gates, in accordance with some embodiments of the present disclosure.

[0040] Fig. 8A is a block diagram that illustrates a computing system, in accordance with some embodiments.

[0041] Fig. 8B illustrates an example cloud computing architecture, in accordance with some embodiments.

[0042] Fig. 8C is a block diagram that illustrates a quantum computing system, in accordance with some embodiments.

[0043] Fig. 8D is a diagram of a qubit register of the quantum computing system, in accordance with some embodiments.

[0044] Fig. 8E is a flow chart that illustrates an example execution of a quantum routine on the computing system, in accordance with some embodiments.

[0045] Fig. 9 is an example architecture of a classical computing system, in accordance with some embodiments.DETAILED DESCRIPTION

[0046] The figures and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed.I. Overview

[0047] In order to compensate for imperfections in current quantum computing systems, a quantum error correction code (QECC) may be used. A QECC provides a mapping from k logical qubits to n physical qubits, where n > k. The quantum circuit provided by the user is described in terms of the k logical qubits. The other n-k physical qubits are additional resources that can be used to store the k logical qubits in a redundant fashion and protect the k logical qubits from sources of error, such as decoherence, imperfect gate control, measurement error, etc. This is similar to classical error correction codes (such as the Hamming code) used in forward error correction. In general, a QECC may be parametrized by [[n, k, d]], in which d is the code distance. The maximum number of errors that can be detected and corrected by an [[n, k, d]] code is given by for aQECC with code distance d.

[0048] To map a user’s logical quantum circuit to a physical quantum circuit that can be executed on quantum computer hardware, the one or more logic gates in the user’s logical quantum circuit are replaced by physical gates that implement the same function as the logic gates and correct errors that may arise during the execution of the physical gates. The set of physical gates that are used to implement a particular logic gate depends on theQECC being used. For example, in an [[8,3,2]] QECC, a logical X gate may require performing 4 physical X gates.

[0049] Fig. 2 shows another example. Here, the logical quantum circuit 202 is a logical H(l) gate (i.e. a Hadamard gate performed on the first logical qubit). The QECC 204 is an [[8,3,2]] QECC. Using this QECC, the logical H(l) gate may be mapped to the physical quantum circuit (a set of physical gates) 206 shown in Fig. 2. This example implementation of the logical H(l) gate in the QECC 204 includes various phase gates (square boxes with an S in it), CNOT gates (circle with a plus sign in it that connects to another qubit) and Hadamard gates (square box with an H in it). That is, to implement a logical H(l) gate in a logical quantum circuit using a [[8,3,2]] QECC, the H(l) gate in the original circuit could be replaced by the gates shown in the physical quantum circuit 206. It will be appreciated that there are other mappings for the logical H(l) gate in the QECC 204 that may be used.

[0050] Many different QECCs may be available to map a given logical quantum circuit to different possible physical quantum circuits for implementation on quantum hardware. The QECC used to implement a logical quantum circuit can influence the total execution time of the circuit, the number of qubits needed to run the circuit, and the number of errors that could potentially be introduced into the circuit. Identifying QECCs with desirable properties is an ongoing challenge. However, for a particular QECC, the mapping from a logical quantum circuit to a physical quantum circuit can be very efficient for some logical quantum gates, and inefficient for others. For example, a QECC may have a high error-spread for one logical quantum gate and a low error-spread for another logical quantum gate. As another example, a QECC may require a large number of auxiliary resources (e.g. Bell pairs, and / or magic states etc.) to implement one sequence oflogical quantum gates and no or few auxiliary resources to implement another sequence of logical quantum gates.

[0051] Since the mapping from a logical quantum circuit to a physical quantum circuit in a particular QECC can be more efficient for some logical quantum gates than others, selecting a QECC based on the properties of a logical quantum circuit can improve the performance of that logical quantum circuit when executed on physical hardware.

[0052] To select from among candidate QECCs, the various candidate QECCs may be evaluated relative to the logical quantum circuit. Certain properties of the logical quantum circuit may be determined based on its description. Certain properties of the candidate QECCs may also be determined. The different candidate QECCs may be evaluated and one selected based on these properties, as described in the examples given herein.

[0053] The technology that carries out this selection may be referred to as a QECC selector or a QECC selector system. It may be implemented on a classical computer, for example. Fig. 1A is a block diagram of a QECC selector system 100. The QECC selector 100 includes a quantum circuit receiver module 102, a quantum circuit analyzer module 104, a selector module 106, and a quantum circuit compiler module 110. It will be appreciated that the modules 102, 104, 106 and 110 are merely one example of how the operations of the QECC selector 100 may be implemented. In other embodiments, some or all of the modules 102, 104, 106 and 110 may be omitted and / or the QECC selector 100 may include one or more other modules. The QECC selector 100 could be a standalone process or could be incorporated into another process or system, such as a compiler that converts a logical quantum circuit to a set of instructions to be executed by a controller for a quantum computing system.

[0054] As illustrated in Fig. 1A, the QECC selector 100 also includes a database 108 of different QECCs. Although the database 108 is shown as forming part of the QECC selector 100, it will be appreciated that the database 108 may, alternatively, be external to the QECC selector 100. For example, the QECC selector 100 may be able to retrieve information from the database 108 over a network (not illustrated).

[0055] Fig. IB is a flow diagram showing operation of the QECC selector 100. Module 102 receives a description of the logical quantum circuit of interest 112. The QECC selector 100 operates to determine which of the QECCs in database 108 is used to implement the logical quantum circuit 112. At 114, module 104 analyzes the logical quantum circuit 112 to determine one or more various properties of the circuit. The database 108 stores candidate QECCs for retrieval by the QECC selector 100. At 116, selector module 106 selects from among the different candidate QECCs. It does so based on the properties of the logical quantum circuit 112.

[0056] In the example of Fig. IB, the system 100 also generates the corresponding physical quantum circuit 120. The compiler module 110 generates the physical quantum circuit 120 at step 118 of Fig. IB by using the selected QECC to map the logical quantum circuit 112 to the physical circuit 120.

[0057] Note that the logical quantum circuit may be the entire circuit of interest or may be a section of a circuit of interest. Different sections may be replaced using different QECCs. Some sections of a quantum circuit may be better implemented using one code, while other sections are better implemented using a different code. For example, if a quantum circuit has a set of k logical qubits, it may be possible to partition that circuit into smaller subcircuits that have sets of kl, k2, k3, ... logical qubits. Each of those subcircuits may be mapped to a physical quantum circuit using sets of nl, n2, n3, ... physical qubits, and possibly using different QECCs for the different mappings.

[0058] The QECC selector 100 thus uses the properties of the logical quantum circuit 112 and, optionally, the hardware that the quantum circuit will run on, to select the QECC for the particular logical quantum circuit 112. The selection may be based on seeking to optimize a particular performance metric, such as reducing the number of potential errors and / or reducing the execution time of a circuit. The QECC selector 100 selects a particular QECC from the database 108 where many QECCs are stored.II. QECC Selector in detail

[0059] The operation of the selector 100 is now described in more detail with respect to the method illustrated in FIG. IB.II. 1. Receiving a description of the logical quantum circuit

[0060] The method begins with the QECC selector 100 receiving a description of the logical quantum circuit 112 (e.g. at the quantum circuit receiver module 102). The description of the logical quantum circuit 112 may be received over a network, via entry by a user into the QECC selector 100 (e.g. using one or more input devices, such as a keyboard and / or a mouse), etc. The QECC selector 100 may receive the circuit 112 in any suitable format, such as OpenQASM (Open Quantum Assembly Language, such as OpenQASM 3.0), Q#, QIR (Quantum Intermediate Representation), or in a graph-based format such as a directed acyclic graph (DAG) with metadata indicating which gates correspond to which nodes in the graph (e.g. in the DAG). The format may include a higher-level language, such as Silq. In some examples, a pre-processing step may be performed to convert the source code (e.g. the expression of the circuit in a higher-level language such as Silq) into logical quantum gates that the QECC selector 112 can operate on. In some examples, one or more additional compilation steps may be performed (by the QECC selector 100 or elsewhere) to reorganize the circuit. This may include removingredundant gates (e.g. two H gates back-to-back) and / or converting arbitrary rotations into a finite sequence of gates, among other things.II. 2. Determining properties of the logical quantum circuit

[0061] In step 114, the QECC selector 100 determines one or more properties (or, equivalently, characteristics) of the logical quantum circuit 112. This analysis may be performed at the quantum circuit analyzer module 104, for example. The properties could include one or more of the following: a gate type of one or more logical quantum gates in the logical quantum circuit 112 (e.g. a count of one or more gate types and / or the most common gate type etc.), a sequence of logical quantum gates in the logical quantum circuit 112, a depth of the logical quantum circuit 112, a metric value indicating an amount of quantum entanglement resulting from implementing the logical quantum circuit 112, and a property of a partition of the logical quantum circuit 112. Each of these properties, which are described in more detail below, may be used alone or in any combination.II. 2. 1. Gate type

[0062] The QECC selector 100 may determine the gate type of one or more logical quantum gates in the logical quantum circuit 112. Example gate types include: a phase gate, a Pauli-X (or bit-flip), a SWAP, a CNOT etc. Since different QECCs may be more efficient for different types of logical quantum gates, determining the gate type may allow for easily eliminating QECCs that are likely to be inefficient for the logical quantum circuit 112.

[0063] The QECC selector 100 may determine the gate type of some or all of the logical quantum gates in the logical quantum circuit 112. That is, the QECC selector 100 may determine the gate type of each logical quantum gate or a subset of logical quantum gates in the logical quantum circuit 112. In some examples, the QECC selector 100 may determine the count (e.g. number) of each type of logical quantum gate present in thecircuit. For example, the QECC selector 100 may analyze the logical quantum circuit 112 and compile the following table indicating the that the logical quantum circuit 112 consists of the following four types of gates in the quantities listed:

[0064] In other examples, the properties may include only the count of one or more particular types of logical gates (e.g. a subset of the gates present in the logical quantum circuit 112). This may be particularly appropriate for re source -intensive gates e.g. gates that are expected to be inefficient. Counting only a subset of gate types may reduce the time taken to analyze the logical quantum circuit 112 whilst still resulting in a more efficient QECC being selected. In some examples, the QECC selector 100 may simply determine whether or not particular types of logical quantum gate are present e.g. whether or not the logical quantum circuit 112 includes a Hadamard gate. Determining whether a particular type of gate is present may be quicker than counting each of the occurrences of that particular gate, further saving the time and computational resources involved in step 114.

[0065] In some examples, the QECC selector 100 may determine the most common (e.g. most frequently occurring) logical quantum gate(s) in the logical quantum circuit 112. Thus, for example, the properties may include the x most frequently occurring logical gates, in which x is a predetermined integer (e.g. x=l, 3 or 5 etc.). Selecting the QECC based on the most common type of logical gate may enable implementing the mostcommon type of logical quantum gate in the logical quantum circuit 112 more efficiently, thereby improving the efficiency of the resulting physical quantum circuit 110.II. 2. 2. Sequence of gates

[0066] The QECC selector 100 may determine (e.g. identify) a sequence of gates in the logical quantum circuit 112. A particular sequence of gates may provide opportunities to combine some of the physical representations of the gates in the sequence and reduce the amount of computation required. For example, a logical Hadamard may commonly follow a logical Phase gate, providing opportunities to combine the physical representations of the two. The length of a sequence may range from a minimum of 2 to any number. For example, the QECC selector 100 may identify each sequence of 2 or more gates. As the number of possibilities increases rapidly with sequence length, even for a circuit of finite length, in some examples, the QECC selector 100 may only identify sequences with a length below a predetermined value. Thus, for example, the QECC selector 100 may identify only sequences that include between 2 and 5 gates. In some examples, the QECC selector 100 may only identify gate sequences that occur more than a threshold number of times (e.g. more than once).II. 2. 3. Depth

[0067] The QECC selector 100 may determine the depth of the logical quantum circuit, which is the number of gates in the longest path through the logical quantum circuit 112. This may alternatively be described as the maximum number of gates for any single qubit line across all qubits. In some examples, the QECC selector 110 may determine the depth of the logical quantum circuit 112 from its description by tracing each qubit line through a directed acyclic graph (DAG) and counting how many gates each qubit line touches.II. 2. 4. Entanglement

[0068] The QECC selector 100 may determine a metric value indicating an amount of entanglement resulting from implementing the logical quantum circuit 112. Example metric values that may be used include: von Neumann entropy, relative entropy, distillable entanglement, and / or entanglement formation. The amount of entanglement may also be indicated by predicting how the size of partitions in the logical quantum circuit 112 may change during execution of the logical circuit 112 (which may vary as partitions are merged on 2-qubit gates, qubits are separated on reset or measurement etc.).II. 2. 5. Partition Properties

[0069] In some examples, the logical quantum circuit 112 may include two or more partitions. In this context, two partitions of a logical quantum circuit are parts of the logical quantum circuit that could be executed on separate components (e.g. with minimal or no communication between the components). Each partition may include two or more qubits (e.g. is a collection of qubits) that interact with one another. Partitioning a circuit may advantageously enable distributed quantum computing. The QECC selector 100 may, in step 114, determine properties of any partitions in the logical quantum circuit 112, such as the size of one or more partitions (e.g. all partitions) in the logical quantum circuit 112, the number of partitions in the logical quantum circuit 112, which gates are in each partition and / or which gates span multiple partitions etc. In some examples, the QECC selector 100 may determine the size of the largest partition in the logical quantum circuit 112 e.g. the maximum partition size. The size of a partition may be expressed in terms of the count or number of qubits in the partition.

[0070] In general, the partitioning of a logical quantum circuit may stay the same or may vary over the course of the circuit e.g. the size of partitions in the circuit may be different at the end of the logical quantum circuit 112 compared to the beginning of thelogical quantum circuit 112. As such, the QECC selector 100 may determine the properties of any partitions that the logical quantum circuit 112 is expected to have at a particular time in execution of the logical quantum circuit 112 or at multiple points in time during execution of the logical quantum circuit 112 (e.g. as a time series).II. 3. Selecting the QECC in step 116

[0071] In step 116, the QECC selector 100 selects a QECC from the database 108 based on the properties of the logical quantum circuit 112 determined in step 114. The database 108 stores two or more different QECCs, which may be referred to as candidate QECCs. The database may store properties of the candidate QECCs together with an identifier (e.g. a name, parity-check matrix etc.) for each candidate QECC. The QECC selector 100 may select the QECC from the database 108 by comparing the properties of the logical quantum circuit 112 determined in step 114 to properties of the candidate QECCs.

[0072] For example, the database 108 may store, for each candidate QECC, an indication of the performance (e.g. efficiency) of that candidate QECC for logical quantum circuits with any of the properties described above in respect of step 114. The performance indication may include one or more rankings of the candidate QECC and / or value of one or more performance metrics. These are discussed in more detail below.II. 3. 1. Ranking candidate QECCs

[0073] The QECC selector 100 may select the QECC from the database 108 by comparing the properties of the logical quantum circuit 112 determined in step 114 to rankings, stored in the database 108, of candidate QECCs for logical quantum circuits with those properties. The rankings may be predetermined (e.g. calculated before runtime of the QECC selector 100) based on one or more of the performance metrics described below in section II. 3. 2. Ranking candidate QECCs in advance may allow the QECC selector 100to identify the optimal QECC more quickly at runtime, thereby resulting in a faster QECC selector 100.

[0074] For example, the QECC selector 100 may determine in step 114 that the most common logical quantum gate in the logical quantum circuit 112 is the Hadamard gate. The database 108 may store a ranking of candidate QECCs for the Hadamard gate, indicating that a first candidate code has the best performance for the Hadamard gate, a second candidate code has the second best performance for the Hadamard gate etc. In step 116, the QECC selector 110 may send a request to the database 108 for the best QECC for the Hadamard gate and may receive, in response, an indication of the first code (that is, the highest ranked code for the Hadamard gate).

[0075] Although the examples provided above refer to ranking candidate QECCs based on only a single property of the logical quantum circuit 112, it will be appreciated that, in general, candidate QECCs may be ranked based on one or more properties of the logical quantum circuit 112.

[0076] Similarly, although the above examples refer to selecting a QECC based on the ranking of candidate QECCs for a single property of the logical quantum circuit 112, the QECC selector 100 may select the QECC based on respective rankings of candidate QECCs for multiple properties of the logical quantum circuit 112. For example, the QECC selector 100 may determine, in step 114, that the most common gate in the logical quantum circuit 112 is a CNOT (or CX) and the logical quantum circuit 112 also includes the gate sequence of a Phase gate following a Hadamard gate. The QECC selector 100 may thus compare the rankings in the database 108 to identify the candidate QECC that has the best rankings for both the CNOT gate and that particular gate sequence.II. 3. 2. Performance metrics for candidate QECCs

[0077] It will be appreciated that there are many different ways of quantifying the performance of a candidate QECC. Thus, the performance metric for a candidate QECC may be based on (e.g. may be calculated using or simply may be) one or more of the following: an error spread, a pseudo-threshold, a number of physical gates, a predicted execution time (or runtime), a number of additional resources (e.g. such as magic states and / or Bell pairs), fidelity, a number of physical qubits (or, equivalently, a number of auxiliary qubits), a code distance, a decoder performance value for a compatible decoder, etc. The database 108 may store values of one or more of these performance metrics for each candidate QECC.

[0078] Some of these performance metrics may depend on (e.g. be associated with) one or more properties of a particular logical quantum circuit for which a candidate QECC may be used. For example, a performance metric may depend on the logical quantum gate(s) in the logical quantum circuit 112 (e.g. a particular gate or sequence of gates). Therefore, the database 108 may associate one or more performance metrics for a candidate QECC with one or more respective properties of a logical quantum circuit (e.g. any of the properties discussed above in respect of step 114). The QECC selector 100 may, in step 116, use such association(s) to select a QECC from the candidate QECCs in the database 108 based on the properties determined in step 114.

[0079] For example, the database 108 may store, for one or more logical quantum gates for each candidate QECC, an error spread for an implementation of the respective logical quantum gate in the candidate QECC. In this context, the error spread indicates the number of qubits that the implementation of a logical gate would spread a 1 -qubit error to e.g. a logical quantum gate implementation that spreads a 1 -qubit error to 8 qubits has an error spread of 8. The QECC selector 100 may, in step 116, select the candidate QECCthat has the lowest error spread for the most common gate in the logical quantum circuit 112. In another example, the QECC selector 100 may select a QECC that will result in more than half of the gates in the physical quantum circuit 120 being low error spread gates. A low error spread gate may be a gate that has an error spread below a predetermined threshold. The predetermined threshold may be based on the number of physical qubits n in the physical quantum circuit mapped to by the candidate QECC. For example, the threshold may be equal to \ln such that any gate with an error spread less than 1 / n is a low error spread gate. Alternatively, the predetermined threshold may be based on the code distance, d. For example, the threshold may be equal to floor(( - 1 ) / 2) such that any gate with an error spread less than (( -l) / 2) is a low error spread gate. As another example, the threshold may be equal to 10% of floor(( - 1 ) / 2) such that any gate with an error spread less than 10% of floor(( -l) / 2) is a low error spread gate.

[0080] Selecting a candidate QECC based on the error spread of the logical quantum gates of the logical quantum circuit 112 in the candidate QECC may advantageously improve the accuracy of the physical quantum circuit whilst minimizing the rounds of error-correction required to achieve that accuracy.

[0081] Another example of a performance metric that may be specific to the properties of the logical quantum circuit 112 is the count of additional resources, such as magic states and / or Bell pairs, to implement one or more logical quantum gates in the candidate QECC. For example, the QECC selector 100 may obtain, from the database 108, the number of Bell pairs required to implement a teleported gate in the logical quantum circuit 112 (such as a CNOT) for candidate QECCs.

[0082] The database 108 may thus store, for one or more logical quantum gates for each candidate QECC, a count of magic states and / or Bell pairs to implement the respective logical quantum gate in the candidate QECC. Physical circuits that require moreBell pairs may have longer execution times since Bell pair generation may be probabilistic (e.g. may not always be successful). As a result, selecting a candidate QECC to minimize the number of Bell pairs to implement the logical quantum circuit 112 can reduce the execution time of the logical quantum circuit 112.

[0083] A further example of a performance metric that may be specific to the properties of the logical quantum circuit 112 is the number of physical gates that one or more logical quantum gates in the logical quantum circuit 112 are mapped to by the candidate QECC. The database 108 may store, for each candidate QECC, the count of physical gates used to implement one or more logical gates in that QECC. The QECC selector 100 may select the QECC from the candidate QECCs based on minimizing the number of physical gates used to implement the logical quantum circuit 112. The QECC selector 100 may calculate the number of physical gates required to implement all of the logical gates in the logical quantum circuit 112 or just some of the logical gates (e.g. the most common logical gate(s)).

[0084] This may be illustrated by an example in which the three most common gates in the logical quantum circuit 112 are the H (Hadamard) gate, the S gate and a T gate. The database 108 may store the following table indicating the count of physical gates used to implement particular logical quantum gates in two candidate codes, QECC 1 and QECC 2:

[0085] The QECC selector 100 may determine, from the table, that implementing the most common logical quantum gates (H, S and T) in the logical quantum circuit 112 would require 26 physical quantum gates for QECC 1 and 21 physical quantum gates forQECC 2. Based on this, the QECC selector 110 may select QECC 2 for use with the logical quantum circuit 112.

[0086] In this example, the QECC selector 100 considers only the total number of physical gates regardless of gate type. In other examples, the QECC selector 100 may also account for physical gate type.

[0087] Other examples of performance metrics for candidate QECCs that may depend on properties of the logical quantum circuit 112 are:• the predicted execution time of one or more logical quantum gates in the logical quantum circuit 112 in the candidate QECC, and• the fidelity of implementing one or more logical quantum gates in the logical quantum circuit 112 in the candidate QECC.

[0088] The QECC selector 100 may thus, for example, obtain an estimate of the execution times of the logical quantum gates in the logical quantum circuit 112 when implemented in a candidate QECC from the database 108 in order to estimate the overall execution time of the logical quantum circuit 112. The QECC selector 100 may select the QECC that is predicted to result in the smallest execution time for the logical quantum circuit 112.

[0089] As another example, the QECC selector 100 may select a QECC that has the highest fidelity implementation of one or more logical quantum gates in the logical quantum circuit 112. The QECC selector 100 may, for example, select the QECC that has the highest fidelity implementation of the most common gate in the logical quantum circuit. In this context, the fidelity of a logical quantum gate in a QECC indicates any deviation of the implementation of that logical quantum gate in the QECC from the theoretical (or ideal) logical quantum gate. That is, the fidelity may indicate how noisy the implementation of a logical quantum gate is in a particular QECC. The fidelity of aparticular logical quantum gate in a QECC may be the average fidelity of that logical quantum gate in the QECC (e.g. averaged over different states that the logical quantum gate may operate on).

[0090] Other performance metrics for a candidate QECC might be independent of the logical quantum circuit 112. Examples of such metrics may include: the number of physical qubits (or, equivalently, a number of auxiliary qubits) to implement a logical quantum circuit with k logical qubits, a code distance for the candidate QECC, a decoder performance value for a decoder that is compatible with the candidate QECC, etc. It will be appreciated that, in practice, some QECC properties may depend on properties of the logical quantum circuit, but for ease of computation may be assumed to be independent or calculated based on an aggregation over many different logical quantum circuits. In some embodiments, the QECC selector 100 may use one or more performance metrics for the candidate QECCs that are independent of the properties of the logical quantum circuit in combination with one or more performance metrics for the candidate QECCs that depend on the properties of the logical quantum circuit to select the QECC for the logical quantum circuit 112.

[0091] The QECC selector 100 may, for example, identify a subset of the candidate QECCs based on one or more performance metrics for the candidate QECCs that depend on a property of the logical quantum circuit 112 and select the QECC from that subset that requires the fewest number of physical qubits. Choosing a QECC that requires a reduced number of physical qubits may free up qubits for other calculations, enabling multiple circuits to be run in parallel.

[0092] As another example, the QECC selector 100 may identify a subset of the candidate QECCs based on one or more performance metrics for the candidate QECCsthat depend on a property of the logical quantum circuit 112 and select the QECC from that subset that has the highest code distance.

[0093] As a further example, the QECC selector 100 may identify a subset of the candidate QECCs based on one or more performance metrics for the candidate QECCs that depend on a property of the logical quantum circuit 112 and select the QECC from that subset that has an optimal decoder performance value for a compatible decoder. Not all QECCs have the same set of decoders. Decoders can be a limiting factor separate from the error correction properties of a QECC since classical computing performance can affect the maximum throughput of a decoder. Slow decoders can incur longer correction cycle times, which may in turn result in longer qubit idle times. This can reduce computation speed and also risk incurring further errors. In addition, different decoders afford different pseudo-thresholds for the same code. Thus, the QECC database 108 may store, for each QECC, a decoder performance value for a decoder that is compatible with the respective QECC. The decoder performance may include one or more of: a correction cycle time, a pseudo-threshold etc. For example, the QECC selector may select a QECC that has a compatible decoder with the lowest correction cycle time.

[0094] In general, the QECC selector 100 may select the candidate QECC based on one or more rankings and / or performance metrics obtained from the database 108. For example, the QECC selector 100 may identify a subset of the candidate QECCs that have an error spread below a threshold for the most common gate in the logical quantum circuit 112 and may select, from that subset, the candidate QECC with the best decoder performance.II. 3. 3. Analyzing the QECC

[0095] In the examples described above, the QECC selector 100 selects a QECC from the candidate QECCs based on an indication of the performance of the candidate QECCs for the logical quantum circuit 112 obtained from the database 108.

[0096] In some examples, the QECC selector 100 may determine the performance of the candidate QECCs for the logical quantum circuit 112 itself e.g. at runtime of the QECC selector 100. The database 108 may store, for each of the candidate QECCs, a description of the physical gates used to implement a logical quantum gate in the respective candidate QECC. That is, the QECC selector 100 may store a description of the physical gates that a particular logical quantum gate is mapped to by the candidate QECC. The QECC selector 100 may obtain, from the database 108, the physical gate descriptions for a particular logical quantum gate or sequence of logical quantum gates in the logical quantum circuit 112 for each candidate QECC. The QECC selector 100 may analyze the physical gate descriptions to predict the performance of the candidate QECCs for the logical quantum circuit 112. The QECC selector 100 may use the physical gate descriptions to calculate any of the rankings described above in Section II. 3. 1 and / or any of the performance metrics described above in Section II. 3. 2.

[0097] For example, the QECC selector 100 may determine in step 114, that the most commonly used gate in the logical quantum circuit 112 is the Hadamard gate. In step 116, the QECC selector 100 may obtain, from the database 108, a description of the physical gates used to implement the Hadamard gate in a first QECC and a second QECC. The QECC selector 100 may, based on the descriptions, determine that the implementation of the Hadamard gate in the first QECC has a higher error spread. Based on this, the QECC selector 100 may select the second QECC to use for the logical quantum circuit112.

[0098] In the above example, the QECC selector 100 considers only the physical gates used to implement a single type of logical quantum gate from the logical quantum circuit 112. In other examples, the QECC selector 100 may consider multiple types of logical quantum gates from the logical quantum circuit 112. For example, the QECC selector 100 may map the entire logical quantum circuit 112 to respective physical quantum circuits for each candidate QECC. The QECC selector 100 may then determine performance metric values for each of the physical quantum circuits and select the candidate QECC that corresponds to the physical quantum circuit with the best performance metric value e.g. by determining that one physical quantum circuit has an improved performance metric value relative to another physical quantum circuit.

[0099] In particular examples, the QECC selector may use a quantum resource estimation tool, such as Azure quantum, to predict the amount of time it is expected to take to implement each logical quantum gate in the logical quantum circuit 112 for a candidate QECC. The QECC selector 100 may repeat this for one or more candidate QECCs in the database 108 to determine predicted execution times for the logical quantum circuit 112 for candidate QECCs in the database 108. The QECC selector 100 may then select the candidate QECC that is predicted to result in the shortest execution time.II. 3. 3. 1 Simulations

[0100] The QECC selector 100 may use a simulation to select a QECC from the candidate QECCs. In particular, the QECC selector may map the logical quantum circuit 112 to a physical quantum circuit for a candidate QECC and simulate the physical quantum circuit. The QECC selector may use simulations for multiple candidate QECCs to predict the performance of the candidate QECCs for the logical quantum circuit 112. That is, the QECC selector 100 may simulate a first physical quantum circuit corresponding to a first candidate QECC to determine a first value of a performancemetric for the first candidate QECC and the QECC selector 100 may simulate a second physical quantum circuit corresponding to a second candidate QECC to determine a second value of a performance metric for the first candidate QECC. The QECC selector 100 may then compare the first and second values of the performance metric to select a QECC from the first and second candidate QECCs e.g. the QECC selector 100 may select the QECC with the best or optimal value of performance metric.

[0101] It will be appreciated that there are various types of simulations which may be used, depending on the performance metric of interest. In some examples, the physical quantum circuits may be simulated using Monte Carlo (classical) simulations. In particular, the QECC selector may generate near-Clifford approximations of the logical quantum circuit 112 to run classical Monte Carlo simulations across a pool of candidate QECCs to select the best one. In this context, a near-Clifford approximation of a logical quantum circuit is a version of a physical quantum circuit used to implement the logical quantum circuit which includes mostly Clifford gates (e.g. only Clifford gates and a few non-Clifford gates). Such a circuit may be simulated on a classical computer. In some embodiments, hardware-specific noise models (e.g. noise models for particular qubits and / or particular gates) may be included in the simulations. This may result in more realistic simulations that yield a better selection of a QECC. To simulate a particular candidate QECC, the QECC selector 100 may take, as input to the Monte Carlo simulation, a near-Clifford circuit that approximates the physical quantum circuit that implements the logical quantum circuit 112 in the particular candidate QECC, and the output may be a success / failure ratio indicating how successfully the incorporated QECC corrected errors arising in the circuit.II. 3. 3. 2 Using machine-learning to select a QECC

[0102] In some examples, the QECC selector 100 may use a machine-learning process (e.g. algorithm) to select a QECC from the candidate QECCs based on properties of the logical quantum circuit 112. The machine-learning process may have been trained using supervised learning. For example, the machine-learning process may have been trained using training data to predict the values of one or more performance metrics for a candidate QECC for a logical quantum circuit, based on the properties of the logical quantum circuit. The training data may have included:• for each of a plurality of logical quantum circuits, values of one of the logical quantum circuit properties described above;• a plurality of QECCs (e.g. parity check matrices for each PCM and / or descriptions of physical quantum circuits that the logical quantum circuits are mapped to by each QECC); and• values of one or more of the performance metrics for each of the QECCs (described in section II. 3. 2) for implementation of each of the logical quantum circuits.

[0103] In use, the properties of the logical quantum circuit 112 obtained in step 114 and candidate QECCs from the database 108 may be input to the trained machine-learning process to predict the values of the performance metric(s) for each candidate QECC for that logical quantum circuit 112. The QECC selector 100 may then select the QECC from the candidate QECCs based on the predicted values of the performance metrics.

[0104] In other examples, the machine-learning process may be trained to select a QECC (e.g. may output a selected QECC, or a ranking of QECCs, rather than predictions of QECC performance).

[0105] Any suitable supervised learning processes may be used to train the machinelearning process, such as a support vector machine, linear regression, a neural network etc.Unsupervised or semi-supervised learning may be used in addition to, or instead of, supervised learning to train the machine-learning process.

[0106] Using a machine -learning process may be particularly advantageous because it may allow for identifying new associations between logical quantum circuit properties and QECC performance.II. 3. 4. Examples of selecting the QECC in step 116

[0107] The QECC selector 100 may thus, in step 116, select a QECC from two or more candidate QECCs based on the properties of the logical quantum circuit 112 determined in step 114. This may involve an explicit comparison of the properties of the logical quantum circuit 112 to any of the properties of the candidate QECCs described above e.g. according to a set of pre-defined rules. Alternatively, this might not involve an explicit comparison e.g. may instead use a machine -learning process.

[0108] It will be appreciated that the implementation of step 116 may depend on the implementation of step 114. To illustrate how these steps may work together, example implementations of steps 114 and 116 are provided.

[0109] In an example, the QECC selector 100 determines, in step 114, which logical quantum gate occurs most commonly in the logical quantum circuit 112. In step 116, the QECC selector 100 may select from the database 108 of QECCs, the QECC that has the most efficient implementation of that logical quantum gate (e.g. using the fewest physical gates or with the shortest predicted runtime). Since that logical quantum gate occurs most frequently in the logical quantum circuit 112, this should result in a more efficient implementation of the overall logical quantum circuit 112. In a more specific example in which the most commonly occurring logical quantum gate in the logical quantum circuit112 is the Hadamard gate, the QECC selector 100 may select the Steane QECC over the Quantum Reed-Muller QECC because the Steane QECC implements the Hadamard gate transversally, whilst the Quantum Reed-Muller QECC implements the Hadamard gate using alternative costlier techniques due to the lack of an efficient direct implementation.

[0110] As another example, the QECC selector 100 may, in step 114, determine the count of each type of gate in the circuit. The QECC selector 100 may, based on the count of each type of gate, predict the resources (e.g. execution time, number of physical qubits etc.) required to implement the logical quantum circuit 112 using each QECC in the database 108 of QECCs. The QECC selector 100 may then, in step 116, select the QECC that is predicted to use the fewest resources (e.g. the QECC that is expected to result in the shortest execution time).

[0111] As another example, the QECC selector 100 may, in step 114, determine the frequency of pairs of gates (e.g. H, CZ), triplets of gates (e.g. H, CZ, T), and / or higher length sequences for the circuit. The QECC selector 100 may, based on these numbers, optimize the selection of the QECC in step 116 that reduces the computational cost of these common sequences. In a more specific example, the QECC selector 100 may determine the number of two-qubit gates that would be required to implement the logical quantum circuit 112 for some or all of the candidate QECCs in the database 108 and select a QECC that would result in the fewest physical two-qubit gates. This may be particularly advantageous for quantum hardware that is based on teleportation, such as quantum computers that use T centre based qubits, as implementation of two-qubit gates on such hardware may require the generation of Bell pairs via an entanglement protocol. As entanglement protocols are probabilistic, they may need to be repeated many times until aBell pair is generated. As such, selecting a QECC that minimizes the number of physical two-qubit gates may significantly reduce execution time, whilst also increasing theprobability of successful execution. A similar approach may be taken to reduce the need for magic states.

[0112] In this context, T centre based qubits refers to qubits provided by spins associated with T centres in silicon, such as T centres in crystalline silicon. The crystalline silicon may be isotopically enriched in28Si (e.g. is made up of 90% or more or 95% or more or 99% or more or 99.5% or more by number28Si).28Si is an isotope of silicon for which the nucleus has zero intrinsic spin. T centre based qubits may include qubits provided by electron, hole and / or nuclear spins associated with T centres in silicon.

[0113] In general, the QECC may be selected based on any of (e.g. any combination of) the circuit properties mentioned in step 114.II. 3. 5. Omitting the database 108

[0114] In the foregoing examples, the QECC selector 100 selects the QECC from candidate QECCs stored in the database 108. Alternatively, the QECC selector 100 might not use a database. For example, properties of the candidate QECCs may be hardcoded in the QECC selector or accounted for in rules hardcoded in the QECC selector 100.II. 4. Generating the physical quantum circuit 120 in step 118

[0115] In step 118, the QECC selector 100 (e.g. the compiler module 110) generates the physical quantum circuit 120 (e.g. a description of the physical quantum circuit 120) by using the selected QECC to map the logical quantum circuit 112 to the physical quantum circuit 120. The physical quantum circuit 120 may be executable on a particular quantum computing system.

[0116] The QECC selector 100 may generate the physical quantum circuit 120 by replacing one or more logical quantum gates of the logical quantum circuit 112 with one or more physical quantum gates in accordance with the selected QECC. The physicalquantum circuit 120 is configured to implement the logical quantum circuit 112 and correct errors that may occur during execution of the physical quantum circuit 120.

[0117] The QECC selector 100 may also generate a set of instructions to be executed by one or more hardware components of a quantum computing system to implement the physical quantum circuit 120. In other examples, the QECC selector 100 may output a description of the physical quantum circuit 120 for the instructions to be generated elsewhere.

[0118] In some cases, the QECC selector 100 might not generate the physical quantum circuit 120 e.g. step 118 may be omitted. The selector system 100 may instead output an indication of the selected QECC, optionally in addition to a description of the logical quantum circuit 112. The system 100 may indicate the selected QECC and the logical quantum circuit to an (external) compiler, for example.

[0119] The QECC selector 100 may further cause a quantum computing system to execute the physical quantum circuit 120. For example, the selector 100 may include the quantum computing system (not illustrated) and may execute the physical quantum circuit 120 on the quantum computing system. Alternatively, the QECC selector may send, to the quantum computing system, a description of the physical quantum circuit 120 and / or an indication of the selected QECC and a description of the logical quantum circuit 112.III. Further embodiments

[0120] Optional modifications to the method described above in respect of FIG. IB are described. The modifications may be combined as appropriate.III. 1. Jointly selecting QECC and basis

[0121] In some examples, the QECC selector 100 may, in step 116, jointly select a QECC and a basis for the selected QECC. For example, in the [[4,2,2]] code, one canchoose a logical basis so that an S gate on every physical qubit (a depth one circuit) implements a depth two logical quantum circuit.III. 2. Properties of the quantum computing system hardware

[0122] In some examples, the QECC selected in step 116 may also be selected based on the hardware of the quantum computing system on which the circuit 112 is to be run.That is, the QECC selector 100 may account for the hardware of the quantum computer on which the logical quantum circuit 112 is to be executed. This may be in addition to any of the properties of the logical quantum circuit 112 and / or the QECC described above.Example hardware properties that may be used by the QECC selector 100, alone or in any combination, are discussed below. These hardware properties may be input to the QECC selector 100 (e.g. by a user), hard-coded into the QECC selector 100 or stored in a database such as the database 108, for example.III. 2. 1. Number of physical qubits

[0123] The QECC selector 100 may select the QECC based on the number of physical qubits provided by the quantum computing system and / or the number of qubits that are expected to be available (e.g. available qubits) when the logical quantum circuit 112 is executed on the quantum computing system. In this context, the number of available qubits is the number of physical qubits in the quantum computing system that are not occupied for another use (e.g. for execution of another circuit, calibration etc.).

[0124] In some examples, the QECC selector 100 may use the number of physical qubits required by a QECC to narrow down the list of candidate QECCs. The QECC selector 100 may exclude any candidate QECCs that would require more physical qubits than the quantum computing system provides or is expected to have available, for example. This may narrow down the candidate QECCs to a smaller subset from which theQECC selector 100 can select a QECC based on one or more of the properties described above in step 116.IH. 2. 2. Qubit connectivity

[0125] The QECC selector 100 may select the QECC based on the qubit connectivity of the quantum computing system. This refers to the number of qubits that are able to interact with a given qubit. This may be represented in the form of a map or graph. Additionally or alternatively, the qubit connectivity may be quantified by the maximum, minimum and / or average number of qubits that each qubit is able to interact with. For example, in a square lattice the connectivity would be 4 for any qubits not at the edge of the lattice because each of those qubits is able to interact with 4 other qubits.

[0126] Having low connectivity means that more physically necessitated SWAP gates are required to implement a logical quantum circuit. This may be illustrated with reference to Figs. 3A-3E.

[0127] Fig. 3A shows an example logical quantum circuit and Fig. 3B shows a qubit arrangement for an example quantum computing system. As shown in Fig. 3B, the qubits are arranged in a linear chain. Since the logical quantum circuit shown in Fig. 3A includes two-qubit operations (CNOTs) on qubits qO and q6, which are not directly connected to one another (i.e. are only connected via other qubits), implementing the circuit from Fig. 3A on the qubit arrangement in Fig. 3B will require a chain of SWAP operations. These SWAP operations may be described as physically necessitated SWAP operations since they are a consequence of the arrangement of qubits. An example physical quantum circuit for implementing the logical quantum circuit of Fig. 3A on the qubit arrangement of Fig. 3B is shown in Fig. 3C. This may be contrasted with Fig. 3E, which shows an example implementation of the logical quantum circuit from Fig. 3A on qubits in the arrangementshown in Fig. 3D. This illustrates how the qubit connectivity can affect the implementation of a logical quantum circuit.

[0128] Since different QECCs will provide different physical implementations of the logical quantum circuit 112, in some embodiments, the QECC selector 100 may jointly select a QECC based on properties of the logical quantum circuit 112 and the qubit connectivity. For example, the QECC selector 100 may select a QECC that maps to a physical quantum circuit that only has 2-qubit gates involving connected qubits instead of a different QECC that maps to a physical quantum circuit that has 2-qubit gates involving qubits that are not (directly) connected to one another. This may simplify the implementation of the logical quantum circuit 112, potentially reducing execution time and the risk of errors. This may be particularly advantageous for quantum computing systems that do not use teleportation to implement 2-qubit gates.IH. 2. 3. T1 (relaxation time) and T2 (dephasing time)

[0129] The QECC selector 100 may select the QECC based on the relaxation time (Tl) and / or the dephasing time (T2) of the quantum computing system on which the logical quantum circuit 112 will be executed. Together, these define the maximum amount of time that unencoded qubit information can be preserved. This means that the duration of the physical quantum circuit that implements a logical operation may be limited. To account for this, the QECC selector 100 may select a QECC that results in a shorter physical quantum circuit for hardware with a shorter Tl and / or T2 than for hardware with longer Tl and / or T2. The Tl and / or T2 times may be specified per individual qubit or for groups of qubits. For example, the QECC selector 100 may select a QECC based on the minimum Tl, T2 or a combination thereof for the qubits that the circuit 112 is to be executed on.

[0130] Specifying the T1 and / or T2 per qubit may be particularly advantageous as it may allow the QECC selector 100 to evaluate candidate QECCs at a detailed mapping level of physical qubits of the code to hardware qubits of the quantum computing system based on the use of those qubits in operations of the code. For example, the QECC selector 100 may rank qubits in the quantum computing system according to their T1 and / or T2 time. The QECC selector 100 may map qubit(s) with the shortest T1 and / or T2 times to the first set of qubit(s) in the physical circuit 120 that get measured in the physical circuit mapped to by the candidate QECCs. The QECC selector 100 may preferentially select candidate QECC(s) for which such a mapping is possible. This may be used as tie-breaker (e.g. to decide between two candidate QECCs) or when evaluating all candidate QECCs. In this context, qubit(s) with the shortest T1 and / or T2 times may be qubit(s) with T1 and / or T2 times below a threshold value or a particular number of qubits with the shortest T1 and / or T2 times.

[0131] In some examples, the QECC selector 100 may select a QECC based on the T1 and / or T2 time of the quantum computing system on which the logical quantum circuit 112 will be executed and the predicted execution time of the physical quantum circuit mapped to by the QECC. If the predicted execution time is greater than the T1 time or the T2 time, then there is a risk that execution of the logical quantum circuit 112 will fail to complete successfully. Although this risk can be mitigated by including an additional error correction cycle during execution of the logical quantum circuit 112 (e.g. using piecewise fault tolerance) or by executing the logical quantum circuit 112 multiple times, both of these mitigation strategies incur significant overhead. To avoid this, the QECC selector 100 may select a QECC from the candidate QECCs for which the predicted execution time is less than the T1 time and the T2 time of the quantum computing system.

[0132] There are many ways the QECC selector 100 may predict the execution time of the physical quantum circuits mapped to by candidate QECCs, including any of the following:• Predicting the execution time based on the count of individual operations in the physical quantum circuits mapped to by each of the candidate QECCs and the predicted time to execute each operation in those physical quantum circuits (e.g. an average time for implementing each operation on that quantum computing system); and• Predicting the execution time based on the depth of the physical quantum circuits mapped to by each of the candidate QECCs and the average time to execute an operation at the quantum computing systems.IH. 2. 4. Native gate set

[0133] Typically, each quantum computer has a native gate set. The native gate set is a collection of physical gates that the quantum computer is configured to implement. This means that the physical quantum circuit for a QECC and the logical quantum circuit 112 may need to be rewritten (e.g. translated) to use only gates from the native gate set before execution. This can result in additional overhead, depending on the logical quantum circuit 112 and the native gate set. Thus, in some embodiments, the QECC selector 100 may select the QECC based on both the logical quantum circuit 112 and the native gate set for the quantum computing system on which the logical quantum circuit 112 is to be executed. For example, the QECC selector 100 may preferentially select QECCs for which the logical quantum circuit 112 can be easily expressed in terms of the native gate set of the quantum computing system. The QECC selector 100 may select the QECC according to a number of resources (e.g. physical quantum gates) to implement the logical quantum circuit using quantum gates of the native gate set.III. 2. 5. Fidelity

[0134] Each operation that is executed on a physical qubit has an associated fidelity, which indicates how closely it matches the ideal operation. Any deviation from unit fidelity can be considered as noise. That is, the noise of a gate may be any mismatch between the desired result of that physical gate and the actual result of implementing that physical gate. In practice, different physical gates have different fidelity (or, analogously, noise). In addition, the fidelity of a particular type of physical gate may differ between different hardware.

[0135] QECCs for which the physical implementations of logical operations tend to rely on higher-fidelity physical gates tend to outperform otherwise similar QECCs on that hardware. As such, the QECC selector 100 may maximize the fidelity of the physical quantum circuit 120 used to implement the logical quantum circuit 112 (or equivalently, reduce the noise) by selecting a QECC at least in part based on the fidelity. For example, the QECC selector 100 may select a QECC code that maximizes the number of high fidelity (or low noise) physical gates in the physical quantum circuit 120. A gate may be high fidelity with respect to other gates (e.g. in the native gate set). Thus, for example, the high fidelity gates for a native gate set may be the a physical gates in the native gate set with the highest fidelities (or equivalently, the a physical gates with the lowest noise), in which a is a predetermined positive integer. Alternatively, high fidelity gates may include any gates with a fidelity above a predetermined threshold (or, equivalently, gates with a noise below a predetermined threshold).III. 2. 6. Measurement characterization

[0136] In some examples, the QECC selector 100 may jointly select a QECC and a type of measurement protocol based on a property of the quantum computing system. There are various different types of measurement protocols used for syndrome extraction,including Shor-style, Stean-style and Flag (or Flag qubit). Different types of measurement protocol typically require different resources to achieve comparable performance. For example, Shor-style measurement protocols typically require Greenberger-Home- Zeilinger (GHZ) states. Which resources are needed will vary depending on the QECC. The cost of providing those resources will depend on the hardware. For example, since a GHZ state involves at least three entangled qubits, using a Shor-style measurement protocol may be less prohibitive (e.g. in terms of execution time) on a quantum computing system with a deterministic entanglement protocol or a probabilistic entanglement protocol with a high probability of success.

[0137] The QECC database 108 may store, for example, an indication of a resource requirement and / or a hardware requirement (e.g. as a range or threshold) for implementing two or more types of measurement protocol for each candidate QECC. The resource requirement may indicate a quantity and / or type of resources for implementing that measurement protocol for the QECC e.g. count of GHZ states. The hardware requirement for a measurement protocol for a particular candidate QECC may indicate a threshold value of a property of the quantum computing system that must be achieved e.g. for that particular measurement protocol to be competitive for that candidate QECC. The QECC selector 100 may, for example, select a QECC based on determining that the quantum computing system satisfies that threshold value.

[0138] The QECC selector 100 may, additionally or alternative, select a QECC for which measurement protocols can be used in such a way as to only need measurement from reliable qubits. That is, the QECC selector 100 may select a QECC which maps to a physical quantum circuit 120 in which measurement is only performed on reliable qubits.In this context, a qubit may be deemed reliable when its fidelity for single and / or two-qubit operations is above a predetermined threshold. The fidelity of a qubit may be measured using quantum tomography, for example.III. 2. 7. 2-qubit gate implementation

[0139] In some quantum computing systems, such as those using T centre based qubits, 2-qubit gates are implemented with teleported operations. Teleported operations require generating entanglement, which can create a bottleneck. This can be a particular issue when a physical quantum circuit involves back-to-back 2-qubit gates on the same pair of qubits. Therefore, in some examples, the QECC selector 100 may, for a quantum computing system that uses teleportation to implement two-qubit gates, select the QECC from the candidate QECCs for which the implementation of the logical quantum circuit 112 in the selected QECC minimizes (e.g. eliminates) the incidence of back-to-back 2- qubit gates in the physical quantum circuit 120. In this context, the expression back-to- back 2-qubit gates refers to a pair of 2-qubit gates performed on the same pair of qubits that are not separated by any other gates.III. 2. 8. Error probability and pseudo-threshold

[0140] Each quantum computing system has an associated error probability, indicating the likelihood of an error occurring during execution of a quantum circuit. The error probability may be expressed as an error rate. The pseudo-threshold for a QECC denotes the error probability value pth below which the error rate becomes lower than the physical error rate applying the QECC in combination with a specific decoder. Thus, the QECC selector 100 may compare the pseudo-thresholds of candidate QECCs to the error probability for the quantum computing system on which the logical circuit 112 is to be executed to determine whether the candidate QECCs are suitable for that particular quantum computing system. More specifically, the QECC selector 100 may select only candidate QECCs with a pseudo-threshold above the error probability of the quantumcomputing system. For example, the QECC selector 100 may reject candidate QECCs with a pseudo-threshold of 0.01 for a quantum computing system with an error probability (e.g. a physical error) of 0.02, even though those candidate QECCs might have a better implementation of particular logical gates in the logical quantum circuit 112.

[0141] The pseudo-threshold for a candidate QECC may be specific to (e.g. may assume) a particular noise model and / or a particular decoder. The noise model may indicate the likelihood of an error, or one or more particular types of error (e.g. X errors and / or Z errors), occurring when one or more logical quantum gates are implemented using that candidate QECC.

[0142] Thus, the database 108 may store, for each candidate QECC, respective pseudo-thresholds for one or more noise models and / or decoders. The QECC selector 100 may, in step 116, select a candidate QECC that has a pseudo-threshold that is higher than the error probability of the quantum computing system that the logical circuit 112 is to be executed on. The values of the pseudo-threshold for different candidate QECCs in the database 108 may assume the same noise model or different noise models. In some examples, the database 108 may include different values of the pseudo-threshold for the same QECC for different noise models and / or different decoders. The QECC selector 100 may, for example, select the candidate QECC, noise model and decoder that has a pseudothreshold above the error probability of the quantum computing system.III. 3. Multiple representations

[0143] A given quantum circuit can be rewritten in various different ways whilst still achieving the same output for a given input. This may be referred to as reconfiguring or translating the circuit. There are known (gate) rewrite rules which specify how to replace a set of one or more gates with another set of one or more gates. Examples of simple rewrite rules include the following:CZ gate is equivalent to a CNOT gate with one Hadamard gate on either side, as shown in Fig. 4A.Hadamard gate is equivalent to XY1 / 2up to a global phase, as shown in Fig. 4B.

[0144] In some embodiments, the QECC selector 100 may use rewrite rules, such as the examples given above, to find logical quantum circuits that are equivalent to the logical quantum circuit 112. These equivalent circuits may be referred to as representations of the logical quantum circuit 112. The QECC selector 100 may jointly optimize the selection of the representation of the logical quantum circuit 112 and the QECC in step 116.

[0145] To achieve this, step 114 described above may be adapted to first generate a set of representations of the logical quantum circuit 112 based on one or more rewrite rules. This set includes both the original circuit and at least one other representation. There are many ways of generating the other representation(s) including using ZX calculus, pattern matching, graph-based techniques etc. Then, in steps 112 and 114 of the method, the QECC selector 100 may simultaneously explore the parameter space of QECCs and representations to simultaneously identify the optimal QECC and the optimal representation. Simultaneously optimizing the choice of QECC and the representation is expected to result in a higher performance physical quantum circuit 120.

[0146] In some embodiments, the QECC selector 100 may identify a subset of QECCs for each representation (e.g. using any of the selection approaches mentioned above in step 116). For each representation of the circuit, the QECC selector 100 may estimate the performance of that representation for each QECC in the respective subset. The QECC selector 100 may use one or more of the performance metrics described above, for example. The QECC selector 100 may then select the QECC and representation withthe best performance (e.g. shortest execution time or shortest execution time for a given fidelity threshold etc.).III. 4. Selecting a QECC with a gate having a classical implementation

[0147] There are quantum logic gates and combinations of quantum logic gates that can be implemented at least in part by classical hardware. For example, the combination of operations: la. Performing an X gate; and2a. Measurement is equivalent to: lb. Measurement to obtain a result, res; and2b. Performing mod2(res + 1) to the result of the measurementThese types of equivalencies are useful because implementing a step classically, rather than in a quantum circuit, is quicker (often in the picosecond to low nanosecond range) and has a reduced (or no) risk of errors. That is, steps lb and 2b may be performed more quickly and more reliably than steps la and 2a because step 2b can be implemented using classical computing hardware (i.e. without sending pulses to the qubits). Another example of quantum operations that can be implemented classically is the algorithmically required SWAP operation.

[0148] In contrast to physically necessitated SWAP operations referred to above, algorithmically required SWAP operations are not a consequence of the arrangement or connectivity of qubits. Algorithmically required SWAP operations may be implemented classically by swapping labels for the qubits involved. For example, if the qubits should be shuffled for reasons other than bringing the qubits into physical proximity, then these can be handled purely in classical hardware by swapping the labels for the qubits. This may be illustrated by Fig. 5, which shows two equivalent circuits. The only difference between theleft side and the right side of the equality is that performing measurements of the qubits from top to bottom would result in |q0, ql> in the first case (left), and |q 1 , q0> in the second (right). This corresponds to a reordering of the Hilbert space but will not affect the results of the quantum circuit as long as they are processed appropriately (e.g. by relabeling the qubits in classical hardware).

[0149] Quantum operations that can be implemented classically, such as algorithmically required SWAP operations, occur in QECC mappings of logic gates. For example, in the [[5, 1, 3]] stabilizer code, the Hadamard gate can be implemented transversally (i.e. across all qubits) by performing a Hadamard gate on each physical qubit, followed by several algorithmically required SWAP operations. This is illustrated in Fig. 6. The permutation gate (illustrated by the lines crossing one another) can be decomposed into a finite number of SWAP operations.

[0150] The [[8, 3, 2]] stabilizer code has a similar construction, in which a logical CNOT operation with an error spread of one is mapped to two algorithmically required SWAP operations. Since SWAPs do not spread errors (they only move them around), it is expected that algorithmically required SWAP operations may be more common in QECCs with low error spread gates.

[0151] As quantum operations that can be implemented classically occur in the physical implementations of logical quantum gates in QECCs, and using these classical implementations can improve runtime and reduce errors, the QECC selector 100 may preferentially select a QECC that would result in the physical quantum circuit 120 including one or more quantum operations that can be implemented at least in part by a classical operation (such as algorithmically required SWAP operations). The substitution of these quantum operations with a classical operation can be implemented when the physical quantum circuit 120 is compiled or at runtime (e.g. using relabeling of qubits foran algorithmically required SWAP operation). Compilation of a physical quantum circuit that includes a classically-implementable operation is discussed in section III. 4. 1. below.

[0152] There are many different ways in which the QECC selector 100 could preferentially select QECCs that would result in a circuit with some quantum operations that can be implemented classically. In some embodiments, the QECC selector 100 may select the QECC that has classically-implementable operations for the most commonly used gate(s) in the logical quantum circuit. For example, the QECC that has an algorithmically required SWAP implementation for the most common gate may be selected.

[0153] In some embodiments, the QECC selector 100 may use the QECC database 108 to determine, for each candidate QECC, which gates in the logical quantum circuit 112 are implementable at least in part using classical operations. The QECC selector 100 may then determine, for each candidate QECC, the total number of physical quantum gates in the physical quantum circuit mapped to by that candidate QECC that include a classically-implementable operation and then select the QECC that would result in the largest number of classically implementable operations or the fewest physical quantum gates (i.e. the fewest quantum operations).

[0154] In some embodiments, the QECC selector 100 may select the QECC that involves a classically-implementable operation for the most computationally expensive gate (i.e. the gate that is expected to be the most computationally expensive). This may advantageously reduce the number of resources required to implement that gate.

[0155] In some embodiments, the QECC selector 100 may combine this analysis with the rewrite rules mentioned above e.g. the QECC selector 100 may select a QECC and a representation which includes a classically implementable operation.III. 4. 1. Compilation using classically-implementable operations

[0156] When compiling a physical quantum circuit that includes a classically- implementable operation (or instruction), the compiler may produce a sequence of operations that also includes a classical implementation of the classically-implementable instruction at the appropriate location. When executing the program, a classical implementation of the classically-implementable instruction executes at the appropriate moment as expected. For example, if the classically-implementable instruction is a qubit swapping operation, the qubit addresses may be updated in control hardware when the instruction executes.III. 5. Example of using rewrite rules and classically-implementable gates

[0157] Figs. 7A and 7B show an example in which the logical quantum circuit 700 involves two logical qubits. The circuit 700 includes a controlled Z gate 702 (indicated by a Z in a box) and a Hadamard gate 704. One implementation of this logical quantum circuit 700 would be to perform the CZ(0,l) followed by a H(l) gate using a particular QECC. In the [[8, 3, 2]] QECC, the CZ(0,l) logical gate 702 is mapped to the physical gate 712, and the H(l) logical gate is mapped to the physical gate 714, as shown in Fig. 7A.

[0158] According to aspects of the present disclosure, the QECC selector 100 may use a rewrite rule to rewrite the logical quantum circuit 700 to obtain logical quantum circuit 709 shown in Fig. 7B. Circuit 709 is equivalent to circuit 700 in that it achieves the same computational results. Circuit 709 includes a Hadamard gate 704 and a CX(0,l) gate 706. The CX(0,l) gate 706 may also be referred to as a CNOT gate. Rewriting the circuit 700 in this manner is advantageous because in the [[8,3,2]] QECC, the CX(0,l) gate 706 can be implemented using only algorithmically required SWAPs. This is shown in circuit 716 of Fig. 7B, which consists of two algorithmically required SWAP gates. This meansthat the user’s logical quantum circuit 700 shown in Fig. 7A can be mapped to a physical quantum circuit with two algorithmically required SWAPs using the [[8,3,2]] QECC. When the physical quantum circuit 716 is executed, the algorithmically required SWAPs can be implemented classically, which will reduce runtime and decrease the risk of errors (e.g. decrease the risk of new errors being introduced). This illustrates that using rewrite rules and preferentially selecting a QECC that results in the physical circuit including classically-implementable operations can result in a faster, more reliable calculation.IIV. Description of a Computing System

[0159] Embodiments described above may be implemented using one or more computing systems. Example computing systems are described below.

[0160] Fig. 8A is a block diagram that illustrates a computing system 800, according to some embodiments. In the example of Fig. 8A, the computing system 800 includes a classical computing system 810 (also referred to as a non-quantum computing system) and a quantum computing system 820, however a computing system may just include a classical computing system or a quantum computing system. An embodiment of the classical computing system 810 is described further with respect to Fig. 9. While the classical computing system 810 and quantum computing system 820 are illustrated together, they may be physically separate systems. For example, Fig. 8B illustrates an example cloud computing architecture where the computing system 810 and the quantum computing system 820 communicate via a network 857. The computing system 800 may include different, additional, or fewer elements than illustrated (e.g., multiple quantum computing systems 820).

[0161] In some embodiments, the QECC selector 100 may be implemented on the classical computing system 810. That is, the classical computing system 810 may be configured to perform operations including some or all steps in the method describedabove in respect of Fig IB (e.g. steps 114-118). The quantum computing system 820 may be the quantum computing system on which the logical quantum circuit 112 is to be executed.

[0162] The classical computing system 810 may also control the quantum computing system 820. For example, the classical computing system 810 generates and transmits instructions for the quantum computing system 820 to execute a quantum algorithm or quantum circuit. Alternatively, another classical computing system 810 may control the quantum computing system 820. Although only one classical computing system 810 is illustrated in Fig. 8A, any number of classical computing system 810 or other external systems may be connected to the quantum computing system 820.

[0163] Fig. 8C is a block diagram that illustrates the quantum computing system 820, according to some embodiments. The quantum computing system 820 includes any number of quantum bits (“qubits”) 850 and associated qubit controllers 840. As illustrated in Fig. 8D, the qubits 850 may be in a qubit register 855 of the quantum computing system 820 (or multiple registers). Qubits are further described below. A qubit controller 840 is a module that controls one or more qubits 850. A qubit controller 840 may include one or more classical processors such as one or more CPUs, one or more GPUs, one or more FPGAs, or some combination thereof. A qubit controller 840 may perform physical operations on one or more qubits 850 (e.g., it can perform quantum gate operations on a qubit 840). In the example of Fig. 8C, a separate qubit controller 840 is illustrated for each qubit 850, however a qubit controller 840 may control multiple (e.g., all) qubits 850 of the quantum computing system 820 or multiple controllers 840 may control a single qubit. For example, the qubit controllers 840 can be separate processors, parallel threads on the same processor, or some combination of both.

[0164] Fig. 8E is a flow chart that illustrates an example execution of a quantum routine on the computing system 800. The classical computing system 810 generates 860 a quantum program to be executed or processed by the quantum computing system 820. The quantum program may include instructions or subroutines to be performed by the quantum computing system 820. The quantum computing program may include instructions or subroutines to be performed by the quantum computing system 820 in order to execute the physical quantum circuit 120. In an example, the quantum program is a quantum circuit, such as the physical quantum circuit 120. The quantum computing system 820 executes 865 the program and computes 870 a result (referred to as a shot or run). Computing the result may include performing a measurement of a quantum state generated by the quantum computing system 820 that resulted from executing the program. Practically, this may be performed by measuring values of one or more of the qubits 850. The quantum computing system 820 typically performs multiple shots to accumulate statistics from probabilistic execution. The number of shots and any changes that occur between shots (e.g., parameter changes) may be referred to as a schedule. The schedule may be specified by the program. The result (e.g., quantum state data) (or accumulated results) is recorded 875 by the classical computing system 810. Results may be returned after a termination condition is met (e.g., a threshold number of shots occur). The classical computing system 810 may determine a quantity based on the received results.

[0165] The quantum computing system 820 exploits the laws of quantum mechanics in order to perform computations. A quantum processing device, a quantum computer, a quantum processor system, and a quantum processing unit (QPU) are each examples of a quantum computing system. The quantum computing system 800 can be a universal or a non-universal quantum computing system (a universal quantum computing system can execute any possible quantum circuit (subject to the constraint that the circuit does not usemore qubits than the quantum computing system)). In some embodiments, the quantum computing system 800 is a gate model quantum computer. As previously described, quantum computing systems use so-called qubits, or quantum bits (e.g., 850A). While a classical bit always has a value of either 0 or 1, a qubit is a quantum mechanical system that can have a value of 0, 1, or a superposition of both values. Example physical implementations of qubits include superconducting qubits, spin qubits, trapped ions, arrays of neutral atoms, and photonic systems (e.g., photons in waveguides). Additionally, the disclosure is not specific to qubits. The disclosure may be generalized to apply to quantum computing systems 820 whose building blocks are qudits ( -level quantum systems, where d> ) or quantum continuous variables, rather than qubits.

[0166] A quantum circuit is an ordered collection of one or more gates. A sub-circuit may refer to a circuit that is a part of a larger circuit. A gate represents a unitary operation performed on one or more qubits. Quantum gates may be described using unitary matrices. A layer of a quantum circuit may refer to a step of the circuit, during which multiple gates may be executed in parallel. A quantum computing system may include both a core quantum device and a classical peripheral / control device (e.g., a qubit controller 840) that is used to orchestrate the control of the quantum device. It is to this classical control device that the description of a quantum circuit may be sent when one seeks to have a quantum computer execute a circuit.

[0167] The parameters of a parameterized quantum circuit may refer to parameters of the gates. For example, a gate that performs a rotation about the y axis may be parameterized by a real number that describes the angle of the rotation.

[0168] The description of a quantum circuit to be executed on one or more quantum computing systems may be stored in a non-transitory computer-readable storage medium.The term “computer-readable storage medium” should be taken to include a singlemedium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) able to store instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing instructions for execution by the quantum computing system and that cause the quantum computing system to perform any one or more of the methodologies disclosed herein. The term “computer-readable medium” includes, but is not limited to, data repositories in the form of solid-state memories, optical media, and magnetic media.

[0169] Fig. 9 is an example architecture of a classical computing system 810, according to some embodiments. The quantum computing system 820 may also have one or more components described with respect to Fig. 9. Fig. 9 depicts a high-level block diagram illustrating physical components of a computer system used as part or all of one or more entities described herein, in accordance with an embodiment. A computer may have additional, less, or variations of the components provided in Fig. 9. Although Fig. 9 depicts a computer 900, the figure is intended as a functional description of the various features which may be present in computer systems rather than a structural schematic of the implementations described herein. In practice, and as recognized by those of ordinary skill in the art, items shown separately could be combined and some items could be separated.

[0170] Illustrated in Fig. 9 are at least one processor 902 coupled to a chipset 904. Also coupled to the chipset 904 are a memory 906, a storage device 908, a keyboard 910, a graphics adapter 912, a pointing device 914, and a network adapter 916. A display 918 is coupled to the graphics adapter 912. In one embodiment, the functionality of the chipset 904 is provided by a memory controller hub 920 and an I / O hub 922. In another embodiment, the memory 906 is coupled directly to the processor 902 instead of the chipset 904. In some embodiments, the computer 900 includes one or morecommunication buses for interconnecting these components. The one or more communication buses optionally include circuitry (sometimes called a chipset) that interconnects and controls communications between system components.

[0171] The storage device 908 is any non-transitory computer-readable storage medium, such as a hard drive, compact disk read-only memory (CD-ROM), DVD, or a solid-state memory device or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. Such a storage device 908 can also be referred to as persistent memory. The pointing device 914 may be a mouse, track ball, or other type of pointing device, and is used in combination with the keyboard 910 to input data into the computer 900. The graphics adapter 912 displays images and other information on the display 918. The network adapter 916 couples the computer 900 to a local or wide area network.

[0172] The memory 906 holds instructions and data used by the processor 902. The memory 906 can be non-persistent memory, examples of which include high-speed random access memory, such as DRAM, SRAM, DDR RAM, ROM, EEPROM, flash memory.

[0173] As is known in the art, a computer 900 can have different or other components than those shown in Fig. 9. In addition, the computer 900 can lack certain illustrated components. In one embodiment, a computer 900 acting as a server may lack a keyboard 910, pointing device 914, graphics adapter 912, or display 918. Moreover, the storage device 908 can be local or remote from the computer 900 (such as embodied within a storage area network (SAN)).

[0174] The computer 900 is adapted to execute computer program modules for providing functionality described herein, such as any of the modules 102, 104, 106 and110 described above in respect of Fig. 1A. As used herein, the term “module” refers to computer program logic utilized to provide the specified functionality. Thus, a module can be implemented in hardware, firmware, or software. In one embodiment, program modules are stored on the storage device 908, loaded into the memory 906, and executed, individually or together, by one or more processors (e.g., 902).V. Additional Considerations

[0175] Although parts of the foregoing disclosure are framed in the context of gate based quantum computing, it will be appreciated that the methods and apparatus described herein may be used more generally for the selection of quantum error correction codes to implement logical quantum programs. For example, the QECC selector 100 may receive a description of a logical quantum program to be executed on a quantum computing system and determine a property of the logical quantum program based on the description of the logical quantum program. The QECC selector 100 may select a QECC from two or more candidate QECCs based on the determined property of the logical quantum program, in which the two or more candidate QECCs are capable of implementing the logical quantum program as a physical implementation executable by the quantum computing system.

[0176] Some portions of above disclosure describe the embodiments in terms of algorithmic processes or operations. These algorithmic descriptions and representations are commonly used by those skilled in the computing arts to convey the substance of their work effectively to others skilled in the art. These operations, while described functionally, computationally, or logically, are understood to be implemented by computer programs comprising instructions for execution, individually or together, by one or more processors, equivalent electrical circuits, microcodes, or the like. Furthermore, it has also proven convenient at times, to refer to these arrangements of functional operations asmodules, without loss of generality. In some cases, a module can be implemented in hardware, firmware, or software.

[0177] As used herein, any reference to “one embodiment” or “an embodiment” means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Similarly, use of “a” or “an” preceding an element or component is done merely for convenience. This description should be understood to mean that one or more of the elements or components are present unless it is obvious that it is meant otherwise. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

[0178] In addition, use of the “a” or “an” are employed to describe elements and components of the embodiments. This is done merely for convenience and to give a general sense of the disclosure. This description should be read to include one or at least one and the singular also includes the plural unless it is obvious that it is meant otherwise. Where values are described as “approximate” or “substantially” (or their derivatives), such values should be construed as accurate + / - 10% unless another meaning is apparent fromthe context. From example, “approximately ten” should be understood to mean “in a range from nine to eleven.”

[0179] Alternative embodiments are implemented in computer hardware, firmware, software, and / or combinations thereof. Implementations can be implemented in a computer program product tangibly embodied in a machine -readable storage device for execution by a programmable processor system including one or more processors that can act individually or together; and method steps can be performed by a programmable processor system executing a program of instructions to perform functions by operating on input data and generating output. Embodiments can be implemented advantageously in one or more computer programs that are executable on a programmable system including one or more programmable processors coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a readonly memory and / or a random-access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto -optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROMdisks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits) and other forms of hardware.

[0180] Although the above description contains many specifics, these should not be construed as limiting the scope of the disclosure but merely as illustrating different examples. It should be appreciated that the scope of the disclosure includes other embodiments not discussed in detail above. Various other modifications, changes, and variations which will be apparent to those skilled in the art may be made in the arrangement, operation, and details of the methods and apparatuses disclosed herein without departing from the spirit and scope of the disclosure.

Claims

CLAIMS:

1. A method comprising: receiving a description of a logical quantum circuit to be executed on a quantum computing system; determining a property of the logical quantum circuit based on the description of the logical quantum circuit; and selecting a first quantum error correction code (QECC) from two or more candidate QECCs based on the determined property of the logical quantum circuit, wherein the two or more candidate QECCs are capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system.

2. The method of claim 1, further comprising generating a first physical quantum circuit executable by the quantum computing system by using the first QECC to map the logical quantum circuit to the first physical quantum circuit.

3. The method of claim 2, further comprising causing the first physical quantum circuit to be executed by the quantum computing system.

4. The method of claim 3, wherein causing the first physical quantum circuit to be executed by the quantum computing system comprises executing the first physical quantum circuit by the quantum computing system.

5. The method of claim 3, wherein causing the first physical quantum circuit to be executed by the quantum computing system comprises transmitting the first physical quantum circuit to the quantum computing system for execution.

6. The method of any one of claims 2-5, wherein selecting the first QECC further comprises:determining that a number of physical qubits to implement the first physical quantum circuit is equal to or smaller than a number of available physical qubits of the quantum computing system.

7. The method of any one of claims 2-6, wherein the first QECC is selected according to the fidelities of the quantum computing system executing particular physical quantum gates and the physical quantum gates of the first physical quantum circuit.

8. The method of any one of claims 2-7, wherein selecting the first QECC is based on a simulation of the first physical quantum circuit.

9. The method of any one of claims 2-7, further comprising: selecting a second QECC from the candidate QECCs, wherein the second QECC is different than the first QECC; generating, using the second QECC, a second physical quantum circuit executable by the quantum computing system, by using the second QECC to map the logical quantum circuit to the second physical quantum circuit; and determining the first physical quantum circuit has an improved performance metric value relative to the second physical quantum circuit.

10. The method of claim 9, wherein determining the first physical quantum circuit has the improved performance metric value relative to the second physical quantum circuit comprises: determining a first value of the performance metric for the first physical quantum circuit based on a simulation of the first physical quantum circuit; determining a second value of the performance metric for the second physical quantum circuit based on a simulation of the second physical quantum circuit; andcomparing the first value of the performance metric for the first physical quantum circuit to the second value of the performance metric for the second physical quantum circuit.

11. The method of any one of claims 1-10, wherein the determined property of the logical quantum circuit includes a gate type of each logical quantum gate in the logical quantum circuit.

12. The method of any one of claims 1-11, wherein the determined property of the logical quantum circuit includes a count of logical quantum gates of each gate type in the logical quantum circuit.

13. The method of any one of claims 1-12, wherein the determined property of the logical quantum circuit includes a most common logical quantum gate type of the logical quantum circuit.

14. The method of any one of claims 1-13, wherein the determined property of the logical quantum circuit includes a sequence of logical quantum gates in the logical quantum circuit.

15. The method of any one of claims 1-14, wherein the determined property of the logical quantum circuit includes a depth of the logical quantum circuit.

16. The method of any one of claims 1-15, wherein the determined property of the logical quantum circuit includes a metric value indicating an amount of quantum entanglement resulting from implementing the logical quantum circuit.

17. The method of any one of claims 1-16, wherein the determined property of the logical quantum circuit includes a property of a partition of the logical quantum circuit.

18. The method of any one of claims 1-17, further comprising determining a property for the two or more candidate QECCs.

19. The method of claim 18, wherein the property for the two or more candidateQECCs relates to one or more logical quantum gates from the logical quantum circuit in the two or more candidate QECCs.

20. The method of claim 19, wherein the determined property of the candidate QECCs is based on a predicted execution time of the one or more logical quantum gates.

21. The method of any one of claim 19-20, wherein the determined property of the candidate QECCs is based on a count of magic states to implement the one or more logical quantum gates.

22. The method of any one of claim 19-21, wherein the determined property of the candidate QECCs is based on a count of Bell pairs to implement the one or more logical quantum gates.

23. The method of any one of claim 19-22, wherein the determined property of the candidate QECCs is based on a fidelity of implementing the one or more logical quantum gates.

24. The method of any one of claim 18-23, wherein the determined property of the candidate QECCs is based on a code distance of the candidate QECCs.

25. The method of any one of claim 18-24, wherein the determined property of the candidate QECCs is based on a number of physical qubits accommodated by the candidate QECCs.

26. The method of any one of claim 18-25, wherein the determined property of the candidate QECCs is based on a distance value of the candidate QECCs.

27. The method of any one of claim 18-26, wherein the determined property of the candidate QECCs is based on a pseudo-threshold value of the candidate QECCs.

28. The method of any one of claim 18-27, wherein the determined property of the candidate QECCs is based on an error spread value for a physical quantum gate of the candidate QECCs.

29. The method of any one of claim 18-28, wherein the determined property of the candidate QECCs is based on a decoder performance value of a decoder for the candidate QECCs.

30. The method of any one of claims 1-5, wherein: the determined property of the logical quantum circuit includes the most common logical gate type of the logical quantum circuit; and the first QECC is selected based on a performance metric value of the first QECC for implementing the most common logical gate type in a physical quantum circuit.

31. The method of any one of claims 1-5, further comprising, for each candidateQECC: determining a predicted execution time to implement the logical quantum circuit using the candidate QECC, the predicted execution time based on the count of gates of each gate type in the logical quantum circuit, wherein the first QECC is selected based on the predicted execution time.

32. The method of any one of claims 1-31, wherein the first QECC is selected additionally according to a property of the quantum computing system.

33. The method of claim 32, wherein: the property of the quantum computing system comprises a qubit connectivity of the quantum computing system, and the first QECC is selected according to the number of SWAP operations to be used to implement the logical quantum circuit using the first QECC.

34. The method of any one of claims 32-33, wherein: the property of the quantum computing system comprises a native gate set of the quantum computing system, and the first QECC is selected according to a number of resources to implement the logical quantum circuit using quantum gates of the native gate set.

35. The method of any one of claims 32-34, wherein: the property of the quantum computing system includes reliability values for implementing measurement protocols, and the first QECC is selected according to the reliability values and a measurement protocol of the first QECC.

36. The method of any one of claims 32-35, wherein the property of the quantum computing system includes whether or not the quantum computing system implements 2- qubit gates using teleportation.

37. The method of any one of claims 1-36, further comprising: determining a second logical quantum circuit that is equivalent to the received logical quantum circuit; and determining second properties of the second logical quantum circuit, wherein the first QECC is selected according to the determined properties of the received logical quantum circuit and the determined second properties of the second logical quantum circuit.

38. The method of claim 37, wherein selecting the first QECC further comprises: selecting a first subset of the candidate QECCs according to the determined properties of the candidate QECCs and the determined properties of the received logical quantum circuit; andselecting a second subset of the candidate QECCs according to the determined properties of the candidate QECCs and the determined second properties of the second logical quantum circuit; wherein the first QECC is part of the first subset or the second subset.

39. The method of claim 38, wherein selecting the first QECC further comprises selecting the first QECC based on a comparison of the first subset and the second subset.

40. The method of any one of claims 1-39, wherein the first QECC is selected due to the first QECC allowing a logical gate of the logical quantum circuit to be implemented at least in part by a classically computable operation.

41. The method of claim 40, wherein selecting the first QECC further comprises: determining the most common gate type of the logical quantum circuit; and selecting the first QECC based on a determination that the first QECC allows the most common gate type of the logical quantum circuit to be implemented at least in part by the classically computable operation.

42. The method of claim 40, wherein selecting the first QECC further comprises: for the candidate QECCs: determining a total number of logical quantum gates of the logical quantum circuit that can be implemented at least in part with classically computable operations using the QECC; and selecting the first QECC based on the determined total numbers of logical quantum gates that can be implemented at least in part by classically computable operations.

43. The method of claim 40, wherein selecting the first QECC further comprises: determining a most computationally expensive logical quantum gate of the logical quantum circuit;selecting the first QECC based on a determination that the first QECC allows the most computationally expensive logical quantum gate to be implemented at least in part by the classically computable operation.

44. The method of any one of claims 1-43, wherein selecting the first QECC from two or more candidate QECCs comprises jointly selecting the first QECC and a basis for the selected first QECC.

45. A computing system comprising: a classical computing system configured to perform operations comprising: receiving a description of a logical quantum circuit to be executed on a quantum computing system; determining properties of the logical quantum circuit based on the description of the logical quantum circuit; determining properties for two or more candidate quantum error correction codes (QECCs) capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system; selecting a first quantum error correction code (QECC) from two or more candidate QECCs based on the determined properties of the candidate QECCs, wherein the two or more candidate QECCs are capable of implementing the logical quantum circuit as physical quantum circuits executable by the quantum computing system; and generating a description of a first physical quantum circuit executable by the quantum computing system, by using the first QECC to map the logical quantum circuit to the first physical quantum circuit; and a quantum computing system configured to perform operations comprising:receiving the description of the first physical quantum circuit; and executing the first physical quantum circuit on physical qubits of the quantum computing system.

46. A non-transitory computer-readable storage medium comprising stored instructions which, when executed by a computing system, cause the computing system to perform any of the methods of claims 1-44.

47. A computing system including a quantum computing system or a classical computing system, the computing system configured to perform any of the methods of claims 1-44.

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