Verifying correctness of computer vision during semiconductor inspection

Abstract

An image of a workpiece is forwarded through a graph of a deep neural network model or directed acyclic graph of deep neural network models. The output is then recorded as an array. A self-test input buffer (X) and expected output buffer (Y) are determined. An actual output (Y') is then predicted with inputs. Shape and float values of the expected output buffer (Y) and actual output (Y') are compared using a tolerance epsilon.

Description

VERIFYING CORRECTNESS OF COMPUTER VISION DURING SEMICONDUCTOR INSPECTIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to the provisional patent application filed December 7, 2023 and assigned U.S. App. No. 63 / 607,109, the disclosure of which is hereby incorporated by reference.FIELD OF THE DISCLOSURE

[0002] This disclosure relates to semiconductor inspection.BACKGROUND OF THE DISCLOSURE

[0003] Evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions continue to shrink, yet the industry needs to decrease time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for a semiconductor manufacturer.

[0004] Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a workpiece, such as a semiconductor wafer, using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. An arrangement of multiple semiconductor devices fabricated on a single semiconductor wafer may be separated into individual semiconductor devices.

[0005] Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yield in the manufacturing process and, thus, higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits (ICs). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devicesbecause smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary because even relatively small defects may cause unwanted aberrations in the semiconductor devices.

[0006] As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitation on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. As design rules shrink, the population of potentially yield-relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more defects may be detected on the workpiece, and correcting the processes to eliminate all of the defects may be difficult and expensive. Determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process-induced failures, in some cases, tend to be systematic. That is, process-induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially-systematic, electrically-relevant defects can have an impact on yield.

[0007] Deep neural networks (DNNs) can be used to identify and classify defects in images generated during semiconductor inspection, but DNNs have limitations. A test set prediction is performed after train time for a DNN. The composed graph or model is shipped to an inference engine (e.g., Tensorflow, PyTorch, TensorRT, etc.). There is limitation with this process in the input processing before prediction. For example, it is common to divide values by 255 with pixels. When a DNN is fed with the pixel values of the image channels, it is common to divide the pixel values in 255 in order to transform the values from 0..255 to 0..1 which is more common in scientific computation. A mismatch between train time and inference time can negatively affect later inspection results using the DNN. Improved systems and techniques are needed.BRIEF SUMMARY OF THE DISCLOSURE

[0008] A system is provided in a first embodiment. The system includes a light source that generates a beam of light, a stage configured to hold a workpiece (e.g., a semiconductor wafer) in a path of the beam of light, a detector that receives the beam of light reflected from the workpiece,and a processor in electronic communication with the detector. The processor (e.g., GPU or CPU) is configured to receive an image of a workpiece based on data from the detector; forward the image through a graph of a deep neural network model or directed acyclic graph of deep neural network models; record the output as an array; determine self-test input buffer (X) and expected output buffer (Y); predict an actual output (Y’) with inputs; and compare shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon. An electronic data storage unit is in electronic communication with the processor. The deep neural network model or directed acyclic graph of deep neural network models is stored on the electronic data storage unit.

[0009] The directed acyclic graph of deep neural network models is used in an instance. The output can include each node output and input.

[0010] The directed acyclic graph of deep neural network models is used in an instance. The recording includes each node output and input in the array.

[0011] The processor may be further configured to communicate a failure message if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon.

[0012] A method is provided in a second embodiment. The method includes receiving, at a processor (e.g., CPU or GPU), an image of a workpiece (e.g., a semiconductor wafer). Using the processor, the image is forwarded through a graph of a deep neural network model or directed acyclic graph of deep neural network models. Using the processor, the output is recorded as an array. Using the processor, self-test input buffer (X) and expected output buffer (Y) are determined. Using the processor, an actual output (Y’) is predicted with inputs. Using the processor, shape and float values of the expected output buffer (Y) and actual output (Y’) are compared using a tolerance epsilon.

[0013] The directed acyclic graph of deep neural network models is used in an instance. The output can include each node output and input.

[0014] The directed acyclic graph of deep neural network models is used in an instance. The recording includes each node output and input in the array.

[0015] The method can include communicating a failure message if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon.

[0016] A non-transitory computer-readable storage medium including one or more programs is provided in a third embodiment. The one or more programs can execute the following steps on one or more computing devices: receive an image of a workpiece (e.g., a semiconductor wafer); forward the image through a graph of a deep neural network model or directed acyclic graph of deep neural network models; record the output as an array; determine self-test input buffer (X) and expected output buffer (Y); predict an actual output (Y’) with inputs; and compare shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon.

[0017] The directed acyclic graph of deep neural network models is used in an instance. The output can include each node output and input.

[0018] The directed acyclic graph of deep neural network models is used in an instance. The recording includes each node output and input in the array.

[0019] The steps can include communicating a failure message if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon.DESCRIPTION OF THE DRAWINGS

[0020] For a fuller understanding of the nature and objects of the disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:FIG. 1 is a flowchart of an embodiment of a method in accordance with the present disclosure;FIG. 2 is a diagram of a system operation in accordance with the present disclosure;FIG. 3 is an embodiment using a user-defined function preprocessor;FIG. 4 is a diagram showing a model accepting multiple named tensors and outputting multiple named tensors multi-input, multi-output (MIMO); andFIG. 5 is a block diagram showing an exemplary inspection system.DETAILED DESCRIPTION OF THE DISCLOSURE

[0021] Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined only by reference to the appended claims.

[0022] In the embodiments disclosed herein, a model or directed acrylic graph (DAG) of models can be used. A DAG is a directed graph that has no cycles. A graph is a data structure with vertices and envelopes. Each vertex has an associated edge that connects it to every other vertex. Vertices and edges in the DAG are configured so that each edge is directed from one vertex to another such that following those directions will never form a closed loop. At a graph saving stage, one example input image of a workpiece is selected and forwarded through the graph.

[0023] The output tensors that include numbers coming out of the DNN execution are recorded in the case of a single DNN or each node output and input is recorded in the case of DAG of DNNs. The inputs and outputs are saved as arrays. At an inference stage (e.g., when using C++ library like Tensorflow, PyTorch, TensorRT, etc.), the model is loaded and the self-test input buffer (X) and expected output buffer (Y) are read. A model predict is performed with inputs and an actual output (Y’) is recorded. The shape and float values are compared using a tolerance epsilon (e.g., 0.0001) and a binary result can be reported. Success or failure can be determined if all shapes match and all differences between Y and Y’ are below the allowed epsilon. In the case of a multi-DNN graph, such as an ensemble of majority -voting five DNNs, the self-test procedure can compare every sub-node input and predicted output and the overall outputs of the composed model. This method can ensure that for the given saved input data “X” and recorded output “Y,” both prediction systems will still generate the same expected output values. This can avoid errors during defect detection for semiconductor wafers, which can have negative consequences during semiconductor manufacturing. The embodiments disclosed herein can be automated, which avoids the error-prone manual or semimanual techniques that were previously used.

[0024] If, by bug or mistake, a DNN is fed with the wrong input at inference time (e.g., values between 0..1 instead of values from 0..255), the result can be negatively affected. The DNNwill output wrong values and this can cause incorrect decisions on the tool. In an instance, such an incorrect decision can include expecting from the DNN to classify images with two output classes: defect or non-defect. When the input does not purely match the DNN expectation, the output probability of the DNN will be wrong so wafers with defects may be classified as not having defects and vice versa. This is a problem for semiconductor manufacturers. Previously, users would manually verify that the same pretrained neural network predicted the same results when executed using a Python and Tensorflow Package and separately using a C++ and Tensorflow C++ Library.

[0025] FIG. 1 is a flowchart of a method 100. FIG. 2 is a diagram of a system operation. Embodiments of FIG. 2 can use a processor, such as a GPU, CPU, Tensor processing unit (TPU), or another processor that can execute an interference on a DNN. X, Y, and Y’ are arrays for multiinput, multi-output support. A model can accept any number of input tensors and output a set of predicted tensors. Thus, X, Y, and Y” in FIG. 2 can be a named dictionary of predicted output tensors.

[0026] In FIG. 2, an image of a workpiece can be received at a processor at 101. For example, the workpiece can be a semiconductor wafer or part of a semiconductor wafer (e.g., a die or device). The image is forwarded through a graph of a DNN model or DAG of DNN models at 102. The output is recorded as an array at 103. When an image is read from a file on disk or fed from a network port, it is saved as a long array of numbers. For example, a wafer image with 50 rows and 40 columns of pixels will be saved as an array of 2000 (50*40) float32 numbers, row by row. First, 40 numbers of row 1 are saved. Then the next 40 numbers of row 2 are saved. This process continues until the last 40 numbers of row 50. When this array is ready, it is saved with the DNN binary file. The recorded X arrays, Y arrays, and the DNN structure and weights can be attached as a single binary file

[0027] A self-test input buffer (X) and expected output buffer (Y) are determined at 104. X is a list of arrays. Each array has a list of numbers and a data type. For example, this can be an image with 50 rows and 40 columns with a data type of float32 (e.g., Float 32 bit). Y is the output list of arrays coming out of the DNN. Y is saved in the same way as X. For example, a DNN with two inputs and three outputs will be saved as five files (e.g., [inputl.float32.bin, input2.int64.bin] and for the outputs [outputl.float32.bin, output2.intl6.bin, output3.float64.bin]).

[0028] An actual output (Y’) is then predicted with inputs at 105. This prediction can include executing the DNN inference function in a programming language, such as Python, C++. So, Y’ is a list of numerical arrays returned from a function call to the DNN model loaded in memory. The inputs can be the same as described in other steps, such as for step 104.

[0029] The shape and float values of the expected output buffer (Y) and actual output (Y’) are compared at 106 using a tolerance epsilon, which is a threshold to determine equality or proximity. A failure message can be communicated if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon. The comparison process can use two numerical arrays having the same data type (e.g., float32 or int64) and the same length (e.g., 2000 numbers). The two arrays can be compared value by value with a tolerance “tol” that is saved with each DNN model. The process is shown in the example below. for each vl, v2 from (Y, Y’): if (abs(vl-v2) > tol): return error no match for arrays of type integer (int8,intl6,int32,int64) we compare using exact comparison: for each vl, v2 from (Y, Y’): if (vl ! = v2): return error no match

[0030] When the DAG of DNN models is used, the output includes each node output and input. The recording includes each node output and input in the array.

[0031] FIG. 3 is an embodiment using a user-defined function preprocessor. FIG. 3 depicts an example code in Python programming language that uses the numpy library. The function depicted on the left accepts a list or dictionary of inputs (X) and it returns the processed inputs. For example, the function may test if the image pixel values are between 0..255 and if so, it will scalethem to be between 0..1 to fit the DNN model expectations. This function can be executed by the inference engine before executing the DNN model.

[0032] A piece of numpy-compatible procedure can be saved in the model for input preprocessing. This piece of Python computer program can take a dictionary X and a piece of code in Python-like language as an input. This optional procedure is saved along with the other binary files, such as with X, Y, the DNN model, and the optional Python function. The final model can hold all these binary files in a package such as a zip file format. In this program, a function can take a three channel RGB color image and for each pixel x (small X) perform the following transform: x = (x-mean) / std. This process is normalization of an image. Other functions may execute different tests and normalization processes. This function can serve as a gate before feeding the inputs to the DNN model.

[0033] During C++ inference, if this code exists, it can be just-in-time (JIT) compiled to a C++ optimized code based on the numpy C library. This embodiment can be applied to deterministic models and not random generators neural networks. This embodiment may ensure exact input and output when crossing predictions from Python to C++ and vice versa. Al and Machine Learning libraries like Tensorflow, PyTorch, and others have different versions and different access points (API). Training a DNN using Python and then doing inference from C++ means that the Tensorflow libraries may perfectly match from Python to C++, but this does not always occur. The embodiment of FIG. 3 can ensure that the same inputs will be fed to the model and the same outputs will be predicted by the DNN model.

[0034] FIG. 4 shows a model accepting multiple named tensors and outputting multiple named tensors MIMO. FIG. 4 depicts an exemplary DNN model that accepts X as three different inputs: a color RGB image, a numerical matrix, and a list of trending values. The DNN model can use X as inputs, execute the inference, and report back a list of probabilities.

[0035] A DNN (e.g., a convolutional neural network (CNN), vision transformer network (VIT), residual network (ResNet), or Auto-Encoder (UNET)) can be executed by the processor. The DNN can have one of the configurations described further herein. Rooted in neural network technology, deep learning is a probabilistic graph model with many neuron layers, commonly known as a deep architecture. Deep learning technology processes the information such as image,text, voice, and so on in a hierarchical manner. In using deep learning in the present disclosure, the embodiments disclosed herein can be accomplished automatically.

[0036] Generally speaking, deep learning (also known as deep structured learning, hierarchical learning, or deep machine learning) is a branch of machine learning based on a set of algorithms that attempt to model high level abstractions in data. In a simple case, there may be two sets of neurons: ones that receive an input signal and ones that send an output signal. When the input layer receives an input, it passes on a modified version of the input to the next layer. In a deep network, there are many layers between the input and output, allowing the algorithm to use multiple processing layers, composed of multiple linear and non-linear transformations.

[0037] Deep learning is part of a broader family of machine learning methods based on learning representations of data. An observation (e.g., a feature to be extracted for reference) can be represented in many ways such as a vector of intensity values per pixel, or in a more abstract way as a set of edges, regions of particular shape, etc. Some representations are better than others at simplifying the learning task (e.g., face recognition or facial expression recognition). Deep learning can provide efficient algorithms for unsupervised or semi-supervised feature learning and hierarchical feature extraction.

[0038] Research in this area attempts to make better representations and create models to learn these representations from large-scale data. Some of the representations are inspired by advances in neuroscience and are loosely based on interpretation of information processing and communication patterns in a nervous system, such as neural coding which attempts to define a relationship between various stimuli and associated neuronal responses in the brain.

[0039] There are many variants of neural networks with deep architecture depending on the probability specification and network architecture, including, but not limited to, Deep Belief Networks (DBN), Restricted Boltzmann Machines (RBM), and Auto-Encoders. Another type of deep neural network, a CNN, can be used for feature analysis. The actual implementation may vary depending on the size of input images, the number of features to be analyzed, and the nature of the problem. Other layers may be included in the deep learning module besides the neural networks disclosed herein.

[0040] In a further embodiment, the DNN can have a set of weights that model the world according to the data that it has been fed to train it. Neural networks can be generally defined as a computational approach, based on a relatively large collection of neural units loosely modeling the way a biological brain solves problems with relatively large clusters of biological neurons connected by axons. Each neural unit is connected with many others, and links can be enforcing or inhibitory in their effect on the activation state of connected neural units. These systems are self-learning and trained rather than explicitly programmed and excel in areas where the solution or feature detection is difficult to express in a traditional computer program.

[0041] Neural networks typically comprise multiple layers, and the signal path traverses from front to back. The goal of the neural network is to solve problems in the same way that the human brain would, although several neural networks are much more abstract. Modern neural network projects typically work with a few thousand to a few million neural units and millions of connections. The neural network may have any suitable architecture and / or configuration known in the art.

[0042] In general, the DNN described herein is a trained DNN. For example, the DNN may be previously trained by one or more other systems and / or methods. The DNN is already generated and trained and then the functionality of the module is determined as described herein, which can then be used to perform one or more additional functions for the deep learning module.

[0043] As stated above, although a CNN is used herein to illustrate the architecture of a DNN, the present disclosure is not limited to a CNN. Other variants of deep learning architectures may be used in embodiments.

[0044] One embodiment of a system 200 is shown in FIG. 5. The system 200 includes optical based subsystem 201. In general, the optical based subsystem 201 is configured for generating optical based output for a workpiece 202 by directing light to (or scanning light over) and detecting light from the workpiece 202. In one embodiment, the workpiece 202 includes a wafer. The wafer may include any wafer known in the art. In another embodiment, the workpiece 202 includes a reticle. The reticle may include any reticle known in the art.

[0045] In the embodiment of the system 200 shown in FIG. 5, optical based subsystem 201 includes an illumination subsystem configured to direct light to workpiece 202. The illumination subsystem includes at least one light source. For example, as shown in FIG. 5, the illumination subsystem includes light source 203. In one embodiment, the illumination subsystem is configured to direct the light to the workpiece 202 at one or more angles of incidence, which may include one or more oblique angles and / or one or more normal angles. For example, as shown in FIG. 5, light from light source 203 is directed through optical element 204 and then lens 205 to workpiece 202 at an oblique angle of incidence. The oblique angle of incidence may include any suitable oblique angle of incidence, which may vary depending on, for instance, characteristics of the workpiece 202.

[0046] The optical based subsystem 201 may be configured to direct the light to the workpiece 202 at different angles of incidence at different times. For example, the optical based subsystem 201 may be configured to alter one or more characteristics of one or more elements of the illumination subsystem such that the light can be directed to the workpiece 202 at an angle of incidence that is different than that shown in FIG. 5. In one such example, the optical based subsystem 201 may be configured to move light source 203, optical element 204, and lens 205 such that the light is directed to the workpiece 202 at a different oblique angle of incidence or a normal (or near normal) angle of incidence.

[0047] In some instances, the optical based subsystem 201 may be configured to direct light to the workpiece 202 at more than one angle of incidence at the same time. For example, the illumination subsystem may include more than one illumination channel, one of the illumination channels may include light source 203, optical element 204, and lens 205 as shown in FIG. 5 and another of the illumination channels (not shown) may include similar elements, which may be configured differently or the same, or may include at least a light source and possibly one or more other components such as those described further herein. If such light is directed to the workpiece at the same time as the other light, one or more characteristics (e.g., wavelength, polarization, etc.) of the light directed to the workpiece 202 at different angles of incidence may be different such that light resulting from illumination of the workpiece 202 at the different angles of incidence can be discriminated from each other at the detector(s).

[0048] In another instance, the illumination subsystem may include only one light source (e.g., light source 203 shown in FIG. 5) and light from the light source may be separated into different optical paths (e.g., based on wavelength, polarization, etc.) by one or more optical elements (not shown) of the illumination subsystem. Light in each of the different optical paths may then be directed to the workpiece 202. Multiple illumination channels may be configured to direct light to the workpiece 202 at the same time or at different times (e.g., when different illumination channels are used to sequentially illuminate the workpiece). In another instance, the same illumination channel may be configured to direct light to the workpiece 202 with different characteristics at different times. For example, in some instances, optical element 204 may be configured as a spectral filter and the properties of the spectral filter can be changed in a variety of different ways (e.g., by swapping out the spectral filter) such that different wavelengths of light can be directed to the workpiece 202 at different times. The illumination subsystem may have any other suitable configuration known in the art for directing the light having different or the same characteristics to the workpiece 202 at different or the same angles of incidence sequentially or simultaneously.

[0049] In one embodiment, light source 203 may include a broadband plasma (BBP) source. In this manner, the light generated by the light source 203 and directed to the workpiece 202 may include broadband light. However, the light source may include any other suitable light source such as a laser. The laser may include any suitable laser known in the art and may be configured to generate light at any suitable wavelength or wavelengths known in the art. In addition, the laser may be configured to generate light that is monochromatic or nearly-monochromatic. In this manner, the laser may be a narrowband laser. The light source 203 may also include a polychromatic light source that generates light at multiple discrete wavelengths or wavebands.

[0050] Light from optical element 204 may be focused onto workpiece 202 by lens 205. Although lens 205 is shown in FIG. 5 as a single refractive optical element, it is to be understood that, in practice, lens 205 may include a number of refractive and / or reflective optical elements that in combination focus the light from the optical element to the workpiece. The illumination subsystem shown in FIG. 5 and described herein may include any other suitable optical elements (not shown). Examples of such optical elements include, but are not limited to, polarizing component(s), spectral filter(s), spatial filter(s), reflective optical element(s), apodizer(s), beam splitter(s) (such as beam splitter 213), aperture(s), and the like, which may include any such suitableoptical elements known in the art. In addition, the optical based subsystem 201 may be configured to alter one or more of the elements of the illumination subsystem based on the type of illumination to be used for generating the optical based output.

[0051] The optical based subsystem 201 may also include a scanning subsystem configured to cause the light to be scanned over the workpiece 202. For example, the optical based subsystem201 may include stage 206 on which workpiece 202 is disposed during optical based output generation. The scanning subsystem may include any suitable mechanical and / or robotic assembly (that includes stage 206) that can be configured to move the workpiece 202 such that the light can be scanned over the workpiece 202. In addition, or alternatively, the optical based subsystem 201 may be configured such that one or more optical elements of the optical based subsystem 201 perform some scanning of the light over the workpiece 202. The light may be scanned over the workpiece202 in any suitable fashion such as in a serpentine-like path or in a spiral path.

[0052] The optical based subsystem 201 further includes one or more detection channels. At least one of the one or more detection channels includes a detector 212 configured to detect light from the workpiece 202 due to illumination of the workpiece 202 by the subsystem and to generate output responsive to the detected light. For example, the optical based subsystem 201 shown in FIG. 5 includes two detection channels, one formed by collector 207, element 208, and detector 209 and another formed by collector 210, element 211, and detector 212. As shown in FIG. 5, the two detection channels are configured to collect and detect light at different angles of collection. In some instances, both detection channels are configured to detect scattered light, and the detection channels are configured to detect light that is scattered at different angles from the workpiece 202. However, one or more of the detection channels may be configured to detect another type of light from the workpiece 202 (e.g., reflected light).

[0053] As further shown in FIG. 5, both detection channels are shown positioned in the plane of the paper and the illumination subsystem is also shown positioned in the plane of the paper. Therefore, in this embodiment, both detection channels are positioned in (e.g., centered in) the plane of incidence. However, one or more of the detection channels may be positioned out of the plane of incidence. For example, the detection channel formed by collector 210, element 211, and detector 212 may be configured to collect and detect light that is scattered out of the plane of incidence.Therefore, such a detection channel may be commonly referred to as a “side” channel, and such a side channel may be centered in a plane that is substantially perpendicular to the plane of incidence.

[0054] Although FIG. 5 shows an embodiment of the optical based subsystem 201 that includes two detection channels, the optical based subsystem 201 may include a different number of detection channels (e.g., only one detection channel or two or more detection channels). In one such instance, the detection channel formed by collector 210, element 211, and detector 212 may form one side channel as described above, and the optical based subsystem 201 may include an additional detection channel (not shown) formed as another side channel that is positioned on the opposite side of the plane of incidence. Therefore, the optical based subsystem 201 may include the detection channel that includes collector 207, element 208, and detector 209 and that is centered in the plane of incidence and configured to collect and detect light at scattering angle(s) that are at or close to normal to the workpiece 202 surface. This detection channel may therefore be commonly referred to as a “top” channel, and the optical based subsystem 201 may also include two or more side channels configured as described above. As such, the optical based subsystem 201 may include at least three channels (i.e., one top channel and two side channels), and each of the at least three channels has its own collector, each of which is configured to collect light at different scattering angles than each of the other collectors.

[0055] As described further above, each of the detection channels included in the optical based subsystem 201 may be configured to detect scattered light. Therefore, the optical based subsystem 201 shown in FIG. 5 may be configured for dark field (DF) output generation for workpieces 202. However, the optical based subsystem 201 may also or alternatively include detection channel(s) that are configured for bright field (BF) output generation for workpieces 202. In other words, the optical based subsystem 201 may include at least one detection channel that is configured to detect light specularly reflected from the workpiece 202. Therefore, the optical based subsystems 201 described herein may be configured for only DF, only BF, or both DF and BF imaging. Although each of the collectors are shown in FIG. 5 as single refractive optical elements, it is to be understood that each of the collectors may include one or more refractive optical die(s) and / or one or more reflective optical element(s).

[0056] The one or more detection channels may include any suitable detectors known in the art. For example, the detectors may include photo-multiplier tubes (PMTs), charge coupled devices (CCDs), time delay integration (TDI) cameras, and any other suitable detectors known in the art. The detectors may also include non-imaging detectors or imaging detectors. In this manner, if the detectors are non-imaging detectors, each of the detectors may be configured to detect certain characteristics of the scattered light such as intensity but may not be configured to detect such characteristics as a function of position within the imaging plane. As such, the output that is generated by each of the detectors included in each of the detection channels of the optical based subsystem may be signals or data, but not image signals or image data. In such instances, a processor such as processor 214 may be configured to generate images of the workpiece 202 from the non-imaging output of the detectors. However, in other instances, the detectors may be configured as imaging detectors that are configured to generate imaging signals or image data. Therefore, the optical based subsystem may be configured to generate optical images or other optical based output described herein in a number of ways.

[0057] It is noted that FIG. 5 is provided herein to generally illustrate a configuration of an optical based subsystem 201 that may be included in the system embodiments described herein or that may generate optical based output that is used by the system embodiments described herein. The optical based subsystem 201 configuration described herein may be altered to optimize the performance of the optical based subsystem 201 as is normally performed when designing a commercial output acquisition system. In addition, the systems described herein may be implemented using an existing system (e.g., by adding functionality described herein to an existing system). For some such systems, the methods described herein may be provided as optional functionality of the system (e.g., in addition to other functionality of the system). Alternatively, the system described herein may be designed as a completely new system.

[0058] The processor 214 may be coupled to the components of the system 200 in any suitable manner (e.g., via one or more transmission media, which may include wired and / or wireless transmission media) such that the processor 214 can receive output. The processor 214 may be configured to perform a number of functions using the output. The system 200 can receive instructions or other information from the processor 214. The processor 214 and / or the electronic data storage unit 215 optionally may be in electronic communication with a wafer inspection tool, awafer metrology tool, or a wafer review tool (not illustrated) to receive additional information or send instructions. For example, the processor 214 and / or the electronic data storage unit 215 can be in electronic communication with a scanning electron microscope.

[0059] The processor 214, other system(s), or other subsystem(s) described herein may be part of various systems, including a personal computer system, image computer, mainframe computer system, workstation, network appliance, internet appliance, or other device. The subsystem(s) or system(s) may also include any suitable processor known in the art, such as a parallel processor. In addition, the subsystem(s) or system(s) may include a platform with highspeed processing and software, either as a standalone or a networked tool.

[0060] The processor 214 and electronic data storage unit 215 may be disposed in or otherwise part of the system 200 or another device. In an example, the processor 214 and electronic data storage unit 215 may be part of a standalone control unit or in a centralized quality control unit. Multiple processors 214 or electronic data storage units 215 may be used.

[0061] The processor 214 may be implemented in practice by any combination of hardware, software, and firmware. Also, its functions as described herein may be performed by one unit, or divided up among different components, each of which may be implemented in turn by any combination of hardware, software and firmware. Program code or instructions for the processor 214 to implement various methods and functions may be stored in readable storage media, such as a memory in the electronic data storage unit 215 or other memory.

[0062] If the system 200 includes more than one processor 214, then the different subsystems may be coupled to each other such that images, data, information, instructions, etc. can be sent between the subsystems. For example, one subsystem may be coupled to additional subsystem(s) by any suitable transmission media, which may include any suitable wired and / or wireless transmission media known in the art. Two or more of such subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown).

[0063] The processor 214 may be configured to perform a number of functions using the output of the system 200 or other output. For instance, the processor 214 may be configured to send the output to an electronic data storage unit 215 or another storage medium. The processor 214 maybe configured according to any of the embodiments described herein. The processor 214 also may be configured to perform other functions or additional steps using the output of the system 200 or using images or data from other sources.

[0064] Program instructions implementing methods such as those described herein may be transmitted over or stored on carrier medium. The carrier medium may include a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid state memory, a magnetic tape, and the like. A carrier medium may include a transmission medium such as a wire, cable, or wireless transmission link. For instance, the various steps described throughout the present disclosure may be carried out by a single processor 214 or, alternatively, multiple processors 214. Moreover, different sub-systems of the system 200 may include one or more computing or logic systems. Therefore, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration.

[0065] In an instance, the processor 214 is in communication with the system 200. The processor 214 is configured to operate a system that compares shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon as disclosed herein.

[0066] An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a controller for performing a computer-implemented method that compares shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon, as disclosed herein. In particular, as shown in FIG. 5, electronic data storage unit 215 or other storage medium may contain non-transitory computer-readable medium that includes program instructions executable on the processor 214. The computer-implemented method may include any step(s) of any method(s) described herein, including method of FIGS. 1-3.

[0067] The program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and / or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extension (SSE), or other technologies or methodologies, as desired.

[0068] While disclosed with an inspection system and a semiconductor wafer, other systems and workpieces can benefit from the embodiments disclosed herein. For example, a review or metrology tool can use the embodiments disclosed herein. Other overlay measurement tools also can use the embodiments disclosed herein. The system can use an electron beam or an ion beam instead of a beam of light. The workpiece can be a flat panel, a printed circuit board, or other substrate instead of a semiconductor wafer.

[0069] Each of the steps of the method may be performed as described herein. The methods also may include any other step(s) that can be performed by the processor and / or computer subsystem(s) or system(s) described herein. The steps can be performed by one or more computer systems, which may be configured according to any of the embodiments described herein. In addition, the methods described above may be performed by any of the system embodiments described herein.

[0070] Although the present disclosure has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure. Hence, the present disclosure is deemed limited only by the appended claims and the reasonable interpretation thereof.

Claims

What is claimed is:

1. A system comprising: a light source that generates a beam of light; a stage configured to hold a workpiece in a path of the beam of light; a detector that receives the beam of light reflected from the workpiece; a processor in electronic communication with the detector, wherein the processor is configured to: receive an image of a workpiece based on data from the detector; forward the image through a graph of a deep neural network model or directed acyclic graph of deep neural network models; record the output as an array; determine self-test input buffer (X) and expected output buffer (Y); predict an actual output (Y’) with inputs; and compare shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon; and an electronic data storage unit in electronic communication with the processor, wherein the deep neural network model or directed acyclic graph of deep neural network models is stored on the electronic data storage unit.

2. The system of claim 1, wherein the directed acyclic graph of deep neural network models is used, and wherein the output includes each node output and input.

3. The system of claim 1, wherein the directed acyclic graph of deep neural network models is used, and wherein the recording includes each node output and input in the array.

4. The system of claim 1, wherein the processor is further configured to communicate a failure message if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon.

5. The system of claim 1, wherein the processor is a GPU.

6. The system of claim 1, wherein the processor is a CPU.

7. The system of claim 1, wherein the workpiece is a semiconductor wafer.

8. A method comprising: receiving, at a processor, an image of a workpiece; forwarding, using the processor, the image through a graph of a deep neural network model or directed acyclic graph of deep neural network models; recording, using the processor, the output as an array; determining, using the processor, self-test input buffer (X) and expected output buffer (Y); predicting, using the processor, an actual output (Y’) with inputs; and comparing, using the processor, shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon.

9. The method of claim 8, wherein the directed acyclic graph of deep neural network models is used, and wherein the output includes each node output and input.

10. The method of claim 8, wherein the directed acyclic graph of deep neural network models is used, and wherein the recording includes each node output and input in the array.

11. The method of claim 8, further comprising communicating a failure message if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon.

12. The method of claim 8, wherein the processor is a GPU.

13. The method of claim 8, wherein the processor is a CPU.

14. The method of claim 8, wherein the workpiece is a semiconductor wafer.

15. A non-transitory computer- readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices: receive an image of a workpiece; forward the image through a graph of a deep neural network model or directed acyclic graph of deep neural network models; record the output as an array;determine self-test input buffer (X) and expected output buffer (Y); predict an actual output (Y’) with inputs; and compare shape and float values of the expected output buffer (Y) and actual output (Y’) using a tolerance epsilon.

16. The non-transitory computer-readable storage medium of claim 15, wherein the directed acyclic graph of deep neural network models is used, and wherein the output includes each node output and input.

17. The non-transitory computer-readable storage medium of claim 15, wherein the directed acyclic graph of deep neural network models is used, and wherein the recording includes each node output and input in the array.

18. The non-transitory computer-readable storage medium of claim 15, wherein the steps further include communicating a failure message if shape match and differences between the expected output buffer (Y) and actual output (Y’) are below the tolerance epsilon.

19. The non-transitory computer-readable storage medium of claim 15, wherein the workpiece is a semiconductor wafer.

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