Multilayer ferroelectric switching

Abstract

A device includes a substrate, first and second electrodes supported by the substrate, and a heterostructure supported by the substrate. The heterostructure includes first and second dielectric layers and a ferroelectric III-nitride alloy layer disposed between the first and second dielectric layers, the ferroelectric III-nitride alloy layer including a Group IIIB element. The ferroelectric III-nitride alloy layer is electrically spaced from the first and second electrodes by the first and second dielectric layers, respectively.

Description

MULTILAYER FERROELECTRIC SWITCHINGCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. provisional application entitled “Multilayer Ferroelectric Switching,” filed August 31 , 2023, and assigned Serial No. 63 / 535,779, the entire disclosure of which is hereby expressly incorporated by reference.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Contract No. HR0011 -22- 2-0024 awarded by the U.S. Department of Defense, Defense Advanced Research Projects Agency. The government has certain rights in the invention.BACKGROUND OF THE DISCLOSUREField of the Disclosure

[0003] The disclosure relates generally to Group Ill-nitride materials.Brief Description of Related Technology

[0004] The incorporation of Group IIIB elements, e.g., Scandium (Sc) and Yttrium (Y), can transform conventional wurtzite Ill-nitride semiconductors to be ferroelectric. These ultrawide bandgap ferroelectric nitride semiconductors promise to overcome the stability and endurance challenges of conventional oxide-based ferroelectrics, given the absence of mobile oxygen vacancies, as well as the negligible nitrogen vacancy related defect formation during epitaxial growth due to the very strong metal-nitride bond. Wurtzite ferroelectric nitrides, e.g., ScAIN and ScGaN, also exhibit linear displacement, high temperature stability, large remnant polarization, and tunable coercive field. However, past studies of wurtzite ferroelectric nitrides have been largely focused on single-layer ferroelectric nitrides.

[0005] Recent advances in molecular beam epitaxy have supported the fabrication of more complex structures. For instance, ferroelectric nitrides down to nanometer and atomic scale have been grown. Multilayer ferroelectric heterostructures with an atomically sharp interface and precisely controlled thickness, stoichiometry, and potentially domain size have alsobeen realized. However, polarization switching in such heterostructures has relied upon intermediate electrodes.SUMMARY OF THE DISCLOSURE

[0006] In accordance with one aspect of the disclosure, a device includes a substrate, first and second electrodes supported by the substrate, and a heterostructure supported by the substrate. The heterostructure includes first and second dielectric layers and a ferroelectric Ill-nitride alloy layer disposed between the first and second dielectric layers, the ferroelectric Ill-nitride alloy layer including a Group II IB element. The ferroelectric Ill-nitride alloy layer is electrically spaced from the first and second electrodes by the first and second dielectric layers, respectively.

[0007] In accordance with another aspect of the disclosure, a method of forming a heterostructure includes providing a template layer of the heterostructure, the template layer being supported by a substrate, growing a first dielectric layer of the heterostructure, the first dielectric layer being supported by the template layer, implementing a non-sputtered, epitaxial growth procedure to form a ferroelectric layer of the heterostructure, the ferroelectric layer being supported by the first dielectric layer, the ferroelectric layer including an alloy of a Ill-nitride material, the non-sputtered, epitaxial growth procedure being configured to incorporate a group 11 IB element into the alloy of the Ill-nitride material, growing a second dielectric layer of the heterostructure such that the ferroelectric layer is disposed between the first and second dielectric layers, and forming first and second electrodes supported by the substrate such that the ferroelectric layer is electrically spaced from the first and second electrodes by the first and second dielectric layers, respectively.

[0008] In connection with any one of the aforementioned aspects, the devices and / or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features. The first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers are piezoelectric. The first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers are lattice mismatched with the ferroelectric Ill-nitride alloy layer. The heterostructure has a collective dielectric constant between dielectric constants of a ferroelectric Ill-nitride alloy of the ferroelectric Ill-nitride alloy layer and a dielectric material of the first and second dielectric layers. The first and second dielectric layers are sufficiently thin to support leakage-assisted switching of the ferroelectric Ill-nitride alloy layer via a voltage applied across the first and second electrodes. The first dielectric layer, the second dielectric layer,or both of the first and second dielectric layers include a Ill-nitride material. The first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers have a wurtzite crystal structure. The first and second dielectric layers include AIN. The first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers have a thickness falling in a range from about 1 nm to about 200 nm. The first and second dielectric layers have a thickness less than about 300 nm. The first and second dielectric layers are electrically conducting at voltage ranges capable of polarization switching of the ferroelectric layer. The first and second dielectric layers are in contact with opposite sides of the ferroelectric Ill-nitride alloy layer. The heterostructure further includes a doped Ill-nitride semiconductor layer disposed between the first dielectric layer and the substrate, the doped Ill-nitride semiconductor layer being configured and positioned as a contact layer for the first electrode. Each of the first and second dielectric layers are non-ferroelectric. The first and second dielectric layers are grown at a lower temperature than the ferroelectric layer. The first and second dielectric layers are grown at a temperature falling in a range from about 100 C to about 600 C. The first and second dielectric layers and the ferroelectric layer are grown in N-rich growth conditions. The first and second dielectric layers and the ferroelectric layer are grown such that the first and second dielectric layers are in contact with opposite sides of the ferroelectric layer. The first dielectric layer and the second dielectric layer are grown such that both of the first and second dielectric layers have a thickness falling in a range from about 1 nm to about 200 nm. The template layer includes a doped Ill-nitride semiconductor material having a lattice mismatch with the first dielectric layer.BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0009] For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawing figures, in which like reference numerals identify like elements in the figures.

[0010] Figure 1 depicts (a) a schematic of a device having a tri-layer structure in accordance with one example, (b) RHEED patterns after the growth of each layer of the tri- layer structure, indicating wurtzite structure throughout growth, (c) an SEM image showing the surface of the layer stack after growth, (d) a 20-® scan showing the wurtzite characteristic peaks of the tri-layer structure, and (e) a 0002 plane rocking curve scan showing an overall FWHM of about 0.6°.

[0011] Figure 2 depicts graphical plots of ferroelectric properties of the tri-layer structure of Figure 1 , including (a) J-E loops and (b) corresponding P-E loops under different biasvoltages applied to a top electrode (the diameter of the electrode was 20 pm), (c) voltagedependent PUND measurements showing saturated switchable polarization, and (d) a C-V loop of the tri-layer structure indicating a butterfly shape hysteresis loop (the loss tangent as a function of measurement voltage is also shown).

[0012] Figure 3 depicts graphical plots of remnant polarization for the tri-layer structure of Figure 1 after (a) multiple switching cycles and (b) different retention times, in which a slight decreasing trend is observed after multiple poling possibly due to pinned domains at AIN / ScAIN interfaces.

[0013] Figure 4 depicts polarity-sensitive etching results of the tri-layer structure of Figure 1 , including (a) SEM images and (b) height profiles of the tri-layer structure subject to TMAH etching before and after removing the top AIN layer, in which switched regions were only etched by TMAH after top AIN removal, indicating that only the ScAIN layer was switched.

[0014] Figure 5 is a cross-sectional, schematic view of a device having a heterostructure with controlled ferroelectric switching in accordance with one example.

[0015] Figure 6 is a flow diagram of a method of forming a heterostructure with controlled ferroelectric switching in accordance with one example.

[0016] The embodiments of the disclosed devices and methods may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.DETAILED DESCRIPTION OF THE DISCLOSURE

[0017] Devices having heterostructures exhibiting controlled ferroelectric switching despite multilayer arrangements are described. In some cases, the heterostructures include a tri- layer arrangement such as AIN / ScAIN / AIN, in which ferroelectric behavior is exhibited only by the sandwiched or clamped ScAIN layer. Other ultrawide bandgap semiconductors may be realized in the heterostructures of the disclosed devices. Methods for fabricating such devices are also described.

[0018] The disclosed methods and devices may be directed to realizing a variety of artificial multilayer composite structures, such as ferroelectric / piezoelectric or ferroelectric / dielectric heterostructures, superlattices, compositionally graded layers, and other structures capable of exhibiting significantly enhanced, or tunable electromechanical, ferroelectric, dielectric, electro-optical, triboelectric, and electrocaloric properties, due to the strain / stress effect,interlayer coupling and interaction effect, etc. The resulting structures may also allow for the tuning of the acoustic resonance frequencies as a function of the period of the structure, as well as for the engineering of the effective electromechanical coupling of film bulk acoustic resonators (FBARs), which are useful in next-generation wireless communication devices and systems due to their high frequency, small size, and excellent performance. The disclosed devices and methods may alternatively or additionally be useful in connection with the stabilization of negative capacitance in ferroelectric / dielectric multilayer structures.

[0019] The controlled polarization switching of the disclosed devices may also be useful in realizing reconfigurable electronic devices, including transistors, filters, and resonators. For instance, the ferroelectric superlattices, or compositionally graded layers, of the disclosed devices may be used in multi-level memory cells and the realization of significantly enhanced linear and nonlinear optical properties. Alternatively, the disclosed devices and methods may be used to provide a multilayer ferroelectric structure that exhibits a tunable Curie temperature (Tc) and / or other pyroelectric devices.

[0020] Described herein are demonstrations of controlled ferroelectric switching in connection with an AIN / ScAIN / AIN tri-layer structure in accordance with one example. The demonstrations establish that the ScAIN layer can be controllably switched. For instance, a clamped or sandwiched Ill-nitride alloy layer may be exclusively switched (e.g., without relying on intermediate electrodes in contact with the Ill-nitride alloy layer and / or other switching of adjacent layers). An example tri-layer structure exhibited leakage-assist- switching behavior and showed large switchable polarization of about 150 pC / cm2with reasonable endurance and retention performance. Polarity-sensitive wet etching further confirmed the controlled switching in the clamped ScAIN layer. The demonstration of controlled ferroelectric switching of multilayer composite ferroelectric structures without the use of any intermediate electrodes simplifies the fabrication process and improves device performance, e.g., for high frequency resonators and filters, multi-level memory cells, and other devices. The controlled ferroelectric switching can also support the excitation of multiple harmonic modes without compromising the performance at different frequencies for high frequency resonators and filters

[0021] Although described in connection with examples of epitaxially grown ScxAli.xN layers, the disclosed methods and devices may be applied to a wide variety of Ill-nitride alloys. The disclosed methods and devices may thus include or involve the incorporation of scandium into other Ill-nitride wurtzite structures. For instance, the disclosed methods and devices may include or involve one or more epitaxially grown ScxAlyGai-x.yN layers, ScxGai-XN layers, or Scxlni.xN layers. The configuration, construction, fabrication, and othercharacteristics of the heterostructures may also vary from the examples described. For instance, the heterostructures may include any number of epitaxially grown layers of ferroelectric and non-ferroelectric nature. The disclosed methods and devices are not limited to Ill-nitride alloys including scandium. For instance, the Ill-nitride alloys may include additional or alternative group I IIB elements, such as yttrium (Y) and lanthanum (La).

[0022] Although described in connection with examples having a template layer composed of a Ill-nitride material, the disclosed methods and devices are not limited to heterostructures including Ill-nitride semiconductor layers as a template, base, or other component. For instance, the heterostructure may be grown on or otherwise supported by a metal layer, such as an aluminum layer. Additional or alternative other types of materials may also be used in the heterostructures, including, for instance, other semiconductor materials.

[0023] Although described in connection with examples having a tri-layer structure, the disclosed methods and devices are not limited to heterostructure having three layers. For instance, the heterostructure may include one or more additional layers (e.g., Ill-nitride dielectric layers).

[0024] Although the disclosed methods are described in connection with MBE growth procedures, additional or alternative non-sputtered epitaxial growth procedures may be used. For instance, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), and atomic layer epitaxy (ALE) growth procedures may be used. Still other procedures may be used, including, for instance, pulsed laser deposition procedures.

[0025] The examples described below were grown on n-GaN / sapphire templates. To begin with, 100 nm thick silicon-doped GaN was grown as a bottom contact layer, following which 50 nm AIN, 100 nm ScAIN and again 50 nm AIN were grown to form a tri-layer structure with a sandwiched ScAIN layer. The n-GaN layer was grown at a temperature of 650 °C (thermocouple reading) and a lll / V ratio of approximately 1 .2, with a silicon dopant cell at 1200 °C. Based on Hall measurements, the carrier concentration of the n-GaN layer is approximately 2x1019cm3. Due to the lattice mismatch between AIN and GaN as well as AIN and ScAIN, a relatively low growth temperature (e.g., 500 °C, thermal couple) was utilized for AIN growth to avoid significant crack formation. The nominal Sc content of the ScAIN layer was 0.25. The in-situ observation of reflection high energy electron diffraction (RHEED) patterns, X-ray diffraction (XRD) characterization and scanning electron microscopy (SEM). Circular 15-nm-Ni / 100-nm-AI pads with diameters of 3-50 p.m were placed via lithography and lift-off process as top electrodes. During the growth process, thefour corners of the substrate were covered by the wafer holder, where no epilayers were deposited. Direct electrical contact was then made to the bottom n-GaN layer by placing Ni / AI electrodes in those regions as bottom electrodes. HF and HCI were used to remove the electrodes after poling and Tetramethylammonium hydroxide (TMAH) was used for polaritysensitive wet etching.

[0026] Further details on the epitaxial growth conditions, procedures, and related parameters that may be used to form the ferroelectric films and heterostructures described herein are set forth in WO 2023 / 022768 ("Epitaxial Nitride Ferroelectronics"), International Application No. PCT / US23 / 13727 ("Epitaxial Nitride Ferroelectronic Devices" filed February 23, 2023), P. Wang, et al., "Fully epitaxial ferroelectric ScAIN grown by molecular beam epitaxy," Applied Physics Letters, vol. 118, p. 223504 (2021), D. Wang et al., "An Epitaxial Ferroelectric ScAIN / GaN Heterostructure Memory," Advanced Electronic Materials, p. 2200005 (2022), D. Wang, et al., "Fully epitaxial ferroelectric ScGaN grown on GaN by molecular beam epitaxy," Appl Phys Lett 119 (11), 111902 (2021), D. Wang et al., "Impact of dislocation density on the ferroelectric properties of ScAIN grown by molecular beam epitaxy," Appl Phys Lett 121 (4), 042108 (2022), and P. Wang et al., "Quaternary alloy ScAIGaN: A promising strategy to improve the quality of ScAIN," Appl Phys Lett 120 (1), 012104 (2022), the entire disclosures of which are hereby incorporated by reference.

[0027] An example tri-layer structure 100 is schematically shown in Figure 1 , part (a). The tri-layer structure 100 includes a heterostructure 102 supported by a substrate 104. In this example, the substrate 104 is composed of n-GaN. The heterostructure 102 includes lower and upper dielectric layers 106, 108, and a ferroelectric Ill-nitride alloy layer 110 disposed between the lower and upper dielectric layers 106. 108. In this example, the lower and upper dielectric layers 106, 108 are composed of AIN. The ferroelectric Ill-nitride alloy layer 110 is composed of, or otherwise includes, a Group II IB element. In this example, the ferroelectric Ill-nitride alloy layer 110 is composed of ScAIN. The tri-layer structure 100 may include additional layers, components, or elements. For instance, and as described further herein, the tri-layer structure 100 may include first and second electrodes from which the ferroelectric Ill-nitride alloy layer 110 is spaced by the lower and upper dielectric layers 106, 108. The compositions, thicknesses, and / or other characteristics of the layers and other elements of the tri-layer structure 100 may differ in other cases.

[0028] Figure 1 , part (b), displays wurtzite RHEED patterns after the growth of each layer. Streaky patterns were observed for the n-GaN contact layer, while segmented patterns were found for the AIN / ScAIN / AIN sandwiched structure, which is ascribed to N-rich growth conditions. The RHEED patterns deteriorated faster after the last AIN growth, possibly due tothe large in-plane lattice mismatch between ScAIN and AIN, which may be indicated by the shallow signature of cracks on the surface. Despite this, the surface looks reasonably smooth. The shallow cracks are actually filled with materials and resistant to electrical breakdown, as described below. Wurtzite characteristic peaks around 36.2° can be observed in the XRD 20-® scan. The relatively weak and broad peaks are due to the limited quality of the films compared with those grown at their optimal conditions. Nevertheless, the overall rocking curve scan FWHM is about 0.6° (Figure 1 , part (e)), which is better than sputter-deposited AIN / ScAIN composite piezoelectric and is useful for a variety of device applications. By carefully deconvoluting the peak near 36°, two peaks located at 35.98° and 36.26° can be found. The peak at 35.98° corresponds to AIN, while the peak at 36.26° corresponds to ScAIN. The full width at half maximum (FWHM) values obtained from the omega scans measured at two distinct peak positions are 0.58° and 1 .2°, respectively.

[0029] To confirm the ferroelectricity in the sandwiched ScAIN layer, J-V loops and P-V loops were performed under different bias voltages driven from the top electrode. Ni / AI electrodes were used for easy removal later on. Non-switching currents have been subtracted to better show the results using a built-in function of the tester. As shown in Figure 2, parts (a) and (b), clear displacement currents and square-shaped hysteresis loops were measured, with a saturated polarization of about 150 pC / cm2. The ferroelectric switching behavior was further confirmed by voltage dependent PUND measurements and C-V loops, as shown in Figure 2, parts (c) and (d). In the PUND measurements, although a clear saturation behavior is absent, a saturation trend can be found near 120 V. This deviation from saturation may be partially attributed to the enhanced leakage current under high electric fields. It has been theoretically predicted that for ferroelectric / dielectric bilayers, the measured polarization will be scaled due to incomplete compensation of polarization charge at the ferroelectric / dielectric interface. Here the extracted polarization values are quite close to that of ScAIN single layers, indicating that the AIN layer can be considered electrically conducting under conditions (e.g., applied voltages) that result in polarization switching. This kind of leakage-assist-switching behavior is also evidenced by the relatively large dielectric loss tangent (about 0.045 at 1 MHz) here compared with pure AIN and ScAIN. The overall dielectric constant is estimated to be about 15, which is lower than that of ScAIN with a Sc content of about 0.25 but larger than AIN, showing the tunability of dielectric constants using ferroelectric / dielectric multilayers. Shown in Figure 2, part (d), the overall loss tangent values are below 0.04, ensuring the accuracy of the C-V measurement results.

[0030] For possible reconfigurable acoustic devices and energy storage applications, the polarization direction of the multilayer structure may be switched multiple times. It is additionally or alternatively useful for the polarization state of the entire structure to be retainable to ensure multi-mode operation. Multiple switching and back-switching sequences were accordingly conducted on the example structures, and the measured switchable polarization is shown in Figure 3, part (a), indicating that the polarization order of the structure is conservable even after hundreds of switching cycles. The stability of the polarization state after poling is further shown in Figure 3, part (b). The remnant polarization remains almost unchanged after more than 104s, exhibiting good temporal stability. Significant retention loss has usually been observed in oxide-based ferroelectric / dielectric bilayers where incomplete polarization charge compensation is attributed. With the example structures, the stable remnant polarization with values similar to single layers indicates that the polarization charge at the interface is highly compensated, possibly by vacancies or crystal defects near the interface. This may cause loss in energy storage applications, yet the long retention nature is useful for, e.g., non-volatile reconfigurable and multi-mode devices.

[0031] AIN is known to also present ferroelectric-like behavior. However, for applications in acoustic devices, it is useful that polarity switching be achieved in a controlled way, e.g., only in a desired layer (exclusive switching). To elucidate the polarization state of each layer after switching, an example tri-layer structure was poled and subjected to TMAH etching to reveal the polarity. As shown in Figure 4, part (a), after TMAH treatment, the top surface became rough for both pristine and poled regions, which could be due to the limited quality of the second AIN layer. The switched region, though showing a different contrast, is of the same height with the pristine area. In contrast, after removing the top AIN layer using RIE, the switched region (ScAIN) underneath the electrode was easily etched by TMAH, leading to a height difference of 80-100 nm which is in good agreement with the thickness of the ScAIN layer, as shown in Figure 4, part (b). The etching rates of AIN and ScAIN were carefully calibrated to ensure a complete removal of the top AIN layer. Those results imply that only the ScAIN layer is switched, which is useful for, e.g., tuning the electro-mechanical coupling in ScAIN / AIN multilayer structures.

[0032] In Figure 4, areas outside the electrode region, which were not subjected to electrical poling, are labelled as pristine. The electrodes were removed by HF and the top AIN layer was removed via RIE. "Pristine" refers to the region that is not covered by the electrode and, therefore, was not subjected to electrical poling. In the "switched" region, the polarity has been switched to a different state from its initial state (i.e., from M-polar to N-polar). In the "back-switched" region, the polarity was first switched to a different state and then switched back using an opposite voltage pulse (M-polar to N-polar then back to M- polar).

[0033] As described above, controlled ferroelectric switching in an AIN / ScAIN / AIN tri-layer structure grown by molecular beam epitaxy was achieved. The tri-layer structure exhibited leakage-assist-switching behavior and showed large switchable polarization of about 150 pC / cm2with endurance greater than 103cycles and retention greater than 104s. Polaritysensitive wet etching further confirmed that polarity switching only occurred in the ScAIN layer. Such ability to control the polarity switching in ScAIN / AIN multilayer structures is useful in a wide variety of electronic, piezoelectronic, and other devices.

[0034] Figure 5 depicts a device 500 having controlled ferroelectric switched in accordance with one example. The device 500 includes a substrate 502, upper and lower electrodes 504, 506 supported by the substrate 502, and a heterostructure 508 supported by the substrate 502. The heterostructure 508 includes upper and lower dielectric layers 510, 512 and a ferroelectric Ill-nitride alloy layer 514 disposed between the upper and lower dielectric layers 510, 512. As shown in Figure 5, the ferroelectric Ill-nitride alloy layer 514 is electrically spaced from the upper and lower electrodes 504, 506 by the upper and lower dielectric layers 510, 512, respectively.

[0035] In the example of Figure 5, the heterostructure 508 further includes a doped Ill- nitride semiconductor layer 516, such as n-GaN, disposed between the lower dielectric layer 512 and the substrate 502. The doped Ill-nitride semiconductor layer 516 may be configured as a template layer. In this example, the doped Ill-nitride semiconductor layer 516 is configured and positioned as a contact layer for (or of) the lower electrode 506.

[0036] In the example of Figure 5, each of the upper and lower electrodes 504, 506 includes a contact pad. Each contact pad may include one or more conductive layers (e.g., metal layers). The construction, composition, shape, configuration, and / or other aspects of the upper and lower electrodes 504. 506 may vary from the example shown. For instance, the upper and lower electrodes 504, 506 may include additional or alternative layers or other elements, including, for instance, a doped semiconductor layer.

[0037] In the example of Figure 5, the upper and lower dielectric layers 510, 512 are in contact with opposite sides of the ferroelectric Ill-nitride alloy layer 514. In other cases, one or more intermediary layers (e.g., Ill-nitride layers) may be included.

[0038] As described herein, the ferroelectric Ill-nitride alloy layer 514 includes a Group IIIB element, such as Sc. For example, the ferroelectric Ill-nitride alloy layer 514 may be composed of, or otherwise include, ScAIN.

[0039] The upper dielectric layer 510 may be composed of, or otherwise include, a Ill- nitride material. The lower dielectric layer 512 may also be composed of, or include, a Ill- nitride material. In some cases, the upper and lower dielectric layers 510, 512 are composed of the same material. For example, the upper and lower dielectric layers 510, 512 may be composed of, or otherwise include, AIN. Other materials having a wurtzite crystal structure may be used. In some cases, the upper dielectric layer 510 and / or the lower dielectric layer 512 are piezoelectric. In some cases, the upper dielectric layer 510 and / or the lower dielectric layer 512 are lattice mismatched with the ferroelectric Ill-nitride alloy layer 514. The lower dielectric layer 512 may also be lattice mismatched with an underlying template layer (e.g., a doped Ill-nitride semiconductor layer). One or both of the upper and lower dielectric layers 510, 512 may be non-ferroelectric.

[0040] The sandwiching of the ferroelectric Ill-nitride alloy layer 514 between the upper and lower dielectric layers 510, 512 may establish a number of properties of the device. For example, the heterostructure 508 may have a collective dielectric constant between the dielectric constants of a ferroelectric Ill-nitride alloy of the ferroelectric Ill-nitride alloy layer and a dielectric material of the first and second dielectric layers 510, 512.

[0041] The upper and lower dielectric layers 510, 512 may be electrically conducting at voltage ranges capable of polarization switching of the ferroelectric layer 514. In some cases, the upper and lower dielectric layers 510, 512 are sufficiently thin to support leakage- assisted switching of the ferroelectric Ill-nitride alloy layer 514 via a voltage applied across the upper and lower electrodes 504, 506. In some cases, the upper dielectric layer 510 and / or the lower dielectric layer 512 have a thickness falling in a range from about 1 nm to about 200 nm. Alternatively, thicknesses up to about 300 nm may be used and still suitably support leakage assisted switching.

[0042] The device 500 may include additional, fewer, or alternative layers or other elements. For example, the device 500 may include one or more additional layers directed to implementing resonator or filter functionality.

[0043] Figure 6 depicts a method 600 of fabricating a heterostructure having a wurtzite structure of an alloy of a Ill-nitride material with scandium incorporated therein in accordance with one example. As described herein, the method 600 is configured such that the wurtzite structure exhibits ferroelectric behavior. The heterostructure may form a device, or a part ofa device, in which one or more layers or regions of the device exhibit the ferroelectric behavior. The method 600 may be used to fabricate the examples of ScxAli.xN films and layers described herein.

[0044] The method 600 may begin with an act 602 in which a substrate is prepared and / or otherwise provided. In some cases, the act 602 includes providing a sapphire substrate in an act 604. Alternative or additional materials may be used, including, for instance, silicon, bulk GaN, bulk AIN, or other semiconductor material. Still other materials may be used, including, for instance, silicon carbide. The substrate may be cleaned in an act 606. In some cases, a native or other oxide layer may be removed from a substrate surface in an act 608. In the example of Figure 6 (e.g., sapphire examples), the act 602 may include implementing a nitridation procedure in an act 609. Additional or alternative processing may be implemented in other cases, including, for instance, doping or deposition procedures. The substrate thus may or may not have a uniform composition. The substrate may be a uniform or composite structure.

[0045] In an act 610, one or more growth templates, buffer, or other layers are formed. The layer(s) are thus formed on, or otherwise supported by, the substrate. The layer(s) may or may not be in contact with the substrate. In some cases, the layer(s) are composed of, or otherwise include, a semiconductor material. For instance, the act 610 may include an act 612 in which a semiconductor layer is formed. For example, a Ill-nitride layer, such as a GaN layer, may be grown or otherwise formed on the substrate. Other compound or other semiconductor materials may be used, including, for instance, AIGaN. The semiconductor layer(s) may be N-polar or metal-polar. The semiconductor layer(s) may form a part of the heterostructure underlying the ferroelectric layer to be grown. The semiconductor layer may be undoped or doped (e.g., Si-doped). The act 612 may thus be implemented before (e.g., in preparation for) implementing an epitaxial growth procedure in which a wurtzite structure is formed. The wurtzite structure may thus be formed on the semiconductor layer. The semiconductor layer may be configured or used as a growth template for the wurtzite structure and / or other elements of the heterostructure. In some cases, the act 612 may include growing the semiconductor layer in an epitaxial growth chamber in which the epitaxial growth procedure for the wurtzite structure is implemented. As a result, the substrate may remain within, e.g., is not removed from, the epitaxial growth chamber between forming the semiconductor layer and implementing the epitaxial growth procedure for growing the wurtzite structure.

[0046] Alternatively or additionally, the act 610 includes an act 614 in which one or more metal or other conductive layers are deposited and patterned. For example, an aluminumlayer may be deposited on a silicon substrate in preparation for the epitaxial growth of the wurtzite structure.

[0047] The method 600 may include an act 616 in which one or more electrodes or contacts or other layers are formed. The layer(s) may form a part of the heterostructure underlying the ferroelectric layer to be grown. Examples of the underlying layer(s) include a lower or bottom electrode or contact of the heterostructure or a channel layer of the heterostructure. The nature of the underlying layer(s) may vary with the device being fabricated. The Si-doped layer may or may not be grown on top of the template or buffer layer formed in the act 610. In the example of Figure 6, the act 616 includes growing a silicon-doped GaN layer in an act 618. The Si-doped GaN layer may be N-polar or metalpolar. Other materials may be used. For instance, the underlying layer(s) may be composed of, or otherwise include, AIGaN, InAIN, InGaN, or InAIGaN. Still other materials may be used. For instance, a channel layer may be composed of, or otherwise include, other types of semiconductors, e.g., GasOs, diamond, Si, SiGe, GaAs, InGaAs, or InP, in addition to one or more of the above-referenced Ill-nitride alloys. The Si-doped GaN layer may act as an electrode layer of a device, such as a memory device. Additional or alternative conductive structures, such as a gate structure, may be deposited and / or patterned in an act 620.

[0048] The method 600 includes an act 621 in which a lower dielectric layer of the heterostructure is grown or form. As described herein, the upper dielectric layer may be composed of, or otherwise include, a Ill-nitride material, such as AIN. Also as described herein, the first dielectric layer is supported by the template layer (e.g., the n-doped GaN layer).

[0049] The temperature at which the lower dielectric layer is grown may be lower than typical for the Ill-nitride material. The low growth temperature may be useful for addressing lattice mismatch between the lower dielectric layer and the underlying template layer. For instance, the lower dielectric layer may be grown at a lower temperature than the growth temperature of a ferroelectric layer of the heterostructure. In some cases, the growth temperature falls in a range from about 100 C to about 600 C. The lower dielectric layer may additionally or alternatively be grown in N-rich conditions.

[0050] The act 621 may be implemented in the same epitaxial growth chamber used to grow other layers of the heterostructure. As a result, the substrate (and heterostructure) may not be removed from the epitaxial growth chamber between implementing the growth- related acts of the method.

[0051] In an act 622, a non-sputtered epitaxial growth procedure is implemented at a growth temperature to form a wurtzite structure supported by the substrate. As described herein, the wurtzite structure is composed of, or otherwise includes, an alloy of a Ill-nitride material. For instance, the Ill-nitride material may be AIN. Additional or alternative Ill-nitride materials may be used, including, for instance, gallium nitride (GaN), indium nitride (InN), and their alloys. As also described herein, the epitaxial growth procedure is configured to incorporate scandium and / or another group 11 IB element into the alloy of the Ill-nitride material. The alloy may thus be ScxAli.xN, for example. In some cases, the act 622 includes an act 624 in which an MBE procedure is implemented. In other cases, an MOCVD or other non-sputtered epitaxial growth procedure is implemented in an act 626.

[0052] The act 622 may constitute a continuation, or part of a sequence, of growth procedures. The growth procedures may be implemented in a common, or same, growth chamber. The act 622 may thus include an act 628 in which epitaxial growth is continued in the same chamber in which one or more other layers of the heterostructure were grown. For instance, one or more of the growth template and the underlying semiconductor layer(s) formed in the acts 610 and 616 may be formed in the same chamber as the ferroelectric layer. Sequential layers of the heterostructure may thus be grown without exposure to the ambient. The quality of the interface between the layers may accordingly be improved.

[0053] The growth temperature may be at a level such that the wurtzite structure exhibits a breakdown field strength greater than a ferroelectric coercive field strength of the wurtzite structure. Ferroelectric switching and other behavior may thus be achieved.

[0054] Growth of the ScxAli.xN layer at the conventional AIN growth temperature (and other temperatures above the upper bound) unexpectedly results in the formation of dislocations and / or other leakage paths in the ScxAli.xN layer. With the leakage paths, the ScxAli.xN layer has a breakdown field strength level too low (e.g., below the ferroelectric coercive field strength level). The layer accordingly does not exhibit ferroelectric behavior.

[0055] In some cases, the growth temperature may be about 650 degrees Celsius or less or about 750 degrees Celsius or less. The growth temperature may correspond with the temperature measured at a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may be slightly different. The growth temperature is accordingly approximated via the temperature measurement at the thermocouple.

[0056] The upper bound of the growth temperature range may vary in accordance with the alloy and / or the epitaxial growth technique. For instance, in other cases, the upper bound on the growth temperature may be higher, such as about 680 degrees Celsius, or about 690degrees Celsius. In still other cases, the upper bound may be lower, including, for instance, about 600 degrees Celsius or about 620 degrees Celsius.

[0057] At each level within the above-described ranges of suitable growth temperatures, the resulting wurtzite structure is monocrystalline. The resulting wurtzite structure is monocrystalline to a degree not realizable via, for instance, sputtering-based procedures for forming ScxAli.xN layers. Such procedures are only capable of producing structures with x- ray diffraction rocking curve line widths on the order of a few degrees at best. In contrast, the structures grown by the disclosed methods exhibit x-ray diffraction rocking curve line widths on the order of a few hundred arc-seconds or less, well over an order of magnitude less. In this manner, leakage current paths are minimized or otherwise sufficiently reduced so that the resulting wurtzite structure has a suitably high breakdown field strength level, e.g., sufficiently greater than the ferroelectric coercive field strength.

[0058] The above-noted differences in crystal quality evidenced via x-ray diffraction rocking curve line widths may also be used to distinguish between monocrystalline and polycrystalline structures. As used herein, the term "polycrystalline" refers to structures having significant in-plane rotation and x-ray diffraction rocking curve line widths on the order of a few degrees or higher. As used herein, the term "monocrystalline" refers to structures having no in-plane rotation and x-ray diffraction rocking curve line widths at least one order of magnitude lower than the order of a few degrees.

[0059] Comparing the wurtzite structures of the layers grown by MBE or other nonsputtered techniques (e.g., MOCVD or HVPE) with sputtering deposition techniques, the microstructure of the former techniques is more uniform with highly ordered stacking sequence of atoms. In sputter deposited layers, domains with cubic phase or domains with in-plane mis-orientation are readily observed. The existence of these mis-aligned domains suppresses the complete switching of polarization, and further results in the fast loss of polarization during fatigue testing. Regarding phase purity, the highly crystallographic orientation of layers grown by MBE or other non-sputtered techniques exhibits more repeatable ferroelectric switching, which is useful in a number of device applications.

[0060] The wurtzite structure of the ferroelectric layer may be nitrogen-polar (N-polar) or metal-polar. The polarity of an underlying layer formed in the act 610 and / or the act 616 may be used to establish the polarity of the ferroelectric layer formed in the act 622. The polarity of the underlying layer may, in turn, be established by a characteristic of the substrate. The polarity may continue across the interface between the underlying layer andthe ferroelectric layer. Either N- or metal-polarity may thus persist as the composition changes from the underlying layer to the ferroelectric layer.

[0061] The method 600 includes an act 630 in which an upper dielectric layer of the heterostructure is grown or formed. As described herein, the upper dielectric layer may be composed of, or otherwise include, a Ill-nitride material, such as AIN.

[0062] The temperature at which the upper dielectric layer is grown may be lower than typical for the Ill-nitride material. The low growth temperature may be useful for addressing lattice mismatch between the upper dielectric layer and the underlying ferroelectric layer. For instance, the upper dielectric layer may be grown at a lower temperature than the growth temperature of the ferroelectric layer. In some cases, the growth temperature falls in a range from about 100 C to about 600 C. The upper dielectric layer may additionally or alternatively be grown in N-rich conditions.

[0063] The act 630 may be implemented in the same epitaxial growth chamber used to grow the other layers of the heterostructure. As a result, the substrate (and heterostructure) may not be removed from the epitaxial growth chamber between implementing the growth- related acts of the method.

[0064] The above-described wurtzite layers may then be annealed in an act 632. The annealing may be implemented at a temperature greater than the growth temperature. In some cases, the annealing temperature falls in a range from about 700 Celsius to about 1500 degrees Celsius. Examples of films prepared with such annealing exhibited stable polarization switching with further reduced leakage current relative to non-annealed films. Film or device uniformity was also improved via the annealing, thereby further improving the polarization switching behavior of the ferroelectric Sc-lll-N alloys. The underlying mechanism for the improved performance and uniformity with annealing is attributed to the reduced threading dislocation density and defect density, which usually act as electric leakage paths. Such usefulness of the post-growth annealing is realized despite past concerns that high processing temperatures can lead to a loss of ferroelectricity.

[0065] Such post-growth high-temperature annealing of ScxAli.xN may be performed in-situ in the same growth chamber (e.g., the same MBE chamber) in an act 634. In other cases, the annealing is performed ex-situ in a chamber directed to annealing procedures.

[0066] The annealing process may be implemented under high vacuum in an act 636 (e.g., in-situ in the growth chamber). In other cases, the annealing may be implemented either with nitrogen plasma radiation or under nitrogen gas flow in an act 638.

[0067] The above-described annealing procedure may be implemented in connection with films grown under any of the above-described growth conditions. For instance, the annealing procedure may be implemented after growth under slightly to moderately N-rich conditions at a growth temperature at or below about 650 degrees Celsius, or at or below about 750 degrees Celsius. The annealing procedure may also be implemented after growth under unbalanced flux ratios (e.g., N-rich or extreme N-rich conditions) at growth temperatures above about 650 degrees Celsius or above about 750 degrees Celsius.

[0068] The method 600 includes an act 640 in which one or more layers are formed after growth of the upper dielectric layer. One or more layers may be configured as an upper electrode. In the example of Figure 6, the act 640 includes an act 642 in which one or more metal or other conductive layers or structures are formed. The layers or structures may be deposited or otherwise formed. In some cases, the conductive structure is configured as an upper or top pad.

[0069] As described herein, the upper and lower contacts are formed such that the ferroelectric layer is electrically spaced from the upper and lower electrodes by the upper and lower dielectric layers, respectively. For instance, the growth-related acts of the method 600 may be implemented such that the upper and lower dielectric layers are in contact with the ferroelectric layer and / or otherwise disposed between the ferroelectric layer and the upper and lower electrodes, respectively.

[0070] The method 600 may include one or more additional acts. For example, one or more acts may be directed to forming other structures or regions of the device and / or heterostructure. For instance, one or more Ill-nitride (e.g., GaN or AIGaN) or other semiconductor layers may be epitaxially grown after the growth of the upper dielectric layer.

[0071] The order of the acts of the method 600 may differ from the example shown in Figure 6. For example, the acts 616, 618, and 620 in which contacts and / or other conductive structures formed may be implemented after the growth of the ferroelectric layer.

[0072] A number of different types of devices may be fabricated by the method 600 of Figure 6. For example, a wide variety of electronic, micromechanical, piezoelectronic, ferroelectric, and optical devices may be fabricated.

[0073] Described above are examples of devices in which controlled polarization switching in artificial multilayer composite structures is achieved. The multilayer composite structures may be configured to provide ferroelectric / piezoelectric, ferroelectric / dielectric, or other heterostructures. The multilayer nature of the heterostructures provides an additional dimension for engineering device properties and improving device performance andfunctionality. The examples described above exhibited controlled ferroelectric switching in a AIN / ScAIN / AIN tri-layer structure grown by molecular beam epitaxy. The example tri-layer structures exhibited large switchable polarization with reasonable endurance and retention performance. Polarity-sensitive wet etching further confirmed the controlled switching in the clamped ScAIN layer. The ability to control the polarity switching in the ScAIN / AIN multilayers may be useful in connection with a wide variety of electronic, micromechanical, piezoelectronic, ferroelectric, and optical devices.

[0074] The term "about" is used herein in a manner to include deviations from a specified value that would be understood by one of ordinary skill in the art to effectively be the same as the specified value due to, for instance, the absence of appreciable, detectable, or otherwise effective difference in operation, outcome, characteristic, or other aspect of the disclosed methods and devices.

[0075] The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not to be limiting of the disclosure. Changes, additions and / or deletions may be made to the examples without departing from the spirit and scope of the disclosure.

[0076] The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

What is Claimed is:

1. A device comprising: a substrate; first and second electrodes supported by the substrate; and a heterostructure supported by the substrate, the heterostructure comprising: first and second dielectric layers; and a ferroelectric Ill-nitride alloy layer disposed between the first and second dielectric layers, the ferroelectric Ill-nitride alloy layer comprising a Group 111 B element; wherein the ferroelectric Ill-nitride alloy layer is electrically spaced from the first and second electrodes by the first and second dielectric layers, respectively.

2. The device of claim 1 , wherein the first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers are piezoelectric.

3. The device of claim 1 , wherein the first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers are lattice mismatched with the ferroelectric Ill- nitride alloy layer.

4. The device of claim 1 , wherein the heterostructure has a collective dielectric constant between dielectric constants of a ferroelectric Ill-nitride alloy of the ferroelectric Ill-nitride alloy layer and a dielectric material of the first and second dielectric layers.

5. The device of claim 1 , wherein the first and second dielectric layers are sufficiently thin to support leakage-assisted switching of the ferroelectric Ill-nitride alloy layer via a voltage applied across the first and second electrodes.

6. The device of claim 1 , wherein the first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers comprise a Ill-nitride material.

7. The device of claim 1 , wherein the first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers have a wurtzite crystal structure.

8. The device of claim 1 , wherein the first and second dielectric layers comprise AIN.

9. The device of claim 1 , wherein the first dielectric layer, the second dielectric layer, or both of the first and second dielectric layers have a thickness falling in a range from about 1 nm to about 200 nm.

10. The device of claim 1 , wherein the first and second dielectric layers have a thickness less than about 300 nm.

11. The device of claim 1 , wherein the first and second dielectric layers are electrically conducting at voltage ranges capable of polarization switching of the ferroelectric layer.

12. The device of claim 1 , wherein the first and second dielectric layers are in contact with opposite sides of the ferroelectric Ill-nitride alloy layer.

13. The device of claim 1 , wherein the heterostructure further comprises a doped Ill- nitride semiconductor layer disposed between the first dielectric layer and the substrate, the doped Ill-nitride semiconductor layer being configured and positioned as a contact layer for the first electrode.

14. The device of claim 1 , wherein each of the first and second dielectric layers are nonferroelectric.

15. A method of forming a heterostructure, the method comprising: providing a template layer of the heterostructure, the template layer being supported by a substrate; growing a first dielectric layer of the heterostructure, the first dielectric layer being supported by the template layer; implementing a non-sputtered, epitaxial growth procedure to form a ferroelectric layer of the heterostructure, the ferroelectric layer being supported by the first dielectric layer, the ferroelectric layer comprising an alloy of a Ill-nitride material, the non-sputtered, epitaxial growth procedure being configured to incorporate a group 11 IB element into the alloy of the Ill-nitride material; growing a second dielectric layer of the heterostructure such that the ferroelectric layer is disposed between the first and second dielectric layers; and forming first and second electrodes supported by the substrate such that the ferroelectric layer is electrically spaced from the first and second electrodes by the first and second dielectric layers, respectively.

16. The method of claim 15, wherein the first and second dielectric layers are grown at a lower temperature than the ferroelectric layer.

17. The method of claim 15, wherein the first and second dielectric layers are grown at a temperature falling in a range from about 100 C to about 600 C.

18. The method of claim 15, wherein the first and second dielectric layers and the ferroelectric layer are grown in N-rich growth conditions.

19. The method of claim 15, wherein the first and second dielectric layers and the ferroelectric layer are grown such that the first and second dielectric layers are in contact with opposite sides of the ferroelectric layer.

20. The method of claim 15, wherein the first dielectric layer and the second dielectric layer are grown such that both of the first and second dielectric layers have a thickness falling in a range from about 1 nm to about 200 nm.

21. The method of claim 15, wherein the template layer comprises a doped Ill-nitride semiconductor material having a lattice mismatch with the first dielectric layer.

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