Conflict-free current distribution in a power management circuit

Abstract

Conflict-free current distribution in a power management circuit is provided herein. The power management circuit includes multiple power management integrated circuits (PMICs) and a distributed PMIC(s) interconnected via a shared current distribution line. In an embodiment, the distributed PMIC(s) is a lightweight version of the PMICs with smaller footprints. As such, the distributed PMIC(s) operates by drawing a low-frequency current from one of the PMICs over a shared current distribution line. To ensure that the distributed PMIC(s) can draw the low-frequency current over the shared current distribution line at any given time, each of the PMICs is configured herein to determine whether the shared current distribution line is idle before distributing the low-frequency current over the shared current distribution line. As such, the power management circuit can provide conflict-free current distribution over the shared current distribution line to help reduce the routing complexity and footprint.

Description

CONFLICT-FREE CURRENT DISTRIBUTION IN A POWER MANAGEMENT CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 579,127, filed on August 28, 2023, and U.S. provisional patent application serial number 63 / 588,773, filed on October 9, 2023, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to distributing current over a shared current distribution line in a power management circuit.Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience requires uninterrupted connectivity, increased bandwidth, and higher data throughput, which can be achieved using such multi-transmission technologies as multiple-input multiple-output (MIMO), beamforming. In this regard, a wireless device needs to employ multiple antennas and power amplifiers to enable such multi-transmission technologies. Accordingly, multiple power management circuits are often needed to supply voltage and / or current to the power amplifiers.

[0005] Oftentimes, the antennas and the power amplifiers are strategically placed farther apart from one another (e.g., at top edge and bottom edge of the wireless device) to help provide uninterrupted connectivity. As such, the powermanagement circuits may have to provide the voltage and / or current to respective power amplifiers over longer routing distances. As more circuits and components are added and the footprint of the wireless device continues to shrink, it becomes increasingly challenging to route the voltage and / or current over multiple distribution lines. As such, it is desirable to reduce the number of distribution lines without compromising the performance of the wireless device.

[0006] Embodiments of the disclosure relate to conflict-free current distribution in a power management circuit. Herein, the power management circuit includes multiple power management integrated circuits (PMICs) and a distributed PMIC(s) interconnected via a shared current distribution line. In an embodiment, the distributed PMIC(s) is a lightweight version of the PMICs with smaller footprints. As such, the distributed PMIC(s) operates by drawing a low- frequency current from one of the PMICs over a shared current distribution line. To ensure that the distributed PMIC(s) can draw the low-frequency current over the shared current distribution line at any given time, each of the PMICs is configured herein to determine whether the shared current distribution line is idle before distributing the low-frequency current over the shared current distribution line. As such, the power management circuit can provide conflict-free current distribution over the shared current distribution line to help reduce the routing complexity and footprint.

[0007] In one aspect, a power management circuit is provided. The power management circuit includes one or more distributed PMICs. Each of the one or more distributed PMICs is coupled to a shared current distribution line. Each of the one or more distributed PMICs is configured to receive a selected one of multiple low-frequency currents via the shared current distribution line. Each of the one or more distributed PMICs is also configured to generate a respective one of multiple distributed voltages based on the selected one of the multiple low-frequency currents. The power management circuit also includes multiple PMICs. Each of the multiple PMICs is coupled to the shared current distributionline. Each of the multiple PMICs is configured to generate a respective one of the multiple low-frequency currents. Each of the multiple PMICs is also configured to determine whether the shared current distribution line is idle. Each of the multiple PMICs is also configured to provide the respective one of the multiple low-frequency currents to any one of the one or more distributed PMICs over the shared current distribution line in response to determining that the shared current distribution line is idle.

[0008] In another aspect, a wireless device is provided. The wireless device includes a power management circuit. The power management circuit includes one or more distributed power management integrated circuits, PMICs. Each of the one or more distributed PMICs is coupled to a shared current distribution line. Each of the one or more distributed PMICs is configured to receive a selected one of multiple low-frequency currents via the shared current distribution line. Each of the one or more distributed PMICs is also configured to generate a respective one of multiple distributed voltages based on the selected one of the multiple low-frequency currents. The power management circuit also includes multiple PMICs. Each of the multiple PMICs is coupled to the shared current distribution line. Each of the multiple PMICs is configured to generate a respective one of the multiple low-frequency currents. Each of the multiple PMICs is also configured to determine whether the shared current distribution line is idle. Each of the multiple PMICs is also configured to provide the respective one of the multiple low-frequency currents to any one of the one or more distributed PMICs over the shared current distribution line in response to determining that the shared current distribution line is idle.

[0009] In another aspect, a method for conflict-free current distribution in a wireless device is provided. The method includes receiving a selected one of multiple low-frequency currents via a shared current distribution line. The method also includes generating a respective one of one or more distributed voltages based on the selected one of the multiple low-frequency currents. The method also includes determining whether the shared current distribution line is idle. The method also includes providing the selected one of the multiple low-frequency currents over the shared current distribution line in response to determining that the shared current distribution line is idle.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 is a schematic diagram of an exemplary wireless device wherein a power management circuit is configured according to embodiments of the present disclosure to enable conflict-free current distribution over a shared current distribution line;

[0013] Figure 2 is a schematic diagram of an exemplary power management integrated circuit (PMIC) in the power management circuit of Figure 1 ;

[0014] Figure 3 is a schematic diagram of an exemplary distributed PMIC in the power management circuit of Figure 1 ;

[0015] Figure 4 is a schematic diagram of an exemplary sensing circuit that can be provided in the PMIC of Figure 2 to determine whether the shared current distribution line is idle;

[0016] Figure 5 is a schematic diagram of an exemplary wireless device configured according to another embodiment of the present disclosure;

[0017] Figure 6 is a schematic diagram of an exemplary communication device wherein the power management circuit of Figure 1 can be provided; and

[0018] Figure 7 is a flowchart of an exemplary process for providing conflict- free current distribution in the wireless device of Figure 1 .Detailed Description

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an elementis referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0022] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Embodiments of the disclosure relate to conflict-free current distribution in a power management circuit. Herein, the power management circuit includes multiple power management integrated circuits (PMICs) and a distributed PMIC(s) interconnected via a shared current distribution line. In an embodiment, the distributed PMIC(s) is a lightweight version of the PMICs with smaller footprints. As such, the distributed PMIC(s) operates by drawing a low- frequency current from one of the PMICs over a shared current distribution line.To ensure that the distributed PMIC(s) can draw the low-frequency current over the shared current distribution line at any given time, each of the PMICs is configured herein to determine whether the shared current distribution line is idle before distributing the low-frequency current over the shared current distribution line. As such, the power management circuit can provide conflict-free current distribution over the shared current distribution line to help reduce the routing complexity and footprint.

[0026] Figure 1 is a schematic diagram of an exemplary wireless device 10 wherein a power management circuit 12 is configured according to embodiments of the present disclosure to enable conflict-free distribution of any one of multiple low-frequency currents IDC-1 , IDC2 over a shared current distribution line 14. The wireless device 10 includes at least two first antennas 16, 18 and at least two second antennas 20, 22. In an embodiment, the first antennas 16, 18 are provided along a top edge 24 of the wireless device 10, and the second antennas 20, 22 are provided along a bottom edge 26 of the wireless device 10. Accordingly, the wireless device 10 can support multiple simultaneous transmissions from any two or more of the first antennas 16, 18 and the second antennas 20, 22.

[0027] In an embodiment, the wireless device 10 also includes a pair of power amplifier circuits 28, 30 and a pair of distributed power amplifier circuits 32, 34. The power amplifier circuits 28, 30 are coupled respectively to the first antenna 16 and the second antenna 20, and the distributed power amplifier circuits 32, 34 are coupled respectively to the first antenna 18 and the second antenna 22. Herein, each of the power amplifier circuits 28, 30 and the distributed power amplifier circuits 32, 34 is configured to amplify a signal for transmission via a respective one of the first antennas 16, 18 and the second antennas 20, 22.

[0028] The power management circuit 12 includes at least two PMICs 36, 38 and at least two distributed PMICs 40, 42 (each denoted as “DPMIC”). The PMICs 36, 38 are configured to generate and provide at least two voltages Vcc-1, Vcc-2 to the power amplifier circuits 28, 30, respectively. The distributed PMICs40, 42 are configured to generate and provide at least two distributed voltages DVcc-i, DVCC-2 to the distributed power amplifier circuits 32, 34, respectively.

[0029] Figure 2 is a schematic diagram providing an exemplary illustration of any of the PMICs 36, 38 in the power management circuit 12 in Figure 1 . Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0030] Herein, each of the PMICs 36, 38 includes a multi-level charge pump (MCP) 44 coupled in series to a power inductor Lp. The MCP 44, which can be a direct-current-direct-current (DC-DC) converter, is configured to generate a low- frequency voltage VDC based on a battery voltage VBAT. In a non-limiting example, the MCP 44 can operate in a buck mode to generate the low-frequency voltage at 0V or VBAT, or in a boost mode to generate the low-frequency voltage at 2*VBAT. Moreover, the MCP 44 may toggle the low-frequency voltage between OV, VBAT, and / or 2*VBAT according to a duty-cycle signal 46 to thereby generate the low-frequency voltage VDC at any desired voltage level. The power inductor Lp is configured to induce a respective one of the low-frequency currents IDC-I , IDC-2 based on the low-frequency voltage VDC.

[0031] Each of the PMICs 36, 38 also includes a voltage amplifier 48 (denoted as “VA”) coupled in series to an offset capacitor COFF. The voltage amplifier 48 is configured to generate an initial voltage VAMP based on a respective one of at least two target voltages VTGT-I , VTGT-2 and a supply voltage VSUP. The offset capacitor COFF is configured to raise the initial voltage VAMP by an offset voltage VOFF to thereby generate a respective one of the voltages Vcc-i, Vcc-2.

[0032] Each of the PMICs 36, 38 further includes a bypass switch SBYP having one end coupled in between the voltage amplifier 48 and the offset capacitor COFF, and another end to a ground (GND). The bypass switch SBYP is closed while the offset capacitor COFF is being charged toward the offset voltage VOFF and opened when the offset capacitor COFF is charged to the offset voltage VOFF.

[0033] Figure 3 is a schematic diagram providing an exemplary illustration of any of the distributed PMICs 40, 42 in the power management circuit 12 in Figure1 . Common elements between Figures 1 , 2, and 3 are shown therein with common element numbers and will not be re-described herein.

[0034] Each of the distributed PMICs 40,42 includes a distributed voltage amplifier 50 (denoted as “DVA”) coupled in series to a distributed offset capacitor DCOFF. The distributed voltage amplifier 50 is configured to generate a distributed initial voltage DVAMP based on a respective one of the distributed target voltages DVTGT-I , DVTGT-2 and a distributed supply voltage DVSUP. In an embodiment, the distributed target voltages DVTGT-I , DVTGT-2 are generated by the PMICs 36, 38 in accordance with the target voltages VTGT-I , VTGT-2, respectively. The distributed offset capacitor DCOFF can be charged by a respective one of the low-frequency currents lcc-1 , Icc2 to raise the distributed initial voltage DVAMP by a distributed offset voltage DVOFF to thereby generate a respective one of the distributed voltages DVcc-i, DVcc-2.

[0035] Each of the distributed PMICs 40, 42 also includes a distributed bypass switch DSBYP having one end coupled in between the distributed voltage amplifier 50 and the distributed offset capacitor DCOFF, and another end to the GND. The distributed bypass switch DSBYP is closed while the distributed offset capacitor DCOFF is being charged toward the distributed offset voltage DVOFF and opened when the distributed offset capacitor DCOFF is charged up to the distributed offset voltage DVOFF.

[0036] To make the distributed PMICs 40, 42 smaller, the distributed PMICs 40, 42 are so configured without the MCP 44 and the power inductor Lp. As such, each of the distributed PMICs 40, 42 needs to draw one of the low- frequency currents lcc-1, Icc2 from one of the PMICs 36, 38 via the shared current distribution line 14.

[0037] In an embodiment, each of the distributed PMICs 40, 42 includes a distributed control circuit 52. The distributed control circuit 52 is configured to monitor the respective one of the low-frequency currents lcc-1, lcc-2 received via the shared current distribution line 14. More specifically, the distributed control circuit 52 determines whether it is necessary to adjust (increase or decrease) the respective one of the low-frequency currents lcc-1, lcc-2 based on the respectiveone of the distributed target voltages DVTGT-I , DVTGT-2. Should the distributed control circuit 52 determine that the respective one of the distributed target voltages DVTGT-I , DVTGT-2 needs to be adjusted, the distributed control circuit 52 will generate a low-frequency current feedback 54 and provide the low-frequency current feedback 54 to the respective one of the PMICs 36, 38 via a shared feedback line 56.

[0038] According to an embodiment of the present disclosure, the distributed control circuit 52 can only communicate the low-frequency current feedback 54 over the shared feedback line 56 when the respective one of the distributed PMICs 40, 42 is receiving the respective one of the low-frequency currents lcc-1 , lcc-2 over the shared current distribution line 14. As such, it is possible to determine whether the shared current distribution line 14 is idle or busy by monitoring the shared feedback line 56.

[0039] In this regard, with reference back to Figure 2, each of the PMICs 36, 38 includes a control circuit 58. In an embodiment, the control circuit 58 further includes a sensing circuit 60 and a controller 62. The sensing circuit 60 is configured to monitor the shared feedback line 56 and, thereby, determine the status of the shared current distribution line 14. In this regard, Figure 4 is a schematic diagram providing an exemplary illustration of the sensing circuit 60 configured according to an embodiment of the present disclosure. Common elements between Figures 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0040] In an embodiment, the sensing circuit 60 includes a transmit buffer 64 and a receive buffer 66. The receive buffer 66 is coupled to the shared feedback line 56 to receive the low-frequency current feedback 54. The transmit buffer 64 may be coupled to the shared feedback line 56 when a switch SW is closed and decoupled from the shared feedback line 56 when the switch SW is opened. In a non-limiting example, the transmit buffer 64 may communicate to any of the distributed PMICs 40, 42 when the switch SW is closed.

[0041] Notably, when the shared feedback line 56 is used by any of the distributed PMICs 40, 42 to communicate the low-frequency current feedback 54,there will be a modulated line voltage VLN on the shared feedback line 56. Accordingly, the sensing circuit 60 further includes a comparator 68 that compares the modulated line voltage VLN against a threshold voltage VTH. When the modulated line voltage LN is lower than the threshold voltage VTH (VLN < VTH), the comparator 68 will output an indication signal 70 to indicate that the shared feedback line 56 and, thus the shared current distribution line 14, is idle. In contrast, when the modulated line voltage VLN is higher than or equal to the threshold voltage VTH (VLN > VTH), the comparator 68 will output the indication signal 70 to indicate that the shared feedback line 56 and, thus the shared current distribution line 14, are busy. In an embodiment, each of the distributed PMICs 40, 42 may force the modulated line voltage VLN to be higher than the threshold voltage VTH to thereby retain access to the shared current distribution line 14, even when the shared feedback line 56 is in fact idle.

[0042] In an embodiment, the sensing circuit 60 may further include a pulldown resistor R that is coupled to the shared feedback line 56 via a pulldown switch SWp. The pulldown switch SWp will be closed to couple the shared feedback line 56 to a ground when the modulated line voltage VLN is lower than the threshold voltage VTH (VLN < VTH). By closing the pulldown switch SWp, the shared feedback line 56 will be released by the control circuit 58. As such, the shared feedback line 56 and, therefore the shared current distribution line 14, will be idle. The pulldown switch SWp will be opened when the modulated line voltage VLN is higher than or equal to the threshold voltage. In an embodiment, the pulldown switch SWp may be controlled via the indication signal 70.

[0043] With reference back to Figure 1 , when any of the PMICs 36, 38 determines that the shared current distribution line 14 is idle, the respective one of the PMICs 36, 38 can then use the shared current distribution line 14 to provide a respective one of the low-frequency currents lcc-1, lcc-2 to any of the distributed PMICs 40, 42. In one example, the PMIC 36 can provide the low- frequency current lcc-1 to the distributed PMIC 40 by closing switches Si, S2 and opening switches S3, S4. In another example, the PMIC 38 can provide the low- frequency current lcc-2 to the distributed PMIC 40 by closing switches S2, S3 andopening switches Si, S4. In each of these examples, switch Ss is closed and switch Se is opened to provide the distributed PMIC 40 with exclusive access to the shared feedback line 56.

[0044] In another example, the PMIC 36 can provide the low-frequency current lcc-1 to the distributed PMIC 42 by closing switches Si, S4 and opening switches S2, S3. In another example, the PMIC 38 can provide the low-frequency current lcc-2 to the distributed PMIC 42 by closing switches S3, S4 and opening switches Si, S2. In each of these examples, switch Se is closed and switch S5 is opened to provide the distributed PMIC 42 with exclusive access to the shared feedback line 56.

[0045] With reference back to Figure 1 , the power management circuit 12 may be adapted to enable conflict-free current distribution over the shared current distribution line 14 with one of the distributed PMICs 40, 42. Figure 5 is a schematic diagram of an exemplary wireless device 10A wherein a power management circuit 12A is configured according to another embodiment of the present disclosure to enable conflict-free current distribution over the shared current distribution line 14. Common elements between Figures 1 and 5 are shown therein with common element numbers and will not be re-described herein.

[0046] In a non-limiting example, the power management circuit 12A includes only the distributed PMIC 42. In this regard, the PMICs 36, 38 can be configured to enable conflict-free current distribution to the distributed PMIC 42 over the shared current distribution line 14.

[0047] The power management circuit 12 in Figure 1 can be provided in a communication device to support the embodiments described above. In this regard, Figure 6 is a schematic diagram of an exemplary communication device 100 wherein the power management circuit 12 in Figure 1 can be provided.

[0048] Herein, the communication device 100 can be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless localarea network (WLAN), Bluetooth, and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 1 10, multiple antennas 112, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 1 10 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0049] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0050] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may providespatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0051] In an embodiment, the communication device 100 can be functionally equivalent to the wireless device 10 of Figure 1 . In another embodiment, the power management circuit 12 in Figure 1 can be provided between the transmit circuitry 106 and the antenna switching circuitry 1 10. Understandably, the power management circuit 12 can also be provided elsewhere in the communication device 100.

[0052] In an embodiment, it is possible to provide conflict-free current distribution in the wireless device of Figure 1 in accordance with a process. In this regard, Figure 7 is a flowchart of an exemplary process 200 for conflict-free current distribution in the wireless device 10 of Figure 1 .

[0053] Herein, the process 200 includes receiving the selected one of the low- frequency currents IDC-I , IDC-2 via the shared current distribution line 14 (step 202). The process 200 also includes generating the respective one of the distributed voltages DVcc-i, DVcc-2 based on the selected one of the low- frequency currents IDC-I , IDC-2 (step 204). The process 200 also includes determining whether the shared current distribution line 14 is idle (step 206). The process 200 also includes providing the selected one of the low-frequency currents IDC-I , IDC-2 over the shared current distribution line 14 in response to determining that the shared current distribution line 14 is idle (step 208).

[0054] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A power management circuit (12) comprising: one or more distributed power management integrated circuits, PMICs, (40, 42) each coupled to a shared current distribution line (14) and configured to: receive a selected one of a plurality of low-frequency currents (IDC-I , IDC-2) via the shared current distribution line (14); and generate a respective one of a plurality of distributed voltages(DVcc-1, DVcc-2) based on the selected one of the plurality of low-frequency currents (IDC-I , IDC-2); and a plurality of PMICs (36, 38) each coupled to the shared current distribution line (14) and configured to: generate a respective one of the plurality of low-frequency currents (IDC-I, IDC-2); determine whether the shared current distribution line (14) is idle; and provide the respective one of the plurality of low-frequency currents (IDC-I, IDC-2) to any one of the one or more distributed PMICs (40, 42) over the shared current distribution line (14) in response to determining that the shared current distribution line (14) is idle.

2. The power management circuit (12) of claim 1 , wherein each of the one or more distributed PMICs (40, 42) is further configured to: receive the selected one of the plurality of low-frequency currents (IDC-I , IDC-2) from a selected one of the plurality of PMICs (36, 38) via the shared current distribution line (14); and send a low-frequency current feedback (54) to the selected one of the plurality of PMICs (36, 38) via a shared feedback line (56) whilereceiving the selected one of the plurality of low-frequency currents (IDC-I, IDC-2) via the shared current distribution line (14).

3. The power management circuit (12) of claim 2, wherein each of the one or more distributed PMICs (40, 42) comprises a distributed control circuit (52) configured to: monitor the selected one of the plurality of low-frequency currents (IDC-I , IDC-2) based on a respective one of a plurality of distributed target voltages (DVTGT-I, DVTGT-2); and provide the low-frequency current feedback (54) to the selected one of the plurality of PMICs (36, 38) over the shared feedback line (56) to thereby cause an adjustment in the selected one of the plurality of low-frequency currents (IDC-I , IDC-2).

4. The power management circuit (12) of claim 3, wherein each of the plurality of PMICs (36, 38) comprises: a multi-level charge pump, MCP, (44) configured to generate a low- frequency voltage (VDC) in accordance with a duty-cycle signal (46); a power inductor (Lp) coupled to the shared current distribution line (14) and configured to induce the respective one of the plurality of low- frequency currents (IDC-I , IDC-2) based on the low-frequency voltage (VDC); and a control circuit (58) coupled to the shared feedback line (56) and configured to: generate the duty-cycle signal (46) based on a respective one of a plurality of target voltages (VTGT -I, VTGT-2); and adjust the duty-cycle signal (46) based on the low-frequency current feedback (54) to thereby cause the adjustment in the selected one of the plurality of low-frequency currents (IDC-I , IDC-2).

5. The power management circuit (12) of claim 4, wherein the control circuit (58) in each of the plurality of PMICs (36, 38) is further configured to generate a respective one of the plurality of distributed target voltages (DVTGT-I , DVTGT-2) from the respective one of the plurality of target voltages (VTGT-I , VTGT-2).

6. The power management circuit (12) of claim 2, wherein each of the plurality of PMICs (36, 38) further comprises a sensing circuit (60) configured to: monitor a modulated line voltage (VLN) on the shared feedback line (56); determine that the shared current distribution line (14) is idle when the modulated line voltage (VLN) is below a threshold voltage (VTH); and determine that the shared current distribution line (14) is busy when the modulated line voltage (VL ) of the shared feedback line is above or equal to the threshold voltage (VTH).

7. The power management circuit (12) of claim 6, wherein the sensing circuit (60) comprises: a receive buffer (66) coupled directly to the shared feedback line (56) and configured to receive the low-frequency current feedback (54); and a comparator (68) coupled directly to the shared feedback line (56) and configured to: compare the modulated line voltage (VLN) against the threshold voltage (VTH); generate an indication signal (70) to indicate that the shared feedback line (56) is idle when the modulated line voltage (VLN) is lower than the threshold voltage (VTH); and generate the indication signal (70) to indicate that the shared feedback line (56) is busy when the modulated line voltage (VLN) is higher than or equal to the threshold voltage (VTH).

8. The power management circuit (12) of claim 7, wherein the sensing circuit (60) further comprises a pulldown resistor (R) coupled to the shared feedbackline (56) via a pulldown switch (SWp), the pulldown switch (SWp) is closed when the modulated line voltage (VLN) is lower than the threshold voltage (VTH) and opened when the modulated line voltage (VLN) is higher than or equal to the threshold voltage (VTH).

9. The power management circuit (12) of claim 6, wherein each of the one or more distributed PMICs (40, 42) is further configured to maintain the modulated line voltage (VLN) above the threshold voltage (VTH) to thereby retain access to the shared current distribution line (14) independent of whether the shared feedback line (56) is idle.

10. A wireless device (10) comprising a power management circuit (12), the power management circuit (12) comprising: one or more distributed power management integrated circuits, PMICs, (40, 42) each coupled to a shared current distribution line (14) and configured to: receive a selected one of a plurality of low-frequency currents (IDC-I , IDC-2) via the shared current distribution line (14); and generate a respective one of a plurality of distributed voltages(DVcc-i, DVcc-2) based on the selected one of the plurality of low-frequency currents (IDC-I , IDC-2); and a plurality of PMICs (36, 38) each coupled to the shared current distribution line (14) and configured to: generate a respective one of the plurality of low-frequency currents (IDC-I, IDC-2); determine whether the shared current distribution line (14) is idle; and provide the respective one of the plurality of low-frequency currents (IDC-I, IDC-2) to any one of the one or more distributed PMICs (40, 42) over the shared current distribution line (14) inresponse to determining that the shared current distribution line (14) is idle.1 1 . The wireless device of claim 10, further comprising: a plurality of power amplifier circuits each coupled to a respective one of the plurality of PMICs; and a plurality of distributed power amplifier circuits each coupled to a respective one of the one or more distributed PMICs.

12. The wireless device of claim 10, wherein each of the one or more distributed PMICs is further configured to: receive the selected one of the plurality of low-frequency currents from a selected one of the plurality of PMICs via the shared current distribution line; and send a low-frequency current feedback to the selected one of the plurality of PMICs via a shared feedback line while receiving the selected one of the plurality of low-frequency currents via the shared current distribution line.

13. The wireless device of claim 12, wherein each of the one or more distributed PMICs comprises a distributed control circuit configured to: monitor the selected one of the plurality of low-frequency currents based on a respective one of a plurality of distributed target voltages; and provide the low-frequency current feedback to the selected one of the plurality of PMICs over the shared feedback line to thereby cause an adjustment in the selected one of the plurality of low-frequency currents.

14. The wireless device of claim 13, wherein each of the plurality of PMICs comprises:a multi-level charge pump, MCP, configured to generate a low-frequency voltage in accordance with a duty-cycle signal; a power inductor coupled to the shared current distribution line and configured to induce the respective one of the plurality of low- frequency currents based on the low-frequency voltage; and a control circuit coupled to the shared feedback line and configured to: generate the duty-cycle signal based on a respective one of a plurality of target voltages; and adjust the duty-cycle signal based on the low-frequency current feedback to thereby cause the adjustment in the selected one of the plurality of low-frequency currents.

15. The wireless device of claim 14, wherein the control circuit in each of the plurality of PMICs is further configured to generate a respective one of the plurality of distributed target voltages from the respective one of the plurality of target voltages.

16. The wireless device of claim 12, wherein each of the plurality of PMICs further comprises a sensing circuit configured to: monitor a modulated line voltage on the shared feedback line; determine that the shared current distribution line is idle when the modulated line voltage is below a threshold voltage; and determine that the shared current distribution line is busy when the modulated line voltage of the shared feedback line is above or equal to the threshold voltage.

17. The wireless device of claim 16, wherein the sensing circuit comprises: a receive buffer coupled directly to the shared feedback line and configured to receive the low-frequency current feedback; and a comparator coupled directly to the shared feedback line and configured to:compare the modulated line voltage against the threshold voltage; generate an indication signal to indicate that the shared feedback line is idle when the modulated line voltage is lower than the threshold voltage; and generate the indication signal to indicate that the shared feedback line is busy when the modulated line voltage is higher than or equal to the threshold voltage.

18. The wireless device of claim 17, wherein the sensing circuit further comprises a pulldown resistor coupled to the shared feedback line via a pulldown switch, the pulldown switch is closed when the modulated line voltage is lower than the threshold voltage and opened when the modulated line voltage is higher than or equal to the threshold voltage.

19. The wireless device of claim 16, wherein each of the one or more distributed PMICs is further configured to maintain the modulated line voltage above the threshold voltage to thereby retain access to the shared current distribution line independent of whether the shared feedback line is idle.

20. A method for conflict-free current distribution in a wireless device comprising: receiving a selected one of a plurality of low-frequency currents via a shared current distribution line; generating a respective one of a plurality of distributed voltages based on the selected one of the plurality of low-frequency currents; determining whether the shared current distribution line is idle; and providing the selected one of the plurality of low-frequency currents over the shared current distribution line in response to determining that the shared current distribution line is idle.

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