Vertical silicon carbide metal oxide semiconductor gate junction field effect transistors
EP4772004A1Pending Publication Date: 2026-07-08POWER INTEGRATIONS INC
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- POWER INTEGRATIONS INC
- Filing Date
- 2024-08-16
- Publication Date
- 2026-07-08
AI Technical Summary
Technical Problem
Existing silicon carbide (SiC) junction field effect transistors (JFETs) face challenges in achieving optimal pinch-off behavior and specific on-resistance for high voltage operation.
Method used
The development of vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs) with a deep gate, sub-surface channel region, and a MOS gate structure, which improves pinch-off behavior and reduces specific on-resistance.
Benefits of technology
The proposed vertical SiC MOS gate JFETs demonstrate enhanced pinch-off performance and reduced on-resistance, making them suitable for high voltage applications.
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Smart Images
Figure US2024042689_06032025_PF_FP_ABST
Abstract
Vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs) are presented herein. An epitaxial region (104) is grown on a substrate layer to form a vertical structure. A vertical JFET is formed within the vertical structure and includes a source region (108) at a device surface, a deep gate (106) formed below the surface, and a drain (102) formed by a substrate layer. A MOS gate (123) is formed above a sub-surface channel implant region to improve pinch-off behavior and specific on-resistance. Pinch-off voltage is determined, at least in part, by a gate dielectric thickness, a dimension of the JFET neck, and a doping concentration of the sub-surface channel implant region.
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