Driving device and display device

Abstract

The driving device may drive the light-emitting element using at least two clock signals having different clock speeds. Accordingly, an input of data and control of emission time are independently controlled, thereby reducing power consumption and improving luminance.

Description

[Technical Field]

[0001] The embodiment relates to a driving device and a display device.[Background Art]

[0002] The display market is growing, and its application scope is continuously expanding. With the expansion of such application scope, the resolution and characteristics of products are diversifying.

[0003] As product specifications diversify, display driving methods are also becoming more complex.

[0004] Driver ICs used to drive display devices are designed specifically for each specific application. Therefore, the range of design applications is limited, so that a suitable driver IC is required for each product when necessary.

[0005] An existing display device employs various methods to ensure uniformity. For example, internal compensation is performed by configuring a light-emitting circuit in each pixel (or subpixel), or external compensation is performed using a specific method.

[0006] Meanwhile, most circuit configurations for the operation of light-emitting circuits incorporate internal capacitors, ensuring constant current characteristics.

[0007] FIG. 1 is a circuit diagram illustrating an existing light-emitting circuit.

[0008] As illustrated in FIG. 1, the existing light-emitting circuit comprises a driving transistor M1, a scan transistor M2, a sensing transistor M3, and a capacitor CSTG.

[0009] When scan transistor M2 is turned on in response to a scan signal SCAN, a data signal VDATA is supplied to the driving transistor M1 via the scan transistor M2. The driving transistor M1 supplies an emission current corresponding to the data signal VDATA to the light-emitting element ED, causing the light-emitting element ED to emit light.

[0010] The capacitor CSTG ensures that the emission current is supplied as a constant current to the light-emitting element ED.

[0011] When the sensing transistor M3 is turned on in response to a sensing control signal SEN, the emission current flowing through the driving transistor M1 is detected as a sensing signal VSEN. The characteristics of the corresponding light-emitting circuit is calibrated or compensated using the sensing signal VSEN.

[0012] Meanwhile, the light-emitting circuit of an active matrix display device controls brightness using either pulse amplitude modulation (PWM) itself or a PWM method utilizing pulse amplitude modulation (PAM). In such cases, a capacitor must be included within each pixel (or subpixel).

[0013] When the light-emitting circuit is designed to comprise a capacitor within every pixel, limitations such as area can arise, or additional problems can arise due to the capacitors within each pixel.[Disclosure][Technical Problem]

[0014] An object of the embodiment is to solve the foregoing and other problems.

[0015] Another object of the embodiment is to provide a driving device and a display device having a novel structure.

[0016] Another object of the embodiment is to provide a driving device and a display device that provide a novel driving scheme.

[0017] Another object of the embodiment is to provide a display device that does not comprise a capacitor in the light-emitting circuit.

[0018] Another object of the embodiment is to provide a driving device and a display device that do not comprise a converter that converts digital data to analog data.

[0019] Another object of the embodiment is to provide a driving device and a display device capable of reducing power consumption.

[0020] Another object of the embodiment is to provide a driving device and a display device capable of improving image quality.

[0021] The technical problems of the embodiments are not limited to those described in this item and comprise those that may be understood through the description of the invention.[Technical Solution]

[0022] According to one aspect of the embodiment to achieve the above or other objects, a driving device that is configured to drive a light-emitting element using at least two clock signals having different clock speeds.

[0023] The at least two clock signals may comprise a first clock signal and a second clock signal. A first clock speed of the first clock signal may be at least 2 4< times greater than a second clock speed of the second clock signal.

[0024] An input of data for emitting light from the light-emitting element may be controlled using the first clock signal, and an emission time of the light-emitting element may be controlled using the second clock signal.

[0025] The driving device may comprise: a first counting block configured to count based on the first clock signal; a first control block configured to control the input of the data using the counted value; a second counting block configured to count based on the second clock signal; and a second control block configured to control an emission time of the light-emitting element using the counted value.

[0026] The first counting block comprises: a first counter configured to output a first count value for controlling the input of the data using the first clock signal and a first reset signal. The first reset signal represents a reference time for controlling the input of the data. The first control block may control the input of the data using the first count value.

[0027] The second counting block comprises: a second counter configured to output a second count value using the second clock signal and a second reset signal; and a third counter configured to output a third count value for emitting light from the light-emitting element using the second clock signal. The light-emitting element may be prepared to emit light by the second count value. The second control block may emit light from the light-emitting element after the second reset signal is received and a predetermined time has elapsed by using the third count value.

[0028] The second reset signal may represent a reference time for emitting light from the light-emitting element. The first control block may output the second reset signal based on the first count value.

[0029] The second control block comprises: a clock controller configured to output a third clock signal using the second clock signal when the second count value is a predetermined value; a bit generator configured to output an emission end signal using an emission control signal; and a comparator configured to output an emission stop signal using the third count value and the emission end signal. The emission end signal may represent an end point in the emission time of the light-emitting element.

[0030] The third counter may output the third count value using the third clock signal.

[0031] The emission stop signal may be generated in response to the third count value becoming equal to the value of the emission end signal.

[0032] The driving device may further comprise: an emission driving circuit configured to drive the light-emitting element to emit light using the emission stop signal.

[0033] According to another aspect of the embodiment to achieve the above or other objects, a display device comprising a plurality of subpixels, comprising: at least one light-emitting element for each of the plurality of subpixels; and a driving device configured to drive at least one light-emitting element using at least two clock signals having different clock speeds.

[0034] The at least two clock signals may comprise a first clock signal and a second clock signal. A first clock speed of the first clock signal may be at least 2 4< times greater than a second clock speed of the second clock signal.

[0035] An input of data for emitting light from the light-emitting element may be controlled using the first clock signal, and an emission time of the light-emitting element may be controlled using the second clock signal.[Advantageous Effects]

[0036] The effects of the driving device and the display device according to the embodiment are described as follows.

[0037] According to at least one of the embodiments, since no capacitor is provided in the light-emitting circuit, there is no area limitation, so that the aperture ratio can be increased, thereby improving the luminance.

[0038] According to at least one of the embodiments, a display driving device including a converter that converts digital data into analog data is not required, thereby simplifying the circuit structure, reducing the area occupied, and reducing the cost.

[0039] According to at least one of the embodiments, data input and control of emission time are independently controlled using at least two clock signals having different clock speeds, thereby reducing power consumption and improving luminance.

[0040] According to at least one of the embodiments, the first counting block and the second counting block, which may operate independently, are designed to operate optimally, thereby improving image quality.

[0041] Additional scope of applicability of the embodiments will become apparent from the detailed description that follows. However, since various changes and modifications within the idea and scope of the embodiments may be clearly understood by those skilled in the art, the detailed description and specific embodiments, such as preferred embodiments, should be understood as being given by way of example only.[Description of Drawings]

[0042] FIG. 1 is a circuit diagram illustrating an existing light-emitting circuit. FIG. 2 schematically illustrates a display device according to an embodiment. FIG. 3 is a block diagram illustrating a display device according to an embodiment in detail. FIG. 4 is a block diagram illustrating a driving device according to an embodiment. FIG. 5 is a signal waveform diagram for operating a driving device according to an embodiment. FIG. 6 is a block diagram illustrating an emission driving circuit according to an embodiment. FIG. 7 is a circuit diagram illustrating an emission driving circuit according to an embodiment.

[0043] The sizes, shapes, dimensions, etc. of elements illustrated in the drawings may differ from actual ones. In addition, even if the same elements are illustrated in different sizes, shapes, dimensions, etc. between the drawings, this is only an example on the drawing, and the same elements have the same sizes, shapes, dimensions, etc. between the drawings.[Mode for Invention]

[0044] Hereinafter, the embodiment disclosed in this specification will be described in detail with reference to the accompanying drawings, but the same or similar elements are given the same reference numerals regardless of reference numerals, and redundant descriptions thereof will be omitted. The suffixes 'module' and 'unit' for the elements used in the following descriptions are given or used interchangeably in consideration of ease of writing the specification, and do not themselves have a meaning or role that is distinct from each other. In addition, the accompanying drawings are for easy understanding of the embodiment disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings. Also, when an element such as a layer, region or substrate is referred to as being 'on' another element, this means that there may be directly on the other element or be other intermediate elements therebetween.

[0045] Hereinafter, "~ module", "~ unit", etc. may be composed of "~ circuit" or "integrated circuit". "~ module", "~ unit", etc. may be used interchangeably with "~ circuit" or "integrated circuit".

[0046] FIG. 2 schematically illustrates a display device according to an embodiment.

[0047] Referring to FIG. 2, the display device according to the embodiment may comprise a driving device 100 and a plurality of light-emitting elements 120-1 to 120-N.

[0048] The display device according to the embodiment may comprise a display panel. The display panel may comprise a plurality of pixels. The display panel may comprise a plurality of subpixels SP-1 to SP-N. A single pixel may comprise a plurality of subpixels SP-1 to SP-N.

[0049] The display panel may comprise a display region comprising a plurality of pixels and a non-display region excluding the display region. In addition, the emission region of the display panel may be a region corresponding to each of the plurality of subpixels SP-1 to SP-N, and the non-emission region may be a region between the plurality of subpixels SP-1 to SP-N.

[0050] In the embodiment, the driving device 100 may be provided in the non-emission region, but is not limited thereto.

[0051] The plurality of subpixels SP-1 to SP-N may comprise a plurality of red subpixels, a plurality of green subpixels, and a plurality of blue subpixels. A unit pixel may be formed by adjacent red subpixel, green subpixel, and blue subpixel. In the drawing, a first subpixel SP-1 may be a red subpixel, a second subpixel SP-2 may be a green subpixel, and a third subpixel SP-3 may be a blue subpixel, but is not limited thereto.

[0052] Each of the plurality of subpixels SP-1 to SP-N may comprise at least one light-emitting element 120-1 to 120-N. For example, the first subpixel may comprise at least one red light-emitting element for emitting red light. For example, the second subpixel may comprise at least one green light-emitting element for emitting green light. For example, the third subpixel may comprise at least one blue light-emitting element for emitting blue light. The plurality of light-emitting elements 120-1 to 120-N may comprise organic semiconductor light-emitting elements, inorganic semiconductor light-emitting elements, micro-level semiconductor light-emitting elements, nano-level semiconductor light-emitting elements, etc.

[0053] While the drawing illustrates the plurality of subpixels SP-1 to SP-N arranged in a vertical line, the plurality of subpixels SP-1 to SP-N may be arranged in a horizontal line or in a matrix form.

[0054] Meanwhile, the driving device 100 may drive the plurality of light-emitting elements 120-1 to 120-N to emit light. The driving device 100 may control the plurality of light-emitting elements 120-1 to 120-N to generate emission currents. The plurality of light-emitting elements 120-1 to 120-N may emit light by the plurality of emission currents.

[0055] The driving device 100 may provide a control signal capable of controlling the emission time for each period (or frame) to the plurality of light-emitting elements 120-1 to 120-N. The emission time of each of the plurality of light-emitting elements 120-1 to 120-N may be controlled differently by the control signal. The luminance of each of the light-emitting elements 120-1 to 120-N varies depending on the differently-controlled emission time, thereby allowing images with different grayscale levels to be displayed.

[0056] The driving device 100 may drive each of the light-emitting elements 120-1 to 120-N using at least two clock signals having different clock speeds. In addition, the driving device 100 may receive data corresponding to each of the plurality of light-emitting elements 120-1 to 120-N.

[0057] For example, the driving device 100 may control inputs of a plurality of data using a first clock signal. For example, the driving device 100 may control an emission time of each of the light-emitting elements 120-1 to 120-N using a second clock signal. A first clock speed of the first clock signal may be at least 2 4< times greater than a second clock speed of the second clock signal.

[0058] In an embodiment, the data used emissions of the light-emitting elements 120-1 to 120-N may be digital data. In this instance, the input of the digital data may be controlled using a high-speed clock signal, such as the first clock signal. Additionally, the emission times of the light-emitting elements may be controlled using a low-speed clock signal, such as the second clock signal.

[0059] When data input and driving of the plurality of light-emitting elements 120-1 to 120-N are performed using only the first clock signal, the data input speed and the emission speed may be individually controlled. That is, the light-emitting elements 120-1 to 120-N may also be controlled according to the input speed of data requiring high-speed driving. In this instance, the plurality of light-emitting elements 120-1 to 120-N, which require low-speed operation, may also be driven at high speed, increasing power consumption.

[0060] For example, to express a 120 Hz time using a first clock signal of 30 MHz, an 18-bit counter capable of counting 30,000 / 0.12 = 250,000≒2 18< counts is required. Since the 18-bit counter must continuously operate not only for data input but also for control of emission time, the counting operation must be performed at 30 MHz. Consequently, power consumption may increase.

[0061] Furthermore, since the control of emission time is tailored to the data input speed, effective or active luminance control may be limited.

[0062] According to an embodiment, the data input and the control of emission time are independently controlled using at least two clock signals having different clock speeds, thereby reducing power consumption and improving luminance.

[0063] For example, when using a first clock signal of 30 MHz and a second clock signal of 400 kHz, a time representation of 5 µs or less may be used as the first clock signal of 30 MHz, and a time representation of 5 µs or more may be used as the second clock signal of 400 kHz. Therefore, when a time representation of 5 µs or less is not required, operation for the first clock signal of 30 MHz is suspended, and only the second clock signal of 400 kHz may be operated. In other words, a high-speed clock signal is no longer required. Consequently, dynamic power dissipation can be dramatically reduced.

[0064] Dynamic power dissipation (DPD) may be expressed by Equation 1. DPD = α ⋅ C L ⋅ V 2 ⋅ f

[0065] α represents an activity factor, C L represents capacitance, V represents voltage, and f may represent an operating frequency.

[0066] The operating frequency f may be related to the clock speed of the first clock signal or the second clock signal. Therefore, by using a second clock signal having a clock speed significantly lower than that of the first clock signal, as in the embodiment, dynamic power consumption can be significantly reduced.

[0067] FIG. 3 is a block diagram illustrating in detail a display device according to an embodiment.

[0068] As illustrated in FIG. 3, a driving device 100 may be provided between the plurality of light-emitting elements 120-1 to 120-N.

[0069] The plurality of light-emitting elements 120-1 to 120-N may be divided into a first light-emitting group 120-A and a second light-emitting group 120-B. The first light-emitting group 120-A may comprise the first light-emitting element 120-1 to the K-th light-emitting element 120-K, and the second light-emitting group 120-B may comprise the (K+1)-th light-emitting element 120-(K+1) to the N-th light-emitting element 120-N. The first light-emitting group 120-A and the second light-emitting group 120-B may comprise the same number of light-emitting elements, but is not limited thereto.

[0070] The first light-emitting elements 120-1 to the Kth light-emitting elements 120-K may be provided on a first side of the driving device 100, and the (K+1)th light-emitting elements 120-(K+1) to the Nth light-emitting elements 120-N may be provided on a second side of the driving device 100.

[0071] Although not illustrated, a plurality of light-emitting groups may be provided along the periphery of the driving device 100. That is, the plurality of light-emitting elements 120-1 to 120-N may be divided into a first light-emitting group 120-A, a second light-emitting group 120-B, a third light-emitting group, and a fourth light-emitting group provided on a first side, a second side, a third side, and a fourth side of the driving device 100, respectively. The first side and the second side may be positioned on opposite sides of the driving device 100, and the third side and the fourth side may be positioned on opposite sides of the driving device 100.

[0072] The driving device 100 may comprise a first counting block 200, a first control block 300, a second counting block 400, a second control block 500, emission driving circuits 105A and 105B, etc.

[0073] Data, clock signals CK F and CK S , control signal ETC, etc. may be received by the driving device 100. The control signal ETC may be omitted. Power voltages PVDD and PVSS may be provided to the driving device 100.

[0074] The data, the clock signals CK F and CK S , etc. may also be output from the driving device 100. When multiple driving devices 100 are provided, the data, the clock signals CK F and CK S , etc. may be transmitted from the driving device 100 illustrated in FIG. 3 to another driving device. For example, some of the data received by the driving device 100 may be used to drive the plurality of light-emitting elements 120-1 to 120-N connected to the driving device 100 to emit light. The remaining data may be transmitted to another driving device along with the clock signals CK F and CK S , and used to drive the plurality of light-emitting elements connected to the other driving device to emit light.

[0075] In an embodiment, the clock signals CK F and CK S may comprise at least two clock signals having different clock speeds. For example, the clock signals may comprise a first clock signal CK F , a second clock signal CK S , etc.

[0076] The first clock signal CK F may be used to control the input of data, and the second clock signal CK S may be used to control the emission time of each light-emitting element 120-1 to 120-N. As described above, while the input of data may be driven at high speed, the emission of each light-emitting element 120-1 to 120-N may be driven at low speed. Accordingly, the first clock signal CK F may be used for the input of data requiring high speed operation, and the second clock signal CK S may be used for the emission of each light-emitting element 120-1 to 120-N requiring low speed operation.

[0077] Meanwhile, the first counting block 200 may count based on the first clock signal CK F , and the first control block 300 may control the input of data using the values counted by the first counting block 200. The second counting block 400 counts based on the second clock signal CK S , and the second control block 500 may control the emission time of each of the light-emitting elements 120-1 to 120-N using the values counted by the second counting block 400.

[0078] According to an embodiment, the first counting block 200 and the second counting block 400, which are independent of each other and thus may be driven separately, may be provided. The first counting block 200 may count to control the input of data requiring high-speed driving using the first clock signal CK F . The second counting block 400 may count to control the emission time of each of the light-emitting elements 120-1 to 120-N requiring low-speed driving using the second clock signal CK S .

[0079] Accordingly, power consumption can be reduced by using the second clock signal CK S having a low frequency instead of a first clock signal CK F having a high frequency to control the emission time of each light-emitting element 120-1 to 120-N. In addition, the first counting block 200 and the second counting block 400, which may operate independently of each other, are designed to operate optimally, thereby improving image quality.

[0080] FIG. 4 is a block diagram illustrating a driving device 100 according to an embodiment. FIG. 5 is a signal waveform diagram for operating a driving device according to an embodiment.

[0081] Although FIG. 5 illustrates a signal waveform for emitting light, for example, the first light-emitting element 120-N among the plurality of light-emitting elements 120-1 to 120-N, the remaining light-emitting elements, i.e., the first light-emitting element to the (N-1)-th light-emitting element 120-(N-1), may also emit light according to signal waveforms identical or similar to the signal waveform illustrated in FIG. 5.

[0082] Hereinafter, the light-emitting element may refer to the first light-emitting element 120-N.

[0083] As illustrated in FIGS. 4 and 5, the first counting block 200 may comprise a first counter 210, etc. The first counter 210 may output a first count signal FC for inputting data using a first clock signal CK F and a first reset signal RS. The first count signal FC may be initialized and accumulated until it reaches a value of 0. The first count signal FC may be initialized in response to the first reset signal RS, but is not limited thereto.

[0084] The first counter 210 may receive a first clock signal CK F and a first reset signal RS. The first reset signal RS may represent a reference time for controlling data input.

[0085] The first counter 210 may count a first count signal FC using the first clock signal CK F in response to receiving a first reset signal RS at a high level with a predetermined width, and output the counted first count signal FC. Thereafter, when a first reset signal RS at a high level is received again, the first count signal FC may be initialized to a value of 0 or ignored, and the first count signal FC may be counted again using the first clock signal CK F .

[0086] The first control block 300 may control data input using the first count signal FC. For example, the first control block 300 may process serially input data in parallel. The parallel-processed data may be temporarily stored, but is not limited thereto. Using the parallel-processed data, the plurality of light-emitting elements 120-1 to 120-N may be simultaneously illuminated, but is not limited thereto.

[0087] The second counting block 400 may comprise a second counter 410, a third counter 420, etc.

[0088] The second counter 410 may output a second count signal QA using the second clock signal CK S and a second reset signal RS EM . The second count signal QA may be initialized and accumulated until it reaches 0. The second count signal QA may be initialized in response to the second reset signal RS EM , but is not limited thereto. In addition, the second counter 410 may output signals LPC and LEZ necessary for emitting light of the light-emitting element 120-N.

[0089] The second reset signal RS EM may represent a reference time for emitting light of the light-emitting element 120-N. The first control block 300 may control data input based on the first count signal FC. When data input is complete, the first control block 300 may generate the second reset signal RS EM . For example, the first control block 300 may be configured to recognize that data input is complete when the first count signal FC reaches a predetermined value. Accordingly, when the first count signal FC reaches the predetermined value, the first control block 300 may generate the second reset signal RS EM .

[0090] The light-emitting element 120-N may be prepared to emit light by the second count signal QA. That is, even if the second reset signal RS EM of high-level is generated, the light-emitting element 120-N may be made to emit light after the second reset signal RS EM is generated and a predetermined period of time has elapsed by using the second count signal QA. In other words, even if the second reset signal RS EM of high-level is generated, the light-emitting element 120-N may not emit light until the second count signal QA reaches the predetermined value. The light-emitting element 120-N may emit light in response to the second count signal QA reaching a predetermined value.

[0091] The second counter 410 may count the second count signal QA using the second clock signal CK S in response to receiving the second reset signal RS EM of high-level having a predetermined width, and output the counted second count signal QA. The second count signal QA may be provided to the clock controller 520 and used to generate a third clock signal CK SE .

[0092] Meanwhile, the third counter 420 may output a third count signal SC for emitting light from the light-emitting element 120-N using the second clock signal CK S . The third count signal SC may be initialized and accumulated until it reaches 0. The third count signal SC may be initialized in response to the second reset signal RS EM , but is not limited thereto.

[0093] The third counter 420 may output the third count signal SC using the second clock signal CK S in response to receiving the second reset signal RS EM of high-level having a predetermined width.

[0094] However, as illustrated in FIG. 5, even if the third counter 420 receives the second reset signal RS EM of high-level, it may be seen that the third counter 420 does not generate the third count signal SC for a predetermined period of time. Here, the predetermined period of time may be a time for preparing the light-emitting element 120-N to emit light.

[0095] To this end, the third counter 420 may receive the third clock signal CK SE generated by the clock controller 520. After the second reset signal RS EM of a high level is received and a certain period of time has elapsed, the third clock signal CKSE may be received by the third counter 420. After the second reset signal RS EM of a high level is received according to the third clock signal CK SE and a certain period of time has elapsed, the third counter 420 may count the third count signal SC.

[0096] Meanwhile, the light-emitting element 120-N may be operated by period having an on-section (or emission section) and an off-section (or non-emission section). The light-emitting element 120-N may emit light during the on-section, and may not emit light during the off-section. Here, the on-section may correspond to the emission time of the light-emitting element 120-N. Therefore, the terms "on-section", "emission section", and "emission time" may be used interchangeably. Controlling the emission time of the light-emitting element 120-N may mean controlling (or adjusting) the on-section (emission time) for each period.

[0097] In an embodiment, the on-section may be changed in response to the grayscale (or luminance) of the data.

[0098] For example, as the grayscale of data increases, the width of the on-section may increase. For example, when the width of the on-section increases in response to data with a high grayscale, the light-emitting element 120-N may emit light during the increased on-section, thereby increasing the luminance of the light-emitting element 120-N.

[0099] As another example, the width of the on-section can be reduced as the grayscale of the data decreases. For example, when the width of the on-section is reduced in response to data with low grayscale, the light-emitting element 120-N may emit light during the reduced on-section, thereby reducing the luminance of the light-emitting element 120-N.

[0100] In a fixed period , the off-section may decrease wen the width of the on-section increases, and the off-section may increase when the width of the on-section decreases.

[0101] In this way, the emission time of the light-emitting element 120-N, i.e., the on-section per period, may be controlled (or controlled) by the second control block 500 according to the grayscale of the data.

[0102] Referring again to FIGS. 4 and 5, the second control block 500 may comprise a clock controller 520, a bit generator 530, a comparator 540, etc.

[0103] When the second count signal QA received from the second counter 410 is a predetermined value, the clock controller 520 may output a third clock signal CK SE using the second clock signal CK S .

[0104] The clock controller 520 may comprise an AND gate operator. Accordingly, the clock controller 520 may perform an AND gate operation on the second count signal QA and the second clock signal CK S to output the third clock signal CK SE .

[0105] The clock controller 520 may receive the second clock signal CK S and the second count signal QA. The clock controller 520 may not output the third clock signal CK SE until the second count signal QA reaches a predetermined value. That is, the clock controller 520 may output the third clock signal CK SE using the second clock signal CK S in response to the second count signal QA reaching the predetermined value. Accordingly, the clock controller 520 may not output the third clock signal CK SE from the time the second count signal QA is first received until the second count signal QA reaches the predetermined value. The clock speed of the third clock signal CK SE may be the same as the clock speed of the second clock signal CK S , but is not limited thereto. When the clock speed of the third clock signal CK SE is the same as the clock speed of the second clock signal CK S , the clock controller 520 may output the second clock signal CK S as the third clock signal CK SE in response to the second count signal QA reaching a predetermined value.

[0106] As described above, the third counter 420 may output the third count signal SC using the third clock signal CK SE . The light-emitting element 120-N may emit light based on the third count signal SC.

[0107] During the section from when the second count signal is first received by the clock controller 520 until the second count signal QA reaches a predetermined value (hereinafter referred to as the "emission preparation section"), the third counter 420 may also not generate the third count signal SC. In other words, the third counter 420 may not operate during the emission preparation section. In other words, the third counter 420 may be operated after the emission preparation section has elapsed. Since the third counter 420 is not operated during the section from when the second reset signal RS EM of high-level is received until the third clock signal CK SE is received, the third count signal SC may not be generated.

[0108] The bit generator 530 may output the emission end signal BW using the emission control signal ETC. The emission control signal ETC may be provided externally, such as from a set-top box, a host, a processor, a data processing device, etc. The emission control signal ETC may comprise grayscale information, emission end information, etc., but is not limited thereto.

[0109] The emission end signal BW may represent the end of the emission section. The end point of the emission section may vary depending on a value of an emission type signal.

[0110] Meanwhile, the light-emitting element 120-N may emit light based on the third count signal SC. The light-emitting element 120-N may emit light for the on-section in each period. The start point of the on-section may be determined using the third count signal SC. The end point of the on-section may be determined by the emission control signal ETC.

[0111] As the value of the emission end signal BW increases, the on-section may become longer, leading to increased luminance. As the value of the emission end signal BW increases, the temporal difference between the end point of the on-section and the start point of the on-section may become greater. Therefore, the emission end signal BW varies depending on the emission control signal ETC, and as the emission end signal BW varies, the on-section also varies, allowing for various grayscales (or luminance) to be expressed.

[0112] For example, when the emission end signal BW consists of 12 bits, it may be expressed as 4096 (=2 12< ) grayscales. In embodiments, the emission end signal BW may consist of a number of bits other than 12 bits.

[0113] In FIG. 4, a first count signal FC consisting of 8 bits, the second count signal QA consisting of 3 bits, the third count signal SC consisting of 12 bits, the emission control signal ETC consisting of 4 bits, and the emission end signal BW consisting of 12 bits are illustrated. However, this is merely an example, and each of the signals may be configured with a different number of bits.

[0114] Meanwhile, the comparator 540 may output an emission stop signal EM D using the third count signal SC and the emission end signal BW. The third count signal SC and the emission end signal BW may be configured with the same number of bits, for example, 12 bits. While the emission end signal BW has a specific value, the third count signal SC may be a value accumulated from 1. The third count signal SC may be accumulated over time and increase in value. Therefore, when a predetermined time has elapsed after the third count signal SC is initialized, the third count signal SC may become equal to the value of the emission end signal BW.

[0115] The comparator 540 may generate the emission stop signal EM D in response to the third count signal SC becoming equal to the value of the emission end signal BW, and output the generated emission stop signal EM D .

[0116] Meanwhile, the emission driving circuits 105A and 105B may drive the light-emitting element 120-N to emit light using the emission stop signal EM D .

[0117] Specifically, the driving device 100 of the embodiment may generate a driving control signal using the emission stop signal EM D , and transmit the generated driving control signal to the emission driving circuits 105A and 105B.

[0118] The emission driving circuits 105A and 105B may drive the light-emitting element 120-N to emit light during the on-section of each period in response to the driving control signal, thereby displaying an image having a desired grayscale (or luminance).

[0119] Meanwhile, the second control block 500 may comprise an OR gate operator 510. The OR gate operator 510 may perform an OR gate operation on the second clock signal CK S and the emission stop signal EM D and transmit the calculated output value to the clock controller 520.

[0120] Referring to FIGS. 6 and 7, the emission driving circuits 105A and 105B will be described in detail.

[0121] FIG. 6 is a block diagram illustrating an emission driving circuit according to an embodiment. FIG. 6 illustrates the emission driving circuits 105A and 105B and the plurality of light-emitting elements 120-1 to 120-N of FIG. 3.

[0122] Referring to FIG. 6, the emission driving circuit according to an embodiment may comprise a plurality of light-emitting circuits 130-1 to 130-N, a reference current generation circuit 110, a voltage generation circuit 150, etc. Each of the reference current generation circuit 110 and the voltage generation circuit 150 may be provided. The number of light-emitting circuits 130-1 to 130-N may be equal to or less than the number of light-emitting elements 120-1 to 120-N.

[0123] The plurality of light-emitting circuits 130-1 to 130-N may be included in the plurality of subpixels SP-1 to SP-N. The plurality of light-emitting circuits 130-1 to 130-N may drive the plurality of light-emitting elements 120-1 to 120-N of the plurality of subpixels SP-1 to SP-N to emit light of a plurality of colors. To this end, the plurality of light-emitting circuits 130-1 to 130-N in the plurality of subpixels SP-1 to SP-N may be electrically connected to the plurality of light-emitting elements 120-1 to 120-N.

[0124] The plurality of light-emitting circuits 130-1 to 130-N may generate a plurality of emission currents IEM1 to IEMN for supplying to the plurality of light-emitting elements 120-1 to 120-N. The emission currents IEM1 to IEMN may be referred to as driving currents.

[0125] For example, in the first subpixel SP-1, the first light-emitting circuit 130-1 may be electrically connected to the first light-emitting element 120-1, and may supply a first emission current IEM1 to the first light-emitting element 120-1 to drive at least the first light-emitting element 120-1 to emit a first color light. For example, in the second subpixel SP-2, the second light-emitting circuit 130-2 may be electrically connected to at least one second light-emitting element 120-2, and may supply a second emission current IEM2 to the second light-emitting element 120-2 to drive the second light-emitting element 120-2 to emit a second color light. In the third subpixel SP-3, the third light-emitting circuit 130-3 may be electrically connected to the third light-emitting element 120-3, and may supply a third emission current IEM3 to the third light-emitting element 120-3 to drive the third light-emitting element 120-3 to emit a third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light, but is not limited thereto.

[0126] In an embodiment, the light-emitting circuits 130-1 to 130-N may be implemented as integrated circuits (hereinafter referred to as ICs), chips, or packages, or may be formed directly on a panel using a semiconductor process. The plurality of light-emitting circuits 130-1 to 130-N may be implemented as individual ICs or may be implemented as a single integrated IC.

[0127] In an embodiment, the plurality of light-emitting elements 120-1 to 120-N in the plurality of subpixels SP-1 to SP-N may be included in the plurality of light-emitting circuits 130-1 to 130-N. That is, the plurality of light-emitting elements 120-1 to 120-N may be included in the plurality of light-emitting circuits 130-1 to 130-N, respectively, and may be implemented as an IC, chip, or package.

[0128] The plurality of light-emitting elements 120-1 to 120-N and the plurality of light-emitting circuits 130-1 to 130-N in the plurality of subpixels SP-1 to SP-N may be electrically connected between a first power line 141 and a second power line 142. For example, one side of each light-emitting element 120-1 to 120-N may be electrically connected to the first power line 141, the other side of each light-emitting element 120-1 to 120-N may be connected to one side of each light-emitting circuit 130-1 to 130-N, and the other side of each light-emitting circuit 130-1 to 130-N may be electrically connected to the second power line 142.

[0129] A first power voltage EVDD may be supplied to a first power line 141, and a second power voltage EVSS may be supplied to a second power line 142. The first power voltage EVDD may be a high-potential voltage and may be higher than the second power voltage EVSS, which is a low-potential voltage. The second power voltage EVSS may be, for example, grounded or 0 V, but is not limited thereto.

[0130] Meanwhile, the reference current generation circuit 110 may generate a reference current IREF. The reference current generation circuit 110 may be electrically connected to the plurality of subpixels SP-1 to SP-N.

[0131] The reference current IREF may be used to generate a plurality of emission currents IEM1 to IEMN flowing through the plurality of subpixels SP-1 to SP-N. That is, the plurality of emission currents IEM1 to IEMN flowing through the plurality of subpixels SP-1 to SP-N may be generated using the reference current IREF. In an embodiment, a current mirror method may be used to generate each of the plurality of emission currents IEM1 to IEMN corresponding to a reference current IREF in the plurality of subpixels SP-1 to SP-N. To this end, a current mirror circuit may be configured by a transistor of the reference current generation circuit 110 and a transistor of each of the plurality of emission circuits 130-1 to 130-N. The transistor of the reference current generation circuit 110 may be diode-connected. The transistor of the reference current generation circuit 110 and the transistor of each of the plurality of emission circuits 130-1 to 130-N may have their gates connected in common.

[0132] The reference current IREF and the plurality of emission currents IEM1 to IEMN may be constant currents. A constant current may mean that a current flows evenly even when the voltage applied to both terminals varies.

[0133] Each of the emission currents IEM1 to IEMN may be a current corresponding to the reference current IREF. The plurality of emission currents IEM1 to IEMN flowing through the plurality of subpixels SP-1 to SP-N may be equal to or greater than the reference current IREF. That is, the plurality of light-emitting circuits 130-1 to 130-N may generate emission currents IEM1 to IEMN equal to or greater than the reference current IREF according to a preset ratio, i.e., a copy ratio.

[0134] The copy ratio may be determined by designing the aspect ratio of each transistor of the plurality of light-emitting circuits 130-1 to 130-N differently from the aspect ratio of the transistor of the reference current generation circuit 110.

[0135] For example, when the aspect ratio of the transistor of each of the light-emitting circuits 130-1 to 130-N is equal to the aspect ratio of the transistor of the reference current generation circuit 110, the copy ratio is 1, and the emission currents IEM1 to IEMN generated by the plurality of light-emitting circuits 130-1 to 130-N may be equal to the reference current IREF. For example, when the aspect ratio of the transistor of each of the light-emitting circuits 130-1 to 130-N is greater than the aspect ratio of the transistor of the reference current generation circuit 110, the copy ratio has a value greater than 1, and thus the plurality of emission currents IEM1 to IEMN generated by the plurality of light-emitting circuits 130-1 to 130-N may be greater than the reference current IREF.

[0136] Therefore, by freely designing the aspect ratio of each of the transistors of the plurality of light-emitting circuits 130-1 to 130-N, the corresponding emission currents IEM1 to IEMN required for the corresponding subpixels SP-1 to SP-N can be accurately and easily obtained.

[0137] According to the embodiment, the aspect ratio of the transistor of each of the light-emitting circuits 130-1 to 130-N may be designed to be larger than the aspect ratio of the transistor of the reference current generation circuit 110. Therefore, by designing the aspect ratio of the transistor of the reference current generation circuit 110 to be small, a relatively small reference current IREF can be generated, so that the burden of generating the reference current IREF can be reduced, the size of the reference current generation circuit 110 can be reduced, and power consumption can be reduced. In addition, since the plurality of light-emitting currents IEM1 to IEMN of the plurality of light-emitting circuits 130-1 to 130-N have large values, the contrast ratio can be improved and high luminance can be implemented.

[0138] Meanwhile, the reference current generation circuit 110 may be electrically connected between a third power line 143 and the second power line 142. A third power voltage PVDD may be supplied to the third power line 143. The third power voltage PVDD is a high-potential voltage and may be similar to the first power voltage EVDD. For example, the third power voltage PVDD may be lower than the first power voltage EVDD, but is not limited thereto.

[0139] The second power line 142 may be commonly connected to the reference current generation circuit 110 and the plurality of light-emitting circuits 130-1 to 130-N. In this instance, the transistor of the reference current generation circuit 110 and the transistor of each of the plurality of light-emitting circuits 130-1 to 130-N constituting the current mirror circuit may commonly use the second power voltage EVSS supplied to the second power line 142. Therefore, since the transistor of the reference current generation circuit 110 and the plurality of transistors of the plurality of light-emitting circuits 130-1 to 130-N are simultaneously affected by the IR drop related to the second power voltage EVSS, they are not affected by the change in the plurality of emission currents IEM1 to IEMN of the plurality of subpixels SP-1 to SP-N, so that poor image quality can be prevented.

[0140] Meanwhile, while the second power line 142 is commonly connected to the reference current generation circuit 110 and the plurality of light-emitting circuits 130-1 to 130-N, the third power line 143 may be connected only to the reference current generation circuit 110 and not electrically connected to the plurality of light-emitting circuits 130-1 to 130-N. Accordingly, the reference current IREF is not affected by the IR drop associated with the second power voltage EVSS supplied to the second power line 142, thereby obtaining an accurate and constant reference current IREF.

[0141] Meanwhile, the plurality of light-emitting circuits 130-1 to 130-N may each use digital data and program signal to control the on-section of each of the plurality of light-emitting elements 120-1 to 120-N for each period, thereby enabling grayscale expression of an image. For example, the digital data may comprise a signal regarding the emission / non- emission of each light-emitting element 120-1 to 120-N. For example, the digital data may comprise "1" as a signal indicating the emission of each light-emitting element 120-1 to 120-N, and "0" as a signal indicating the non-emission of each light-emitting element 120-1 to 120-N, but is not limited thereto.

[0142] When each light-emitting element 120-1 to 120-N is turned on, each light-emitting element 120-1 to 120-N may emit light, and when each light-emitting element 120-1 to 120-N is turned off, each light-emitting element 120-1 to 120-N may stop emitting light. For example, the program signal may comprise grayscale information, etc., as a control signal for writing input data.

[0143] Each light-emitting element 120-1 to 120-N emits light according to digital data, and by controlling the on-section of each light-emitting element 120-1 to 120-N according to a program signal, an image having a desired grayscale may be displayed. The on-section may refer to a section during which each light-emitting element 120-1 to 120-N emits light. For example, a longer on-section may result in a higher grayscale image being displayed. For the same subpixel, for example, the first subpixel SP-1, the light-emitting element 120-1 emit light in different on-sections on a frame-by-frame basis, thereby displaying an image having different grayscales on a frame-by-frame basis.

[0144] In the drawing, the node G may be a node between the gate of the transistor of the reference current generation circuit 110 and the gate of each transistor of the plurality of light-emitting circuits 130-1 to 130-N constituting the current mirror circuit.

[0145] A predetermined voltage may be generated at the node G through the transistor of the reference current generation circuit 110 by using the reference current IREF generated in the reference current generation circuit 110. A plurality of emission currents IEM1 to IEMN may be generated in the transistors of the plurality of light-emitting elements 120-1 to 120-N by using the predetermined voltage. In this instance, as described above, the aspect ratio of the transistor of each of the light-emitting elements 120-1 to 120-N is designed to be the same as or different from the aspect ratio of the transistor of the reference current generation circuit 110, so that the same or different emission currents IEM1 to IEMN may be generated in the transistor of each of the plurality of light-emitting elements 120-1 to 120-N based on the voltage on the node G.

[0146] Meanwhile, in an embodiment, the plurality of subpixels SP-1 to SP-N may be driven simultaneously. That is, the plurality of subpixels SP-1 to SP-N are driven simultaneously within one frame, and the on-sections of the plurality of light-emitting elements 120-1 to 120-N of the plurality of subpixels SP-1 to SP-N may be controlled so that images of different grayscales may be displayed on the plurality of subpixels SP-1 to SP-N.

[0147] Meanwhile, the voltage generation circuit 150 may provide a reference voltage VREF to the reference current generation circuit 110. The voltage generation circuit 150 may be connected to the reference current generation circuit 110 and may provide the reference voltage VREF to the reference current generation circuit 110. The reference current generation circuit 110 may generate a reference current IREF based on the reference voltage VREF.

[0148] FIG. 7 is a circuit diagram illustrating an emission driving circuit according to an embodiment. While the drawing illustrates one subpixel SP-1 among the plurality of subpixels SP-1 to SP-N illustrated in FIG. 6, the remaining subpixels SP-2 to SP-N may also have the same or similar circuit structure as the corresponding subpixel SP-1.

[0149] Referring to FIG. 7, the emission driving circuit according to the embodiment may comprise a voltage generation circuit 150, a reference current generation circuit 110, a light-emitting circuit 130-1, and at least one light-emitting element 120-1.

[0150] The voltage generation circuit 150 may comprise a plurality of first transistors T31 to T33 connected in series between a third power line 143 and a fourth power line 144. Although three first transistors T31 to T33 are illustrated in the drawing, four or more may be provided.

[0151] The first transistors T31 to T33 may be PMOS transistors, but may also be NMOS transistors.

[0152] The plurality of first transistors T31 to T33 may each be diode-connected. Each diode-connected first transistor T31 to T33 may be applied with a predetermined voltage corresponding to a threshold voltage. Accordingly, a constant current may flow to the voltage generation circuit 150 corresponding to a voltage obtained by adding a predetermined voltage equal to the number of first transistors T31 to T33.

[0153] Meanwhile, one of the plurality of first transistors T31 to T33, i.e., the transistor T31, may form a current mirror circuit with a fourth transistor T24 of the reference current generation circuit 110. That is, a gate of one transistor T31 among the plurality of first transistors T31 to T33 and a gate of the fourth transistor T24 of the reference current generation circuit 110 may be commonly connected to the node X. One transistor T31 among the plurality of first transistors T31 to T33 may output a reference voltage VREF to the node X using a constant current. The fourth transistor T24 of the reference current generation circuit 110 may generate a reference current IREF based on the reference voltage VREF.

[0154] As the number of the plurality of first transistors T31 to T33 of the voltage generation circuit 150 increases, the reference voltage VREF increases, and thus the reference current IREF generated by the reference current generation circuit 110 may also increase. Therefore, when the target reference current IREF to be obtained from the reference current generation circuit 110 is determined, the number of the plurality of first transistors T31 to T33 of the voltage generation circuit 150 and the threshold voltage, etc. may be determined so that the target reference current IREF is generated.

[0155] Meanwhile, the reference current generation circuit 110 may comprise a first transistor T21, first control switches 113-1 and 113-2, a fourth transistor T24, etc.

[0156] The first control switches 113-1 and 113-2 may comprise a second transistor T22 and a third transistor T23. One of the second transistor T22 and the third transistor T23 may be omitted. The second transistor T22 may be connected between the first transistor T21 and the second power line 142, and the third transistor T23 may be connected between the first transistor T21 and the fourth transistor T24. The fourth transistor T24 may be connected between the third power line 143 and the third transistor T23.

[0157] For example, the first transistor T21 and the second transistor T22 may be NMOS transistors, and the third transistor T23 and the fourth transistor T24 may be PMOS transistors, but is not limited thereto.

[0158] The second transistor T22 and the third transistor T23 may be turned on or off simultaneously by first control signals D1 and D2. When the second transistor T22 and the third transistor T23 are in an open state by the first control signals D1 and D2, the reference current IREF does not flow to the first transistor T1, which may mean that the reference current IREF is turned off. When the second transistor T22 and the third transistor T23 are in a closed state by the first control signals D1 and D2, the reference current IREF may flow to the first transistor T21, which may mean that the reference current IREF is turned on. A section during which the reference current IREF flows to the first transistor T21 may be defined as an on-section. A section during which the reference current IREF does not flow through the first transistor T21 may be defined as an off-section.

[0159] For example, the period may be divided into an on-section and an off-section. The period may be, for example, one frame, but is not limited thereto. During the on-section, the second transistor T22 and the third transistor T23 are in a closed state, allowing the reference current IREF to flow through the first transistor T21. During the off-section, the second transistor T22 and the third transistor T23 are in an open state, preventing the reference current IREF from flowing through the first transistor T21.

[0160] Although not illustrated, the reference current generation circuit 110 may comprise a reference current control circuit capable of controlling the reference current IREF. The reference current control circuit may comprise a plurality of constant current sources and a plurality of selection switches. The plurality of constant current sources may be connected to the first transistor T21. The fourth transistor T24 may be one of the plurality of constant current sources.

[0161] A plurality of constant current sources may be connected in parallel to each other to generate constant currents, respectively. A plurality of selection switches may be connected in series with the plurality of constant current sources to select at least one constant current source among the plurality of constant current sources. In this instance, a reference current IREF may be generated based on at least one constant current selectively generated from the plurality of constant current sources. For example, the reference current IREF may be the sum of the at least one selected constant current source.

[0162] A first transistor T21 may be connected between a second transistor T22 and a third transistor T23, and may form a current mirror circuit with the first transistor T11 of the light-emitting circuit 130-1.

[0163] A first transistor T21 of the reference current generation circuit 110 may be diode-connected, and a gate of the first transistor T21 of the reference current generation circuit 110 and a gate of the first transistor T11 of the light-emitting circuit 130-1 may be commonly connected to the node G. Additionally, a source of the first transistor T21 of the reference current generation circuit 110 and a source of the first transistor T11 of the light-emitting circuit 130-1 may be commonly connected to the second power line 142.

[0164] In this instance, the reference current IREF flowing through the reference current generation circuit 110 may be expressed by Equation 2, and the emission current IEM1 flowing through the light-emitting circuit 130-1 may be expressed by Equation 3. IREF = μ ⋅ C ox ⋅ W D L D ⋅ V G − EVSS − V TH 2 2 IEM = μ ⋅ C ox ⋅ W E L E ⋅ V G − EVSS − V TH 2 2

[0165] IEM represents first transistor. From Equation 2, the voltage V G of the node G may be calculated. That is, the first transistor T21 of the reference current generation circuit 110 may be a conversion element that converts the reference current IREF into the voltage V G of the node G.

[0166] The first transistor T11 of the light-emitting circuit 130-1 may be a conversion element that converts the voltage V G of the node G into the emission current IEM1.

[0167] From Equations 2 and 3, when the process constants µ, Cox, and the aspect ratios W D / L D and W E / L E are the same in the first transistor T21 of the reference current generation circuit 110 and the first transistor T11 of the light-emitting circuit 130-1, the reference current IREF and the emission current IEM1 may be the same. In this instance, the reference current IREF may be copied as is and generated as the emission current IEM1 in the light-emitting circuit 130-1.

[0168] Alternatively, when the process constants µ and Cox are the same in the first transistor T21 of the reference current generation circuit 110 and the first transistor T11 of the light-emitting circuit 130-1 but the aspect ratios W D / L D and W E / L E are different, the reference current IREF and the emission current IEM1 may be different. For example, when the aspect ratio W E / L E of the first transistor T11 of the light-emitting circuit 130-1 is greater than the aspect ratio W D / L D of the first transistor T21 of the reference current generation circuit 110, the emission current IEM1 may be greater than the reference current IREF. For convenience, the aspect ratio W D / L D of the first transistor T21 of the reference current generation circuit 110 may be referred to as a first aspect ratio, and the aspect ratio W E / L E of the first transistor T11 of the light-emitting circuit 130-1 may be referred to as a second aspect ratio.

[0169] Therefore, by designing the first aspect ratio W D / L D to be small, a small reference current IREF may be generated in the reference current generation circuit 110. Accordingly, the burden of generating the reference current can be reduced, the size of the reference current generation circuit 110 can be reduced, and power consumption can be reduced.

[0170] Furthermore, by designing the second aspect ratio W E / L E to be large, a large emission current IEM1 may be generated in the light-emitting circuit 130-1. Accordingly, since the light-emitting element 120-1 emits light through the large emission current IEM1, the contrast ratio can be improved and high luminance can be achieved.

[0171] Meanwhile, the light-emitting circuit 130-1 may comprise a first transistor T11, second control switches SW11 and SW12, and a digital storage 135-1.

[0172] The digital storage 135-1 may generate second control signals C11 and C12 for switching the second control switches SW11 and SW12 using digital data DM-1.

[0173] The second control switches SW11 and SW12 may be connected to the first transistor T11 and may control the on / off of the emission current IEM1. The switches may comprise a first-first control switch SW11 and a first-second control switch SW12. The first-first control switch SW11 may be connected between the first transistor T11 and the second power line 142, and the first-second control switch SW12 may be connected between the light-emitting element 120-1 and the first transistor T11.

[0174] The first-first control switch SW11 and the first-second control switch SW12 may be turned on or off simultaneously according to the second control signals C11 and C12. When the first-first control switch SW11 and the first-second control switch SW12 are in an open state by the second control signals C11 and C12, the emission current IEM1 does not flow to the first transistor T11, which may mean that the emission current IEM1 is turned off. When the first-first control switch SW11 and the first-second control switch SW12 are in a closed state by the second control signals C11 and C12, the emission current IEM1 flows to the first transistor T11, which may mean that the emission current IEM1 is turned on. The section during which the emission current IEM1 flows through the first transistor T11 may be defined as an on-section. The section during which the emission current IEM1 does not flow through the first transistor T11 may be defined as an off-section.

[0175] The first control signals D1 and D2 and the second control signals C11 and C12 may be included in the driving control signal generated by the driving device (100 of FIGS. 3 and 4), but is not limited thereto.

[0176] For example, each period may be divided into an on-section and an off-section. A period may be, for example, one frame, but is not limited thereto. During the on-section, the first-first control switch SW11 and the first-second control switch SW12 are closed, allowing the emission current IEM1 to flow through the first transistor T11. During the off-section, the first-first control switch SW11 and the first-second control switch SW12 are in the open state, so that the emission current IEM1 may not flow to the first transistor T11.

[0177] For convenience of explanation, the on-section during which the reference current IREF flows to the first transistor T21 of the reference current generation circuit 110 may be referred to as a first on-section SS1, and the on-section during which the emission current IEM1 flows to the first transistor T11 of the light-emitting circuit 130-1 may be referred to as a second on-section SS2.

[0178] In the above, the driving device 100 and the plurality of light-emitting elements 120-1 to 120-N are considered as a single block (or module), and the display device or display panel according to the embodiment may be configured as a plurality of blocks.

[0179] The above detailed description should not be construed as limiting in all respects and should be considered illustrative. The scope of the embodiment should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent range of the embodiment are included in the scope of the embodiment.

Claims

1. A driving device that is configured to drive a light-emitting element using at least two clock signals having different clock speeds.

2. The driving device of claim 1, wherein the at least two clock signals comprise a first clock signal and a second clock signal, and wherein a first clock speed of the first clock signal is at least 24 times greater than a second clock speed of the second clock signal.

3. The driving device of claim 2, wherein an input of data for emitting light from the light-emitting element is configured to be controlled using the first clock signal, and wherein an emission time of the light-emitting element is configured to be controlled using the second clock signal.

4. The driving device of claim 1, comprising: a first counting block configured to count based on the first clock signal; a first control block configured to control the input of the data using the counted value; a second counting block configured to count based on the second clock signal; and a second control block configured to control an emission time of the light-emitting element using the counted value.

5. The driving device of claim 4, wherein the first counting block comprises: a first counter configured to output a first count value for controlling the input of the data using the first clock signal and a first reset signal, wherein the first reset signal represents a reference time for controlling the input of the data, and wherein the first control block is configured to control the input of the data using the first count value.

6. The driving device of claim 4, wherein the second counting block comprises: a second counter configured to output a second count value using the second clock signal and a second reset signal; and a third counter configured to output a third count value for emitting light from the light-emitting element using the second clock signal, wherein the light-emitting element is prepared to emit light by the second count value, and wherein the second control block is configured to emit light from the light-emitting element after the second reset signal is received and a predetermined time has elapsed by using the third count value.

7. The driving device of claim 6, wherein the second reset signal represents a reference time for emitting light from the light-emitting element, and wherein the first control block is configured to output the second reset signal based on the first count value.

8. The driving device of claim 6, wherein the second control block comprises: a clock controller configured to output a third clock signal using the second clock signal when the second count value is a predetermined value; a bit generator configured to output an emission end signal using an emission control signal; and a comparator configured to output an emission stop signal using the third count value and the emission end signal, and wherein the emission end signal represents an end point in the emission time of the light-emitting element.

9. The driving device of claim 8, wherein the third counter is configured to output the third count value using the third clock signal.

10. The driving device of claim 8, wherein the emission stop signal is configured to be generated in response to the third count value becoming equal to the value of the emission end signal.

11. The driving device of claim 6, further comprising: an emission driving circuit configured to drive the light-emitting element to emit light using the emission stop signal.

12. A display device comprising a plurality of subpixels, comprising: at least one light-emitting element for each of the plurality of subpixels; and a driving device configured to drive at least one light-emitting element using at least two clock signals having different clock speeds.

13. The display device of claim 12, wherein the at least two clock signals comprise a first clock signal and a second clock signal, and wherein a first clock speed of the first clock signal is at least 24 times greater than a second clock speed of the second clock signal.

14. The display device of claim 13, wherein an input of data for emitting light from the light-emitting element is configured to be controlled using the first clock signal, and wherein an emission time of the light-emitting element is configured to be controlled using the second clock signal.

Images