Display method and display device

Abstract

The present disclosure provides a display method and a display apparatus, and belongs to the field of display technology. In the display method of the present disclosure, a physical resolution of the display panel is M1×N1; and the display method includes: converting, by the main board, first original image data sent by the graphics card into first image data, and sending the first image data to the timing controller; a resolution of the first image data is M2×N2; and N2:N1=a:b≤1; and providing, by the timing controller, P clock signals to a gate driving circuit in the display panel, and providing a data control signal to a source driving circuit; where P=i×b; the gate driving circuit selectively turns on rows of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal, and writes the display data of a (b×j-1)-th row and a (bxj+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; where j is a positive integer greater than or equal to 1, and b×j+1≤N1.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology, and in particular to a display method and a display apparatus.BACKGROUND

[0002] An improvement in performance of a current electronic sports display is mainly the synchronous improvement of resolution and refresh rate, thereby achieving a better user experience. However, it is inevitable that the synchronous improvement of resolution and refresh rate may cause charging time of pixels to be rapidly shortened. Although the above problem may be alleviated by adjusting the panel process, changing a design material (from a-Si to Oxide) and adopting an IC with a stronger driving capability, the problem of insufficient charging still exists. In addition, with the synchronous improvement of refresh rate and resolution, in order to support such a high display specification, a display card and a scalar board are also required to be synchronously improved to exhibit the excellent display performance, which often increases the cost of the user and affects the market sales volume.SUMMARY OF THE INVENTION

[0003] The present disclosure is directed to at least one of the technical problems of the prior art, and provides a display method and a display apparatus.

[0004] The embodiment of the present disclosure provides a display method applied to a display apparatus, and the display apparatus includes a graphics card, a main board, a timing controller and a display panel; a physical resolution of the display panel is M1×N1; and the display method includes: converting, by the main board, first original image data sent by the graphics card into first image data, and sending the first image data to the timing controller; a resolution of the first image data being M2×N2; and N2:N1=a:b≤1; and providing, by the timing controller, P clock signals to a gate driving circuit in the display panel, and providing a data control signal to a source driving circuit; where P=i×b; and i is a positive integer greater than or equal to 1; the gate driving circuit selectively turns on each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal, and writes the display data of a (b×j-1)-th row and a (b×j+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; where j is a positive integer greater than or equal to 1, and b×j+1≤N1.

[0005] In some embodiments, start time of an active level of a (k+1)-th clock signal is earlier than end time of an active level of a k-th clock signal; where K is in a range from 1 to P-1; and in the P clock signals, except for a (b×j)-th clock signal, a phase difference between start times of the active levels of the adjacent clock signals is 1H1, a phase difference between start times of the active levels of the (b×j)-th clock signal and a (b×j-1)-th clock signal is A, and a phase difference between start times of the active levels of a (b×j+1)-th clock signal and the (b×j)-th clock signal is B; where A+B=H1; and H1 is a phase difference between start times of two adjacent active levels of the data control signal.

[0006] In some embodiments, the phase difference between the start times of the active levels of the (b×j)-th clock signal and the (b×j-1)-th clock signal is H1 / 2, and the phase difference between the start times of the active levels of the (b×j+1)-th clock signal and the (b×j)-th clock signal is H1 / 2.

[0007] In some embodiments, the clock signals provided by the timing controller to the gate driving circuit and the data control signal provided to the source driving circuit satisfy: except for the (j×b)-th row of sub-pixels, end time of writing data signals into the sub-pixels by the source driving circuit is earlier than end time of an active level of a gate driving signal loaded to the sub-pixels.

[0008] In some embodiments, the clock signals provided by the timing controller to the gate driving circuit and the data control signal provided by the timing controller to the source driving circuit satisfy: except for the (j×b)-th row of sub-pixels, a phase difference between the end time of writing the data signals into the sub-pixels by the source driving circuit and the end time of the active level of the gate driving signal loaded to the sub-pixels is H1 / 2, and H1 is a phase difference between start times of two adjacent high levels of the data control signal.

[0009] In some embodiments, the clock signals provided by the timing controller to the gate driving circuit satisfy: a duration during which gate driving signals loaded to adjacent rows of sub-pixels are simultaneously in an active level is not less than 2H1, and H1 is a phase difference between start times of two adjacent high levels of the data control signal.

[0010] In some embodiments, a:b=3:4 and P=4i; except for a 4e-th clock signal, start time of active levels of the other clock signals sequentially differs by 1H1; where e is a positive integer in a range from 1 to i; H1 is a phase difference between start times of two adjacent active levels of the data control signal; and a phase difference between start times of active levels of the 4e-th clock signal and a (4e-1)-th clock signal is H1 / 2.

[0011] In some embodiments, a:b =2:3 and P =3i; except for a 3e-th clock signal, start time of active levels of the other clock signals sequentially differs by 1H1; where e is a positive integer in a range from 1 to i; H1 is a phase difference between start times of two adjacent active levels of the data control signal; and a phase difference between start times of active levels of the 3e-th clock signal and a (3e-1)-th clock signal is H1 / 2.

[0012] In some embodiments, a duty ratio of an active level of each clock signal is 50%, a duration of the active level of the clock signal is 3H1; and H1 is a phase difference between start times of two adjacent active levels of the data control signal.

[0013] In some embodiments, M1 is equal to M2.

[0014] In some embodiments, the display method further includes: receiving a display mode selection instruction, and sending, by the graphics card, the received first original image data to the main board with the display mode selection instruction indicating a first display mode; a resolution of the first original image data being M3×N3; and M3<M2; and the converting, by the main board, the first original image data sent by the graphics card into the first image data, includes: performing, by the main board, a horizontal interpolation process on the first original image data to obtain the first image data.

[0015] In some embodiments, the display method further includes: receiving the display mode selection instruction, and sending, by the graphics card, received second original image data to the main board with the display mode selection instruction indicating a second display mode; converting, by the main board, the second original image data into second image data; where a resolution of the second image data is M4×N4; and N4:N1=1:2; a refresh frequency of the second image data being greater than a refresh frequency of the first image data; providing, by the timing controller, the plurality of clock signals to the gate driving circuit in the display panel and providing the data control signal to the source driving circuit; selectively turning on, by the gate driving circuit, the rows of sub-pixels in the display panel according to the plurality of clock signals, writing, by the source driving circuit, the second image data into sub-pixels in even-numbered rows row by row according to the data control signal, and writing display data of sub-pixels in two even-numbered rows adjacent to each odd-numbered row into sub-pixels in the odd-numbered row; or selectively turning on, by the gate driving circuit, the rows of sub-pixels in the display panel according to the plurality of clock signals, writing, by the source driving circuit, the second image data into sub-pixels in odd-numbered rows row by row according to the data control signal, and writing display data of sub-pixels in two odd-numbered rows adjacent to each even-numbered row into sub-pixels in the even-numbered row.

[0016] In some embodiments, in the second display mode, start time of the active levels of the plurality of clock signals sequentially differs by 1H2, and H2 is a half of a phase difference between start times of two adjacent active levels of the data control signal.

[0017] In some embodiments, in the second display mode, a duration of the active level of each clock signal is 4H2, and a duty ratio of the active level of the clock signal is 50%; and the plurality of clock signals satisfy that a duration during which the adjacent rows of sub-pixels are simultaneously turned on is 3H2.

[0018] The embodiment of the present disclosure provides a display apparatus, including a graphics card, a main board, a gate driving circuit, a source driving circuit and a display panel; and a physical resolution of the display panel is M1×N1; the main board is configured to convert first original image data sent by the graphics card into first image data, and send the first image data to a timing controller; and a resolution of the first image data is M2×N2; and N2:N1=a:b≤1; and the timing controller is configured to provide P clock signals to the gate driving circuit in the display panel, and provide a data control signal to the source driving circuit; where P=i×b; and i is a positive integer greater than or equal to 1; and the gate driving circuit selectively turns on each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal, and writes the display data of a (b×j-1)-th row and a (b×j+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; where j is a positive integer greater than or equal to 1, and b×j+1≤N1. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a schematic diagram of a display apparatus according to an embodiment of the present disclosure. FIGS. 2A and 2B are exemplary structural diagrams of a gate driving circuit according to an embodiment of the present disclosure. FIG. 3 is a timing diagram illustrating signals in a display method according to an embodiment of the present disclosure. FIG. 4 is a flowchart of a display method according to an embodiment of the present disclosure. FIG. 5 is a timing diagram of a display method according to an embodiment of the present disclosure. FIG. 6 is a flowchart of a display method according to an embodiment of the present disclosure. FIG. 7 is a timing diagram of a display method in a second display mode according to an embodiment of the present disclosure. FIG. 8 is a timing diagram of another display method in a second display mode according to an embodiment of the present disclosure. DETAIL DESCRIPTION OF THE EMBODIMENTS

[0020] In order to enable one of ordinary skill in the art to better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and the detailed description.

[0021] Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and the like used in the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used for distinguishing one element from another. Further, the term "a", "an", "the", or the like used herein does not denote a limitation of quantity, but rather denotes the presence of at least one element. The term "comprising", "including", or the like means that the element or item preceding the term contains the element or item listed after the term and its equivalent, but does not exclude other elements or items. The term "connected", "coupled", or the like is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect connections. The terms "upper", "lower", "left", "right", and the like are used only for indicating relative positional relationships, and when the absolute position of an object being described is changed, the relative positional relationships may also be changed accordingly.

[0022] FIG. 1 is a schematic diagram of a display apparatus according to an embodiment of the present disclosure; as shown in FIG. 1, a display apparatus 100 includes a display panel including a plurality of sub-pixels arranged in an M1×N1 array, where N1 and M1 each are an integer greater than 1.

[0023] The display apparatus 100 may further include a gate driving circuit 10, and the gate driving circuit 10 is connected to the plurality of sub-pixels. The gate driving circuit 10 may be connected to the N1 rows of sub-pixels through a plurality of gate signal lines extending in a first direction (an x direction in FIG. 1). For example, the gate driving circuit 10 is connected to a first row of sub-pixels through a first gate signal line to provide a first gate driving signal G1 to the first row of sub-pixels, connected to a second row of sub-pixels through a second gate signal line to provide a second gate driving signal G2 to the second row of sub-pixels, and so on. The first row of sub-pixels is turned on in response to the received first gate driving signal G1, the second row of sub-pixels is turned on in response to the received second gate driving signal G2, and so on.

[0024] In some embodiments, the gate driving circuit 10 may scan the N1 rows of sub-pixels row by row or rows by rows. For example, the gate driving circuit 10 may scan one row of sub-pixels at a time, for example, sequentially generate N1 gate driving signals G1, G2 and ...... GN to sequentially turn on the first row of sub-pixels P, the second row of sub-pixels P, ... ..., and the N1-th row of sub-pixels P. The gate driving circuit 10 may alternatively scan two or more rows of sub-pixels P at a time. For example, the gate driving circuit 10 may simultaneously generate the first gate driving signal G1 and the second gate driving signal G2 to simultaneously turn on the first row of sub-pixels and the second row of sub-pixels, and then the gate driving circuit 10 may simultaneously generate a third gate driving signal G3 and a fourth gate driving signal G4 to simultaneously turn on a third row of sub-pixels and a fourth row of sub-pixels, and so on. In some embodiments, the gate driving circuit 10 may scan the N1 rows of sub-pixels every other at least one row to sequentially turn on some rows of sub-pixels. For example, the gate driving circuit 10 may sequentially turn on odd-numbered rows of sub-pixels (e.g., sequentially turn on the first row of sub-pixels, the third row of sub-pixels, a fifth row of sub-pixels, and so on), or sequentially turn on even-numbered rows of sub-pixels (e.g., sequentially turn on the second row of sub-pixels, the fourth row of sub-pixels, a sixth row of sub-pixels, and so on).

[0025] The display apparatus 100 may further include a source driving circuit 20, and the source driving circuit 20 is connected to the plurality of sub-pixels. For example, the source driving circuit 20 may be respectively connected to the M1 columns of sub-pixels P through a plurality of data lines extending in a second direction (a y direction in FIG. 1). For example, the source driving circuit 20 may be connected to a first column of sub-pixels through a first data line to provide a first data signal D1 to the first column of sub-pixels, connected to a second column of sub-pixels through a second data line to provide a second data signal D2 to the second column of sub-pixels, and so on.

[0026] For example, when the first row of sub-pixels are turned on, the source driving circuit 20 may provide M1 data signals D11, D12, ......, and D1M for the first row to the M1 sub-pixels of the first row through M1 data lines, respectively; when the second row of sub-pixels are turned on, the source driving circuit 20 may respectively provide M1 data signals D21, D22, ......, and D2M1 for the second row to the M1 sub-pixels in the second row through the data lines, and so on. Alternatively, embodiments of the present disclosure are not limited thereto, which will be described in further detail below.

[0027] In some embodiments, the display apparatus 100 may further include a graphics card 50, a main board 40, and a timing controller 30, where the main board 40 may be a scalar main board 40, the graphics card 50 is used for image formation, and the main board 40 is used for data transmission. For example, the graphics card 50 transmits image data to the main board 40, and the main board 40 transmits the image data to the timing controller 30.

[0028] The timing controller 30 is connected to the gate driving circuit 10 and the source driving circuit 20, and may provide related control signals to the gate driving circuit 10 and the source driving circuit 20. For example, the timing controller 30 may provide a data control signal TP to the source driving circuit 20, and the source driving circuit 20 may output the data signals for the rows under the control of the data control signal TP. The timing controller 30 may further provide other control signals to the source driving circuit 20, including, but not limited to, a row data start signal, a data sync signal, a data inversion signal, and the like. The timing controller 30 may further provide various control signals, including, but not limited to, a frame start signal, a clock signal, and the like required by the gate driving circuit 10, to the gate driving circuit 10. In the present disclosure, as an example, an active level of each signal is a high level, and correspondingly an inactive level is a low level.

[0029] FIGS. 2A and 2B are exemplary structural diagrams of a gate driving circuit according to an embodiment of the present disclosure. As shown in FIGS. 2A and 2B, the gate driving circuit includes a plurality stages of cascaded shift registers GOA1, GOA2, ... ..., and GOAN. For example, for an ultra-high definition (QHD: a resolution of 2560×1440) display panel, the number of horizontal pixels is 2560, the number of vertical pixels is 1440. When a plurality of sub-pixels included in each pixel are arranged in the horizontal direction, the display panel includes 1440 rows of sub-pixels, and in the case where the display panel includes the 1440 rows of sub-pixels and each shift register corresponds to one row of sub-pixels, the number of shift registers included in the gate driving circuit may be 1440.

[0030] FIG. 2A shows a first stage of shift register unit GOA1 to a ninth stage of shift register unit GOA9. As shown in FIG. 2A, STV1 represents a frame start signal, and when the gate driving circuit is connected to 8 clock signals CLK, input terminals Input of the first stage of shift register unit GOA1 to the fourth stage of shift register unit GOA4 may be connected to the frame start signal terminal STV1. After the fourth stage of shift register unit GOA4, an input terminal Input of the n-th stage of shift register unit GOAn is connected to an output terminal of an (n-4)-th stage of shift register unit GOA(n-4), where 5≤n≤N. For example, the output terminal of the shift register unit GOA1 is connected to the input terminal of the shift register unit GOA5, the output terminal of the shift register unit GOA2 is connected to the input terminal of the shift register unit GOA6, the output terminal of the shift register unit GOA3 is connected to the input terminal of the shift register unit GOA7, the output terminal of the shift register unit GOA4 is connected to the input terminal of the shift register unit GOA8, the output terminal of the shift register unit GOA5 is connected to the input terminal of the shift register unit GOA9, and so on. A reset terminal RST of the n-th stage of shift register unit GOAn is connected to the output terminal OUT of the (n+4)-th stage of shift register unit GOA(n+4), where 1≤n≤N-4. FIG. 2B shows a last stage of shift register unit GOA1440 and a dummy shift register unit (Dummy GOA). As shown in FIG. 2B, the last 4 rows of shift register units GOA may be reset by 4 rows of dummy shift register units, for example, the Dummy GOA1 (Dum1) resets the shift register unit GOA1437, the Dummy GOA2 (Dum2) reset the shift register unit GOA1438, and so on, and each Dummy GOA may be reset by the frame start signal STV1.

[0031] It should be noted that in the above example, as an example, the reset terminal RST of the n-th stage of shift register unit GOAn is connected to the output terminal OUT of the (n+4)-th stage of shift register unit GOA(n+4). In some examples, alternatively, the reset terminal RST of the n-th stage of shift register unit GOAn may be connected to the output terminal OUT of the (n+5)-th stage of shift register unit GOA(n+5), where 1≤n≤N-5. Accordingly, the gate driving circuit includes 5 dummy shift register units, and the last 5 rows of shift register units GOA may be reset by the 5 rows of dummy shift register units. For example, the Dummy GOA1 (Dum1) reset the shift register unit GOA1436, the Dummy GOA2 (Dum2) reset the shift register unit GOA1437, and so on. That is, the dummy shift register units may be flexibly provided according to the reset relationship between the shift register units GOA. The gate driving circuit shown in FIGS. 2A and 2B employs 8 clock signals CLK1 to CLK8, a clock signal terminal CLK of the first stage of shift register unit GOA1 is connected to receive the first clock signal CLK1, a clock signal terminal CLK of the second stage of shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on, and a clock signal terminal CLK of the eighth stage of shift register unit GOA8 is connected to receive the eighth clock signal CLK8. In a similar manner, the ninth stage of shift register unit GOA9 to the sixteenth stage of shift register unit GOA16 are respectively connected to receive the first clock signal CLK1 to the eighth clock signal CLK8.

[0032] Each stage of the shift register units GOA1, GOA2, ......, GOAN may generate an output signal at its output terminal OUT as a gate driving signal (or a gate scanning signal) under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first stage of shift register unit GOA1 generates a first gate driving signal G1, the second stage of shift register unit GOA2 generates a second gate driving signal G2, and so on. In a cascade mode, a gate driving signal generated by one stage of shift register unit may be shifted relative to a gate driving signal generated by the other stage of shift register unit.

[0033] The above is merely an example description of the display apparatus of the embodiment of the present disclosure, and the structure of the display apparatus of the embodiment of the present disclosure is not limited thereto, and may have other structure as needed. For example, the display apparatus may be a display apparatus based on a liquid crystal display (LCD) technology, or a display apparatus based on an organic light emitting diode (OLED) display technology. The gate driving circuit of the display apparatus may adopt a cascade mode different from that shown in FIGS. 2A and 2B, for example, may be cascaded in a different mode with 10 or 12 clock signals.

[0034] FIG. 3 is a timing diagram illustrating signals of a display method according to an embodiment of the present disclosure. The timing diagram illustrating signals of FIG. 3 will be described below by taking the display apparatus in FIGS. 1, 2A and 2B as an example. As shown in FIG. 3, during each frame of image is displayed, under control of the clock signals CLK1 to CLK8, the gate driving circuit 10 sequentially generates the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, the fourth gate driving signal G4 at a preset time interval, and so on. A difference between start time points of writing data signals into two adjacent rows of sub-pixels is H. In FIG. 3, a duration of an active level of each gate driving signal is 4H, for example.

[0035] For the first row of sub-pixels, the first gate driving signal G1 is at a high level in time periods T1 to T4, so that the first row of sub-pixels are in an ON state, where the time periods T1 to T4 are all H in length, that is, the first row of sub-pixels are turned on for a duration of 4H. In the period T4, a first high-level pulse of the data control signal TP comes, thereby controlling the source driving circuit 20 to apply a data signal (also referred to as a first row data signal) DATA1 for the first row to the first row of sub-pixels in the ON state. The first row data signal DATA1 may include M1 data signals D11, D12, ......, D1M for the M1 sub-pixels in the first row, respectively, where a data signal D11 is provided to the sub-pixel in the first row and the first column, a data signal D12 is provided to the sub-pixel in the first row and the second column, ... ..., and a data signal D1M is provided to the sub-pixel in the first row and the M1-th column.

[0036] Similarly, for the second row of sub-pixels, the second gate driving signal G2 is at a high level in time periods T2 to T5, so that the second row of sub-pixels are in an ON state. In the period T4, a second high level pulse of the data control signal TP comes, thereby controlling the source driving circuit 20 to apply a data signal (also referred to as a second row data signal) DATA2 for the second row of sub-pixels to the second row of sub-pixels in the ON state. The second row data signal DATA2 may include M1 data signals D21, D22, ......, D2M for the M1 sub-pixels in the second row, respectively, where a data signal D21 is provided to the sub-pixel in the second row and the first column, a data signal D22 is provided to the sub-pixel in the second row and the second column, ... ..., and a data signal D2M is provided to the sub-pixel in the second row and the M1-th column. This may be done for other rows of sub-pixels.

[0037] According to display of the above one frame of image, a refresh frequency of the QHD display panel is 180 Hz. The refresh frequency of the QHD display panel is increased from 180Hz to 240Hz, that is, increased by 4 / 3 times. Specifically, when an original image data received by the graphics card 50 is adjusted from 2560×1440×180Hz to 1920×1080×240Hz and is output as 2560×1080×240Hz after the processing of the scalar main board 40, for image data received by the timing controller 30, the reception bandwidth remains unchanged due to 2560×1440×180=2560×1080×240. Therefore, the refresh frequency is increased from 180Hz to 240 Hz. However, the timing controller 30 actually receives 1080 display data rows but the display panel includes 1440 rows of physical sub-pixels, which results in missing display data on the display panel. In view of this problem, the present disclosure provides the following technical solutions.

[0038] The embodiment of the present disclosure provides a display method, which may also be applied to the display apparatus shown in FIG. 1, where a physical resolution of the display panel is M1×N1, and as shown in FIG. 4, the display method includes steps S10 to S20: Step S10 includes converting, by the main board 40, first original image data sent by the graphics card 50 into first image data, and sending the first image data to the timing controller 30; a resolution of the first image data is M2×N2; N2:N1=a:b≤1.

[0039] Specifically, in the display method according to the embodiment of the present disclosure, a refresh frequency of the first image data is higher than the normal refresh frequency of the display apparatus, for example: the normal refresh frequency of the display panel is 180Hz, the refresh frequency of the first image data is 240Hz, and the physical resolution of the display panel is M1×N1=2560×1440; a resolution of the first image data is M2×N2=2560×1080. Corresponding, N2:N1=3:4, that is, a =3, b = 4.

[0040] Step S20 includes providing, by the timing controller 30, P clock signals to the gate driving circuit 10 in the display panel, and providing a data control signal to the source driving circuit 20; P=i×b; i is a positive integer greater than or equal to 1. The gate driving circuit 10 selectively turns on each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit 20 writes display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal; and writes the display data of a (b×j-1)-th row and a (b×j+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; j is a positive integer greater than or equal to 1, and j×b+1≤N1.

[0041] That is, the data written into the rows of the sub-pixels except for the (j×b)-th row in the display panel is real display data in the first image data, and the display data written into the sub-pixels of the (j×b)-th row is the interpolation of the display data of the sub-pixels in the upper and lower rows arranged adjacent to the (j×b)-th row. In this way, the display data is written into each sub-pixel on the display panel, and the interpolation of the display data of the sub-pixels in the upper and lower rows arranged adjacent to the (j×b)-th row of sub-pixels is written into the (j×b)-th row of sub-pixels, thereby avoiding the problem of excessive differences between the row of sub-pixels written with the interpolation and each adjacent row of sub-pixels, which may cause display abnormalities.

[0042] Specifically, taking a=3 and b=4 in step S10 as an example, if i is 2, P =8, that is, the timing controller 30 generates 8 clock signals, which are CLK1 to CLK8 respectively. At this time, the 8 clock signals and the data control signal generated by the timing controller 30 may control the sub-pixels in all rows except for a (3j+1)-th row of sub-pixels (for example: fourth, eighth, twelfth ... ...) to be written with the real display data, and for the sub-pixel in the (3j+1)-th row, interpolation of the display data of the sub-pixels in the upper and lower rows arranged adjacent to the (3j+1)-th row is used for displaying. For example: a fourth row of sub-pixels adopt the display data written by a third row of sub-pixels and a fifth row of sub-pixels for hybrid charging.

[0043] It should be noted that in the case of the above example, the number of clock signals is not limited to 8, and may specifically be an integer multiple of 4, for example, 4, 8, or 12. In the above example, as an example, a resolution of the first image data is M2×N2=2560×1080, and 2560×1080 data is filled into the display panel with a physical resolution M1×N1=2560×1440, if the resolution of the first image data is M2×N2=2560×1440, and 2560×1440 data is filled into the display panel with the physical resolution M1×N1=3840×2160, then N2: N1=2:3, that is, a =2, and b =3. At this time, the display data of the display panel needs to be filled into one row every two rows, that is, each of the third row of sub-pixels, the sixth row of sub-pixels, and the ninth row of sub-pixels ...... needs to adopt the display data written by the adjacent upper and lower rows of sub-pixels for hybrid charging. This requires that the number of clock signals generated by the timing controller 30 at this time is a multiple of 3, such as 6, 9, 12, and so on, which are not listed here.

[0044] In some examples, start time of a high level of a (k+1)-th clock signal is earlier than end time of a high level of a k-th clock signal; K is in a range from 1 to P-1; in the P clock signals, except for a (b×j)-th clock signal, a phase difference between start times of the active levels of the adjacent clock signals is 1H1, a phase difference between start times of the active levels of the (b×j)-th clock signal and a (b×j-1)-th clock signal is A, and a phase difference between start times of the active levels of a (b×j+1)-th clock signal and the (b×j)-th clock signal is B; A+B=H1; H1 is a phase difference between start times of two adjacent active levels of the data control signal. For example: the phase difference between the start times of the high levels of the (b×j)-th clock signal and the (b×j-1)-th clock signal is H1 / 2, and the phase difference between the start times of the high levels of the (b×j+1)-th clock signal and the (b×j)-th clock signal is H1 / 2. Specifically, similarly, a =3, b =4, i is 2, and P =8 is taken as an example; except for a 4e-th clock signal, the start time of the active levels of the other clock signals sequentially differs by 1H1; e is a positive integer of 1 or 2; H1 is a phase difference between start times of two adjacent active levels of the data control signal; the phase difference between the start times of the active levels of the 4e-th clock signal and the (4e-1)-th clock signal is H1 / 2. Alternatively, in the embodiment of the present disclosure, the phase difference between the start times of the high levels of the (b×j)-th clock signal and the (b×j-1)-th clock signal is H1 / 3, the phase difference between the start times of the high levels of the (b×j+1)-th clock signal and the (b×j)-th clock signal is 2H1 / 3, and so on, which are not enumerated here.

[0045] Because the clock signal determines the output of the gate driving circuit 10, in the output stage of the gate driving circuit 10, the clock signal is at a high level, and at this time, the gate driving signal output by the gate driving circuit 10 is at a high level, so the start time of the high level of the (k+1)-th clock signal is earlier than the end time of the high level of the k-th clock signal, that is, two adjacent rows of sub-pixels are simultaneously turned on for a period of time for pre-charging before writing the sub-pixel data, so as to improve the charging efficiency of the sub-pixels. In the embodiment of the present disclosure, except for a fourth clock signal and an eighth clock signal, the phase difference between the start times of the high levels of adjacent clock signals is 1H1, a phase difference between the start times of the high levels of the fourth clock signal and the third clock signal is H1 / 2, and a phase difference between the start times of the high levels of the fourth clock signal and the fifth clock signal is H1 / 2; that is, the start times of the high levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6 and the seventh clock signal CLK7 sequentially differs by 1H1, the phase difference between the start times of the high levels of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the start times of the high levels of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2, so that it is ensured that the (3j+1)-th row of sub-pixels adopt the display data written by the upper and lower rows of sub-pixels adjacent to the (3j+1)-th row for hybrid charging.

[0046] In some examples, the clock signals provided by the timing controller 30 to the gate driving circuit 10 and the data control signal provided to the source driving circuit 20 satisfy: except for a (j×b)-th row of sub-pixels, end time of writing data signals into the sub-pixels by the source driving circuit 20 is earlier than end time of the high level of the gate driving signal loaded to the sub-pixels. In this way, it is ensured that the (j×b)-th row of sub-pixels are charged with the display data of the sub-pixels adjacent to the (j×b)-th row.

[0047] In one example, the clock signals provided by the timing controller 30 to the gate driving circuit 10 and the data control signal provided to the source driving circuit 20 satisfy: except for the (j×b)-th row of sub-pixels, a phase difference between the end time of writing the data signals into the sub-pixels by the source driving circuit 20 and the end time of the high level of the gate driving signal loaded to the sub-pixels is H1 / 2, and H1 is a phase difference between start times of two adjacent high levels of the data control signal.

[0048] In some examples, the clock signals provided by the timing controller 30 to the gate driving circuit 10 satisfy: a duration during which the gate driving signals loaded to adjacent rows of sub-pixels are simultaneously in the high level is not less than 2H1, and H1 is a phase difference between start times of two adjacent high levels of the data control signal. For example: a duty ratio of the high level of each clock signal is 50%, a clock for the high level may be 3H1, and correspondingly, a duration of the low level is also 3H1. At this time, the duration during which the gate driving signals loaded to the adjacent rows of sub-pixels are simultaneously in the high level is not less than 2H1.

[0049] In order to further understand the displaying of the received first image data by the display panel in the embodiment of the present disclosure, the display method in the embodiment of the present disclosure is described by taking an example that the gate driving circuit 10 of the display panel is controlled by 8 clock signals.

[0050] Referring to FIG. 5, a duty ratio of a high level of each of 8 clock signals CLK1 to CLK8, provided from the timing controller 30 to the gate driving circuit 10 is 50%, a clock of the high level may be 3H1, and the duration of the corresponding low level is 3H1. The start time of the high levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6 and the seventh clock signal CLK7 sequentially differs by 1H1, a phase difference between the start times of the high levels of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and a phase difference between the start times of the high levels of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2. A phase difference between start time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and end time of a high level of a gate driving signal for a sub-pixel row corresponding to the data row is 3H1 / 4, and a phase difference between end time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the end time of the high level of the gate driving signal for the sub-pixel row corresponding to the data row is H1 / 2. In this case, a sub-pixel row 1 is charged by a data row 1, a sub-pixel row 2 is charged by a data row 2, a sub-pixel row 3 is charged by a data row 3, a sub-pixel row 4 is charged by data rows 3 and 4, a sub-pixel row 5 is charged by a data row 4, a sub-pixel row 6 is charged by a data row 5, a sub-pixel row 7 is charged by a data row 6, a sub-pixel row 8 is charged by data rows 6 and 7, and so on.

[0051] In some examples, referring to FIG. 6, before the above steps, the display method in the present embodiment further includes receiving a display mode selection instruction, and when the display mode selection instruction indicates a first display mode, the graphics card 50 sends received first original image data to the main board 40; a resolution of the first original image data is M3×N3; M3<M2. The main board 40 converts the first original image data sent by the graphics card 50 into first image data, including: performing, by the main board 40, a horizontal interpolation process on the first original image data to obtain the first image data.

[0052] It should be noted that the display apparatus in the embodiment of the present disclosure supports display in multiple modes, for example: the display apparatus includes a normal display mode, that is, a resolution of image data is the same as that of the display panel, at this time, the data of the sub-pixel rows and the data of the data rows are in one-to-one correspondence with each other, and the display data written into each sub-pixel are real data. The display apparatus includes the first display mode, and when the display mode selection instruction for selecting the first display mode by a user is received, the graphics card 50 sends the received first original image data to the main board 40; the resolution of the first original image data is M3×N3; M3<M2; the main board 40 performs the horizontal interpolation process on the first original image data to obtain the first image data. For example: the resolution of the first original image data in the first display mode is M3×N3=1920×1080, a refresh frequency is 240Hz, and the main board 40 performs the horizontal interpolation process on the first original image data to obtain the first image data with M2×N2=2560×1080, and the refresh frequency of 240 Hz.

[0053] In some examples, referring to FIG. 6, the display method according to the embodiment of the present disclosure may include not only the above steps but also include: receiving the display mode selection instruction, and when the display mode selection instruction indicates a second display mode, the graphics card 50 sends received second original image data to the main board 40.

[0054] The main board 40 converts the second original image data into second image data; a resolution of the second image data is M4×N4; N4:N1=1:2; a refresh frequency of the second image data is greater than the refresh frequency of the first image data. For example: the resolution of the second image data is M4×N4=2560×720, and the refresh frequency is 360 Hz.

[0055] The converting the second original image data into the second image data by the main board 40 specifically includes: performing, by the main board 40, the horizontal interpolation process on the second original image data to obtain the second image data. For example: a resolution of the second original image data is 1280×720, a refresh frequency is 360Hz, and the main board 40 performs the horizontal interpolation process on the second original image data to obtain the second image data, the resolution of the second image data is 2560×720, and the refresh frequency is 360 Hz.

[0056] The timing controller 30 provides a plurality of clock signals to the gate driving circuit 10 in the display panel and provides the data control signal to the source driving circuit 20.

[0057] The gate driving circuit 10 selectively turns on the rows of sub-pixels in the display panel according to the plurality of clock signals, and the source driving circuit 20 writes the second image data into sub-pixels in even-numbered rows row by row according to the data control signal, and writes display data of sub-pixels in two even-numbered rows adjacent to each odd-numbered row into sub-pixels in the odd-numbered row; alternatively, the gate driving circuit 10 selectively turns on the rows of sub-pixels in the display panel according to the plurality of clock signals, and the source driving circuit 20 writes the second image data into sub-pixels in odd-numbered rows row by row according to the data control signal, and writes display data of sub-pixels in two odd-numbered rows adjacent to each even-numbered row into sub-pixels in the even-numbered row.

[0058] The refresh frequency of the second display mode is higher than the refresh frequency of the first display mode and is twice the refresh frequency of the normal display mode, and the data rows of the second image data in the second display mode is half of the sub-pixel rows of the display panel. At this time, the source driving circuit 20 writes real data into the sub-pixels in the odd-numbered rows by controlling the data control signal generated by the timing controller 30, and the hybrid charging is performed on the sub-pixels in each of the even-numbered rows by the sub-pixels in the upper and lower rows; alternatively, the source driving circuit 20 writes real data into the sub-pixels in the even-numbered rows, and the hybrid charging is performed on the sub-pixels in each of the odd-numbered rows by the sub-pixels in the upper and lower rows. In this way, image quality loss can be reduced.

[0059] In some examples, in the second display mode, the start time of the active levels of the plurality of clock signals sequentially differs by 1H2, and H2 is half a phase difference between the start times of two adjacent active levels of the data control signal. A duration of the active level of each clock signal is 4H2, and a duty ratio of the active level of the clock signal is 50%; and the plurality of clock signals satisfy that the duration during which two adjacent rows of sub-pixels are simultaneously turned on is 3H2.

[0060] In order to make the display method in the second display mode of the present disclosure clearer, the display method will be described in detail below with reference to the timing shown in FIG. 7.

[0061] The duty ratio of the high level of each of the 8 clock signals CLK1 to CLK8, provided by the timing controller 30 to the gate driving circuit 10 is 50%, a clock of the high level may be 4H2, and the duration of the corresponding low level is also 4H2. The start time of the high levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7, and the eighth clock signal CLK8 sequentially differs by 1H2. A phase difference between start time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and end time of a high level of a gate driving signal for a sub-pixel row (an odd-numbered row) corresponding to the data row is 5H2 / 3, and a phase difference between end time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the end time of the high level of the gate driving signal for the sub-pixel row corresponding to the data row is 4H2 / 3. In this case, a sub-pixel row 1 is charged by a data row 1, a sub-pixel row 2 is charged by data rows 1 and 2, a sub-pixel row 3 is charged by a data row 2, a sub-pixel row 4 is charged by data rows 2 and 3, a sub-pixel row 5 is charged by a data row 3, a sub-pixel row 6 is charged by data rows 3 and 4, a sub-pixel row 7 is charged by a data row 4, a sub-pixel row 8 is charged by data rows 4 and 5, and so on. That is, the real display data is written into the odd-numbered rows of sub-pixels, and the hybrid charging is performed on the sub-pixels in each of the even-numbered rows by the display data of the sub-pixels in the upper and lower rows adjacent to the even-numbered row. Similarly, referring to FIG. 8, the sub-pixel row 1 is charged by the data row 1, the sub-pixel row 2 is charged by the data row 1, the sub-pixel row 3 is charged by the data rows 1 and 2, the sub-pixel row 4 is charged by the data row 2, the sub-pixel row 5 is charged by the data rows 2 and 3, the sub-pixel row 6 is charged by the data row 3, the sub-pixel row 7 is charged by the data rows 3 and 4, the sub-pixel row 8 is charged by the data row 4, and so on. In this case, in addition to the first row of sub-pixels, the real display data is written into the even-numbered rows of sub-pixels, and the hybrid charging is performed on the sub-pixels in each of the odd-numbered rows by the display data of the sub-pixels in the upper and lower rows adjacent to the odd-numbered row.

[0062] With reference to FIG. 1, the embodiment of the present disclosure further provides the graphics card 50, the main board 40, the gate driving circuit 10, the source driving circuit 20, and the display panel; the physical resolution of the display panel is M1×N1. The main board 40 is configured to convert first original image data sent by the graphics card 50 into first image data, and send the first image data to the timing controller 30; a resolution of the first image data is M2×N2; N2:N1=a:b≤1. The timing controller 30 is configured to provide P clock signals to the gate driving circuit 10 in the display panel, and provide a data control signal to the source driving circuit 20; P=i×b; i is a positive integer greater than or equal to 1. The gate driving circuit 10 selectively turns on each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit 20 writes display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal; and writes the display data of a (b×j-1)-th row and a (b×j+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; j is a positive integer greater than or equal to 1, and b×j+1≤N1.

[0063] The display apparatus in the embodiment of the present disclosure may be any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game console, a television, a digital photo frame, a navigator or the like, or any combination of a display apparatus and a hardware, which is not limited in the embodiment of the present disclosure.

[0064] It should be noted that for clarity and conciseness of representation, not all the components forming the display apparatus are given in the embodiments of the present disclosure. Other components not shown may be provided and disposed by one of ordinary skill in the art according to specific needs to realize the necessary functions of the display apparatus, which is not limited in the embodiment of the present disclosure.

[0065] For the related description and technical effects of the display apparatus, reference may be made to those of the display method provided in the embodiments of the present disclosure, which are not described herein again.

[0066] It should be understood that, the above embodiments are merely exemplary embodiments adopted to explain the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to one of ordinary skill in the art that, various changes and modifications may be made therein without departing from the spirit and scope of the present disclosure, and such changes and modifications also fall within the scope of the present disclosure.

Claims

1. A display method for a display apparatus, wherein the display apparatus comprises a graphics card, a main board, a timing controller and a display panel; a physical resolution of the display panel is M1×N1; and the display method comprises: converting, by the main board, first original image data sent by the graphics card into first image data, and sending the first image data to the timing controller; wherein a resolution of the first image data is M2×N2; and N2:N1=a:b≤1; and providing, by the timing controller, P clock signals to a gate driving circuit in the display panel, and providing a data control signal to a source driving circuit; where P=i×b; and i is a positive integer greater than or equal to 1; wherein the gate driving circuit selectively turns on rows of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal, and writes the display data of a (b×j-1)-th row and a (b×j+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; where j is a positive integer greater than or equal to 1, and b×j+1≤N1.

2. The display method of claim 1, wherein start time of an active level of a (k+1)-th clock signal is earlier than end time of an active level of a k-th clock signal; where K is in a range from 1 to P-1; and in the P clock signals, except for a (b×j)-th clock signal, a phase difference between start times of active levels of every two adjacent clock signals is 1H1, a phase difference between start times of active levels of the (b×j)-th clock signal and a (b×j-1)-th clock signal is A, and a phase difference between start times of active levels of a (b×j+1)-th clock signal and the (b×j)-th clock signal is B; where A+B=H1; and H1 is a phase difference between start times of two adjacent active levels of the data control signal.

3. The display method of claim 1, wherein a phase difference between start times of active levels of a (b×j)-th clock signal and a (b×j-1)-th clock signal is H1 / 2, and a phase difference between start times of active levels of (b×j+1)-th clock signal and the (b×j)-th clock signal is H1 / 2.

4. The display method of claim 1, wherein the clock signals provided by the timing controller to the gate driving circuit and the data control signal provided by the timing controller to the source driving circuit satisfy: except for the (j×b)-th row of sub-pixels, end time of the data signal written into the sub-pixel by the source driving circuit is earlier than end time of an active level of a gate driving signal loaded to the sub-pixel.

5. The display method of claim 4, wherein the clock signals provided by the timing controller to the gate driving circuit and the data control signal provided by the timing controller to the source driving circuit satisfy: except for the (j×b)-th row of sub-pixels, a phase difference between the end time of the data signal written into the sub-pixel by the source driving circuit and the end time of the active level of the gate driving signal loaded to the sub-pixel is H1 / 2, and H1 is a phase difference between start times of two adjacent high levels of the data control signal.

6. The display method of claim 1, wherein the clock signals provided by the timing controller to the gate driving circuit satisfy: a duration during which gate driving signals loaded to two adjacent rows of sub-pixels are simultaneously at an active level is not less than 2H1, and H1 is a phase difference between start times of two adjacent high levels of the data control signal.

7. The display method of claim 1, wherein a:b=3:4 and P=4i; except for a 4e-th clock signal, start times of active levels of every two adjacent clock signals of the other clock signals differs by 1H1; where e is a positive integer in a range from 1 to i; H1 is a phase difference between start times of two adjacent active levels of the data control signal; and a phase difference between start times of active levels of the 4e-th clock signal and a (4e-1)-th clock signal is H1 / 2.

8. The display method of claim 1, wherein a:b =2:3 and P=3i; except for a 3e-th clock signal, start times of active levels of every two adjacent clock signals of the other clock signals differs by 1H1; where e is a positive integer in a range from 1 to i; H1 is a phase difference between start times of two adjacent active levels of the data control signal; and a phase difference between start times of active levels of the 3e-th clock signal and a (3e-1)-th clock signal is H1 / 2.

9. The display method of claim 1, wherein a duty ratio of an active level of each of the clock signals is 50%, and a duration of the active level of the clock signal is 3H1; and H1 is a phase difference between start times of two adjacent active levels of the data control signal.

10. The display method of any one of claims 1 to 9, wherein M1 is equal to M2.

11. The display method of any one of claims 1 to 9, further comprising: receiving a display mode selection instruction, and sending, by the graphics card, the received first original image data to the main board with the display mode selection instruction indicating a first display mode; wherein a resolution of the first original image data is M3×N3; and M3<M2; and wherein the converting, by the main board, the first original image data sent by the graphics card into the first image data, comprises: performing, by the main board, a horizontal interpolation process on the first original image data to obtain the first image data.

12. The display method of claim 11, further comprising: receiving the display mode selection instruction, and sending, by the graphics card, received second original image data to the main board with the display mode selection instruction indicating a second display mode; converting, by the main board, the second original image data into second image data; where a resolution of the second image data is M4×N4; and N4:N1=1:2; wherein a refresh frequency of the second image data is greater than a refresh frequency of the first image data; providing, by the timing controller, a plurality of clock signals to the gate driving circuit in the display panel and providing a data control signal to the source driving circuit; selectively turning on, by the gate driving circuit, the rows of sub-pixels in the display panel according to the plurality of clock signals, writing, by the source driving circuit, the second image data into sub-pixels in even-numbered rows row by row according to the data control signal, and writing, into sub-pixels in each odd-numbered row, display data of sub-pixels in two even-numbered rows adjacent to this odd-numbered row; or selectively turning on, by the gate driving circuit, the rows of sub-pixels in the display panel according to the plurality of clock signals, writing, by the source driving circuit, the second image data into sub-pixels in odd-numbered rows row by row according to the data control signal, and writing, into sub-pixels in each even-numbered row, display data of sub-pixels in two odd-numbered rows adjacent to this even-numbered row.

13. The display method of claim 12, wherein in the second display mode, start times of active levels of every two adjacent clock signals of the plurality of clock signals differs by 1H2, and H2 is a half of a phase difference between start times of two adjacent active levels of the data control signal.

14. The display method of claim 13, wherein in the second display mode, a duration of the active level of each of the clock signals is 4H2, and a duty ratio of the active level of the clock signal is 50%; and the plurality of clock signals satisfy that a duration during which every two adjacent rows of sub-pixels are simultaneously turned on is 3H2.

15. A display apparatus, comprising a graphics card, a main board, a gate driving circuit, a source driving circuit and a display panel; wherein a physical resolution of the display panel is M1×N1; the main board is configured to convert first original image data sent by the graphics card into first image data, and send the first image data to a timing controller; wherein a resolution of the first image data is M2×N2; and N2:N1=a:b≤1; and the timing controller is configured to provide P clock signals to the gate driving circuit in the display panel, and provide a data control signal to the source driving circuit; where P=i×b; and i is a positive integer greater than or equal to 1; wherein the gate driving circuit is configured to selectively turn on rows of sub-pixels of the display panel according to the P clock signals, and the source driving circuit is configured to write display data of N2 rows in the first image data row by row into the rows of the sub-pixels except for a (j×b)-th row in a scanning sequence according to the data control signal, and write the display data of a (b×j-1)-th row and a (b×j+1)-th row of sub-pixels into the (j×b)-th row of sub-pixels; where j is a positive integer greater than or equal to 1, and b×j+1≤N1.

Images