Integrated circuit for identifying address bits for a d ejection device

Abstract

An integrated circuit may include a first contact to receive a first data packet from a host controller, the first data packet including address bits and random data, a second contact to transmit a second data packet to a fluid ejection device, and control logic to generate the second data packet including second address bits based on the first address bits.

Description

INTEGRATED CIRCUIT FOR IDENTIFYING ADDRESS BITS FOR A FLUIDEJECTION DEVICEBACKGROUND

[0001] Fluid ejection devices deposit print fluid (e.g., ink, resin, biological materials, or other substances, etc.) onto a substrate (e.g., paper, powder, support structures, etc.) to print in two or three dimensions. A print die may dispense the print fluid for printing. An integrated circuit may interface with a printer control interface and the print die to receive signals from and transmit signals to the printer control interface and the print die.

[0002] Certain cartridges and / or fluid ejection devices (AKA printheads) may be made compatible with certain host printers through certain encodings or configurations. Also the cartridges may be provided with a memory that includes an updated print material (e.g., agent, liquid, ink level). It may be advantageous to provide for additional or alternative memory functions, associated with the cartridge and / or fluid ejection device. It may be advantageous to provide for alternative solutions for certain functions, such as said encodings, configurations and / or print material level.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 A is a block diagram of an example integrated circuit.

[0004] FIG. IB is a block diagram of the integrated circuit of FIG. 1 A including control logic.

[0005] FIG. 2 is a block diagram of the integrated circuit of FIG. IB including a host-side contact array and a device- si de contact array.

[0006] FIG. 3 illustrates the host-side contact array of FIG. 2.

[0007] FIG. 4 illustrates the device-side contact array of FIG. 2.

[0008] FIG. 5 illustrates an example fluidic structure assembly including a fluidic structure, a fluid ejection device having one fluid ejection die, and an interconnect circuit.

[0009] FIG. 6A illustrates an example print component including the fluidic structure assembly of FIG. 5.

[0010] FIG. 6B illustrates the example print component of FIG. 6 A and the integrated circuit of FIG. 2.

[0011] FIG. 7 is a block diagram illustrating data packets for delivering information to a fluid ejection device.

[0012] FIG. 8 is a block diagram illustrating an example repeating address sequence of the data packets of FIG. 7.

[0013] FIG. 9 illustrates an example of modifying the data packets associated with the repeating address sequence of FIG. 8 to generate second data packets associated with a second repeating address sequence.

[0014] FIG. 10 illustrates an example of modifying the data packets of FIG. 7 to remove random data.

[0015] FIG. 11 illustrates an example of identifying the ends of the data packets of FIG. 7 based on a clock idle time or a predetermined amount of time between the non-random data of subsequent data packets.

[0016] FIG. 12 illustrates using predefined bits to identify the non-random data of the packets of FIG. 7.

[0017] FIG. 13 illustrates an example method of using masks to identify the non-random data of the data packets of FIG. 7.

[0018] FIG. 14 is a flowchart of an example method access protocol.

[0019] FIG. 15 illustrates an example configuration register write protocol.

[0020] FIG. 16 illustrates an example status register access protocol.

[0021] FIG. 17 illustrates an example integrated circuit causing a host to treat a fluid ejection device having a second address offset as if it were a fluid ejection device having a first address offset.

[0022] FIG. 18 illustrates an example integrated circuit mapping bits of a fluid ejection device to other bits of the fluid ejection device.

[0023] FIG. 19 illustrates an example response curve for incremental programming of a nonvolatile memory bit.

[0024] FIG. 20 illustrates an example integrated circuit providing responses to incremental write and read signals from a host.

[0025] FIG. 21 illustrates example voltage response curves for parallel bit reads.

[0026] FIG. 22 illustrates example current response curves for parallel bit reads.

[0027] FIG. 23 illustrates an example integrated circuit providing responses to parallel bit reads from a host.

[0028] The foregoing and other features of the present disclosure will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several examples in accordance with the disclosure and are therefore, not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings.DETAILED DESCRIPTION

[0029] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identifysimilar components, unless context dictates otherwise. The illustrative examples described in the detailed description, drawings, and claims are not meant to be limiting. Other implementations may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and made part of this disclosure.

[0030] This disclosure relates to print components. Print components may include reservoirs to provide ink to a printhead. Print components may be printheads. Print components may be print cartridges. Print components may include integrated circuits to communicate with the host printer. The integrated circuits may be part of the printhead or may be separate from the printhead. The printhead may include at least one fluid ejection die.

[0031] A print component may be any component for print systems, such as an exchangeable print cartridge, or a component of a cartridge such as a fluid ejection device (e.g., printhead) or other integrated circuit associated with a cartridge. A print component may include a print component for dispensing print fluid and a reservoir for storing the print fluid. The print fluid may include any 2D or 3D print agent including ink for printing on a medium such as paper (2D) or (e.g., powdered) build material (3D). The print fluid may include dispensable fluid to be dispensed at relatively high precision (as to volume and / or location) for fields of implementation other than 2D or 3D imaging, including but not limited to forensic, laboratory or pharmaceutical applications.

[0032] In one example of this disclosure, integrated circuits are intermediate circuits configured to detect certain host printer signals, and / or respond to and / or transmit these host printer signals. These integrated circuits may be used to change, add or renew certain functions with respect to an associated fluid ejection device or cartridge. It is noted that thefunctions disclosed in this disclosure can also be implemented in a fluid ejection device, rather than separate from it. The integrated circuit may be implemented as a part of a fluid ejection die or printhead. The integrated circuit may be a part of an original OEM printhead or an alternative printhead of a third party that is not an OEM. Integrated circuits disclosed herein could be part of the fluid ejection device or printhead, unless disclosed otherwise.

[0033] To the extent the integrated circuits are separate from the fluid ejection device, the signals can be transmitted to the separate fluid ejection device. The integrated circuit can be attached or attachable to a cartridge, whereby the cartridge may be provided with a plastic body (e.g., including a reservoir), a fluid ejection device, and an interconnect circuit to route signals between the host and the fluid ejection device. The integrated circuit can be communicatively connected to the interconnect circuit and / or fluid ejection device of the cartridge. It may comprise a thin circuit such as a thin PCB or flexible circuit to allow it to be attached over a cartridge’s interconnect circuitry between the interconnect circuitry and printer-side (carriage) interconnect circuitry. In other examples, the integrated circuit may be part of a fluid ejection device.

[0034] In one example, the integrated circuit may receive signals from a host controller (such as an ASIC print controller of a printer) and respond to the host controller with response signals, for example, in lieu of an associated fluid ejection device memory. In another example the integrated circuit attached to a print cartridge may receive signals from the host controller and modify them for delivery to a fluid ejection device of the print cartridge. The integrated circuit may modify signals from the fluid ejection device and modify them for delivery to the host controller. The integrated circuit may allow some signals to pass unchanged between the host controller and the print component. The integrated circuit may be a thin circuit attached to the print cartridge with a device-side contact array connected tothe fluid ejection device and a host-side contact array connected to the host controller when the print cartridge is in an installed state.

[0035] The integrated circuit may be attached to the print cartridge in order to modify signals of the host controller and / or the host, such as a printer, to the fluid ejection device, to modify output from the fluid ejection device to the host; or, outputting signals to the host directly that are generated and / or stored by the integrated circuit. Different types of fluid ejection devices may be compatible with certain series of hosts, and incompatible with other series of hosts. Furthermore, fluid ejection devices may include memory bits indicating use of the fluid ejection devices, for example indicating consumed and / or remaining fluid level. The integrated circuit attached to the print cartridge may provide and / or modify signals to / from the host such that the host views the cartridge as being compatible and / or filled. Furthermore, hosts, such as printers, may be configured to analyze signals from fluid ejection devices to verify that the cartridges are in good condition and / or operating as expected and / or compatible. The integrated circuit attached to the print cartridge may provide and / or modify signals to / from the host such that the host treats the cartridge with integrated circuit the same as a compatible and / or filled cartridge, or a cartridge that is in good condition and / or operating as expected. In an example, a printer may indicate a low ink level, based on the printer’s estimate of an ink level of a print cartridge. In this example, if the original fluid ejection device is associated with a low-fill original print cartridge, butthat cartridge has been refilled to a level associated with a high-fill print cartridge, the integrated circuit may modify signals between the fluid ejection device and the host such that the host views the fluid ejection device as a high-fill print cartridge.

[0036] FIG. 1 A is a block diagram of an example integrated circuit 100. The integrated circuit 100 may have a first contact 101 and a second contact 102. The first contact 101 is to electrically connect the integrated circuit 100 to a host controller. The first contact 101corresponds to a contact on a host controller. The first contact 101 is to transmit signals between the integrated circuit 100 and the host controller. The second contact 102 is to electrically connect the integrated circuit 100 to a fluid ejection device. The second contact 102 corresponds to a contact on an interconnect circuit of the fluid ejection device. The second contact 102 is to transmit signals between the integrated circuit 100 and the fluid ejection device.

[0037] FIG. IB is a block diagram of the integrated circuit of FIG. 1 A including control logic. The control logic 105 controls signals transmitted by the integrated circuit 100. The control logic 105 receives signals from the first contact 101 and / or the second contact 102. In some implementations, the control logic 105 analyzes signals received at the first contact 101 and / or the second contact 102. In some implementations, the control logic 105 modifies the signals received at the first contact 101 and / or the second contact 102. In some implementations, the control logic generates signals to be transmitted at the first contact 101 and / or the second contact 102.

[0038] Note that it could be possible that the first and second contact 101, 102 form one integral contact, whereby the same integral contact is used to, on the one hand, transmit signals to / from the host, and, on the other hand, to transmit signals to / from the fluid ejection device, as controlled by the logic 105. Certain other examples of integrated circuits of this disclosures could intercept signals from the host and communicate with the host without receiving signals from, or transmitting signals to, the fluid ejection device, whereby effectively there is no device-side contact array 120.

[0039] FIG. 2 is a block diagram of the integrated circuit of FIG. IB including a host-side contact array 110 and a device-side contact array 120. In some implementations, the host-side contact array 110 includes the first contact 101. In some implementations, the device-side contact array 120 includes the second contact 102. The host-side contact array 110 is toelectrically connect the integrated circuit 100 to a host controller. The host-side contact array 110 corresponds to a contact array on a host controller. The host-side contact array 110 is to transmit signals between the integrated circuit 100 and the host controller. The host-side contact array 110 includes multiple contacts, each contact to receive and / or transmit different electrical signals. In some implementations, the host-side contact array 110 receives and / or transmits combinations of signals on the multiple contacts. The device-side contact array 120 is to electrically connect the integrated circuit 100 to a fluid ejection device. The device-side contact array 120 corresponds to a contact array on an interconnect circuit of the fluid ejection device. The device-side contact array 120 is to transmit signals between the integrated circuit 100 and the fluid ejection device. The device-side contact array 120 includes multiple contacts, each contact to receive and / or transmit different electrical signals. In some implementations, the device-side contact array 120 receives and / or transmits combinations of signals on the multiple contacts.

[0040] The integrated circuit 100 may receive signals at the host-side contact array 110 and allow the received signals to be transmitted to a fluid ejection device at the device-side contact array 120. In this way, the integrated circuit allows signals from the host controller to pass through to the fluid ejection device. The integrated circuit 100 may receive signals at the hostside contact array 110 and modify the received signals and / or generate different signals for transmission at the device-side contact array. In this way, the integrated circuit 100 intercepts signals from the host controller intended for the fluid ejection device. The integrated circuit 100 may allow signals received at the host-side contact array 110 to be transmitted at the device-side contact array 120 and generate additional signals in parallel at the device-side contact array. In this way, the integrated circuit overrides the signals from the host controller to the fluid ejection device. The integrated circuit may similarly treat signals from the fluidejection device intended for the host controller by passing them through, intercepting them, and / or overriding them.

[0041] Note that it could be possible that certain opposite contacts of the contact arrays 110, 120 form an integral contact, used to transmit signals to / from the host and to transmit signals to / from the fluid ejection device, as controlled by the logic 105. Certain other examples of integrated circuits of this disclosure could intercept signals from the host and communicate with the host without receiving signals from, or transmitting signals to, the fluid ejection device, whereby effectively there is no second contact 102.

[0042] The integrated circuit 100 may be a thin circuit. In some implementations, the integrated circuit 100 is thin printed circuit board (PCB). The integrated circuit 100 may be thin enough to fit between a host controller contact array and an interconnect circuit contact array of the cartridge, without interfering with relative positions of the host controller contacts and the interconnect circuit contacts. Without the integrated circuit in between, in an installed state of the cartridge, the host controller contacts and the interconnect circuit contacts of the cartridge are in permanent contact. An interconnecting portion of the integrated circuit 100 may be thin enough to be able to be placed between the host controller and the interconnect circuit in the installed state. In some implementations, interconnecting portions of the integrated circuit 100, including routing and support / insulative substrate, have a maximum thickness of less than two millimeters or less than a millimeter.

[0043] As discussed herein, the integrated circuit 100 may be used to modify signals between the host controller and the fluid ejection device such that the host controller views the fluid ejection device as a compatible, and / or unused (or less used) fluid ejection device in good condition and / or operating as expected. Thus, the integrated circuit 100 may need to be thin enough to fit between the host controller and the fluid ejection device without requiring modification of the host structure or host signals. The integrated circuit may include a flexiblecircuit with the contacts on two side, the respective host and device-side, whereby there may be an insulative layer between some of the host- and device-side circuitry (e.g., contacts).

[0044] FIG. 3 illustrates the host-side contact array 110 of FIG. 2. The host-side contact array 110 may include contacts 112a-112k. The host-side contact array 110 may include a first contact 112a, a second contact 112b, a third contact 112c, a fourth contact 112d, a fifth contact 112e, a sixth contact 112f, a seventh contact 112 g, an eighth contact 112h, a ninth contact 112i, a tenth contact 112j, and an eleventh contact 112k. Each of the contacts 112a-l 12k may correspond to a host controller contact on a host controller contact array.

[0045] The first contact 112a may be a pen detect contact, in contact with pen detect logic, for example a pull-down device with transistor. In use, the first contact 112a may have a voltage of 0-3.3 V. The second contact 112b may be a sense, and / or analog reading signal contact which is a low-voltage input / output contact for temperature measurement, strain gauge sensing and / or non-volatile memory reads. The second contact 112b may provide analog data signals in response to data reading signals from the host. The second contact may be connected to a memory of the integrated circuit. In operation, the second contact 112b may have a voltage of 0-3.3 V. In operation, the second contact 112b may transmit and / or receive analog signal values between 0 and 3.3 V. The third contact 112c may be a mode contact which supplies a low-voltage input signal for selecting between a data loading mode and a register access mode. The third contact 112c may be connected to the control logic 105. In operation, the third contact 112c may have a voltage of 0-3.3 V. In operation, the third contact 112c may transmit and / or receive a logic low signal and a logic high signal. In some examples, the logic low signal may be approximately 0 V and the logic high signal may be approximately 3.3 V. In some examples, the logic low signal may be approximately 3.3 V and the logic high signal may be approximately 0 V. The fourth contact 112d may be a clock contact which is a low-voltage input signal for providing a clock signal and for loading firepulse group data and for register access. The fourth contact 112d may be connected to the control logic 105. In operation, the fourth contact 112d may have a voltage of 0-3.3 V. The fifth contact 112e may be a data select contact. The data select contact may be a low-voltage input / output signal contact for receiving input for loading for pulse data packets and configuration register data. The fifth contact 112e may be connected to the control logic 105. In operation, the data select contact may be used for sending output from the integrated circuit 100 to the host controller contact array when serially shifting out status register data. In operation, the fifth contact 112e may have a voltage of 0-3.3 V. In operation, the fifth contact 112e may transmit and / or receive logic low signals and logic high signals. In some examples, the logic low signals may be approximately 0 V and the logic high signals may be approximately 3.3 V. In some examples, the logic low signals may be approximately 3.3 V and the logic high signals may be approximately 0 V.

[0046] The sixth contact 112f may be a low-voltage ground contact. The seventh contact 112g may be a high-voltage power supply input contact. In operation, the seventh contact 112g may have a voltage of 0-35 volts. The eighth contact 112h may be a high-voltage ground contact. The seventh and / or eight contact 112g, 112h may be connected to the fluid ejection device, to transmit the power signal, at least in a condition where it is assembled to the cartridge. The ninth contact 112i may be low-voltage power supply input contact. In operation, the ninth contact 112i may have a voltage of 0-5.7 volts, plus or minus 3%. The sixth contact 112f and / or the ninth contact 112i may be connected to the control logic 105, and / or selectively transmit signals to the fluid ejection device as controlled by the control logic 105, at least in a condition where it is assembled to the cartridge. The tenth contact 112j may be a fire contact. In operation, the tenth contact 112j may transmit and / or receive a logic low signal and a logic high signal of approximately 0 V and 3.3 V, respectively. The tenth contact 112j may be connected to the control logic 105. The eleventh contact 112k may be areset contact. The eleventh contact 112k may transmit and / or receive a logic low signal and a logic high signal of approximately 0 V and 3.3 V, respectively. The eleventh contact 112k may be connected to the control logic 105 and / or, in a condition where it is assembled to the cartridge, to the fluid ejection device.

[0047] The voltages discussed herein may be DC voltages. Furthermore, the voltages discussed herein may be approximate values. The voltages described in conjunction with the various contacts 112a-l 12k may be voltages that are applied to the contacts 112a-l 12k during operation. The voltages described herein may be analog voltages, or digital voltages, such as the aforementioned logic high and logic low voltages. Furthermore, the voltages used for logic high and logic low may be dependent on the voltages used by the host controller. In an example, a host controller may use approximately 0 V for logic low and approximately 3.3 V for logic high. In another example, a host controller may use approximately 3.3 V for logic low and approximately 0 V for logic high.

[0048] The first through fifth contacts 112a-112e may be in a first column of the host-side contact array 110. The sixth through eleventh contacts 112f- 112k may be in a second column of the host-side contact array 110. The first column and the second column may correspond to columns of contacts on the interconnect circuit for a fluid ejection device and / or columns of contacts on the host controller contact array. The first and second contact column may be arranged along straight, parallel lines.

[0049] In some implementations, the host-side contact array 110 does not include all of the contacts 112a-112k. In one example, the integrated circuit includes a sub-set of the contacts of the contact array 110 of Fig. 3. In some implementations, the host-side contact array 110 only includes contacts corresponding to signals the integrated circuit 100 needs to receive and / or transmit. On the other hand, the integrated circuit 100 may include all the indicated contacts, whereby there may be contacts that do not require further processing (i.e., switching,modifying, calculating, data storing, responding, etc.) by the integrated circuit 100, which contacts will directly pass through signals in either direction between the host and the fluid ejection device. The integrated circuit 100 may be configured to “use” (i.e., process) signals from only a portion of the contacts 112a-l 12k. The integrated circuit 100 may require a first subset of the contacts 112a-l 12k for first functions and a second subset of the contacts 112a- 112k for second functions. Thus, the host-side contact array 110 may include or “use” some of the contacts 112a-l 12k depending on functions performed by the integrated circuit 100, as discussed herein. In an example, the host-side contact array 110 includes only the second through fifth contacts 112b-l 12e and the tenth contact 112j, as these contacts are needed to receive signals of a memory access protocol, as discussed herein. In an example, the hostside contact array 110 does not include the seventh contact 112g, as the integrated circuit can receive power over different contacts.

[0050] In some implementations, the host-side contact array 110 may include additional contacts. The illustrated example of the host-side contact array 110 includes eleven contacts, with the fifth contact 112e corresponding to a single data contact. A single data contact may be used with fluid ejection devices having a single fluid ejection die, such as a black ink fluid ejection die. However, fluid ejection devices for color printing may include multiple fluid ejection dies, such as three fluid ejection dies, requiring three different data contacts. The host-side contact array 110 may include additional contacts corresponding to additional fluid ejection dies. In an example, the host-side contact array 110 may include thirteen contacts, three of which correspond to data contacts.

[0051] FIG. 4 illustrates the device-side contact array 120 of FIG. 2. The device-side contact array 120 may include contacts 122a- 122k. The device-side contact array 120 may include a first contact 122a, a second contact 122b, a third contact 122c, a fourth contact 122d, a fifth contact 122e, a sixth contact 122f, a seventh contact 122 g, an eighth contact 122h, a ninthcontact 122i, a tenth contact 122j, and an eleventh contact 122k. Each of the contacts 122a- 122k may correspond to an interconnect circuit contact of an interconnect circuit contact array. The device-side contact array 120 may be a mirror image of the host-side contact array 110, as the interconnect circuit contact array is a mirror image of the host controller contact array.

[0052] The first contact 122a may be a pen detect contact, in contact with pen detect logic, for example a pull-down device with transistor. In operation, the first contact 122a may have a voltage of 0-3.3 V. The second contact 122b may be a sense, and / or analog reading signal contact which is a low-voltage input / output contact for temperature measurement, strain gauge sensing and non-volatile memory reads. The second contact 122b may provide analog data signals in response to data reading signals from the host. The second contact may be connected to a memory of the integrated circuit. In operation, the second contact 122b may have a voltage of 0-3.3 V. In operation, the second contact 122b may transmit and / or receive analog signal values between 0 and 3.3 V. The third contact 122c may be a mode contact which transmits and / or receives a low-voltage input signal for selecting between a data loading mode and a register access mode. The third contact 122c may be connected to the control logic 105. In operation, the third contact 122c may have a voltage of 0-3.3 V. In operation, the third contact 122c may transmit and / or receive a logic low signal and a logic high signal. In some examples, the logic low signal may be approximately 0 V and the logic high signal may be approximately 3.3 V. In some examples, the logic low signal may be approximately 3.3 V and the logic high signal may be approximately 0 V. The fourth contact 122d may be a clock contact which is a low-voltage input signal for providing a clock signal and for loading fire pulse group data and for register access. The fourth contact 122d may be connected to the control logic 105. In operation, the fourth contact 122d may have a voltage of 0-3.3 V. The fifth contact 122e may be a data select contact. The data select contact maybe a low-voltage input / output signal contact for receiving input for loading for pulse data packets and configuration register data. The fifth contact 122e may be connected to the control logic 105. The data select contact may be used for sending output from the integrated circuit 100 to the host controller contact array when serially shifting out status register data. In operation, the fifth contact 122e may have a voltage of 0-3.3 V. In operation, the fifth contact 122e may transmit and / or receive logic low signals and logic high signals. In some examples, the logic low signals may be approximately 0 V and the logic high signals may be approximately 3.3 V. In some examples, the logic low signals may be approximately 3.3 V and the logic high signals may be approximately 0 V.

[0053] The sixth contact 122f may be a low-voltage ground contact. The seventh contact 122g may be a high-voltage power supply input contact. In operation, the seventh contact 122g may have a voltage of 0-35 volts. The eighth contact 122h may be a high-voltage ground contact. The seventh and / or eight contact 122g, 122hh may be connected to the fluid ejection device, to transmit the power signal, at least in a condition where it is assembled to the cartridge. The ninth contact 122i may be low-voltage power supply input contact. In operation, the ninth contact 122i may have a voltage of 0-5.7 volts, plus or minus 3%. The sixth contact 122f and / or ninth contact 122i may be connected to the control logic 105, and / or selectively transmit signals to the fluid ejection device as controlled by the control logic 105, at least in a condition where it is assembled to the cartridge. The tenth contact 122j may be a fire contact. In operation, the tenth contact 122j may transmit and / or receive a logic low signal and a logic high signal of approximately 0 V and 3.3 V, respectively. The tenth contact 122j may be connected to the control logic 105. The eleventh contact 122k may be a reset contact. In operation, the eleventh contact 122k may transmit and / or receive a logic low signal and a logic high signal of approximately 0 V and 3.3 V, respectively. The eleventh contact 122kmay be connected to the control logic 105 and / or, in a condition where it is assembled to the cartridge, to the fluid ejection device.

[0054] The voltages discussed herein may be DC voltages. Furthermore, the voltages discussed herein may be approximate values. The voltages described in conjunction with the various contacts 112a-l 12k may be voltages that are applied to the contacts 112a-l 12k during operation. The voltages described herein may be analog voltages, or digital voltages, such as the aforementioned logic high and logic low voltages. Furthermore, the voltages used for logic high and logic low may be dependent on the voltages used by the host controller. In an example, a host controller may use approximately 0 V for logic low and approximately 3.3 V for logic high. In another example, a host controller may use approximately 3.3 V for logic low and approximately 0 V for logic high.

[0055] The first through fifth contacts 122a-122e may be in a first column of the device-side contact array 120. The sixth through eleventh contacts 122f-122k may be in a second column of the device-side contact array 120. The first column and the second column may correspond to columns of contacts on the interconnect circuit for a fluid ejection device and / or columns of contacts on the host controller contact array. The first and second contact column may be arranged along straight, parallel lines.

[0056] In some implementations, the device-side contact array 120 does not include all of the contacts 122a- 122k. In one example, the integrated circuit includes a sub-set of the contacts of the contact array 110 of Fig. 3. In some implementations, the device-side contact array 120 only includes contacts corresponding to signals the integrated circuit 100 needs to receive and / or transmit. On the other hand, the integrated circuit 100 may include all the indicated contacts, whereby there may be contacts that do not require further processing (i.e., switching, modifying, calculating, data storing, responding, etc.) by the integrated circuit 100, which contacts will directly pass through signals in either direction between the host and the fluidejection device. The integrated circuit 100 may be configured to “use” (i.e., process) signals from only a portion of the contacts 112a-l 12k. The integrated circuit 100 may require a first subset of the contacts 122a-122k for first functions and a second subset of the contacts 122a- 122k for second functions. Thus, the device-side contact array 120 may include or “use” some of the contacts 122a- 122k depending on functions performed by the integrated circuit 100, as discussed herein. In an example, the device-side contact array 120 includes only the second through fifth contacts 122b-122e and the tenth contact 122j, as these contacts are needed to transmit signals of a memory access protocol, as discussed herein. In an example, the deviceside contact array 120 does not include the seventh contact 122g, as the interconnect circuit can receive power directly from the host controller.

[0057] In some implementations, the device-side contact array 120 may include additional contacts. The illustrated example of the device-side contact array 120 includes eleven contacts, with the fifth contact 122e corresponding to a single data contact. A single data contact may be used with fluid ejection devices having a single fluid ejection die, such as a black ink fluid ejection die. However, fluid ejection devices for color printing may include multiple fluid ejection dies, such as three fluid ejection dies, requiring three different data contacts. The device-side contact array 120 may include additional contacts corresponding to additional fluid ejection dies. In an example, the device-side contact array 120 may include thirteen contacts, three of which correspond to data contacts.

[0058] FIG. 5 illustrates an example fluidic structure assembly including a fluidic structure 140, a fluid ejection device 142, and an interconnect circuit 130. The interconnect circuit 130 may include an interconnect circuit contact array 132. Contacts of the interconnect circuit contact array 132 may be arranged along both sides of a center axis of the interconnect circuit contact array 132. The contacts of the interconnect circuit contact array 132 may correspond to the contacts 122a-122k of the device-side contact array 120 and / or contacts of a hostcontroller contact array. The contacts of the interconnect circuit contact array 132 may be arranged in two columns with one column on a first side of the center axis of the interconnect circuit contact array 132 and a second column on a second side of the center axis of the interconnect circuit contact array 132. The two columns may extend substantially parallel to each other and the center axis of the interconnect circuit contact array 132. The center axis of the interconnect circuit contact array 132 may align with the fluid ejection die 144 in an installed state or a center fluid ejection die of the fluid ejection device 142 if the fluid ejection device 142 includes multiple fluid ejection dies. In the illustrated example, the contacts of the interconnect circuit contact array 132 are provided in no more than two columns.

[0059] FIG. 6 A illustrates an example print component 160 including the fluidic structure assembly of FIG. 5. The print component 160 may include a molded body 150, the interconnect circuit 130, and the fluid ejection device 140. The molded body 150 may include a reservoir to store print fluid. The reservoir may be fluidically connected to the fluid ejection device 140 such that the fluid ejection device 140 can output the print fluid according to signals received via the interconnect circuit 130. The print component 160 may, in an installed state, be flipped vertically relative to its illustration in FIG. 6 A such that the fluid ejection device 140 is facing downwards (e.g., towards a print surface).

[0060] FIG. 6B illustrates the integrated circuit 100 of any of FIGS. 2 - 4 attached to the print component 160 of FIG. 6 A. The integrated circuit 100 may overlay the interconnect circuit 130. The integrated circuit 100 may overlay the interconnect circuit 130 such that the integrated circuit covers the interconnect circuit contact array 132. The integrated circuit 100 may overlay the interconnect circuit contact array 132 such that the host-side contact array 110 occupies a location of the interconnect circuit contact array 132. In this way, the hostside contact array 110 may contact the host controller contact array when the print component 160 is installed, as the interconnect circuit contact array 132 is configured to contact the hostcontroller contact array when the print component 160 is installed. Contacts of the host controller contact array may contact the host-side contact array 110 and / or the interconnect circuit array 132, depending upon which contacts are included in the host-side contact array 110. As said, in some instances, certain contacts of the host-side contact array 110 may directly contact the contacts 132 of the cartridge, to pass through the signals. For example, in certain instances it may be more advantageous to directly pass through signal through a contact than to leave an open space for the original contacts 132 of the cartridge to contact the host through that open space. Hence, in some implementations, one or more contacts in the host-side contact array 110 are replaced with holes to allow contacts of the host controller contact array to directly contact corresponding contacts of the interconnect circuit contact array 132, and / or one or more contacts in the host-side contact array 110 are replaced with conductive pads to allow contacts of the host controller contact array to directly contact corresponding contacts of the interconnect circuit contact array 132.

[0061] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may receive first address bits from a host controller. The second contact 102 may transmit second address bits to a fluid ejection device. The second address bits may be based on the first address bits. In an example, the second address bits may be obtained by performing a mathematical operation on the first address bits. In an example, the second address bits may be obtained by using a lookup table to map the first address bits to the second address bits.

[0062] The first address bits may include a first address code and the second address bits may include a second address code, the first address code to select a first nozzle circuit of the fluid ejection device, and the second address code to select a second nozzle circuit of the fluid ejection device. The first nozzle circuit may be located at a first location on the fluid ejectiondevice and the second nozzle circuit may be located at a second location on the fluid ejection device. The integrated circuit 100 may receive a first data packet from the host controller at the first contact 101 and transmit a second data packet to the fluid ejection device at the second contact 102, the first and second data packets including the first and second address codes, respectively.

[0063] The integrated circuit 100 may include control logic that maps the first address code to the second address code. The control logic may determine, based on a first address bit sequence received from the host controller, the second address bits associated with a second address bit sequence. The control logic may include at least one of a mathematical operation and a lookup table. The second data packet may include a head including a first subset of the address bits, a middle portion, and a tail including a second subset of the address bits, the first and second subsets of the address bits comprising the second address code. The middle portion may include primitive data. Primitives may include groups of nozzle circuits. The primitive data may indicate to which primitives the second address code should be applied. In this way, the second data packet may include information for delivering instructions for each nozzle circuit. The fluid ejection device may include a nozzle circuit array to eject drops from each nozzle circuit of the array, the second address bits to select the second nozzle circuit for ejecting drops. The tail may include control bits. The control bits may control actions of the fluid ejection device, such as warming the fluid ejection device.

[0064] In some implementations, the first data packet and the second data packet include the same primitive bits. The second data packet may be based on the first data packet to include the same primitive bits. The integrated circuit 100 may modify the address bits of the first data packet to generate the second data packet. In some implementations, the integrated circuit 100 modifies a first portion of the first packet containing the address bits, and does notmodify a second portion of the packet. In some implementations, the integrated circuit 100 modifies the address bits and does not modify the primitive bits.

[0065] In some implementations, the integrated circuit 100 includes a host-side contact array including the first contact, the host-side contact array including at least one column of contacts to contact a corresponding contact column of the host controller for transmitting signals between the integrated circuit and the host printer. The integrated circuit 100 may include a device-side contact array including the second contact. The integrated circuit 100 may include a first clock contact to receive first clock signal from the host controller and a second clock contact to output a second clock signal to the fluid ejection device. The second clock signal may be the same as the first clock signal. The second clock signal may have a higher frequency than the first clock signal. The integrated circuit 100 may include a first fire contact to receive a first fire signal from the host controller and a second fire contact to output a second fire signal to the fluid ejection device. The first fire signal may be in phase with the first address bits based on the first clock signal and the second fire signal may be in phase with the second address bits based on the second clock signal.

[0066] In some implementations, the integrated circuit 100 is attached to a print cartridge including the fluid ejection device. The print cartridge may be configured to be inserted in a printer including the host controller. The integrated circuit 100 may receive, analyze, and / or modify signals from the host controller to the fluid ejection device. The integrated circuit 100 may modify print instructions from the host controller to the fluid ejection device to accommodate for a mismatch between a type of print cartridge for which the printer supplies instructions and a type of print cartridge of the print cartridge including the fluid ejection device.

[0067] In an example, the fluid ejection device is integrated in a low-fill print cartridge and the fluid ejection device is configured to receive print data according to a low-fill sequenceof addresses of nozzle circuits on the fluid ejection device. The low-fill sequence of addresses may be associated with the low-fill print cartridge. In this example, the integrated circuit 100 attached to the low-fill print cartridge, (low-fill fluid ejection device) modifies signals between the host controller and the fluid ejection device such that the host controller views and treats the fluid ejection device as a fluid ejection device integrated in a high-fill print cartridge (high-fill fluid ejection device). In this way, the integrated circuit 100 causes the host controller to estimate the fill level of the low-fill print cartridge based on a fill level of the high-fill print cartridge. In this way, the low-fill print cartridge may be filled to the fill level of the high-fill print cartridge. However, high-fill fluid ejection devices are associated with a high-fill sequence of addresses of nozzle circuits. Thus, when the host controller treats the low-fill fluid ejection device as a high-fill fluid ejection device, the host controller provides print data in an address sequence not compatible with the low-fill fluid ejection device. To address this issue, the integrated circuit 100 modifies the print data (e.g., data packets containing the print data) from the host controller to translate between the high-fill sequence of addresses and the low-fill sequence of addresses. In this way, the integrated circuit 100 causes the host controller to treat the low-fill print cartridge as a high-fill print cartridge while causing the low-fill print cartridge to print correctly by modifying the print data from the host controller.

[0068] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the integrated circuit 100 may include a host-side contact array 110 including a host-side data contact to receive first data packets from a host controller, and a device side contact array 120 including a device-side data contact to output second data packets to a fluid ejection device, each second data packet corresponding to a received first data packet, wherein the integrated circuit is configured to transmit the second data packets that are modified with respect tocorresponding first data packets so that the fluid ejection device prints based on the second data packets.

[0069] The host-side contact array 110 may include a host-side clock contact to receive a first clock signal from the host controller, and a host-side fire contact to receive a first fire signal from the host controller, the device-side contact array including a device-side clock contact to output a second clock signal to the fluid ejection device, and a device-side fire contact to output a second fire signal to the fluid ejection device. The first address bits of a first data packet of the first data packets may include a first address code and second address bits of a second data packet of the second data packet may include a second address code, wherein the first address code selects a first nozzle circuit of the fluid ejection device, and the second address code selects a second nozzle circuit of the fluid ejection device. The first nozzle circuit may be located at a first location on the fluid ejection device and the second nozzle circuit may be located at a second location on the fluid ejection device. Thus, if the integrated circuit 100 did not modify the first data packets, the fluid ejection device would eject fluid at the first location, causing a printing error.

[0070] The control logic 105 may map the first address code to the second address code. The control logic may determine the second address code based on a first address bit sequence received from the host controller, the second address bits associated with a second address bit sequence. The control logic may determine the second address bits as being next address bits in the second address bit sequence. The control logic 105 may include at least one of a mathematical operation and a lookup table. The mathematical operation and / or lookup table may be used to map the first address code to the second address code.

[0071] In some implementations, the second data packet includes a head including a first subset of the address bits a middle portion, and a tail including a second subset of the address bits, the first and second subsets of the address bits comprising the second address code. Themiddle portion may include primitive data. The tail may include control bits. The first and second data packets may include the same primitive bits. In some implementations, the fluid ejection device comprises a nozzle circuit array to eject drops from each nozzle circuit of the array, the second address bits to select the second nozzle circuit for ejecting drops. The primitive data along with the address bits may select the second nozzle circuit for ejecting drops.

[0072] In some implementations, the host-side contact array 110 includes a first column of contacts including the host-side fire contact and a second column of contacts including the host-side clock contact and the host-side data contact, and the device-side contact array includes a first column of contacts including the device-side fire contact and a second column of contacts including the device-side clock contact and the device-side data contact.

[0073] The integrated circuit 100 may modify the first packet such that a first portion of the first packet is modified, the first portion including the address bits, and a second portion of the first packet is not modified. The second portion may include the primitive data.

[0074] In some implementations, the first fire signal is in phase with the first address bits based on the first clock signal and the second fire signal is in phase with the second address bits based on the second clock signal. The integrated circuit 100 may modify the first clock signal to obtain the second clock signal. The second clock signal may have the same frequency or a higher frequency than the first clock signal.

[0075] In some implementations, the integrated circuit is attached to a print cartridge including the fluid ejection device, the print cartridge to be inserted in a printer including the host controller.

[0076] FIG. 7 is a block diagram illustrating data packets 710 for delivering information to a fluid ejection device, such as the fluid ejection device 142 of FIG. 5. The data packets 710are to deliver fluid ejection instructions to the fluid ejection device. The fluid ejection instructions may correspond to portions of a print job. In an example, the data packets may include instructions for printing a portion of a print job, for example a drop from a nozzle.

[0077] A fluid ejection die, such as the fluid ejection die 144 of FIG. 5, may include a nozzle array. The nozzle array may include nozzle columns arranged in rows along the fluid ejection die. Each nozzle column includes a plurality of nozzles arranged to dispense fluid onto a substrate, such as a piece of paper or 3D-printing surface. The nozzles may be arranged into groups called “primitives.” The primitives may be further arranged into groups called “virtual primitives.” The number and arrangement of the nozzles in the primitives and / or virtual primitives may vary depending on the desired print density. The fluid ejection die may include a fluid ejection controller connected to the nozzle array. The fluid ejection controller may receive the data packets 710 from the host controller and / or the integrated circuit 100 for controlling ejection of fluid by the nozzles of the nozzle array. The fluid ejection array controller may generate ejection control data for the nozzles of the nozzle array based on the contents of the data packets 710.

[0078] The data packets 710 may include a first data packet 710a, a second data packet 710b, a third data packet 710c, a fourth data packet 710d, a fifth data packet 710e, and any number of additional data packets. In some implementations, each of the data packets 710 have a same structure, with different or similar information within the same structure.

[0079] The third data packet 710c may include random data 711c, zero-pad data 712c, a head 713c, primitive data 714c, and atail 715c. The random data 711c may include pseudo-random data. The random data 711c may include a random or pseudo-random number of bits. In an example, the random data 711c includes zero, two, four, six, or eight random bits. The third packet 710c may vary in length based on the length of the random data 711c. The fluid ejection device may include a shift register corresponding to a length of the third packet 710cminus the random data 711c. The random data 711c may be fed into the shift register first, causing the random data 711c to be dropped as the remainder of the third packet 710c is loaded into the shift register.

[0080] The data packets 710 may include the random data 711 to determine that the fluid ejection device is operating as expected. The random data 711 may include a random number of random bits. As noted above, as used herein, the term “random” includes pseudo-random data. The host device including the host controller may generate the random data 711 to ensure that the fluid ejection device is operating correctly. The host device may generate the random data 711 to obfuscate a beginning of the heads 713 of the data packets 710. In this way, the host device may force the integrated circuit 100, in modifying the data packets 710, to introduce latency into the delivery of modified data packets and / or to use probabilistic methods of identifying which bits to modify, as discussed herein. The examples discussed herein regarding identifying the random data 711, the non-random data, and / or the ends of the data packets 710 are directed to overcoming and / or mitigating this security feature of the data packets 710.

[0081] In FIG. 7, timing of the data packets 710 and their components is shown with time advancing from left to right, causing the packets to be delivered from left to right. The arrows between a tail 715b of the second data packet 710b and the random data 711c and between the tail 715c and random data 71 Id of the fourth data packet 710d illustrate an order in which the data packets 710 and their components are delivered to the integrated circuit 100 and / or the fluid ejection device.

[0082] The zero-pad data 712c may include one or more zeroes. The zero-pad data 712c may have a same length in all of the data packets 710. The head 713c may include a first subset of address bits. The tail 715c may include a second subset of address bits and control bits. The first subset of address bits and the second subset of address bits may be an address codecorresponding to addresses of nozzle circuits on the fluid ejection die. The primitive data 714c may include data identifying primitives, or groups of nozzle circuits, on the fluid ejection die. The address code and the primitive data may identify nozzle circuits for printing. In an example, the address code identifies an address within a primitive, where each primitive on the fluid ejection die includes the same addresses, and the primitive data specifies for which primitives the nozzle circuit corresponding to the address code is activated. In an example, the address code specifies address “1,” and the primitive data specifies in which primitives the nozzle circuit corresponding to address “1” is activated for printing. Thus, different address codes correspond to different locations on the fluid ejection die. A first address code may select a first nozzle circuit on a first location in a nozzle circuit array on the fluid ejection die and a second address code may select a second nozzle circuit on a second location in the nozzle circuit array on the fluid ejection die.

[0083] FIG. 8 is a block diagram illustrating an example repeating address sequence 800 of the data packets 710 of FIG. 7. The repeating address sequence 800 may be a repeating sequence of address codes. Successive address codes of successive data packets of the data packets 710 follow the repeating address sequence 800. In some implementations, the repeating address sequence 800 may be associated with a first type of fluid ejection die. A fluid ejection die of the first type may have circuitry which is configured to process address bits received according to the repeating address sequence 800. A fluid ejection die of a second type may have circuitry which is configured to process address bits received according to a second repeating address sequence. Thus, the fluid ejection die of the second type may print incorrectly if it receives address bits received according to the repeating address sequence 800 instead of according to the second repeating address sequence. In some implementations, the fluid ejection die of the second type may not function if it receives address bits received according to the repeating address sequence 800 instead of according to the second repeatingaddress sequence. In some implementations, different address bits correspond to different nozzle circuit locations on different types of fluid ejection dies. In some implementations, in order to modify data packets having the repeating address sequence 800 for use with a fluid ejection die of the second type, the repeating address sequence 800 must be modified to be the second address sequence, requiring the address bits in the data packets 710 to be modified.

[0084] In an example, the repeating address sequence 800 is transmitted from the host controller to the integrated circuit 100 and the repeating address sequence 800 is incompatible with the fluid ejection device. In this example, the integrated circuit 100 modifies the data packets 710 to translate from the repeating address sequence 800 to a second repeating address sequence to ensure that the fluid ejection device ejects fluid correctly. By modifying the data packets 710, the integrated circuit 100 causes the fluid ejection actions performed by the fluid ejection device to correctly correspond to fluid ejection actions determined by the host device.

[0085] FIG. 9 illustrates an example of modifying the data packets 710 associated with the repeating address sequence 800 of FIG. 8 to generate second data packets 910 associated with a second repeating address sequence. The integrated circuit 100 may modify the data packets 710 to obtain the second data packets 910. In some implementations, the integrated circuit 100 may receive the data packets 710 and generate the second data packets 910. In some implementations, the integrated circuit 100 may modify the data packets 710 to obtain the second data packets 910. As discussed herein, the integrated circuit 100 may modify the address bits of the data packets 710 while leaving other portions of the data packets 710 unchanged to obtain the second data packets 910.

[0086] The integrated circuit 100 may perform an operation 920 to obtain the second data packets 910. The control logic 105 of the integrated circuit 100 may map a first address code to a second address code. The control logic may include the operation 920. The operation 920may include at least one of a mathematical operation and a lookup table. In an example, the operation 920 is an addition / modulo operation. In an example, the operation 920 is a lookup using a lookup table. In some implementations, the lookup table may be based on a mathematical operation. Using the lookup table allows for mapping the packets 710 associated with the repeated address sequence 800 to any other repeating address sequence.

[0087] The data packets 710 and the second data packets 910 may include the same address bits, but in different sequences. In an example, the data packets 710 and the second data packets 910 include address bits corresponding to sixteen different address codes. The repeating address sequence 800 and the second repeating address sequence may each include the sixteen different address codes in a different repeating order. In some implementations, the repeating address sequence 800 and the second repeating address sequence each correspond to a same location sequence corresponding to locations of nozzle circuits on fluid ejection dies. In an example, the repeating address sequence 800 corresponds to nozzle circuits firing down columns from left to right on a fluid ejection die of the first type configured to receive data packets according to the repeating address sequence 800 and the second repeating address sequence corresponds to nozzle circuits firing down columns from left to right on a second fluid ejection die of the second type configured to receive data packets according to the second repeating address sequence.

[0088] In an example, the host controller determines print data including locations of nozzle circuits. The host controller determines first address bits for a first fluid ejection die of the first type associated with the repeating address sequence 800, where the first address bits correspond to nozzle circuits on the first fluid ejection die of the first type in the determined locations of nozzle circuits. However, in this example, a second fluid ejection die of the second type is installed in a printer including the host controller. If the first address bits were delivered to the second fluid ejection die, the second fluid device would either printincorrectly or not function. Thus, in this example, the integrated circuit 100 translates first data packets having the first address bits associated with the repeating address sequence 800 to the second data packets 910 having second address bits associated with the second repeating address sequence. In this example, the second address bits correspond to nozzle circuits on the second fluid ejection die in the determined locations of nozzle circuits of the print data. The integrated circuit 100 delivers the second data packets to the second fluid ejection die, causing the fluid ejection die to print according to the print data.

[0089] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may receive a first data packet from a host controller. The first data packet may include address bits and random data. The second contact 102 may transmit a second data packet including second address bits based on the first address bits to a fluid ejection device. The control logic 105 may generate the second data packet including the second address bits based on the first address bits.

[0090] In some implementations, the integrated circuit 100 generates the second data packet by identifying the first address bits and / or the random data. The control logic 105 may identify the first address bits and / or the random data based on an end of the first data packet. The first data packet may have a standard length or number of bits from the end of the first data packet to the first address bits and / or a beginning of the non-random data of the first data packet. The control logic 105 may identify the first address bits and / or the random data based on a number of bits from the end of the first data packet. In an example, the control logic 105 counts a number of bits from the end of the first data packet to identify the first address bits and / or the random data. In some implementations, generating the second data packet based on the end of the first data packet includes removing and / or changing at least part of the random data from the first data packet. In some implementations, generating the second datapacket includes converting the first address bits to the second address bits according to an address bit sequence associated with the fluid ejection device. In some implementations, generating the second data packet includes applying an address offset associated with the fluid ejection device to the one or more address bits. In some implementations, generating the second data packet includes modifying one or more control bits of the first data packet. In some implementations, the first data packet and the second data packet include a same primitive data.

[0091] In some implementations, the integrated circuit 100 includes a third contact to receive a fire signal from the host controller, wherein identifying the end of the first data packet includes identifying a rising edge of the fire signal. The rising edge of the fire signal may be a predetermined identifier of an end of a data packet and / or a predetermined control to end loading of a data packet. The fire signal may be part of a signal protocol for loading data packets. The rising edge of the fire signal may indicate an end of the signal protocol and / or an end of loading a data packet.

[0092] In some implementations, the integrated circuit 100 includes a third contact to receive a clock signal from the host controller, wherein identifying the end of the first data packet includes determining a clock idle time of the clock signal. The clock idle time may be a portion of time exceeding a period of the clock signal, identifying when the clock signal is silent or idle. The clock signal may be idle at the end of data packets. The clock signal may be used to drive the data packets to the fluid ejection die, allowing for identification of the ends of the data packets based on the clock idle time.

[0093] In some implementations, the first data packet includes the random data, a first head, a first middle portion and a first tail, wherein the first head includes the first address bits, the first middle portion includes the primitive data, and the first tail includes the first address bits and first control bits, wherein the second data packet includes a second head, a second middleportion, and a second tail, wherein the second head includes the second address bits, the second middle portion includes the primitive data, and the second tail includes the second address bits and second control bits. In some implementations, the random data is and / or includes pseudo-random data.

[0094] In some implementations, the first address bits correspond to a first nozzle circuit in a nozzle circuit array of the fluid ejection device, and wherein the second address bits correspond to a second nozzle circuit in the nozzle circuit array of the fluid ejection device.

[0095] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B,, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may receive a first data packet from a host controller, the first data packet including a first payload and additional bits, and the second contact 102 may transmit a second data packet to a fluid ejection device. The control logic 105 may generate the second data packet including a second payload based on the first payload.

[0096] In some implementations, the additional bits include random or pseudo-random data. In some implementations, the first payload includes a first head, a first middle portion and a first tail, wherein the first head includes first address bits, the first middle portion includes primitive data, and the first tail includes the first address bits and first control bits, wherein the second payload includes a second head, a second middle portion, and a second tail, wherein the second head includes the second address bits, the second middle portion includes the primitive data, and the second tail includes the second address bits and second control bits. In some implementations, the second control bits are the same as the first control bits.

[0097] In some implementations, the integrated circuit 100 generates the second data packet by identifying the first payload based on a predetermined amount of time between the first payload and a preceding packet. In some implementations, the control logic 105 determinesthe predetermined amount of time based on identifying ends of adjacent data packets. In some implementations, the control logic 105 reads a clock signal received from the host controller. The control logic 105 may measure the predetermined amount of time using the clock signal.

[0098] In some implementations, generating the second data packet based on the payload of the first data packet includes removing and / or changing the additional bits. In some implementations, generating the second data packet includes modifying the first address bits of the first data packet to generate the second address bits. In some implementations, modifying the first address bits includes converting the first address bits to the second address bits according to an address bit sequence associated with the fluid ejection device. In some implementations, modifying the first address bits includes applying an address offset associated with the fluid ejection device to the one or more address bits.

[0099] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may receive a first data packet from a host controller, the first data packet including random data. The random data may pseudo-random data. The second contact 102 may transmit a second data packet to a fluid ejection device. The control logic 105 may, as the first packet is received, generate the second data packet based on the first packet.

[0100] In some implementations, the integrated circuit 100 generates the second data packet by comparing one or more bits of the first packet to predefined bits and generating the second data packet based on the comparison. Comparing the one or more bits of the first packet to the predefined bits may include using one or more masks or masking state machines to compare the one or more bits to the predefined bits. The predefined bits may follow a pattern of bits. The control logic may determine the predefined bits based on one or more patterns of bits in successive data packets. The predefined bits may be predefined address bits. The patterns of bits may correspond to a repeating address sequence, such as the repeating addresssequence 800 of FIG. 8. In some implementations, the control logic 105 may determine the predefined address bits based on a sequence of address bits received at the first contact. In an example, the first contact 101 may receive a set of data packets from the host controller and the control logic 105 may determine a repeating address sequence based on the set of data packets. In some implementations, the integrated circuit 100 may be configured for use with a specific repeating address sequence. In some implementations, the repeating address sequence is associated with a first type of fluid ejection device and the integrated circuit 100 is connected to a second type of fluid ejection device to translate commands from the host controller for the first type of fluid ejection device into commands for the second type of fluid ejection device. The integrated circuit 100 may transmit one or more signals to the host controller indicating that the host controller should provide commands for a fluid ejection device of the first type. In this way, the fluid ejection device 100 may cause a printer including the host controller to identify the fluid ejection device of the installed print cartridge as a fluid ejection device of the first type. In an example, a printer tracks an ink fill level of a print cartridge to determine when the print cartridge is empty. In this example, the integrated circuit 100 causes the printer to treat the print cartridge to which the integrated circuit 100 is attached as a print cartridge having a first fill level when the print cartridge would be treated as a print cartridge of a second fill level if the integrated circuit 100 were not attached to the print cartridge. In this way, the integrated circuit 100 may change actions taken by the printer, such as low ink warnings.

[0101] In some implementations, the first data packet includes the random data, a first head, a first middle portion and a first tail, wherein the first head includes the first address bits, the first middle portion includes the primitive data, and the first tail includes the first address bits and first control bits. The second data packet may include a second head, a second middle portion, and a second tail, wherein the second head includes the second address bits, thesecond middle portion includes the primitive data, and the second tail includes the second address bits and second control bits.

[0102] In some implementations, the integrated circuit 100 generates the second data packet by modifying the first address bits of the first data packet to generate the second data packet. In some implementations, modifying the one or more address bits includes converting the first address bits to the second address bits according to an address bit sequence associated with the fluid ejection device. In some implementations, modifying the first address bits includes applying an address offset associated with the fluid ejection device to the first address bits.

[0103] In some implementations, the control logic 105, as the first packet is being received, begins transmitting the second data packet to the fluid ejection device. In this way, the integrated circuit 100 may achieve low latency between receiving the first packet and transmitting the second packet, beginning to send the second data packet before the first data packet is entirely received. The control logic 105 may, as the first packet is being received, begin transmitting the second data packet to the fluid ej ection device based on a determination to transmit the second data packet with low latency. The determination to transmit the second data packet with low latency may be based on one or more signals received from the host controller. The control logic 105 may begin transmitting the second data packet based on a set of bits of the first data packet matching a set of bits of the predefined bits and a probability of the set of bits of the first data packet being a beginning of a payload of the first data packet. In some implementations, the control logic 105 may use one or more masking state machines to compare the set of bits of the first data packet to the set of bits of the predefined bits.

[0104] In some implementations, the control logic 105 may generate a third data packet based on a second set of bits of the first data packet not matching a second set of bits of the predefined bits, and transmit the third data packet to the fluid ejection device using the secondcontact. The control logic 105 may compare the second set of bits of the first data packet to the second set of bits of the predefined bits to verify that the determination to begin transmitting the second data packet was correct. The control logic 105 may, based on the second set of bits of the first data packet not matching the second set of bits of the predefined bits, determine that the second data packet contains incorrect information or that the second data packet was incorrectly transmitted, and generate the third data packet to correct the information transmitted in the second data packet. In some implementations, the third data packet may replace the second data packet.

[0105] In some implementations, the control logic may determine, based on a target latency, a transmit point in the first data packet at which the integrated circuit begins transmitting the second data packet, and begin transmitting the second data packet to the fluid ejection device based on the set of bits of the first data packet being the transmit point. The transmit point may be a last position in the first data packet at which the second data packet can be sent to satisfy the target latency, or a time corresponding to receipt at the integrated circuit 100 of the last position in the first data packet at which the second data packet can be sent to satisfy the target latency.

[0106] FIG. 10 illustrates an example of modifying the data packets 710 of FIG. 7 to remove the random data 711. The integrated circuit 100 may receive the data packets 710 at the hostside contact array 110 and transmit the second data packets 910 at the device-side contact array. The integrated circuit 100 may receive signals 701, 702, and 703 at the host-side contact array 110 and transmit signals 901, 902, and 903 at the device-side contact array. The data packets 710 may each include the random data 711 and non-random data 716. The nonrandom data 716 may include the zero-pad data 712, the head 713, the primitive data 714, and the tail 715. The non-random data 716 of each of the data packets 710 may be referred to as a “payload” of each data packet. The non-random data 716 may include the informationactually used by the fluid ejection die. As discussed herein, the random data 711 may be dropped off of a shift register of the fluid ejection device such that the random data 711 is not used by the fluid ejection device in printing. The second data packets 910 may include only non-random data 916 such that the integrated circuit 100 delivers only the non-random data 916 which is actually used by the fluid ejection device in printing to the fluid ejection device.

[0107] In some implementations, the second data packets 910 include the random data 711 or other random data. As discussed herein, as data packets are delivered to the fluid ejection device, extra bits, such as the random data 711, are dropped, meaning that once the data packets 710 have been modified, or the second data packets 910 have been generated, it does not matter whether they contain random data. As discussed herein, the random data 711 is intended to obfuscate the identities of the different bits (e.g., random data 711c, zero-pad data 712c, the head 713c, etc.) to prevent modification of the data packets 710. Once the random data has been identified and / or the identities of the bits of the data packets 710 have been identified, the data packets 710 may be modified, negating the utility of the random data 711. In an example, once the second data packets 910 have been generated based on the data packets 710, new random data and / or the random data 711 may be included in the second data packets 910 which will not affect printing, as the new random data and / or the random data 711 will be dropped by the fluid ejection device.

[0108] A DATA xin signal 704 may be and / or includes the data packets 710. The integrated circuit 100 may receive the DATA xin signal 701 using the fifth contact 112e, the host-side data contact, of the host-side contact array 110. A DCLKin signal 702 may be an input clock signal. The integrated circuit 100 may receive the DCLKin signal 702 using the fourth contact 112d, the host-side clock contact, of the host-side contact array 110. A FIREin signal 703 may be a fire signal. The integrated circuit 100 may receive the FIREin signal 703 using the tenth contact 112j, the host-side fire contact, of the host-side contact array 110. The FIREin signal703 may be in phase with the DCLKin signal 702. The FIREin signal 703 may be synchronized with the non-random data 716 of the data packets 710. In an example, the FIREin signal 703 is synchronized with the address bits in the head 712 and tail 715 and the primitive data 714 of the data packets 710. The FIREin signal 703 may be in phase with the address bits of the data packets 710 based on the DCLKin signal 702. In this way, the FIREin signal 703 lines up with the non-random data 716 to provide correctly synchronized data for controlling the fluid ejection device.

[0109] A DATA xout signal 901 and / or includes the second data packets 910. The integrated circuit 100 may output the DATA xout signal 901 using the fifth contact 122e, the device-side data contact, of the device-side contact array 120. A DCLKout signal 902 may be an output clock signal. The integrated circuit 100 may output the DCLKout signal 902 using the fourth contact 122d, the device-side clock contact, of the device-side contact array 120. In some implementations, the DCLKout signal 902 may be faster than the DCLKin signal 702. A FIREout signal 903 may be a fire signal for controlling firing of nozzle circuits of the fluid ejection device. The integrated circuit 100 may output the FIREout signal 903 using the tenth contact 122j, the device-side fire contact, of the device-side contact array 120. The FIREout signal 903 may be in phase with the DCLKout signal 902. The FIREout signal 903 may be synchronized with the non-random data 916 of the second data packets 910. In an example, the FIREout signal 903 is synchronized with the address bits in the head and tail and the primitive data of the data packets 910. The FIREout signal 903 may be in phase with the address bits of the data packets 710 based on the DCLKout signal 902. In this way, the FIREout signal 903 lines up with the non-random data 916 to provide correctly synchronized data for controlling the fluid ejection device.

[0110] The integrated circuit 100 may identify the random data 711 and the non-random data716 of the data packets 710 based on the ends of the data packets 710. The ends of the datapackets may be ends of the non-random data 716 or ends of the tails 715 of the data packets 710. The integrated circuit 100 may identify the random data 711 and the non-random data 716 of the data packets 710 in order to identify the address bits in order to modify the address bits, as discussed herein. In some implementations, The integrated circuit 100 may identify the random data 711 and the non-random data 716 of the data packets 710 in order to identify the address bits in order to modify the address bits and / or remove the random data 711.[OHl] The integrated circuit 100 may identify the ends of the data packets 710 based on rising edges of fire 1002. The rising edges of fire 1002 may be portions of the FIREin signal 703 where the FIREin signal 703 transitions from logic low to logic high. The rising edges of fire 1002 may be a predetermined identifier of an end of a data packet and / or a predetermined control to end loading of a data packet. The FIREin signal 703 may be part of a signal protocol for loading data packets. The rising edges of fire 1002 may indicate an end of the signal protocol and / or an end of loading a data packet.

[0112] A first rising edge of fire 1002a may indicate an end of the second data packet 710b. The integrated circuit 100 may determine, based on the first rising edge of fire 1002a that data immediately preceding the first rising edge of fire 1002a is the second data packet 710b. The integrated circuit 100 may determine, based on the first rising edge of fire 1002a that a predefined number of bits immediately preceding the first rising edge of fire 1002a is the nonrandom data 716b of the second data packet 710b. In this way, the integrated circuit 100 may utilize known data transfer protocols between the host controller and the fluid ejection device. The integrated circuit 100 may be configured based on the known data transfer protocols to recognize different sequences of signals and / or protocols which the host controller uses to communicate with the fluid ejection device. In an example, the integrated circuit 100 may determine that fourteen bits received immediately preceding the first rising edge of fire 1002a are the non-random data 716b of the second data packet 710b. The integrated circuit 100 maydetermine, based on the first rising edge of fire 1002a that a first set of bits and a second set of bits received a first predefined number of bits and a second predefined number of bits, respectively, immediately preceding the first rising edge of fire 1002a are the address bits of the second data packet 710b. In an example, the integrated circuit 100 may determine that a first pair of bits and a second pair of bits received twenty -five and three bits, respectively, before the first rising edge of fire 1002a are the address bits of the second data packet 710b.

[0113] A second rising edge of fire 1002b may indicated an end of the third data packet 710c. The integrated circuit 100 may determine, based on the second rising edge of fire 1002b that data immediately preceding the second rising edge of fire 1002b is the third data packet 710c. The integrated circuit 100 may determine, based on the second rising edge of fire 1002b that a predefined number of bits immediately preceding the second rising edge of fire 1002b is the non-random data 716c of the third data packet 710c. In an example, the integrated circuit 100 may determine that 14 bits received immediately preceding the second rising edge of fire 1002b are the non-random data 716c of the third data packet 710c. The integrated circuit 100 may determine, based on the second rising edge of fire 1002b that a first set of bits and a second set of bits received a first predefined number of bits and a second predefined number of bits, respectively, immediately preceding the second rising edge of fire 1002b are the address bits of the third data packet 710c. In an example, the integrated circuit 100 may determine that a first pair of bits and a second pair of bits received twenty-five and three bits, respectively, before the second rising edge of fire 1002b are the address bits of the third data packet 710c.

[0114] FIG. 11 illustrates an example of identifying the ends of the data packets 710 of FIG. 7 based on a clock idle time 1102a, 1102b or a predetermined amount of time 1104a, 1104b between the non-random data 716 of successive data packets.

[0115] The integrated circuit 100 may identify the end of the second data packet 710b based on a first clock idle time 1102a. The first clock idle time 1102a may be a period of time, longer than a period of the DCLKin signal 702, when the DCLKin signal 702 is idle, or is not oscillating between logic high and logic low. The integrated circuit 100 may determine that the second data packet 710b has been received based on the first clock idle time 1102a. The integrated circuit 100 may determine that bits received immediately preceding the first clock idle time 1102a are the second data packet 710b. The integrated circuit 100 may, in like manner, identify the end of the third data packet 710c based on a second clock idle time 1102b. The first clock idle time 1102a and the second clock idle time 1102b may have different lengths, both being longer than the period of the DCLKin signal 702. The first clock idle time 1102a and the second clock idle time 1102b may have different lengths based on the random data 711c of the third data packet and the random data 71 Id of the fourth data packet having different lengths. In an example, the first clock idle time 1102a is longer than the second clock idle time 1102b based on the random data 711c of the third data packet being shorter than the random data 71 Id of the fourth data packet.

[0116] The integrated circuit 100 may identify the end of the second data packet 710b based on a first predetermined amount of time 1104a between the non-random data 716b of the second data packet 710b and the non-random data 716c of the third data packet 710b. The integrated circuit 100 may identify the end of the third data packet 710c based on a second predetermined amount of time 1104b between the non-random data 716c of the third data packet 710c and the non-random data 716d of the fourth data packet 710d. The first predetermined amount of time 1104a and the second predetermined amount of time 1104b may be the same amount of time. The integrated circuit 100 may determine the ends of the data packets 710 based the predetermined amounts of time 1104 when a common predetermined amount of time exists between the non-random data of successive data packets.

[0117] FIG. 12 illustrates using predefined bits to identify the non-random data 716 of the data packets of FIG. 7. The predefined bits may be bits that are known and / or predicted by the integrated circuit 100. The predefined bits may be bits that are determined by the integrated circuit 100 based on analyzing previous data packets of the data packets 710. In an example, the integrated circuit 100 may determine values for one or more control bits of the data packets 710 based on values of control bits of previous data packets of the data packets 710. The predefined bits may be bits that are initially programmed in the control logic 105 of the integrated circuit 100. In an example, the predefined bits may be a repeating address sequence that is initially programmed in the control logic 105, such as the repeating address sequence 800 of FIG. 8.

[0118] A table 1200 and / or one or more masks may be used to compare bits of the data packets 710 to the predefined bits. The table 1200 is provided for illustrative purposes to describe a logic of comparing the bits of the data packets 710 to the predefined bits. The table 1200 may simply be a representation of masks that are used to compare the bits of the data packets 710 to the predefined bits. The masks may be included in or be representations of masking state machines. Other data structures are contemplated and may be used in similar or different manner for the comparison.

[0119] The table 1200 may include bit numbers 1210 indicating a number of bits from a beginning of a series of bits. In the illustrated example, the bit numbers 1210 may include thirty-four bits, representing data packets having twenty-six bits of non-random data and zero to eight bits of random data. The table 1200 may include mask numbers 1220 identifying different masks used for comparing the bits of the data packets 710 to the predefined bits. In the illustrated example, five different masks are used, corresponding to five different amounts of bits in the random data. The table 1200 may include random bit amount indicators 1230 associated with the mask numbers 1220, the random bit amount indicators 1230 indicatinghow many random bits are associated with each mask. In the illustrated example, the five masks have zero, two, four, six, and eight random bits, respectively. The table 1200 may include indications of random bits 1240. The indications of random bits 1240 may represent the random bits of the random data 711 in the data packets 710. A number of bits in a packet may correspond to the random bit amount indicators 1230. In the illustrated example, the first mask includes zero bits, the second mask includes two bits, the third mask includes four bits, the fourth mask includes six bits, and the fifth mask includes eight bits in the indications of random bits 1240. The table 1200 may include primitive bit indicators 1260 corresponding to the primitive data 714 of the data packets 710.

[0120] The table 1200 may include first predefined bits 1250 and second predefined bits 1270. The first predefined bits 1250 may correspond to the heads 713 of the data packets 710. The first predefined bits 1250 may correspond to the address bits in the heads 713 of the data packets 710. The second predefined bits 1270 may correspond to the tails 715 of the data packets 710. The second predefined bits 1270 may correspond to the address bits and control bits in the tails 715 of the data packets 710. The first predefined bits 1250 and the second predefined bits 1270 may represent bits that are known or which can be determined or predicted by the integrated circuit 100.

[0121] The first predefined bits 1250 and the second predefined bits 1270 may correspond to the masks. In some implementations, the masks include only the first predefined bits 1250. In an example, the masks may include only the first predefined bits 1250 corresponding to the first set of address bits in the heads 713 of the data packets 710. In some implementations, the masks include only the second predefined bits 1270. The masks may be static or dynamic. In an example, the masks are static and correspond to the address bits of a known repeating address sequence. In an example, the masks are dynamic and correspond to the address bits of a known repeating address sequence and control bits, which may change periodically.

[0122] The masks may be programmed with the predefined bits to compare the bits of the data packets 710 with the predefined bits. In an example, the integrated circuit 100, as the integrated circuit 100 receives bits of a first data packet, compares the bits to masks programmed with a repeating address sequence of address bits to determine which of the masks matches the bits. Once a mask matching the bits has been identified, the integrated circuit generates and transmits a second data packet based on the first data packet.

[0123] FIG. 13 illustrates an example method 1300 of using masks to identify the nonrandom data 716 of the data packets of FIG. 7. The integrated circuit 100 may perform the method 1300. The table 1200 of FIG. 12 may be used by the integrated circuit 100, or another similar data structure may be used in performing the method 1300. The method 1300 may include additional, fewer, or different operations than illustrated. The operations may be performed in the order shown, in a different order, or concurrently.

[0124] At 1301, a decision index and mask index may be set. The mask index may correspond to a mask of the masks. In an example, the mask index corresponds to a mask number of the mask numbers 1220 of FIG. 12. The decision index may be a point in a data packet and / or a time after the beginning of the data packet at which a decision identifying the non-random data of the data packet is made. The decision index may correspond to a bit number of the bit numbers 1210 of FIG. 12. The decision index may be or define a transmit point at which a second data packet of the second data packets 910 must be sent or begin to be sent. In an example, the decision index may be a transmit point of six bits indicating that the integrated circuit 100 will begin to transmit a second data packet based on a first data packet once six bits of the first data packet have been received. The integrated circuit 100 may generate the second data packet as the integrated circuit 100 receives the first data packet. Identifying the non-random data of the data packets 710 as the data packets 710 are received is probabilistic, as there is a chance of misidentifying the random data of a data packet as the non-randomdata of the data packet. In an example, the first address bits in the head 713c of the third data packet 710c may be “0, 5” and a first mask may be programmed with predefined bits “0, 5” based on a known repeating address sequence to compare the bits of the third data packet 710c with the predefined bits. In this example, if the random data 711c of the third data packet 710c includes a pair of bits “0, 5” the mask may match the random data 711c, causing the random data 711c to be incorrectly identified as the beginning of the non-random data 716c of the third data packet 710c. The later the decision index, and thus, the greater number of bits compared to masks, the greater the probability that the non-random data 716 is identified. If the decision index is at the end of a packet, the decision is the same as identifying the end of the packet, and is deterministic.

[0125] The decision index may be based on a target latency. The target latency may be an amount of latency allowed between receiving the start of a first data packet from the host controller and transmitting the start of a second data packet to the fluid ejection device. The target latency may be based on an acceptable latency for printing and / or a minimum response latency required by the host controller.

[0126] At 1302, a determination is made as to whether low latency is needed 1302. The determination that low latency is needed may be based on the acceptable latency for printing and / or the minimum response latency required by the host controller. The determination that low latency is needed may be based on a determination that the host controller is monitoring the latency and / or that the host controller is monitoring a timing of responses from the fluid ejection device. In an example, the determination that low latency is needed may be based on one or more control bits indicating that the host controller is monitoring the latency. If low latency is not needed, the end of the packet is observed at 1303. As discussed herein, observing the end of the packet is a deterministic approach to identifying the non-random data 716 of the packets 710. Other deterministic approaches to identifying the non-randomdata 716 of the packets 710 may be used, such as using the clock idle times 1102 or the predetermined times 1104 of FIG. 11.

[0127] If low latency is needed, a determination is made at 1304 as to whether the decision point is reached as bits of data packet are received. The decision point, or transmit point, corresponds to the decision index. The decision index may correspond to the mask index. In some implementations, each mask index has a different corresponding decision point. Once the decision point is reached, a determination is made at 1305 as to whether the received bits match the mask corresponding to the mask index. In an example, if the decision point is at bit number 2, then once two bits have been received, the two bits are compared to the mask corresponding to the mask index. If the bits do not match the mask, at 1306 the decision index and the mask index are iterated. In an example, if the decision point corresponding to an initial decision index is at bit number 2, causing comparison between an initial mask including predefined bits and the first two bits, a subsequent decision index may be at bit number 4, causing comparison between a subsequent mask including the predefined bits and the third and fourth bits. Once the subsequent decision point corresponding to the subsequent decision index is reached at 1304, the bits are compared to the subsequent mask 1305. Operations 1304-1306 repeat until the bits match the mask.

[0128] Once the determination is made that the bits match the mask at 1305, a second packet, based on the first packet begins to be sent. In an example, the integrated circuit 100 modifies the address bits of the first data packet to generate the second data packet. In this example, the integrated circuit can identify the address bits upon determining that the received bits of the first data packet match the mask including predefined address bits of a repeating address sequence at 1305. In this example, once the address bits of the first data packet are identified, the integrated circuit can modify the address bits and begin to transmit the second data packet at 1307. In some implementations, transmitting the second data packet includes modifyingthe address bits of the first data packet and allowing the primitive data of the first data packet to pass through to the fluid ejection device unchanged. In some implementations, modifying the address bits of the first data packet includes translating between repeating address sequences and / or applying an address offset to the address bits, as discussed herein. The address offset may be one or more address offsets. In an example, a first address offset associated with a first type of fluid ejection device and a second address offset associated with a second type of fluid ejection device corresponding to the fluid ejection device connected to the integrated circuit 100 are applied to the address bits. In some implementations, transmitting the second data packet includes generating the second data packet based on the first data packet.

[0129] At 1308, a determination is made as to whether the mask decision was correct. The determination may be made based on comparing later bits in the first data packet to other predefined bits. In an example, if the decision point allows only for comparison of the first predefined bits 1250 of FIG. 12 to the bits of the first data packet, then the decision identifying the address bits and to begin transmitting the second data packet may be verified by comparing the second predefined bits 1270 to the bits of the first data packet. In an example, the decision identifying the address bits and to begin transmitting the second data packet may be verified by identifying the end of the first data packet to identify the address bits. As the identification of the address bits using the mask was probabilistic, there is a chance that the decision was incorrect.

[0130] If the mask decision made at 1305 was correct, as verified at 1308, the decision index and mask index are set at 1301. The decision index and mask index may be set to initial values. The masks may be updated with new predefined bits, such as subsequent address bits in a repeating address sequence and / or updated control bits.

[0131] If the mask decision made at 1305 was incorrect, as determined at 1308, a determination is made at 1309 as to whether low latency is needed. As the second packet has already begun to be transmitted, or is currently being transmitted, the determination at 1309 as to whether low latency is needed depends on whether low latency is more important than printing quality, as the second data packet, based on the decision at 1305, includes incorrect print data. In an example, the second data packet includes incorrect print data due to the random data being incorrectly identified as the address bits, causing the address bits and potentially additional random bits of the random data to be sent as primitive data. In this example, the contents of the second data packet are shifted based on the incorrect identification of the random data as the address bits, causing the incorrectly identified random bits to be modified as address bits, any subsequent random bits and the actual address bits to be sent as primitive data, and the actual primitive data to be shifted based on the position of the incorrectly identified random bits. Thus, the second data packet includes print data that does not match the print data sent by the host controller.

[0132] In some implementations, the determination at 1309 as to whether low latency is needed depends on whether the host controller is checking for low latency. The integrated circuit may determine that low latency is needed based on the printer monitoring the latency of packets sent to the fluid ejection device and / or the printer requiring a response from the fluid ejection device within a predetermined time period.

[0133] In an example, if the random bits at bit positions “3” and “4” in the table 1200 of FIG. 12 are incorrectly identified as the address bits while the actual address bits are at bit positions “7” and “8,” the random bits at bit positions “3” and “4” will be modified as address bits, the random bits at bit positions “5” and “6” and the actual address bits at bit positions “7” and “8” will be transmitted as primitive bits, the primitive bits at bit positions “9-18” (the first ten primitive bits) will be transmitted as the fifth through fourteenth primitive bits of the seconddata packet, and the primitive bits at bit positions “19-22” will be transmitted as control bits of the second data packet. In this example, as the primitive bits in the second data packet are incorrect, the fluid ejection device will not print according to the print data sent by the host controller, but will print according to the incorrect primitive data.

[0134] If the determination is made at 1309 that low latency is not needed, the second data packet is re-transmitted at 1311 to align with the correct address bits, or a third data packet based on a correct identification of the address bits is transmitted at 1311 to replace the transmitted second data packet. In some implementations, the second data packet is retransmitted at 1311 or the third data packet is transmitted based on comparison of the additional predefined bits with the first data packet. In some implementations, the second data packet is re-transmitted at 1311 or the third data packet is transmitted at 1311 based on identifying the end of the first data packet to identify the address bits of the first data packet. The re-transmitted second data packet or third data packet may be sent to the fluid ejection device, causing the fluid ejection device to print according to the print data from the host controller, but with increased latency. As discussed herein, the clock signal from the integrated circuit 100 may be faster than the clock signal from the host controller, meaning that the latency incurred by re-transmitting the second data packet or transmitting the third data packet is less than an amount of time required to determine at 1308 that the mask decision was incorrect and to re-generate the second data packet or generate the third data packet.

[0135] If the determination is made at 1309 that low latency is not needed, the second data packet is not re-transmitted, and the fluid ejection device is allowed to print with the incorrect print data in the second data packet as transmitted at 1310.

[0136] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the integrated circuit 100 may receive, at the host-side contact array 110, a first data packetcorresponding to a request to read a first memory bit on a fluid ejection device. The integrated circuit 100 may transmit, from the device-side contact array 120, a second data packet corresponding to a request to read a second memory bit on the fluid ejection device. The integrated circuit 100 may receive, at the device-side contact array 120, a read response corresponding to a state of the second memory bit. The integrated circuit 100 may transmit, from the host-side contact array, the read response. In this way, the integrated circuit 100 may intercept requests from the host controller to read bits on the fluid ejection device, causing a different read response to be sent to the host controller than would be sent to the host controller from the fluid ejection device in response to the read request from the host controller. The integrated circuit 100 may redirect the read response from the host controller to a different bit on the fluid ejection device, or generate a new read response directed to the different bit. By redirecting the read request and receiving a response from the fluid ejection die, the integrated circuit 100 can ensure that the response from the fluid ejection die has all of the characteristics associated with a genuine and / or expected fluid ejection device.

[0137] The integrated circuit 100 may determine what memory bits the host controller is attempting to read and / or write to. The integrated circuit 100 may transmit one or more signals to the host controller to respond to the request received from the host controller. In some implementations, the integrated circuit 100 may generate the response and / or transmit the request or a request generated by the integrated circuit to the fluid ejection device to obtain the response.

[0138] The host-side contact array 110 may include a first column including the host-side fire contact 112j and a second column including the host-side data contact 112e, the host-side mode contact 112c, and the host-side clock contact 112d.

[0139] In some implementations, the control logic 105 is configured to receive the first data packet by receiving one or more signals corresponding to a memory access protocolincluding: at the host-side mode contact 112c, a first transition to logic high, at the host-side data contact 112e, a logic high signal, and at the host-side fire contact 112j, a second transition to logic high. The host-side contact array 110 may include the host-side sense contact 112b. The control logic 105 may transmit the read response by transmitting the read response at the host-side sense contact 112b.

[0140] In some implementations, the second memory bit is an unused bit. As used herein, an “unused bit” may refer to a bit on the fluid ejection device that is not normally accessed by the host controller or which does not correspond to information requested by the host controller during ordinary operation. In an example, the fluid ejection device may include one hundred bits, fifteen of which are used to store information accessed by the host controller. In this example, all of the functions of the host controller can be performed using the fifteen bits on the fluid ejection device which are used to store the information accessed by the host controller. Over a lifetime of the fluid ejection device, only the fifteen bits are accessed by the host controller. In this example, the other eighty-five bits that are not accessed by the host controller are unused bits.

[0141] In some implementations, the control logic 105 may receive, at the host-side contact array 110, a third data packet corresponding to a request to write to the first memory bit. The control logic 105 may transmit, at the device-side contact array 120, a fourth data packet corresponding to a write to the second memory bit. In this way, the integrated circuit 100 may store, or record, the request to write to the first memory bit from the host controller in the second memory bit. In some implementations, the read response corresponds to the write to the second memory bit. In an example, if the host controller attempts to read a bit to which the host controller previously wrote, the integrated circuit 100 can redirect the read request to the bit in which the integrated circuit 100 recorded the original write request, or to which the integrated circuit 100 redirected the original write request. In this way, the integrated circuit100 may provide responses to the host controller consistent with previous actions of the host controller. The control logic 105 may include a mapping of the first memory bit to the second memory bit. The control logic 105 may direct read requests and write requests from the host controller directed to the first bit to the second bit based on the mapping.

[0142] The second data packet may be based on the first data packet. In some implementations, the second data packet includes different address bits and / or different primitive bits than the first data packet. The integrated circuit 100 may modify the first data packet to modify the address bits of the first data packet to generate the second data packet such that the second data packet is identical to the first data packet except that the second data packet is directed to the second bit.

[0143] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the integrated circuit 100 may include one or more host-side contacts, one or more deviceside contacts, and control logic to receive, at the one or more host-side contacts, a first read request for a first memory bit on a fluid ejection device, in response to the first read request, transmit, at the one or more device-side contacts, a second read request for a second memory bit on the fluid ejection device, receive, at the one or more device-side contacts, a read response corresponding to a state of the second memory bit, and transmit, at the one or more host-side contacts, the read response.

[0144] The one or more contacts may include a first column including the host-side fire contact 112j and a second column including the host-side data contact 112e, the host-side mode contact 112c, and the host-side clock contact 112d.

[0145] In some implementations, the control logic 105 is configured to receive the first read request by receiving one or more signals corresponding to a memory access protocolincluding: at the host-side mode contact 112c, a first transition to logic high, at the host-side data contact 112e, a logic high signal, and at the host-side fire contact 112j, a second transition to logic high. The one or more contacts may include the host-side sense contact 112b. The control logic 105 may transmit the read response by transmitting the read response at the hostside sense contact 112b.

[0146] In some implementations, the second memory bit is an unused bit. In some implementations, the control logic 105 may receive, at the one or more contacts, a first write request for the first memory bit. The control logic 105 may transmit, at the device-side contact array 120, a second write request for the second memory bit. In this way, the integrated circuit 100 may store, or record, the first write request to the first memory bit from the host controller in the second memory bit. In some implementations, the read response corresponds to the second write request for the second memory bit. In an example, if the host controller attempts to read a bit to which the host controller previously wrote, the integrated circuit 100 can redirect the read request to the bit in which the integrated circuit 100 recorded the original write request, or to which the integrated circuit 100 redirected the original write request. In this way, the integrated circuit 100 may provide responses to the host controller consistent with previous actions of the host controller. The control logic 105 may include a mapping of the first memory bit to the second memory bit. The control logic 105 may direct read requests and write requests from the host controller directed to the first bit to the second bit based on the mapping.

[0147] The second data packet may be based on the first data packet. In some implementations, the second data packet includes different address bits than the first data packet. The integrated circuit 100 may modify the first read request to modify the address bits of the first read request to generate the second read request such that the second read requestis identical to the first read request except that the second read request is directed to the second bit.

[0148] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, the integrated circuit 100 may be configured to be attached to, or attached to, a print cartridge including a fluid ejection device, the host-side contact array 110 including at least one contact column to contact corresponding printer contacts. The host-side contact array 110 may include a fire contact and a contact column comprising an analog contact, a mode contact, a clock contact and at least one data contact. The control logic 105 may receive, over a period of a plurality of (e.g., 13) clock cycles, a first data access signal sequence comprising a high signal over the mode contact, a low signal over the fire contact, and a signal over the data contact. The control logic 105 may receive, a second data access signal sequence comprising a high signal over the mode contact and a low signal over the fire contact, and data access signals over the data contact. The data signals may indicated a read or write event. The second data access signal may be received over a period of a plurality of (e.g., 3, 13) clock cycles.

[0149] In response to the first and second data access signal sequences, the control logic 105 may respond with a data value corresponding to the data access signals of the read event, if the data access signals indicated a read event, and process bits of the write event, if the data access signals indicated a write event, to respond with the processed bits in a later read event. The control logic 105 may not respond with data values in response to other signal sequences that do not comprise the first and second data access signal sequence.

[0150] In some implementations, the device-side contact array 120 includes device-side contacts to contact the fluid ejection device. The control logic 105 may be configured to modify and / or transmit some of the other signals to the fluid ejection device. In some implementations, the host-side contact array 110 and / or the device-side contact array isarranged in two columns that extend over two parallel lines and includes further contacts including at least one of logic power, high power, ground, reset and a pen detect contact.

[0151] In some implementations, the contact array is a host-side contact array and the integrated circuit further comprises a device-side contact array to contact the fluid ejection device with some or all of the same contacts in at least partially the same yet mirrored arrangement, whereby the integrated circuit comprises a thin substrate including an isolation layer between at least some of the host-side and device-side circuitry.

[0152] By redirecting read and / or write requests from the host controller and receiving a response from the fluid ejection die, the integrated circuit 100 can ensure that the response from the fluid ejection die has all of the characteristics associated with a genuine and / or expected response from the fluid ejection device. Thus, the host controller will recognize the response as a genuine and / or expected response from the fluid ejection device. Furthermore, the integrated circuit 100 can manipulate various different memory access protocols to deliver specific responses to the host controller. In an example, if the host controller attempts to access a memory bit associated with a use of the fluid ejection device to determine whether to send fluid ejection commands to the fluid ejection device, the integrated circuit 100 may redirect the host controller’s attempted memory access to a different bit such that the host controller determines that the fluid ejection device is not used or substantially unused (e.g., 90% ink level remaining). In this example, if a specific use gauge on the fluid ejection device includes bits that are written to as the fluid ejection device prints, the integrated circuit may redirect reads from the host controller of the use gauge to other, unwritten bits on the fluid ejection device. In this way, the integrated circuit 100 may modify actions of the host controller, causing the host controller to treat the fluid ejection device as an unused, and / or less used fluid ejection device, in good condition and / or operating as expected. In an example, the integrated circuit 100 may cause the host controller to treat the fluid ejection device asbeing used for 5% of its expected lifetime instead of 100% of its expected lifetime. By redirecting bit access requests from the host controller, the fluid ejection device 100 may modify various operations of the host controller and / or the fluid ejection device performed in response to known access protocols between the host controller and the fluid ejection device.

[0153] FIG. 14 is a flowchart of an example memory access protocol 1400. The method access protocol 1400 may include more, fewer, or different operations than shown. The operations may be performed in the order shown, in a different order, or concurrently. The memory access protocol may be used to access memory bits on a fluid ejection device, such as memory bits for controlling actuation of nozzle circuits. The memory access protocol 1400 may be observed, modified, and / or performed by the integrated circuit 100. In an example, the integrated circuit 100 may receive one or more signals corresponding to the memory access protocol 1400 from the host controller. While specific bits, signals, and circuit components such as registers are named, these specific elements are merely examples of more general components and elements that may also have the same results.

[0154] At 1402, a non-volatile memory (NVM) enable bit is written in a configuration register. As used herein, the NVM-enable bit may refer to a bit to enable a floating gate avalanche metal oxide semiconductor (FAMOS) element that may act as a memory element. As noted above, other memory elements capable of storing and switching between at least two states of a bit of information may also be used. The writing of the NVM-enable bit to a configuration register may also refer to other examples of other storage elements other than registers. The configuration register may be replaced by other circuitry or data organization methods capable of receiving and storing information such as the NVM-enable bit for a configuration circuit within the fluid ejection device.

[0155] At 1404, nozzle data is loaded to the integrated circuit and / or to the fluid ejection device. The nozzle data may include information for setting the NVM-enable bit in the datastream as well as the information for selecting a nonvolatile memory (NVM) bit to access using a specific address for a nozzle. The nozzle data may be loaded using the data contact 112e of the host-side contact array 110 and / or the data contact 122e of the device-side contact array. When the host controller is loading the nozzle data to the integrated circuit 100, the data contact 112e of the host-side contact array 110 may be used. When the integrated circuit 100 is loading the nozzle data or modified nozzle data to the fluid ejection device, the data contact 122e of the device-side contact array 120 may be used.

[0156] The nozzle data may indicate a selection of which nozzle circuits are to be fired in response to an upcoming FIRE signal. The selection of which nozzle circuits are to be fired next can be stored in nozzle memory bits (e.g., flops or latches) corresponding to the nozzle circuits. In an example, the selection data provided by the data contact 122e of the deviceside contact array 120 also includes a corresponding NVM-enable bit in the nozzle selection data. In an example, the NVM-enable bit may be transmitted in the header or footer of the nozzle selection data. In some implementations, the selection data provided by the data contact 122e of the device-side contact array 120 also includes bank-select bits, indicating in which memory bank the selected bits are located in the fluid ejection device.

[0157] As noted above, 1402 and 1404 may be done in either order. The result of these two steps is that the NVM-enable bit is written into the configuration register and the NVM-enable bit is set.

[0158] At 1406, a FIRE signal is driven to signal high then low. The FIRE signal may be a signal that is sent to each nozzle circuit of the fluid ejection device. The FIRE signal may be transmitted from the integrated circuit 100 using the fire contact 122j of the device-side contact array 120. The bits of the registers may be electrically connected to the nozzle circuits and the fire contact 122j of the device-side contact array 120 which results in actions being taken at the configuration register when signals are sent using the fire contact 122j of thedevice-side contact array 120. A signal being driven high then low may refer to an amplitude of the signal roughly corresponding to the intensity of the signal whether it is a current or voltage. In an example, driving a FIRE signal high can be interpreted as a value of 1, while a FIRE signal driving low or not at all can be interpreted as having a value of 0. These high and low values may be referred to as “logic high” and “logic low,” respectively. In an example, the FIRE signal drives from 0 to 1 to 0. The variation in the signaling can indicate when an action, such as firing nozzles should take place. The driving of the FIRE pad from high to low may clear the NVM-enable bit of the configuration register. The driving of the FIRE pad from high to low may set a latch within the fluid ejection device. This internal latch combined with future signaling may enable a memory bit access.

[0159] At 1408, an NVM-enable bit is written in a configuration register. This is the same action as at 1402 however at 1408, the internal latch has been set and the NVM-enable bit was cleared in the configuration register. Writing the NVM-enable bit again into the configuration register, while the NVM-enable bit is being transmitted using the data contact 122e enables access to a memory access bit in a memory configuration register.

[0160] At 1410, the memory access bit is written in the memory configuration register. The memory configuration register can be another storage element separate from the configuration register. In some examples there are fewer bits in the memory configuration register than the configuration register. Once the memory access bit is written into the memory configuration register, the memory of the fluid ejection device may be accessed. The enabled bits of the memory configuration register can act as control signals that enable the NVM or FAMOS memory elements to be accessed.

[0161] At decision 1412, a determination is made based on the control signals indicated by the bits of the memory configuration register, as written at 1410. If the bits of the memory configuration register indicate a memory write, the method 1400 proceeds to 1414. If the bitsof the memory configuration register do not indicate a memory write, the method 1400 proceeds to 1416.

[0162] At 1414, the FIRE contact 122j is driven high for a desired write time, then low. In an example, the driving of the FIRE contact 122j can include providing a 0 signal, then a 1 signal, then a 0 signal on the fire line. The value of the signal can correspond to a current or voltage on the FIRE contact 122j. During the duration of the write time, the memory element, such as a FAMOS, may be accessed. Accessing the FAMOS or other memory element can include writing information into the FAMOS or memory element.

[0163] At 1416, the FIRE contact 122j may be driven high and a voltage or current forced on the sense contact 122b for measurement, then returning the FIRE contact 122j to a low signal. During the duration of the read time, the memory element (e.g., FAMOS), may be accessed. A current or voltage response on sense contact 122b may indicate a value (e.g. programming level) of the memory element. The sense contact 122b may be used to detect conditions in the fluid ejection device such as cracks or a temperature of a print die. Whether proceeding through 1414 or 1416, the falling edge of the FIRE signal clears the memory configuration register and clears the NVM-enable bit of the configuration register.

[0164] The memory access protocol 1400 includes various signals which cause specific responses at the fluid ejection die of the fluid ejection device. When the integrated circuit 100 performs the memory access protocol 1400 by transmitting the various signals of the memory access protocol 1400 to the fluid ejection device using the device-side contact array 120, the fluid ejection device responds as described in steps 1402-1414. However, when the host controller performs the memory access protocol 140 by transmitting the various signals of the memory access protocol 1400 to the integrated circuit 100, the integrated circuit 100 does not necessarily respond in the same manner as the fluid ejection device. The integrated circuit 100 may include memory elements to mirror the memory elements of the fluid ejectiondevice, or the integrated circuit may have different memory elements. In this way, the integrated circuit 100 may provide different responses than would be provided by the fluid ejection device. The integrated circuit 100 may provide responses to the host controller configured to elicit specific responses from the host controller. In an example, if the host controller attempts to read memory bits to determine whether the fluid ejection device is used or of a compatible type of fluid ejection device, the integrated circuit 100 provides responses that cause the host controller to view the fluid ejection device as an unused, less used, and / or compatible type of fluid ejection device.

[0165] The integrated circuit 100 may receive the various signals of the memory access protocol 1400, recognize that the memory access protocol 1400 is being performed, and respond accordingly. The integrated circuit 100 may respond by redirecting the signals of the memory access protocol 1400 to another bit not specified in the memory access protocol 1400. The integrated circuit 100 may respond by generating its own signals for the memory access protocol 1400 to access the memory bits of the fluid ejection device. The integrated circuit 100 may allow some signals of the memory access protocol 1400 to be delivered from the host controller to the fluid ejection device while modifying other signals of the memory access protocol 1400. As discussed herein, the integrated circuit may pass through, intercept, and / or override signals from the host controller intended for the fluid ejection device. In an example, the integrated circuit 100 may allow the signals of the memory access protocol 1400 to pass through from the host controller to the fluid ejection device, changing only which bits are addressed in the memory access protocol 1400.

[0166] FIG. 15 illustrates an example configuration register write protocol 1500. The configuration register write protocol 1500 may include a series of signals for accessing a configuration register of the fluid ejection device. The configuration register write protocol 1500 may be used at 1410 of FIG. 14 for writing the memory access bit in the memoryconfiguration register. The integrated circuit 100 may use the configuration register write protocol 1500 to access the memory configuration register of the fluid ejection device as at 1410. The integrated circuit 100 may receive the configuration register write protocol 1500 from the host controller at the host-side contact array 110 and transmit the configuration register write protocol 1500 at the device-side contact array 120.

[0167] As noted above, other data organizing and storing structures other than registers are contemplated. In an example, other storage elements may be used in place of a register. The signal sets are provided to illustrate one way of accessing the configuration register using the same contacts that are used to provide data to fluid actuation devices such as nozzle circuits.

[0168] The configuration register write protocol 1500 can include a MODE signal 1502, a FIRE signal 1504, a DCLK signal 1506, and a DATA signal 1508. As discussed herein, the host controller and / or the integrated circuit 100 may generate and / or transmit the configuration register write protocol 1500 to the fluid ejection device. The mode signal 1502 may be transmitted using the mode contact 122c of the device-side contact array 120. The fire signal 1504 may be transmitted using the fire contact 122j of the device-side contact array 120. The fire signal 1504 may be transmitted to the configuration register of the fluid ejection device as well as the nozzle circuits and may instruct actuation of the nozzle circuits. Actuation of the nozzle circuits can include dispersing ink droplets corresponding to selected nozzle circuits towards a print medium. The FIRE signal 1504 may also cause writing or clearing of bits in registers or memory, as discussed in the memory access protocol 1400 of FIG. 14. The DCLK signal 1506 may be transmitted using the clock contact 122d of the device-side contact array 120. The DCLK signal 1506 enables actions on the rising actions of each clock tick. The DATA signal 1508 may be transmitted using the data contact 122e of the device-side contact array 120. The DATA signal 1508 can include configuration data transmitted during the memory access protocol of FIG. 14.

[0169] The configuration register may be enabled for a write action when the MODE signal 1502 transitions to logic high at 1510 with the DATA signal 1508 also being logic high at 1512. After this configuration register enabling action in the MODE signal 1502 and the DATA signal 1508, further data may be loaded into the configuration register in time with the rising edges of the DCLK signal 1506. The DCK signal 1506 may include a first rise 1514, a second rise 1016, a third rise 1518, and a fourth rise 1520. In time with each of these rises, data from the DATA signal 1508 may be transmitted to the configuration register.

[0170] In an example, data for a third place bit 1522 for a configuration register may be shifted into the configuration register when the DATA signal 1508 is signaling high at the time of the first rise 1514 on the DCLK signal 1506. Data for a second place bit 1524 for the configuration register may be shifted into the configuration register when the DATA signal 1508 is at logic low at the time of the second rise 1516 on the DCLK signal 1506. Data for a first place bit 1526 for the configuration register may be shifted into the configuration register when the DATA signal 1508 is at logic high at the time of the third rise 1518 on the DCLK signal 1506. Data for a zero place bit 1528 for the configuration register may be shifted into the configuration register when the DATA signal 1508 is at logic high at the time of the fourth rise 1528 on the DCLK signal 1506. This example shows a 4-bit long configuration register write, thus the four places of data that may be indicated on the DATA signal 1508 with the corresponding rising actions on the DCLK signal 1506. As noted above, other lengths of configuration register writes could be larger or smaller in size depending on the size of the configuration register. Likewise, similar signaling can be used to write to other memory configurations and can also vary in length and amount of data transferred in accordance with the size and structure of the memory. In an example, the rising edges of the DCLK signal 1506 shift data into the configuration register, and old / extra bits are shifted off the end.

[0171] FIG. 16 illustrates an example status register access protocol 1600. The status register access protocol 1600 may be used to access a status register of the fluid ejection device and / or of a status register or similar function on the integrated circuit. The example status register access protocol 1600 may be received and / or processed by either the fluid ejection device or the integrated circuit 100. The fluid ejection device may include a status register which is accessed using the status register access protocol 1600. The integrated circuit 100 may include hardware, software, or a combination of hardware and software that performs similar functions to the status register, or which provides signals similar to signals provided by the fluid ejection device in response to the status register access protocol 1600.

[0172] As discussed herein, the integrated circuit 100 may pass through, intercept, and / or override the status register access protocol 1600 as provided by the host controller. The integrated circuit 100 may generate the signals of the status register access protocol 1600 to access the status register of the fluid ejection device. The integrated circuit 100 may recognize the signals of the status register access protocol 1600 and respond accordingly. The integrated circuit 100 may respond by redirecting the signals of the status register access protocol 1600 to another bit not specified in the status register access protocol 1600. The integrated circuit 100 may respond by generating its own signals for the status register access protocol 1600 to access the memory bits of the fluid ejection device. The integrated circuit 100 may allow some signals of the status register access protocol 1600 to be delivered from the host controller to the fluid ejection device while modifying other signals of the status register access protocol 1600.

[0173] The status register access protocol 1600 can include a MODE signal 1601, a FIRE signal 1603, a DCLK signal 1605, and a DATA signal 1607. As discussed herein, the host controller and / or the integrated circuit 100 may generate and / or transmit the status register access protocol 1600 to the fluid ejection device. The MODE signal 1601 may be transmittedusing the mode contact 122c of the device-side contact array 120. The FIRE signal 1603 may be transmitted using the fire contact 122j of the device-side contact array 120. The DCLK signal 1605 may be transmitted using the clock contact 122d of the device-side contact array 120. The DCLK signal 1605 enables actions on the rising actions of each clock tick. The DATA signal 1607 may be transmitted using the data contact 122e of the device-side contact array 120.

[0174] With the DATA signal 1607 at logic high at 1602, the MODE signal 1601 is transitioned from logic low to logic high at 1604. The DATA signal 1607 is then transitioned to floating at 1606. With the DATA signal 1607 floating, the FIRE signal 1603 is transitioned from logic low to logic high at 1608 to enable reading of the status register.

[0175] The status register access protocol 1600 may be similar to the configuration register write protocol 1500 of FIG. 15, with the exception that the FIRE signal 1603 is logic high at 1608 in the status register access protocol 1600 as opposed to the FIRE signal 1504 in the configuration register write protocol 1500 being logic low.

[0176] By setting an NVM-enable bit and an NVM-lock bit before executing the status register access protocol 1600, the status register access protocol 1600 may be used to access a special status register of the fluid ejection device. In an example the NVM-enable bit and the NVM-lock bit may be set at 1408 of the memory access protocol 1400 of FIG. 14.

[0177] With the status register (or special status register) enabled for reading, the status register may output a data stream via the DATA signal 1607. In this example, the data stream (i.e., bits MSB, MSB-1, MSB-2, MSB-3, etc.) is read from the status register. Any suitable number of bits may be read from the status register. Each bit of the data stream may be read from the status register in response to the DCLK signal 1605. For example, the MSB bit may be read from the status register in response to enabling the status register for reading. Therising edge of the DCLK signal 1605 as indicated at 1610 may output the MSB-1 bit via the data signal. Likewise, the rising edges of the DCLK signal 1605 as indicated at 1612, 1614, etc. may output bits MSB-2, MSB-3, etc., respectively, via the DATA signal 1607. In other examples, each bit of the data stream may be output from the status register in response to each corresponding falling edge of the clock signal or in response to the rising and falling edges of the clock signal. Reading of the status register may be disabled by transitioning the FIRE signal 1603 back to a logic low as indicated at 1616 and / or by transitioning the MODE signal 1601 back to a logic low as indicated at 1618.

[0178] The special status register may store an address offset, or bits related to the address offset. In an example, the address offset includes four bits stored in non-volatile memory. The address offset may be specific to a type of the fluid ejection device. In an example, the address offset corresponds to a particular product, such as a print cartridge, including the fluid ejection device. The address offset may be used by the fluid ejection device to modify print data received at the fluid ejection device. The address offset may be used by the fluid ejection device to modify the address bits or address code of data packets received at the fluid ejection device. The host controller may prepare the data packets based on the address offset. In this way, the data packets provided by the host controller correspond to the type of the fluid ejection device, as the data packets are prepared based on the address offset of the fluid ejection device. The integrated circuit may modify the data packets, such as the data packets 710 of FIG. 7, to allow for data packets provided based on a first address offset to be used with a fluid ejection device having a second address offset.

[0179] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may be a host-side data contact to receive a first address data packet from a host controller and the second contact 102 may be a device-side data contact to transmit asecond address packet to a fluid ejection device. The control logic 105 may modify the first address data packet based on an address offset to generate the second packet.

[0180] The address offset may be of the fluid ejection device and / or pre-configured in the integrated circuit. The address offset may be stored on the fluid ejection device. The fluid ejection device may include non-volatile memory bits including the address offset of the fluid ejection device. The address offset may be stored on the integrated circuit 100. The address offset may be specific to a type of the fluid ejection device, or a print cartridge including the fluid ejection device. Modifying the first packet to generate the second packet may include subtracting the address offset from first address bits of the first packet to obtain second address bits of the second packet. The fluid ejection device may modify the second address bits of the second packet using the address offset to obtain modified address bits. In some implementations, modifying the address bits of the second packet includes summing the second address bits of the second packet and the address offset to obtain the modified address bits. The fluid ejection device may include a nozzle circuit array to eject drops from each nozzle circuit of the array, the modified address bits to select a nozzle circuit for ejecting drops.

[0181] In an example, the fluid ejection device adds the address offset to address bits received at the fluid ejection device, meaning that to obtain correct print data, the control logic 105 subtracts the address offset from the address bits of the first packet. In this example, once the fluid ejection device adds the address offset to the second address bits, the fluid ejection device will have correct print data including correct address bits. Based on the correct print data, the fluid ejection device actuates nozzle circuits of the nozzle circuit array to print. It should be understood that adding and subtracting may include wrapping around maximum and minimum values. In an example, with a 4-bit adder, once the counter reaches fifteen, adding 1 more bit results in zero because the data wraps around. In this example, subtractingone from a value of zero results in fifteen because the data wraps around. Thus, addition or subtraction may both be used to obtain correctly modified address bits based on the address offset.

[0182] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may be a host-side data contact to receive a first address offset read request from a host controller and the second contact 102 may be a device-side data contact to transmit a second address offset read request to a fluid ejection device. The control logic 105 may, in response to an address offset read response transmitted by the fluid ejection device, determine an address offset of the fluid ejection device. As discussed above, the integrated circuit 100 may be preconfigured using the address offset of the fluid ejection device. In some implementations, however, the integrated circuit 100 may learn the address offset based on the address offset read response.

[0183] The control logic 105 may receive, at the host-side contact, a first data packet, and based on the determined address offset of the fluid ejection device, transmit, at the deviceside data contact, a second data packet based on the first data packet.

[0184] The integrated circuit 100 may include a host-side mode contact, and a host-side fire contact, the control logic 105 to determine that the first data packet is associated with the address offset read by identifying an access protocol and the one or more bits in the packet associated with the address offset read. The access protocol may be the status register read protocol 1600 discussed in FIG. 16. The one or more bits in the packet associated with the access protocol may be the NVM-enable and the NVM-lock bits associated with the special status register read protocol. Thus, the address offset read may be a special status register read, requiring the NVM-enable and the NVM-lock bits to be set prior to the status register read protocol 1600 discussed in FIG. 16.

[0185] The access protocol may include, at the host-side mode contact, a first transition to logic high, at the host-side data contact, a logic high signal, and at the host-side fire contact, a second transition to logic high. In some implementations, determining the address offset of the fluid ejection device includes transmitting the access protocol and first address bits of the first packet to the fluid ejection device, and comparing the first address bits of the first packet to a response from the fluid ejection device. In an example, the fluid ejection device responds to the special status register read with a response including provided address bits summed with the address offset bits. In this example, the address offset can be determined by recording the first address bits provided in the first data packet and comparing them to the response from the fluid ejection device. In some implementations, determining the address offset of the fluid ejection device includes comparing the response from the fluid ejection device to default packet address bits. The integrated circuit 100 may provide the default packet address bits to the fluid ejection device to determine the address offset based on the response from the fluid ejection device. In an example, the integrated circuit 100 provides four address bits of “0” to the fluid ejection device such that the response represents the address offset.

[0186] In some implementations, determining the address offset of the fluid ejection device includes comparing a plurality of address bits of a plurality of packets to a plurality of responses from the fluid ejection device. In some implementations, determining the address offset of the fluid ejection device includes comparing a set of default packet address bits to a plurality of responses from the fluid ejection device. In an example, the integrated circuit 100 may provide sixteen different sets of four address bits to the fluid ejection device to receive sixteen different responses to determine the address offset. In this way, any errors in individual responses can be accounted for.

[0187] In some implementations, modifying the second packet to generate the third packet includes subtracting the address offset from second address bits of the second packet to obtainthird address bits of the third packet. The fluid ejection device may include non-volatile memory bits including the address offset of the fluid ejection device. The fluid ejection device may modify the third address bits of the third packet using the address offset to obtain modified address bits. In some implementations, modifying the address bits of the third packet includes summing the third address bits of the third packet and the address offset to obtain the modified address bits. In some implementations, the fluid ejection device includes a nozzle circuit array to eject drops from each nozzle circuit of the array, the modified address bits to select a nozzle circuit for ejecting drops.

[0188] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the host-side contact array 110 may include a host-side mode contact, a host-side fire contact, and a host-side data contact, and the device-side contact array 120 may include a device-side data contact. The control logic 105 may identify an address offset read, the address offset read including a read-enable data packet to set two read-enable bits on the fluid ejection die, with the two read-enable bits set to the fluid ejection die, the host-side mode contact at logic high, the host-side fire contact at logic high, and the host-side data contact at logic high. The control logic 105 may, in response to the address offset read, transmit, at the host-side data contact, a first address offset, receive, at the host-side data contact, a first data packet including first address bits for use with the first address offset, and transmit, at the device-side data contact, a second data packet based on the first data packet, the second data packet including second address bits for use with a second address offset associated with the fluid ejection device.

[0189] The control logic 105 may modify the first address bits of the first packet using the first address offset and the second address offset to obtain the second address bits of the second packet. The integrated circuit of claim 20, wherein modifying the first address bits of the first packet includes adding the first address offset and subtracting the second addressoffset to obtain the second address bits. In an example, the host controller generates print data including actual address bits, and subtracts the first address offset to obtain the first address bits. In this example, the integrated circuit 100 adds the first address offset to obtain the actual address bits and subtracts the second address offset to obtain the second address bits in anticipation of the fluid ejection device adding the second address offset to the second address bits.

[0190] In some implementations, modifying the first address bits of the first packet includes applying an address offset adjustment based on the first address offset and the second address offset. In an example, the address offset adjustment is a net mathematical operation based on the first address offset and the second address offset. In an example, the first address offset is seven, the second address offset is fifteen, and the address offset adjustment is negative eight,” based on the net result of adding seven and subtracting fifteen.

[0191] The fluid ejection device may include non-volatile memory bits including the second address offset of the fluid ejection device. The fluid ejection device may modify the second address bits to obtain modified address bits. The fluid ejection device may include a nozzle circuit array to eject drops from each nozzle circuit of the array, the modified address bits to select a nozzle circuit for ejecting drops.

[0192] In some implementations, transmitting, at the host-side data contact, the first address offset includes transmitting, at the device-side data contact, a modified address offset read, and receiving, at the device-side data contact, the first address offset. The integrated circuit 100 may receive an address offset read from the host controller, modify the address offset read to ensure that the fluid ejection device responds with the first address offset, and provide the first address offset to the host controller. In an example, the first address offset is seven, the second address offset is fifteen, and the host controller provides an address offset read with address bits having a value of zero. If the fluid ejection device were to respond, theresponse would be fifteen. However, in this example, the integrated circuit 100 modifies the address offset read to have address bits having a value of negative eight such that the response from the fluid ejection device is seven, the first address offset.

[0193] By providing the host controller with the first address offset, the integrated circuit 100 may cause the host controller to treat the fluid ejection device as of a type of fluid ejection device associated with the first address offset. By modifying address bits provided in packets from the host controller, the integrated circuit 100 may compensate for the fact that the host controller provides print data in packets configured for use with the first address offset. In an example, the integrated circuit 100 provides an address offset of a fluid ejection device installed in a high-fill print cartridge when a low-fill print cartridge is installed, causing the host controller to estimate a fill level of the low-fill print cartridge based on characteristics of the high-fill print cartridge. Although, in this example, the host controller provides data packets for use by the fluid ejection device installed in the high-fill print cartridge, the integrated circuit 100 may modify them for use by the fluid ejection device installed in the low-fill print cartridge.

[0194] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, the integrated circuit 100 includes the host-side contact array 110 including a mode contact, a fire contact, and a data contact. The control logic 105 may identify an address offset read including a read-enable data packet to set two read-enable bits and, with the two read-enable bits set, the mode contact at logic high, the fire contact at logic high, and the data contact at logic high. The control logic 105 may, in response to the address offset read, provide, at the data contact, an address offset. In this way, an integrated circuit or fluid ejection device may provide an address offset to a host controller. The address offset may be associated with the fluid ejection device or a different fluid ejection device.

[0195] The integrated circuit 100 may include non-volatile memory bits including the address offset. The control logic 105 may receive, at the data contact, a data packet including address bits, and modify the address bits using the address offset to obtain modified address bits. The integrated circuit 100 may include a nozzle circuit array to eject drops from each nozzle circuit of the array, the modified address bits to select a nozzle circuit for ejecting drops.

[0196] FIG. 17 illustrates an example integrated circuit 1720 causing a host 1710 to treat a fluid ejection device 1730 having a second address offset as if it were a fluid ejection device having a first address offset. The host 1710 may include a host controller, as discussed herein. In an example, the host 1710 is a printer. The integrated circuit 1720 may be the integrated circuit 100 discussed herein. The fluid ejection device 1730 may be a fluid ejection device of a second type having stored thereon the second address offset.

[0197] At 1701, the integrated circuit 1720 receives a query for an address offset from the host 1710. The query may be address offset read. At 1702, in response to the query, the integrated circuit provides the first address offset. The first address offset may be associated with a first type of fluid ejection device. In an example, the first type of fluid ejection device may be installed in high-fill print cartridges, causing the host 1710 to estimate a fill level of a print cartridge including the fluid ejection device 1730 based on characteristics of the high- fill print cartridges. In this example, this allows a low-fill print cartridge to be filled to a level of the high-fill print cartridges with the host 1710 reading and / or indicating an ink level that corresponds to the high fill.

[0198] At 1703, the host 1710 provides data based on the first address offset. The data may be data packets including address bits prepared by the host 1710 based on the first address offset. At 1704, the integrated circuit 1720 modifies the data based on the second address offset. In some implementations, the integrated circuit 1720 modifies the data based on boththe first address offset and the second address offset, as discussed herein. At 1705, the integrated circuit 1720 provides the modified data to the fluid ejection device 1730.

[0199] FIG. 18 illustrates an example integrated circuit 1820 mapping bits of a fluid ejection device 1830 to other bits of the fluid ejection device 1830. A host 1810 may include a host controller, as discussed herein. In an example, the host 1810 is a printer. The integrated circuit 1820 may be the integrated circuit 100 discussed herein. The fluid ejection device 1830 may be a fluid ejection device having first bits that are written. In an example, a first bit is part of a gauge of use of the fluid ejection device 1830. In this example, the host 1810 may not allow the fluid ejection device 1830 to print due to bits of the gauge being written. The host 1810 may write to gauges of fluid ejection devices as the fluid ejection devices print in order to measure use of the fluid ejection devices and possible degradation. In order to prevent degraded print quality, the host 1810 may generate warnings and / or other indications when providing print data to a used, and possibly degraded, fluid ejection device to print.

[0200] In some implementations, the integrated circuit 1820 may include in the memory 2322 a memory array of a fluid ejection device in good condition and / or operating as expected to identify programming states of the memory bits of the fluid ejection device in good condition and / or operating as expected. In this way, the integrated circuit 1820 does not have to know what type of bit is being requested, as the integrated circuit 1820 includes the entire memory array of the fluid ejection device. In some implementations, the integrated circuit 1820 may include in the memory 2322 a mapping of different types of bits to specific bits on the fluid ejection device in good condition and / or operating as expected. In an example, the memory 2322 may include a mapping from use gauge bits to specific bits on the fluid ejection device in good condition and / or operating as expected so the integrated circuit 1820 can know which bits are requested and identify what their programming state is on a fluid ejection device in good condition and / or operating as expected.

[0201] At 1801, the host 1810 provides a read request for a first bit 1832 to the integrated circuit 1820. The read request may include one or more identifiers of the first bit 1832 corresponding to a location on the fluid ejection device 1830 where the first bit 1832 is located.

[0202] At 1802, the integrated circuit provides a read request for a second bit 1834 to the fluid ejection device 1830. The integrated circuit 1820 may provide the read request for the second bit 1834 in response to the read request for the first bit 1832. The integrated circuit 1820 may determine that the read request for the first bit 1832 should not be delivered to the fluid ejection device 1830. In an example, the first bit 1832 is a use gauge bit corresponding to use of the fluid ejection device 1830. The integrated circuit 1820 may include a mapping of bits 1822. The mapping of bits 1822 may map bits on the fluid ejection device to other bits. In an example, the mapping of bits 1822 may map bits corresponding to a status or type of the fluid ejection device 1830 to other bits in order to present a different status or type to the host 1810.

[0203] The mapping of bits 1822 may map the first bit 1832 to the second bit 1834. In some implementations, the second bit 1834 is an unused bit on the fluid ejection device. The unused bit may be a bit not normally accessed by the host controller 1810 or which does not correspond to information requested by the host controller 1810 during ordinary operation. In some implementations, the mapping of bits 1822 maps all of the used bits of the fluid ejection device 1830 to unused bits on the fluid ejection device 1830. In some implementations, the mapping of bits 1822 maps a subset of the used bits of the fluid ejection device 1830 to unused bits on the fluid ejection device 1830, the subset of the used bits corresponding to bits, the values of which the integrated circuit 1820 modifies for presentation to the host 1810. In subsequent requests, the mapping of bits 1822 may be used to provide responses to the host 1810 consistent with actions of the host 1810. In an example,the mapping of bits 1822 may cause a write to the first bit to be applied to the second bit, causing a subsequent read of the first bit to be redirected to the second bit which was written in accordance with the earlier write to the first bit from the host 1810.

[0204] At 1803, the fluid ejection device 1803 provides a read response for the second bit 1834 to the integrated circuit 1820 in response to the read request for the second bit 1834. At 1804, the integrated circuit 1820 provides the read response for the second bit to the host 1810. In some implementations, the integrated circuit al 820 at 1804 allows the read response for the second bit from the fluid ejection device 1830 to be passed through unchanged or delivered directly to the host 1810. The host 1810 may interpret the read response for the second bit as a read response for the first bit. In this way, the integrated circuit 1820 may redirect read requests for the first bit to the second bit.

[0205] The integrated circuit 1820 may redirect read and / or write requests to the first bit to other bits for a variety of reasons. As discussed herein, the integrated circuit 1820 may alter indications of use of the fluid ejection device 1830. In some implementations, the integrated circuit 1820 may write a false address offset to unused bits on the fluid ejection device 1830 and direct address offset reads from the host 1810 to the false address offset. In some implementations, the integrated circuit 1820 may redirect read and / or write requests in order to change a value of the first bit as seen by the host 1810. The integrated circuit 1820 may redirect the read and / or write requests in order to provide correct or expected responses to the host 1810 from the fluid ejection device. In an example, the integrated circuit 1820 may redirect the read and / or write requests in order to provide expected responses to partial programming write requests from the fluid ejection device 1830. In an example, the integrated circuit 1820 may redirect the read and / or write requests in order to provide genuine and / or expected responses to parallel read requests from the fluid ejection device 1830.

[0206] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the first contact 101 may receive a first write signal corresponding to a write to a non-volatile memory bit on a fluid ejection device. The control logic 105 may, in response to the first write signal, store, in a memory of the integrated circuit, a programming level of the non-volatile memory bit based on the first write signal. The first contact 101 may receive a first read signal corresponding to a read of the non-volatile memory bit. The control logic 105 may, in response to the first read signal, transmit, based on the stored programming level, at the first contact 101, a first response signal. The first contact 101 may receive a second write signal corresponding to a write to the non-volatile memory bit on the fluid ejection device. In response to the second write signal, the control logic 105 may update the stored programming level of the non-volatile memory bit based on the second write signal, wherein a first change to the programming level based on the first write signal is greater than a second change to the programming level based on the second write signal. The first contact 101 may receive a second read signal corresponding to a read of the non-volatile memory bit. The control logic 105 may, in response to the second read signal, transmit, based on the stored programming level, at the host-side contact, a second response signal. In the examples discussed in the present disclosure, the integrated circuit 100 may generally receive signals at its contacts that are thus received by the integrated circuit 100 and, more specifically, by the control logic 105 of the integrated circuit 100.

[0207] The multiple signals corresponding to reads and writes to the non-volatile memory bit may comprise a “tap test” of the non-volatile memory bit. The tap test may be used to verify that the non-volatile memory bit is in good condition and / or operating as expected and can be incrementally programmed by multiple incremental writes (“taps”). The host controller may perform the tap test in order to verify that the fluid ejection device is in good condition and / oroperating as expected. The examples discussed herein are directed to actions the integrated circuit 100 may take in order to provide expected responses to the host controller and continue to modify signals between the host controller and the fluid ejection device, as discussed herein. The integrated circuit 100 may include the stored programming level in order to keep track of the multiple incremental writes of the tap test to ensure that the integrated circuit 100 provides correct responses to the host controller, or responses that correspond to how an original OEM fluid ejection device would respond.

[0208] In some implementations, the integrated circuit 100 may allow the host controller to perform the tap test on the fluid ejection device such that the host controller receives correct responses to the tap test. However, the tap test on which the host controller is performing the tap test may be already written, causing the fluid ejection device to give incorrect or unexpected responses and thus fail the tap test. In some implementations, the integrated circuit 100 may provide responses to the tap test performed by the host controller by redirecting the signals of the tap test to an unused bit, as discussed in conjunction with FIG. 18. In this way, the integrated circuit provides correct responses to the tap test, as the unused bit is a non-volatile memory bit in good condition and / or operating as expected on the fluid ejection device.

[0209] In some implementations, the stored programming level corresponds to a time length of the first write signal. In some implementations, updating the stored programming level includes updating the stored programming level to correspond to the time length of the first write signal and a time length of the second write signal. In an example, a bit on the fluid ejection device may be programmed by applying a voltage for a predetermined amount of time. In this example, the greater the amount of time the voltage is applied, the greater the voltage level of the bit, and the greater the programming level.

[0210] In some implementations, the time length of the first write signal is equal to the time length of the second write signal. In an example, the incremental writes of the tap test each have a same magnitude. In some implementations, the first write signal and the second write signal each increase the stored programming level. In some implementations, the increases to the stored programming level are cumulative. Cumulative increases to the stored programming level correspond to a non-volatile memory bit being cumulatively programmed as a voltage of the non-volatile memory bit increases.

[0211] In some implementations, the first response signal is based on whether the first read signal is voltage-driven or current-driven. The host controller can apply a predetermined voltage to a non-volatile memory bit and read a current response or apply a predetermined current to the non-volatile memory bit and read a voltage response. Thus, in order to provide a correct response, the integrated circuit must determine whether the first read signal is voltage-driven or current-driven and provide a current response or a voltage response, respectively.

[0212] In some implementations, the integrated circuit includes a device-side contact electrically connected to the fluid ejection device and the control logic 105 transmits, at the device-side contact, the first write signal. Transmitting the first response signal at the hostside contact may include transmitting, at the device-side contact, the first read signal and receiving, at the device-side contact, the first response signal. In this way, the fluid ejection device can transmit the first read signal to the fluid ejection device (to the intended bit or another bit) and use the response from the fluid ejection device (which response is inherently correct) to respond to the host controller.

[0213] The control logic may determine, in response to the first write signal, that the nonvolatile bit is already programmed. As noted above, if the non-volatile bit is already programmed, it will not give correct responses to the tap test. Thus, if the non-volatile bit isalready programmed, the integrated circuit may generate responses to the tap test or redirect the tap test to another bit.

[0214] In some implementations, the control logic 105, in response to the first write signal, based on the first write signal, transmits a modified write signal at the device-side contact corresponding to a write to a second non-volatile memory bit on the fluid ejection device. Transmitting the first response signal may include transmitting, at the device-side contact, the modified write signal, and receiving, at the device-side contact, the first response signal. The modified write signal may be the first write signal, modified to redirect the first write signal to another bit, such as an unused bit. In some implementations, the control logic 105, in response to the second write signal, based on the second write signal, transmits a second modified write signal at the device-side contact corresponding to a write to the second nonvolatile memory bit on the fluid ejection device, wherein transmitting the second response signal includes transmitting, at the device-side contact, the second modified write signal and receiving, at the device-side contact, the second response signal. The second modified write signal may be the second write signal, modified to redirect the second write signal to the bit to which the first write signal was redirected. In this way, the integrated circuit may redirect the tap test to another bit in order to provide correct responses to the tap test, as discussed herein. In some implementations, the stored programming level comprises the programming level of the second non-volatile memory bit.

[0215] In some implementations, the first write signal includes at a host-side mode contact, a first transition to logic high, at a host-side data contact, a logic high signal, and at a hostside fire contact, a second transition to logic high. In this way, the first write signal may include one or more operations of the memory access protocol 1400 of FIG. 14. In some implementations, the first read signal comprises at the host-side mode contact, a first transition to logic high at the host-side data contact, a logic high signal, and at the host-sidefire contact, a second transition to logic high with the signal on the host-side data contact floating. In some implementations, after these register accesses are complete, the host-side mode and host-side data contacts return to logic low. Thus, when the actual write or read event occurs, the host-side mode contact is in a low state, the host-side data contact is in a low state, and only the host-side fire contact is in a high state. In this way, the first read signal may include one or more operations of the memory access protocol 1400 of FIG. 14.

[0216] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the host-side contact array 110 (e.g., printer-side contact array) may receive a first write signal sequence, the write signal sequence including a first write signal to a data address, the first write signal having a first magnitude. The host-side contact array 110 may, subsequent to receiving the first write signal sequence, receive a first read signal sequence to read the data address. The integrated circuit 100 may, in response to the first read signal sequence, provide, at the host-side contact array 110, a first response signal of a first level. The integrated circuit 100 may receive, at the host-side contact array 110, a second write signal sequence, including a second write signal to the same data address, the second write signal having a second magnitude. The integrated circuit 100 may, subsequent to receiving the second write signal, receive a second read signal sequence to read the data address, and in response to the second read signal sequence, provide, at the host-side contact array 110, a second response signal of a second level, wherein the ratio of the first magnitude to the first level is greater than the ratio of the second magnitude to the second level.

[0217] In some implementations, the first magnitude is different from the second magnitude. The first level may correspond to the first magnitude, and the second level may correspond to the second magnitude. The first magnitude may correspond to at least one of a time length, a voltage level, or a current level of the first write signal. The second magnitude maycorrespond to at least one of a time length, a voltage level, or a current level of the second write signal. The time length of the first write signal may be equal to a time length of the second write signal.

[0218] In some implementations, the first write signal and the second write signal each increase a response associated with the data address. The increases to the response may be cumulative. The first response signal may be based on whether the first read signal is voltage- driven or current-driven. In an example, the first response signal includes a current response based on the first read signal being voltage-driven. In an example, the first response signal includes a voltage response based on the first read signal being current-driven.

[0219] In some implementations, the control logic 105 may transmit, at the device-side contact array 120, the first write signal, wherein transmitting the first response signal at the host-side contact array 110 includes transmitting, at the device-side contact array, the first read signal and receiving, at the device-side contact array, the first response signal. The control logic 105 may determine, in response to the first write signal, that a memory bit corresponding to the memory address is programmed.

[0220] In some implementations, the control logic 105 may, in response to the first write signal, based on the first write signal, transmit a modified write signal at the device-side contact array corresponding to a write to a second memory address, wherein transmitting the first response signal includes transmitting, at the device-side contact array, the modified write signal, and receiving, at the device-side contact array, the first response signal. The control logic 105 may, in response to the second write signal, based on the second write signal, transmit a second modified write signal at the device-side contact array corresponding to a write to the second memory address, wherein transmitting the second response signal includes transmitting, at the device-side contact array, the second modified write signal and receiving, at the device-side contact array, the second response signal.

[0221] In some implementations, the first write signal comprises at a host-side mode contact, a first transition to logic high, at a host-side data contact, a logic high signal, and at a hostside fire contact, a second transition to logic high. In some implementations, the first read signal comprises, at the host-side mode contact, a first transition to logic high, at the hostside data contact, a logic high signal, and at the host-side fire contact, a second transition to logic high with the signal on the host-side data contact floating.

[0222] FIG. 19 illustrates an example response curve 1900 for incremental programming of a non-volatile memory (NVM) bit. The response curve 1900 may show a relationship between a programming level of the NVM bit and a current response. A predetermined voltage may be applied to the NVM bit, and the resulting current measured as the current response. In an example, two volts are applied to the NVM bit and the current response ranges from zero to five hundred microamps. In some implementations, a predetermined current may be applied to the NVM bit, and the resulting voltage measured as a voltage response.

[0223] The response curve 1900 may include a first measure point 1901, a second measure point 1902, a third measure point 1903, a fourth measure point 1904, a fifth measure point 1905, and a sixth measure point 1906. The measure points 1901-1906 may correspond to incremental programming steps of the tap test. In some implementations, the tap test includes a subset of the measure points 1901-1906. In an example, the tap test includes only the first measure point 1901, the third measure point 1903, and the fifth measure point 1905. In an example, the tap test includes only the first measure point 1901, the second measure point 1902, and the third measure point 1903.

[0224] Each of the measure points 1901-1906 may correspond to reads and writes of the tap test. In an example, the host controller may transmit a first write signal to cause the NVM bit to have a programming level associated with the first measure point 1901. The host controller may then transmit a first read signal to read the programming level of the NVM bit to verifythat the NVM bit has a current response associated with the first measure point 1901. The host controller may then transmit a second write signals to cause the NVM bit to have a programming level associated with the second measure point 1902. The host controller may then transmit a second read signal to read the programming level of the NVM bit to verify that the NVM bit has a current response associated with the second measure point 1902. In this example, the host controller may transmit successive write and read signals to verify that the NVM bit responds according to the response curve 1900. In this way, the host controller may verify that the NVM bit is in good condition and / or operating as expected.

[0225] However, the integrated circuit 100 may provide current and / or voltage responses to the host controller according to the response curve 1900 in response to the tap test performed by the host controller. In this way, the integrated circuit 100 may modify signals between the host controller and the fluid ejection device without causing the host controller to detect normal operation only. The integrated circuit 100 may determine a magnitude of the various write signals of the tap test and determine correct responses to the read signals of the tap test based on the response curve 1900. The integrated circuit 100 may store a programming level of the NVM bit to determine correct responses to the read signals of the tap test. The integrated circuit 100 may determine whether the read signals are current-driven or voltage- driven and provide a correct voltage response or current response, respectively.

[0226] If the integrated circuit 100 were to simply determine whether the NVM bit is written or unwritten (e.g., programmed or unprogrammed), without taking into account the magnitude of the write, the integrated circuit 100 would respond to an incremental write with a current response characteristic of a fully written or programmed bit, allowing the host controller to determine that the NVM bit is not in good condition and / or operating as expected or that signals between the host controller and the fluid ejection device are compromised (e.g., not properly transmitted due to an issue with the electrical interface between the hostcontroller and the fluid ejection device). Thus, to avoid causing the host controller to determine that there is an issue with the electrical interface between the host controller and the fluid ejection device, the integrated circuit 100 identifies incremental writes and responds according to the response curve 1900 or redirects the incremental writes to another bit on the fluid ejection die.

[0227] In some implementations, the integrated circuit 100 may redirect the read and write signals of the tap test to a different NVM bit on the fluid ejection device, as discussed herein. In this way, the different NVM bit provides correct responses, as the different NVM bit is a NVM bit in good condition and / or operating as expected on the fluid ejection device.

[0228] In some implementations, the measure points 1901-1906 are evenly spaced according to programming level. The measure points 1901-1906 may be evenly spaced according to programming level due to the write signals of the tap test having a same magnitude. Successive write signals having the same magnitude may increment the programming level of the NVM bit by a same amount. Successive write signals having the same magnitude may increase the current response by successively diminishing amounts. In an example, a first difference between the current response of the NVM bit with a programming level of zero and the current response of the NVM bit at the first measure point 1901 may be larger than a second different between the current response of the NVM bit at the first measure point 1901 and the current response of the NVM bit at the second measure point 1902.

[0229] FIG. 20 illustrates an example integrated circuit 2020 providing responses to incremental write and read signals from a host 2010. The incremental write and read signals may be the tap test, as discussed herein. The host 2010 may include a host controller. The host 2010 may perform the tap test to verify that a fluid ejection device is operating as expected. In an example, the host 2010 may determine that there is a problem with the electrical interface or connection between the host 2010 and the fluid ejection device andindicate that the print cartridge must be reinstalled. The integrated circuit 2020 may determine correct responses to the tap test in order to prevent the host 2010 from determining that there is an issue with the fluid ejection device or with the electrical interface between the host 2010 and the fluid ejection device.

[0230] At 2001, the host 2010 transmits a first write signal to the integrated circuit 2020 for an NVM bit. In an example, the first write signal corresponds to the first measure point 1901 of FIG. 19. The host 2010 transmits the first write signal on one or more contacts that are to be electrically connected to the fluid ejection device. Thus, the host 2010 is not aware of the integrated circuit 2020 and must use the responses to the tap test to determine whether the host 2010 is in communication with a fluid ejection device in good condition and / or operating as expected. The first write signal may include a write signal sequence including a sequence of signals from different contacts on the host controller. Each of the different write signals of the tap test may include the write signal sequence and each of the different read signals of the tap test may include a read signal sequence.

[0231] In some implementations, in response to the first write signal, the integrated circuit 2020 determines a programming level of the NVM bit corresponding to a magnitude of the first write signal. The integrated circuit 2020 does not transmit the first write signal to the fluid ejection die and the NVM bit is not actually written. Thus, the stored programming level of the NVM bit does not correspond to an actual programming level of the NVM bit. The integrated circuit 2020 stores the determined programming level of the NVM bit as a stored programming level in a memory 2022 of the integrated circuit 2020.

[0232] In some implementations, in response to the first write signal, the integrated circuit 2020 redirects the first write signal to a second NVM bit on the fluid ejection die. The integrated circuit 2020 may redirect the first write signal to the second NVM bit based on a mapping stored in the memory 2022. The integrated circuit 2020 may redirect the first writesignal to the second NVM bit and store a mapping from the NVM bit to the second NVM bit in the memory 2022.

[0233] At 2002, the host 2010 transmits a first read signal for the NVM bit to the integrated circuit 2020. In an example, the first read signal corresponds to the first measure point 1901 of FIG. 19. The first read signal may include the read signal sequence including a sequence of signals from different contacts on the host controller.

[0234] In some implementations, in response to the first read signal, the integrated circuit 2020 determines a first response based on the stored programming level of the NVM bit in the memory 2022. The integrated circuit 2020 determines whether the first read signal is a current-driven or voltage-driven read of the NVM bit. The integrated circuit 2020 may calculate the first response based on how the NVM bit would respond. In an example, the integrated circuit 2020 calculates the first response based on the response curve 1900 of FIG. 1.

[0235] In some implementations, in response to the first read signal, the integrated circuit 2020 redirects the first read signal to the second NVM bit on the fluid ejection die. The integrated circuit 2020 may redirect the first read signal to the second NVM bit based on the mapping stored in the memory 2022. The integrated circuit 2020 may receive the first response from the second NVM bit.

[0236] At 2003, the integrated circuit 2020 transmits the first response to the host 2010. The host 2010 may compare the first response to a predetermined response to determine whether the first response is correct, or corresponds to a response from an NVM bit in good condition and / or operating as expected. Alternatively, the host 2010 may determine that the first response is incorrect. If the host 2010 determines that the first response is correct, the host 2010 may complete the tap test and begin sending print data or continue with the tap test.

[0237] At 2004, the host 2010 transmits a second write signal to the integrated circuit 2020 for the NVM bit. As noted above, the host 2010 is unaware of the integrated circuit 2020, and the second write signal is intended for the NVM bit on the fluid ejection device. In an example, the second read signal corresponds to the second measure point 1902 of FIG. 19.

[0238] In some implementations, in response to the second write signal, the integrated circuit 2020 determines a programming level of the NVM bit corresponding to a magnitude of the second write signal and the first write signal. The integrated circuit 2020 may increment the stored programming level of the NVM bit in the memory 2022 based on the magnitude of the second write signal. The integrated circuit 2020 does not transmit the second write signal to the fluid ejection die and the NVM bit is not actually written. Thus, the stored programming level of the NVM bit does not correspond to an actual programming level of the NVM bit. The integrated circuit 2020 updates the stored programming level of the NVM bit in the memory 2022 of the integrated circuit 2020.

[0239] In some implementations, in response to the second write signal, the integrated circuit 2020 redirects the second write signal to the second NVM bit on the fluid ejection die. The integrated circuit 2020 may redirect the second write signal to the second NVM bit based on the mapping stored in the memory 2022.

[0240] At 2005, the host 2010 transmits a second read signal for the NVM bit to the integrated circuit 2020. In an example, the second read signal corresponds to the second measure point 1902 of FIG. 19. The second read signal may include the read signal sequence including a sequence of signals from different contacts on the host controller.

[0241] In some implementations, in response to the second read signal, the integrated circuit 2020 determines a second response based on the updated stored programming level of the NVM bit in the memory 2022. The integrated circuit 2020 determines whether the secondread signal is a current-driven or voltage-driven read of the NVM bit. The integrated circuit 2020 may calculate the second response based on how the NVM bit would respond. In an example, the integrated circuit 2020 calculates the second response based on the response curve 1900 of FIG. 1.

[0242] In some implementations, in response to the second read signal, the integrated circuit 2020 redirects the second read signal to the second NVM bit on the fluid ejection die. The integrated circuit 2020 may redirect the second read signal to the second NVM bit based on the mapping stored in the memory 2022. The integrated circuit 2020 may receive the second response from the second NVM bit.

[0243] At 2006, the integrated circuit 2020 transmits the second response to the host 2010. The host 2010 may compare the second response to a predetermined response to determine whether the second response is correct, or corresponds to a response from an NVM bit in good condition and / or operating as expected on the fluid ejection die. Alternatively, the host 2010 may determine that the second response is incorrect If the host 2010 determines that the second response is correct, the host 2010 may complete the tap test and begin sending print data or continue with the tap test.

[0244] Referring to any of FIGS. 1A, IB, 2 - 4 and 6B, when the integrated circuit 100 is coupled to the fluid ejection device, and the fluid ejection device is installed in the host device, the control logic 105 may, in response to a first memory access sequence to access a first memory bit, provide, at the host-side contact array 110, a first signal having a first value corresponding to the first memory bit. The first value may correspond to a programming level of the first memory bit. In an example, if the first memory bit is unprogrammed, the first value corresponds to a current or voltage response characteristic of an unprogrammed bit. In an example, if the first memory bit is programmed, the first value corresponds to a current or voltage response characteristic of a programmed bit. In response to a second memory accesssequence to access a second memory bit, the control logic 105 may provide, at the host-side contact array 110, a second signal having a second value corresponding to the second memory bit. The second value may correspond to a programming level of the second memory bit. In some implementations, the programming level of the second memory bit may be programmed or unprogrammed.

[0245] In response to a third memory access sequence to access a combination of the first and second memory bits, the control logic 105 may provide, at the host-side contact array 110, a third signal having a third value, corresponding to the combination of the first and second memory bits. The third value may correspond to the programming levels of the first and second memory bits. The third value corresponds to a current or voltage response characteristic of the combination of the programming levels of the first and second memory bits. In an example, if both of the first and second memory bits are programmed, the third value corresponds to a current or voltage response characteristic of two programmed bits in parallel. In an example, if both of the first and second memory bits are unprogrammed, the third value corresponds to a current or voltage response characteristic of two unprogrammed bits in parallel. In an example, if one of the first and second memory bits is programmed and the other is unprogrammed, the third value corresponds to a current or voltage response characteristic of a programmed bit and an unprogrammed bit in parallel.

[0246] In some implementations, a memory of the integrated circuit 100 stores the first, second and third values separately. The integrated circuit 100 may, based on the received memory access sequence, determine which of the first, second, and third values to provide at the host-side contact array 110. The host controller may perform the first, second, and third memory access sequences in order to verify that the first and second memory bits are in good condition and / or operating as expected and / or that the fluid ejection device is in good condition and / or operating as expected.

[0247] In some implementations, the third value corresponds to a number of programmed bits of the first and second memory bits. As discussed above, the third value may depend on whether zero, one, or two of the first and second memory bits are programmed. The control logic 105 may determine the number of programmed bits of the first and second memory bits. The control logic 105 may determine the number of programmed bits in order to determine the correct response to the host controller. The control logic 105 may determine the number of programmed bits based on a mapping of bits of the fluid ejection die to a memory of the integrated circuit 100. In an example, the control logic 105 may identify the first and second memory bits, use the mapping of bits to map the first and second memory bits to a location in the memory of the integrated circuit 100, and read the location in the memory to determine whether the first and second memory bits are programmed.

[0248] In some implementations, transmitting the third signal includes determining whether the read of the combination of the first and second memory bits is voltage-driven or current- driven. As discussed herein, a voltage-driven read produces a current response and a current- driven read produces a voltage response. The control logic 105 may determine whether the read of the combination of the first and second memory bits is voltage-driven or current- driven in order to provide a current response or a voltage response, respectively.

[0249] In some implementations, the memory access sequence comprises, at a host-side mode contact of the contact array, a first transition to logic high, at a host-side data contact of the contact array, a logic high signal, and at a host-side fire contact of the contact array, a second transition to logic high.

[0250] In some implementations, the control logic 105 may disable the third signal in response to detecting an end of the memory access protocol. In this way, the control logic 105 may provide the third signal only when the host controller is requesting the third signal or only when the host controller is expecting the third signal. The control logic 105 may disablethe third signal after a predetermined amount of time. The control logic 105 may provide the third signal for as long as the memory access protocol lasts. In an example, the control logic 105 may provide the third signal at the host-side data contact as long as a logic high signal remains on the host-side fire contact.

[0251] The control logic 105 may, in response to a fourth memory access sequence to access a combination of the second memory bit and a third memory bit, provide a fourth signal having a fourth value corresponding to the combination of the second and third memory bits. In this way, the integrated circuit 100 may store values and provide responses corresponding to various parallel reads of different memory bits. The control logic 105 may, in response to a fifth memory access sequence to access a combination of the first, second, and third memory bits, provide a fifth signal having a fifth value corresponding to the combination of the first, second, and third memory bits. In this way, the integrated circuit 100 may store values and provide responses corresponding to parallel reads of various different memory bits and various different numbers of memory bits. In some implementations, the memory of the integrated circuit stores the first, second, third, and fifth values separately.

[0252] Referring to any of FIGS. 1 A, IB, 2 - 4 and 6B, the host-side contact array 110 may include a first host-side column including a host-side fire contact. The host-side contact array may include a second host-side column including a host-side mode contact and a host-side data contact. The control logic 105 may receive, at the host-side contact array 110, one or more first signals corresponding to a memory access protocol for accessing a memory of a fluid ejection die, receive, at the host-side contact array, a data packet indicating a first bit and a second bit, and in response to the data packet, transmit, at the host-side contact array, a second signal corresponding to a read of the first bit and the second bit. The second signal may correspond to a signal obtained by connecting both the first bit and the second bit in parallel to a single contact. In an example, the second signal corresponds to a current thatcould be obtained by driving a predetermined voltage across the first and second bits in parallel. In this way, the integrated circuit 100 may provide correct responses to parallel reads of multiple bits on the fluid ejection device. The host controller may request parallel reads of multiple bits on the fluid ejection device in order to verify that the fluid ejection device is operating as expected. If the integrated circuit 100 provides incorrect responses to the parallel bit reads, the host controller may determine that the fluid ejection device is damaged, and / or that there is an issue with the electrical interface between the host controller and the fluid ejection device. The integrated circuit 100 may recognize the parallel bit reads and provide expected responses to the host controller.

[0253] In some implementations, the one or more first signals corresponding to the memory access protocol include at the host-side mode contact, a first transition to logic high, at the host-side data contact, a logic high signal, and at the host-side fire contact, a second transition to logic high. In some implementations, as discussed herein, during the actual read event, only the host-side fire contact remains at logic high. The data contact may be floating in order to transmit a response to the read request.

[0254] In some implementations, the control logic 105 receives the data packet by receiving, at the host-side data contact, the data packet. The data packet may include address bits indicating address corresponding to the first and second memory bits.

[0255] In some implementations, the second signal is based on a number of programmed bits of the first and second bits. In some implementations, the second signal has a first value if none of the first and second bits are programmed, a second value if one of the first and second bits is programmed, and a third value if both of the first and second bits are programmed. In some implementations, the control logic 105 determines the number of programmed bits of the first and second bits. In some implementations, the control logic 105 determines the number of programmed bits based on a mapping of bits of the fluid ejection die to a memoryof the integrated circuit. In some implementations, transmitting the second signal includes determining whether the read of the first bit and the second bit is voltage-driven or current- driven.

[0256] In some implementations, the control logic receives, at the host-side contact array, a second data packet indicating the second bit and a third bit, and in response to the second data packet, transmit, at the host-side contact array, a third signal corresponding to a read of the second bit and the third bit. In this way, the integrated circuit 100 can provide correct responses to parallel bit reads of various different bits. In some implementations, the control logic 105 receives, at the host-side contact array, a third data packet indicating the first bit, the second bit, and the third bit, and in response to the second data packet, transmits, at the host-side contact array, a third signal corresponding to a read of the first bit, the second bit, and the third bit. In this way, the integrated circuit 100 can provide correct responses to parallel reads of different bits and different numbers of bits.

[0257] In some implementations, the device-side contact array 120 includes a first deviceside column including a device-side fire contact and a second device-side column including a device-side mode contact, and a device-side data contact. The device-side contact array 120 may include additional contacts, as illustrated in FIG. 4.

[0258] As discussed herein, the integrated circuit 100 may redirect reads directed to bits on the fluid ejection device to other bits in order to provide correct responses to the host controller. In an example, the integrated circuit 100 receives a parallel read request for two bits in a use gauge of the fluid ejection device, the use gauge containing bits to track use of the fluid ejection device. In this example, the fluid ejection device has a fully filled use gauge (i.e., all bits are programmed), indicating extensive use and potentially degraded print quality. In this example, the integrated circuit 100 redirects the parallel read request for the two bitsto two other, unprogrammed bits on the fluid ejection die. In this example, the host controller may determines that the memory bits have values that match expected values and / or states.

[0259] FIG. 21 illustrates example voltage response curves 2100 for parallel bit reads. The response curves 2100 show example voltage responses for parallel bit reads at different programming levels. The voltage response curves may be obtained by driving a predetermined current to two bits in parallel to measure the voltage response. The voltage response curves may include a one-bit response curve 2110 and a two-bit response curve 2120. The one-bit response curve 2110 corresponds to a parallel bit read of two bits where one of the two bits is programmed. The two-bit response curve 2120 corresponds to a parallel bit read of two bits where both of the two bits are programmed. The two bits may have a same programming level. If both of the two bits are not programmed, the voltage response is zero.

[0260] The one-bit response curve 2110 and the two-bit response curve 2120 do not cross, so the number of programmed bits is distinguishable despite different levels of programming of the programmed bits. A first programming level 2101 shows a first difference between the one-bit response curve 2110 and the two-bit response curve 2120. A second programming level 2102 shows a second difference between the one-bit response curve 2110 and the two- bit response curve 2120. The second programming level 2102 is higher than the first programming level 2101 and the second difference is greater than the first difference. A third programming level 2103 shows a third difference between the one-bit response curve 2110 and the two-bit response curve 2120. The third programming level 2103 is higher than the second programming level 2102 and the third difference is greater than the second difference.

[0261] FIG. 22 illustrates example current response curves 2200 for parallel bit reads. The response curves 2200 show example current responses for parallel bit reads at different programming levels. The current response curves may be obtained by driving a predetermined voltage to two bits in parallel to measure the current response. The current response curvesmay include a one-bit response curve 2210 and a two-bit response curve 2220. The one-bit response curve 2210 corresponds to a parallel bit read of two bits where one of the two bits is programmed. The two-bit response curve 2220 corresponds to a parallel bit read of two bits where both of the two bits are programmed. The two bits may have a same programming level. If both of the two bits are not programmed, the voltage response is zero.

[0262] The one-bit response curve 2210 and the two-bit response curve 2220 do not cross, so the number of programmed bits is distinguishable despite different levels of programming of the programmed bits. A first programming level 2201 shows a first difference between the one-bit response curve 2210 and the two-bit response curve 2220. A second programming level 2202 shows a second difference between the one-bit response curve 2210 and the two- bit response curve 2220. The second programming level 2202 is higher than the first programming level 2201 and the second difference is greater than the first difference. A third programming level 2203 shows a third difference between the one-bit response curve 2210 and the two-bit response curve 2220. The third programming level 2203 is higher than the second programming level 2202 and the third difference is greater than the second difference.

[0263] FIG. 23 illustrates an example integrated circuit 2320 providing responses to parallel bit reads from a host 2310. At 2301, the host 2310 transmits a first request to read a first memory bit on a fluid ejection device. The first request may include a first memory access sequence to access the first memory bit. The first memory access sequence may include one or more operations of the memory access protocol 1400 of FIG. 14 and a data packet including an address bit for the first memory bit.

[0264] In some implementations, in response to the first request to read the first memory bit, the integrated circuit 2320 determines a programming state of the first bit and selects a first value 2324 from a memory 2322 of the integrated circuit 2320 based on the programming state of the first bit. The host 2310 has an expected value corresponding to what the host 2310expects the first value to be. The host 2310 compares the expected value to the response from the integrated circuit 2320 to ensure that the fluid ejection device gives a correct response. The expected value at the host 2310 may be based on the state of memory bits of a fluid ejection die in good condition and / or operating as expected. In some implementations, the integrated circuit 2320 may include in the memory 2322 a copy of a memory array of a fluid ejection device in good condition and / or operating as expected to identify programming states of the memory bits of the copy of the memory array. In this way, the integrated circuit 2320 does not have to know what type of bit is being requested, as the integrated circuit 2320 includes a copy of the entire memory array of the fluid ejection device. In some implementations, the integrated circuit 2320 may include in the memory 2322 a mapping of different types of bits to specific bits on the associated fluid ejection device, to the extent those bits are in good condition and / or operating as expected. In an example, the memory 2322 may include a mapping from use gauge bits to specific bits on the associated fluid ejection device, to the extent those bits are in good condition and / or operating as expected so the integrated circuit 2320 can know which bits are requested and identify what their programming state is and / or operating as.

[0265] In some implementations, in response to the first request to read the first memory bit, the integrated circuit 2320 identifies a first other bit on the fluid ejection device having a desired programming state and redirects the first request to read the first memory bit to the first other memory bit. The integrated circuit 2320 may identify the first other bit based on a mapping in the memory 2322 of the first bit to the first other bit. Based on the redirected third request, the integrated circuit 2320 may receive, from the fluid ejection device, a signal having the first value 2324.

[0266] At 2302, the integrated circuit 2320 provides a first signal having the first value corresponding to the first memory bit in response to the first request. At 2303, the host 2310transmits a second request to read a second memory bit on a fluid ejection device. The first request may include a second memory access sequence to access the first memory bit. The second memory access sequence may include one or more operations of the memory access protocol 1400 of FIG. 14 and a data packet including an address bit for the second memory bit. The second memory access sequence may be the same as the first memory access sequence, except the first memory access sequence includes the address bit for the first memory bit and the second memory access sequence includes the address bit for the second memory bit.

[0267] In some implementations, in response to the second request to read the second memory bit, the integrated circuit 2320 determines a programming state of the second bit and selects a second value 2326 from a memory 2322 of the integrated circuit 2320 based on the programming state of the second bit.

[0268] In some implementations, in response to the second request to read the second memory bit, the integrated circuit 2320 identifies a second other bit on the fluid ejection device having a desired programming state and redirects the second request to read the second memory bit to the second other memory bit. The integrated circuit 2320 may identify the second other bit based on a mapping in the memory 2322 of the second bit to the second other bit. Based on the redirected third request, the integrated circuit 2320 may receive, from the fluid ejection device, a signal having the second value 2326.

[0269] At 2304, the integrated circuit 2320 provides a second signal having the second value corresponding to the second memory bit in response to the second request. At 2305, the host 2310 transmits a third request to read the first and second memory bits in parallel. The third request may include a third memory access sequence to access the first and second memory bits. The third memory access sequence may include one or more operations of the memory access protocol 1400 of FIG. 14 and a data packet including address bits for the first andsecond memory bits. The third memory access sequence may be the same as the first memory access sequence and the second memory access sequence, except the third memory access sequence includes the address bits for the first memory bit and the address bits for the second memory bit.

[0270] By transmitting the first, second, and third requests, the host 2310 is able to receive values for the first bit and the second bit and then compare those values to a parallel bit read. This allows the host 2310 to ensure that the parallel bit read is consistent with the previously returned values for the first and second bits individually. The integrated circuit 2320 may store the first value 2324 and the second value 2326 in the memory 2322 in order to provide consistent responses to multiple reads and parallel reads of the first and second memory bits.

[0271] In some implementations, in response to the third request to read the first and second memory bits, the integrated circuit 2320 determines a programming state of the first and second memory bits and selects a third value 2328 from a memory 2322 of the integrated circuit 2320 based on the programming state of the first and second memory bits and / or the first value 2324 and the second value 2326. In some implementations, the integrated circuit 2320 selects the third value 2328 based on the response curves 2100 of FIG. 21 or the response curves 2200 of FIG. 22.

[0272] In some implementations, in response to the third request to read the first and second memory bits, the integrated circuit 2320 redirects the third request to read the first and second memory bits to the first and second other memory bits. The integrated circuit 2320 may identify the first and second other memory bits based on the mapping in the memory 2322 of the first and second memory bits to the first and second other memory bits. Based on the redirected third request, the integrated circuit 2320 may receive, from the fluid ejection device, a signal having the third value 2328.

[0273] At 2306, the integrated circuit 2320 provides a third signal having the third value 2328 corresponding to the parallel read of the first and second memory bits to the host 2310. In this way, the integrated circuit 2320 provides consistent and expected response signals to multiple reads and parallel reads of the first and second memory bits. In response to the third signal, the host 2310 may determine that the fluid ejection device is in good condition and / or operating as expected.

[0274] The present disclosure addresses examples of integrated circuits for association with printhead cartridges. These cartridges are provided with a printhead, also referred to as fluid ejection device (which may find implementation beyond print). The integrated circuit may be an intermediate circuit between the OEM (Original Equipment Manufacturer) cartridge and the printer, or the integrated circuit could be a part of a printhead, for example a non-OEM printhead. Different aspects of the integrated circuit may comprise any or any combination of the following features.

[0275] The integrated circuit may comprise a first contact to receive first address bits from a host controller. The integrated circuit may comprise a second contact to transmit second address bits to a fluid ejection device, the second address bits based on the first address bits. The first contact may be a contact of a host-side contact array including a host-side data contact to receive first data packets from a host controller. The second contact may be a contact of a device side contact array including: a device-side data contact to output second data packets to a fluid ejection device, each second data packet corresponding to a received first data packet. The integrated circuit may be configured to transmit the second data packets that are modified with respect to corresponding first data packets so that the fluid ejection device ejects fluid based on the second data packets. The first contact may be to receive a first data packet from the host controller, the first data packet including address bits and random data. The second contact may be to transmit a second data packet to the fluid ejection device.

[0276] The integrated circuit may comprise control logic to generate the second data packet including second address bits based on the first address bits. The control logic may be configured to, as the first packet is received, generate the second data packet based on the first packet. The first data packet may include a first payload and additional bits. The control logic may be configured to generate the second data packet including a second payload based on the first payload. The control logic may be configured to modify the first address data packet based on an address offset to generate the second packet. The first data packet may include random data. The control logic is configured to respond with data signals to the host controller, in response to a memory read request from the host controller, for example, without transmitting signals to the fluid ejection device, whereby the control logic is further configured to transmit other signals to the fluid ejection device in modified or unmodified format.

[0277] The integrated circuit may comprise a contact array of parallel contact columns to align to corresponding host contact and / or cartridge contacts. The contact array may include one or more of a fire contact, an analog contact, a mode contact, a clock contact and at least one data contact. The control logic may be configured to (a) receive, (i) over a period of a plurality of clock cycles, a first data access signal sequence comprising high signal over the mode contact, a low signal over the fire contact, and a signal over the data contact, (ii) a second data access signal sequence comprising a high signal over the mode contact and a low signal over the fire contact, and data access signals over the data contact, the data signals indicating a read or write event; and, in response to the first and second data access signal sequence, (c) respond with a data value corresponding to the data access signals of the read event, if the data access signals indicated a read event, and (b) process bits of the write event, if the data access signals indicated a write event, to respond with the processed bits in a later read event; and, not respond with data values in response to other signal sequences that donot comprise the first and second data access signal sequence, whereby the control logic may be configured to transmit the other signal sequences in modified or unmodified format.

[0278] The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable," to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interacting and / or logically interactable components.

[0279] With respect to the use of substantially any plural and / or singular terms herein, those having skill in the art can translate from the plural to the singular and / or from the singular to the plural as is appropriate to the context and / or application. The various singular / plural permutations may be expressly set forth herein for sake of clarity. For example, recitations of plural elements can be understood to include of the element discussed.

[0280] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limitedto," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and / or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In those instances where a convention analogous to "at least one of A, B, or C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A andB together, A and C together, B and C together, and / or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and / or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B." Further, unless otherwise noted, the use of the words “approximate,” “about,” “around,” “substantially,” etc., mean plus or minus ten percent.

[0281] The foregoing description of illustrative examples has been presented for purposes of illustration and of description. It is not intended to be exhaustive or limiting with respect to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed examples. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. An integrated circuit comprising: a first contact to receive a first data packet from a host controller, the first data packet including address bits and random data; a second contact to transmit a second data packet to a fluid ejection device; and control logic to: generate the second data packet including second address bits based on the first address bits.

2. The integrated circuit of claim 1, wherein generating the second data packet includes identifying the first address bits and / or the random data.

3. The integrated circuit of any of claims 1-2, the control logic to identify the first address bits and / or the random data based on an end of the first data packet.

4. The integrated circuit of claim 3, the control logic to identify the first address bits and / or the random data based on the first address bits being located a predetermined number of bits from the end of the first data packet.

5. The integrated circuit of any of claims 3-4, wherein generating the second data packet based on the end of the first data packet includes removing and / or changing at least part of the random data from the first data packet.

6. The integrated circuit of any of claims 1-5, wherein generating the second data packet includes converting the first address bits to the second address bits according to an address bit sequence associated with the fluid ejection device.

7. The integrated circuit of any of claims 1-6, wherein generating the second data packet includes applying an address offset associated with the fluid ejection device to the one or more address bits.

8. The integrated circuit of any of claims 1-7, wherein generating the second data packet includes modifying one or more control bits of the first data packet.

9. The integrated circuit of any of claims 1-8, wherein the first data packet and the second data packet include a same primitive data.

10. The integrated circuit of any of claims 3-9, further comprising a third contact to receive a fire signal from the host controller, wherein identifying the end of the first data packet includes identifying a rising edge of the fire signal.

11. The integrated circuit of any of claims 3-10, further comprising a third contact to receive a clock signal from the host controller, wherein identifying the end of the first data packet includes determining a clock idle time of the clock signal.

12. The integrated circuit of any of claims 1-11, wherein the first data packet includes the random data, a first head, a first middle portion and a first tail, wherein the first head includes the first address bits, the first middle portion includes the primitive data, and the first tail includes the first address bits and first control bits, wherein the second data packet includes a second head, a second middle portion, and a second tail, wherein the second head includes the second address bits, the second middle portion includes the primitive data, and the second tail includes the second address bits and second control bits.

13. The integrated circuit of any of claims 1-12, wherein the random data includes pseudo-random data.

14. The integrated circuit of any of claims 1-13, wherein the first address bits correspond to a first nozzle circuit in a nozzle circuit array of the fluid ejection device, and wherein the second address bits correspond to a second nozzle circuit in the nozzle circuit array of the fluid ejection device.

15. An integrated circuit comprising: a first contact to receive a first data packet from a host controller, the first data packet including a first payload and additional bits;a second contact to transmit a second data packet to a fluid ejection device; and control logic to: generate the second data packet including a second payload based on the first payload.

16. The integrated circuit of claim 15, wherein the additional bits include random or pseudo-random data.

17. The integrated circuit of any of claims 1-16, wherein the first payload includes a first head, a first middle portion and a first tail, wherein the first head includes first address bits, the first middle portion includes primitive data, and the first tail includes the first address bits and first control bits, wherein the second payload includes a second head, a second middle portion, and a second tail, wherein the second head includes the second address bits, the second middle portion includes the primitive data, and the second tail includes the second address bits and second control bits.

18. The integrated circuit of claim 15, wherein the second control bits are the same as the first control bits.

19. The integrated circuit of any of claims 15-18, wherein generating the second data packet includes identifying the first payload based on a predetermined amount of time between the first payload and a preceding packet.

20. The integrated circuit of claim 19, the control logic to determine the predetermined amount of time based on identifying ends of adjacent data packets.

21. The integrated circuit of any of claims 15-20, the control logic to read a clock signal received from the host controller.

22. The integrated circuit of claim 21, the control logic to measure the predetermined amount of time using the clock signal.

23. The integrated circuit of any of claims 15-22, wherein generating the second data packet based on the payload of the first data packet includes removing and / or changing the additional bits.

24. The integrated circuit of any of claims 17-23, wherein generating the second data packet includes modifying the first address bits of the first data packet to generate the second address bits.

25. The integrated circuit of claim 24, wherein modifying the first address bits includes converting the first address bits to the second address bits according to an address bit sequence associated with the fluid ejection device.

26. The integrated circuit of any of claims 24-25, wherein modifying the first address bits includes applying an address offset associated with the fluid ejection device to the one or more address bits.

27. An integrated circuit comprising: a first contact to receive a first data packet from a host controller, the first data packet including random data; a second contact to transmit a second data packet to a fluid ejection device; and control logic to: as the first packet is received, generate the second data packet based on the first packet.

28. The integrated circuit of claim 27, wherein generating the second data packet includes: comparing one or more bits of the first packet to predefined bits; and generating the second data packet based on the comparison.

29. The integrated circuit of any of claims 27-28, wherein the random data includes pseudo-random data.

30. The integrated circuit of any of claims 27-29, the control logic to determine the predefined bits based on one or more patterns of bits in successive data packets.

31. The integrated circuit of any of claims 27-30, wherein the predefined bits are predefined address bits, the control logic to determine the predefined address bits based on a sequence of address bits received at the first contact.

32. The integrated circuit of any of claims 27-31, wherein the first data packet includes the random data, a first head, a first middle portion and a first tail, wherein the first head includes the first address bits, the first middle portion includes the primitive data, and the first tail includes the first address bits and first control bits, wherein the second data packet includes a second head, a second middle portion, and a second tail, wherein the second head includes the second address bits, the second middle portion includes the primitive data, and the second tail includes the second address bits and second control bits.

33. The integrated circuit of any of claims 27-32, wherein generating the second data packet includes modifying the first address bits of the first data packet to generate the second data packet.

34. The integrated circuit of claim 33, wherein modifying the one or more address bits includes converting the first address bits to the second address bits according to an address bit sequence associated with the fluid ejection device.

35. The integrated circuit of any of claims 27-34, wherein modifying the first address bits includes applying an address offset associated with the fluid ejection device to the first address bits.

36. The integrated circuit of any of claims 27-35, the control logic to, as the first data packet is being received, begin transmitting the second data packet to the fluid ejection device.

37. The integrated circuit of claim 36, the control logic to determine to transmit the second data packet to the fluid ejection device as the first data packet is being received based on a low latency requirement.

38. The integrated circuit of any of claims 36-37, the control logic to begin transmitting the second data packet based on a set of bits of the first data packet matching a set of bits of the predefined bits and a probability of the set of bits of the first data packet being a beginning of a payload of the first data packet.

39. The integrated circuit of claim 38, the control logic to: generate a third data packet based on a second set of bits of the first data packet not matching a second set of bits of the predefined bits; and transmit the third data packet to the fluid ejection device using the second contact.

40. The integrated circuit of any of claims 38-39, the control logic to: determine, based on a target latency, a transmit point in the first data packet at which the integrated circuit begins transmitting the second data packet; and begin transmitting the second data packet to the fluid ejection device based on the set of bits of the first data packet being the transmit point.

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