Method for producing an integrated photonic circuit, and integrated photonic circuit

Abstract

The invention relates to a method for producing an integrated photonic circuit (10), comprising the following steps: (11) providing a waveguide layer (12), in particular on a wafer (14) or on a chip; (13) thinning the waveguide layer (12) in at least one region (16); (15) forming at least one waveguide (18) in the waveguide layer (12). The invention also relates to an integrated photonic circuit (10) produced according to such a method.

Description

[0001] Method for producing an integrated photonic circuit and an integrated photonic circuit

[0002] Description

[0003] The invention relates to a method for producing an integrated photonic circuit having the features of claim 1 and to an integrated photonic circuit having the features of claim 7.

[0004] A photonic integrated circuit (PIC) typically comprises a portion of a wafer on which a layer containing a core material (waveguide layer) is arranged. Typically, a plurality of (similar) integrated photonic circuits are formed or manufactured on a wafer. After the integrated photonic circuits have been formed, the wafer is cut in such a way that the integrated photonic circuits are separated from one another. Each of the separated integrated photonic circuits comprises a portion of the wafer. Typically, the waveguide layer has a nearly uniform thickness across the entire wafer. This results in the waveguides formed in the core material having a uniform height across the wafer.However, to couple light into the waveguide, a height of the waveguide that differs from the usual cross-section of the waveguide and is usually smaller is desirable (for reasons of coupling efficiency).

[0005] It is therefore an object of the present invention to provide a method for producing an integrated photonic circuit and an integrated photonic circuit, wherein the above disadvantages are eliminated.

[0006] The above object is achieved by a method for producing an integrated photonic circuit having the features of claim 1.

[0007] The procedure includes the following steps:

[0008] Providing a waveguide layer. The waveguide layer can be provided or arranged on a wafer or on a chip. The waveguide layer can be formed from lithium niobate. The wafer can be a silicon wafer with a base layer (buffer layer) made of silicon dioxide (SiO2). The waveguide layer can be covered by a silicon dioxide cap layer. The waveguide layer can be arranged between two silicon dioxide layers.

[0009] Thinning the waveguide layer in at least one region. Forming at least one waveguide in the waveguide layer.

[0010] In the present case, "thinning" means a region-by-region and / or layer-by-layer removal of at least one atomic or molecular layer, in particular several such layers, of the waveguide layer and / or the waveguide.

[0011] This allows the height of the waveguide layer or waveguide to be well controlled and (spatially) varied. Thus, in the thinned region, the waveguide layer or waveguide can be manufactured with a first, e.g., lower, height, while the waveguide layer or waveguide outside the thinned region has a second, e.g., greater, height.

[0012] In this case, "height" refers to the thickness of the waveguide layer or the extension of the waveguide along a surface normal of the waveguide layer (vertical extension).

[0013] In this context, "wafer" refers to at least a portion of a wafer. In particular, it does not refer to the entire wafer with a multitude of integrated photonic circuits (before separation).

[0014] According to a further development of the method, the step of thinning the waveguide layer in at least one region can be performed prior to the step of forming at least one waveguide in the waveguide layer. In other words, the waveguide layer can first be thinned in regions, and then the waveguide can be produced in the (regionally thinned) waveguide layer.

[0015] This allows the temporal sequence of the procedural steps and thus the entire process to be designed flexibly.

[0016] According to a further development of the method, the step of forming at least one waveguide in the waveguide layer can be performed prior to the step of thinning the waveguide layer (or the waveguide formed in the waveguide layer) in at least one region. In other words, the waveguide can first be produced in the waveguide layer and then thinned in certain regions.

[0017] This allows the temporal sequence of the procedural steps and thus the entire process to be designed flexibly.

[0018] According to a further development of the method, the step of thinning the waveguide layer in at least one region can be carried out by ablation using a focused ion beam. A degree of thinning can be linked to a dwell time of the ion beam. A higher degree of thinning can thus be achieved by a longer dwell time of the ion beam. In other words, the longer the ion beam remains at one point (dwell time), the more material is removed from the waveguide layer.

[0019] This allows the thinning of the waveguide layer to be implemented as simply and efficiently as possible.

[0020] According to a further development of the method, the step of forming at least one waveguide in the waveguide layer can be carried out using a lithography process. In particular, UV (ultraviolet) lithography or electron beam lithography can be used for this purpose. The waveguide can be structured (or manufactured) using standard methods such as lithography with etching.

[0021] This allows the formation of the waveguide in the waveguide layer to be implemented as simply and efficiently as possible.

[0022] According to a further development of the method, the method may comprise the step:

[0023] Creating and / or providing a map. The map can be a two-dimensional (2D) map. The map can comprise at least one height value, in particular a plurality of height values, for the waveguide layer and / or the waveguide. The step of thinning the waveguide layer and / or the waveguide in at least one region can be carried out according to the at least one height value of the map. In other words, the thinning of the waveguide layer and / or the waveguide can be carried out based on the map.

[0024] According to a further development of the method, the method may comprise the step:

[0025] Creating an actual map. The actual map may be a two-dimensional (2D) map. The actual map may include at least one measured actual height value of the waveguide layer and / or the waveguide. The step of thinning the waveguide layer and / or the waveguide in at least one region may be performed until the actual map conforms to the map.

[0026] The step of creating the actual map can be repeated several times for this purpose. In other words, the actual height value in an area is measured and compared with the height value from the map. If the actual height value from the actual map does not match the height value from the map, or if the difference between the actual height value and the height value is a certain size, the thinning of the waveguide layer and / or the waveguide is continued. An actual map is then created again by measuring the actual height value and comparing it with the map or its height value. This can be repeated until the actual height value and the height value match, or until the difference between the actual height value and the height value (or between the actual map and the map) has reached an acceptable level.

[0027] In this way, the required height (or heights) for the waveguide and / or the waveguide layer for the entire wafer can be transferred to the map or recorded in the map. The waveguide and / or the waveguide layer can then be thinned using the map. This can be achieved, for example, by processing with a focused ion beam. The dwell time of the focused ion beam at the various points on the wafer can be programmed so that the ablation caused by the ion beam reflects the map with the corresponding heights. This means that the heights recorded in the map are transferred to the waveguide and / or the waveguide layer. In this way, the waveguide and / or the waveguide layer can be realized with simple means with heights that vary spatially across the wafer.Based on the map and / or the actual map, an exact positioning of the varying heights can be determined and / or implemented.

[0028] A layout mask can be created for the entire wafer, e.g., using suitable layout software. One layer of this layout mask can comprise the outline of the waveguide, while another layer can comprise the outline of at least one integrated photonic circuit, in particular several integrated photonic circuits.

[0029] Furthermore, using suitable layout software, the map can be generated with at least one height value or with several height values ​​for the required height of the waveguide layer. The map can also include values ​​or settings for the respective transitions (e.g. continuously variable) between the different height values. For example, the map can be used to determine or specify that the height of the waveguide layer or of the waveguide along the edges of the integrated photonic circuit can be in a range from 50 nm to 200 nm, in particular should be 100 nm, while everywhere else on the integrated photonic circuit it should be in a range from 600 nm to 1000 nm, in particular should be 800 nm. It is also conceivable that, for example, the map can be used to determine or specify that the height of the waveguide layer or of the waveguideof the waveguide along the edges of the integrated photonic circuit should be in a range of 600 nm to 1000 nm, in particular 800 nm, for example, while everywhere else on the integrated photonic circuit it should be in a range of 50 nm to 200 nm, in particular 100 nm.

[0030] The wafer can be coated with a resist (e.g. photoresist). The layout mask, which defines the outline of the waveguide, can be exposed using a suitable means or tool (UV lithography, electron beam lithography, etc.). The waveguide is formed in the waveguide layer by etching. The steps of forming the waveguide and thinning can be swapped over in time. The waveguide can then first be formed or structured with a uniform (same) height and then thinned out in certain areas, for example using a focused ion beam.

[0031] In further process steps, the wafer can be completed and the integrated photonic circuits can be separated according to the contours defined in the layout mask.

[0032] The above object is achieved by an integrated photonic circuit having the features of claim 7. The integrated photonic circuit is manufactured by the method according to the above statements.

[0033] With regard to the advantages that can be achieved, reference is made to the relevant explanations of the method. The measures described in connection with the method and / or those explained below can be used to further refine the integrated photonic circuit.

[0034] According to a further development of the integrated photonic circuit, the waveguide layer can be made of lithium niobate. This allows for the most optimal waveguiding or waveguide possible (due to the different refractive indices of lithium niobate and air or silicon dioxide).

[0035] According to a development of the integrated photonic circuit, the integrated photonic circuit can comprise the waveguide layer, the waveguide, a wafer, a chip and / or a base layer. The wafer can be formed as a silicon wafer. The base layer can be arranged between the wafer and the waveguide layer. The base layer can be formed from silicon dioxide. The waveguide layer or the waveguide can be arranged directly at or on the base layer. The base layer can be arranged directly at or on the wafer or the chip.

[0036] In this way (due to a different refractive index of lithium niobate and air or silicon dioxide) the most optimal wave guidance or waveguide can be produced.

[0037] According to a further development of the integrated photonic circuit, the waveguide layer and / or the waveguide can have a first height in the at least one thinned region. The waveguide layer and / or the waveguide can have a second height outside the at least one thinned region. The transition between the first height and the second height can be continuous. The first height can be 100 nm (nanometers). The first height can be in a range of 50 nm and

[0038] 200 nm . The second height can be 800 nm . The second height can be in a range between 600 nm and 1000 nm .

[0039] For example, an integrated photonic circuit can be manufactured with a waveguide layer or waveguide in which the waveguide is, for example, 100 nm high at the edges of the circuit. This can improve the coupling or decoupling (e.g., to optical fibers).

[0040] Everywhere else on the integrated photonic circuit, the waveguide layer or waveguide can be 800 nm high. This allows the light coupled into the waveguide to be particularly well confined and guided within the waveguide.

[0041] Further features, details and advantages of the invention will become apparent from the wording of the claims and from the following description of exemplary embodiments with reference to the drawings. They show:

[0042] Fig. 1 is a flowchart of a method for manufacturing an integrated photonic circuit;

[0043] Fig. 2 is a schematic sectional view of an integrated photonic circuit and

[0044] Fig. 3 is a schematic perspective view of the integrated photonic circuit according to Figure 2.

[0045] In the following description and in the figures, corresponding components and elements have the same reference numerals. Figure 1 shows a flowchart of a method for producing an integrated photonic circuit 10 (cf.

[0046] Figure 2 ) according to a first embodiment.

[0047] The procedure includes the following steps:

[0048] 11: Providing a waveguide layer 12. This can be provided in particular on a wafer 14 or on a chip (see Figure 2).

[0049] 13 : Thinning of the waveguide layer 12 in at least one region 16 (cf. Figure 2 ).

[0050] 15 : Formation of at least one waveguide 18 in the waveguide layer 12 (cf. Figure 2 ).

[0051] The step 13 of thinning the waveguide layer 12 in at least one region 16 is carried out in the present case before the step 15 of forming at least one waveguide 18 in the waveguide layer 12.

[0052] Step 13 of thinning the waveguide layer 12 in at least one region 16 can be performed by ablation using a focused ion beam. A higher degree of thinning can be achieved by a longer residence time (on the waveguide layer 12) of the ion beam. Accordingly, a lower degree of thinning can be achieved by a shorter residence time of the ion beam.

[0053] It is also conceivable that step 15 of forming at least one waveguide 18 in the waveguide layer 12 is carried out before step 13 of thinning the waveguide layer 12 in at least one region 16. The temporal sequence of steps 13 and 15 can therefore be interchanged.

[0054] The step 15 of forming at least one waveguide 18 in the waveguide layer 12 can be carried out using a (standard) lithography method. UV lithography or electron beam lithography can be used for this purpose.

[0055] The procedure in this case comprises step 17 :

[0056] Creating and / or providing a map. The map can be a two-dimensional map. The map can include at least one height value for the waveguide layer 12 and / or the waveguide 18. In this case, step 13 of thinning the waveguide layer 12 and / or the waveguide 18 in at least one region 16 can be carried out according to the at least one height value of the map. In other words, the heights stored or saved as height values ​​in the map can be transferred to the waveguide layer and / or the waveguide.

[0057] The method may comprise the step of:

[0058] 19: Creating an actual map. The actual map can be a two-dimensional map. The actual map can comprise at least one measured actual height value of the waveguide layer 12 and / or the waveguide 18. In this case, step 13 of thinning the waveguide layer 12 and / or the waveguide 18 can be carried out in at least one region 16 until the actual map corresponds to the map (or until the actual height value corresponds to the height value). Figure 2 shows a schematic sectional view (cross section) of an integrated photonic circuit 10. The integrated photonic circuit 10 is produced by means of the method according to the above explanations.

[0059] The integrated photonic circuit 10 in the present case comprises the waveguide layer 12 and the waveguide 18 formed in the waveguide layer (shown in longitudinal section in Figure 2). The integrated photonic circuit 10 can comprise a wafer 14 or a chip. The wafer 14 can be formed as a silicon wafer. The integrated photonic circuit 10 in the present case comprises a base layer 20. The base layer 20 is arranged between the wafer 14 and the waveguide layer 12. In Figure 2, the waveguide layer 12 and the waveguide 18 are arranged directly on the base layer 20 and the base layer 20 is arranged directly on the wafer 14 (or chip). The waveguide layer 12 can be formed from lithium niobate. The base layer 20 can be formed from silicon dioxide.

[0060] The thinned region 16 is located in the present case at the edge of the integrated photonic circuit 10 (on the left and right in Figure 2). The waveguide 18 is formed in the waveguide layer 12 and runs in a straight line from left to right in the schematic sectional view of Figure 2. Of course, a different course or path of the waveguide 18 is also conceivable.

[0061] The waveguide layer 12 and / or the waveguide 18 in the at least one thinned region 16 has a first height 22 in the present case. Outside the at least one thinned region 16, the waveguide layer 12 and / or the waveguide 18 has a second height 24. A transition 26 between the first height 22 and the second height 24 is formed in the present case as a continuous step.

[0062] The first height 22 can be 100 nm. The second height 24 can be 800 nm. This allows the light to be coupled into the integrated photonic circuit 10 to be coupled into a waveguide 18 that is 100 nm high at the edge of the integrated photonic circuit 10 (e.g. on the left in Figure 2) or coupled out (e.g. on the right in Figure 2). After the light has been coupled in, the light can be guided by means of a waveguide 18 that is 800 nm high in this case. This makes it possible to increase the efficiency when coupling in or out and / or when guiding the light. Corresponding losses (e.g. losses in light intensity) can be reduced.

[0063] Figure 3 shows a schematic perspective view of the integrated photonic circuit 10 according to Figure 2. The waveguide 18 is merely indicated in Figure 3 by a dashed line. For clarity, the first height 22 and second height 24 are not shown (see Figure 2) and are shown in a different relationship to one another with respect to Figure 2.

Claims

Patent claims 1. A method for producing an integrated photonic circuit (10) comprising the steps: (11) Providing a waveguide layer (12), in particular on a wafer (14) or on a chip; (13) thinning the waveguide layer (12) in at least one region (16); (15) Forming at least one waveguide (18) in the waveguide layer (12).

2. Method according to claim 1, characterized in that the step (13) of thinning the waveguide layer (12) in at least one region (16) is carried out before the step (15) of forming at least one waveguide (18) in the waveguide layer (12).

3. The method according to claim 1, characterized in that the step (15) of forming at least one waveguide (18) in the waveguide layer (12) is carried out before the step (13) of thinning the waveguide layer (12) in at least one region (16).

4. Method according to one of the preceding claims, characterized in that the step (13) of thinning the waveguide layer (12) in at least one region (16) is carried out by means of ablation by a focused ion beam, in particular wherein a higher degree of thinning is achieved by a longer residence time of the ion beam.

5. Method according to one of the preceding claims, characterized in that the step (15) of forming at least one waveguide (18) in the waveguide layer (12) is carried out by means of a lithography method, in particular by means of UV lithography or electron beam lithography.

6. Method according to one of the preceding claims, characterized in that the method comprises the step: (17) Creating and / or providing a map, in particular a two-dimensional map, wherein the map comprises at least one height value for the waveguide layer (12) and / or the waveguide (18), wherein the step (13) of thinning the waveguide layer (12) and / or the waveguide (18) in at least one region (16) is carried out according to the at least one height value of the map.

7. The method according to claim 6, characterized in that the method comprises the step: Creating an actual map, in particular a two-dimensional map, wherein the actual map comprises at least one measured actual height value of the waveguide layer (12) and / or the waveguide (18), wherein the step (13) of thinning the waveguide layer (12) and / or the waveguide (18) in at least one region (16) is carried out until the actual map corresponds to the map.

8. Integrated photonic circuit (10), characterized in that the integrated photonic circuit (10) is manufactured by means of the method according to one of the preceding claims.

9. Integrated photonic circuit (10) according to claim 8, characterized in that the waveguide layer (12) is formed from lithium niobate.

10. Integrated photonic circuit (10) according to claim 8 or 9, characterized in that the integrated photonic circuit (10) comprises the waveguide layer (12), the waveguide (18), a wafer (14), in particular a silicon wafer, a chip and / or a base layer (20), wherein the base layer (20) is arranged between the wafer (14) or chip and the waveguide layer (12), in particular wherein the base layer (20) is formed from silicon dioxide.

11. Integrated photonic circuit (10) according to one of claims 8 to 10, characterized in that the waveguide layer (12) and / or the waveguide (18) has a first height (22) in the at least one thinned region (16) and a second height (24) outside the at least one thinned region (16), wherein a transition (26) between the first height (22) and the second height (24) is formed steplessly, in particular wherein the first height (22) is between 50 nm and 200 nm, in particular 100 nm, and / or the second height (24) is between 600 nm and 1000 nm, in particular 800 nm.

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