Executing quantum programs on modular quantum processing units

Abstract

In a general aspect, quantum programs are executed on modular quantum processing units in a quantum computing system. In some implementations, a method includes receiving a quantum program including a sequence of quantum logic operations; decomposing the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; and segmenting the sequence of quantum logic gates into an equivalent sequence of quantum circuit widgets. Each quantum circuit widget includes a subset of the quantum logic gates in the sequence and corresponds to a time slice of the quantum program. The quantum circuit widgets are compiled to produce a set of compiled quantum circuit widgets to be executed on multiple quantum processor modules of the quantum computing system.

Description

Attorney Docket No.: RIGET-125WO1 Executing Quantum Programs on Modular Quantum Processing Units CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 595,227, filed November 1, 2023, entitled “Guidestars for Modular Quantum Computing;” U.S. Provisional Patent Application No.63 / 561,601, filed March 5, 2024, entitled “Quantum Algorithm Partitioning, Graph Compilation and Scheduling on a Large- scale Quantum Computer;” U.S. Provisional Patent Application No.63 / 656,904, filed June 6, 2024, entitled “Quantum Algorithm Partitioning, Graph Compilation and Scheduling on a Large-scale Quantum Computer;” and U.S. Provisional Patent Application No.63 / 693,929, filed September 122024, entitled “Quantum Algorithm Partitioning, Graph Compilation and Scheduling on a Large-scale Quantum Computer.” The above-referenced priority documents are incorporated herein by reference. TECHNICAL FIELD

[0002] The following description relates generally to executing quantum programs on modular quantum processing units. GOVERNMENT SUPPORT

[0003] This invention was made with Government support under agreement No. HR00112230006, awarded by DARPA. The Government has certain rights in the invention. BACKGROUND

[0004] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in, and represented by, an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconducting circuits, trapped ions, spin systems, and others.Attorney Docket No.: RIGET-125WO1 BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG.1 is a block diagram of an example computing environment.

[0006] FIG.2 is a flow chart showing aspects of an example process.

[0007] FIG.3 is a flow chart showing aspects of an example process.

[0008] FIG.4 is a schematic diagram showing aspects of an example tree structure of an example quantum program.

[0009] FIG.5 is a schematic diagram showing aspects of an example quantum logic circuit.

[0010] FIG.6 is a schematic diagram showing aspects of an example process.

[0011] FIG.7 is a schematic diagram showing aspects of an example modular quantum processing unit.

[0012] FIG.8 is a schematic diagram showing a portion of an example process for performing a modular graph state processing.

[0013] FIG.9 is a schematic diagram showing aspects of an example modular quantum processing unit.

[0014] FIG.10 is a schematic diagram showing a portion of an example process for performing a modular graph state processing.

[0015] FIG.11 is a schematic diagram of a top view showing a portion of an example superconducting quantum processing unit.

[0016] FIG.12 is a block diagram showing a top view of an example modular quantum processing unit.

[0017] FIG.13 is a schematic diagram showing aspects of an example quantum processor module.

[0018] FIG.14 is a schematic diagram showing aspects of an example quantum processor module.Attorney Docket No.: RIGET-125WO1

[0019] FIG.15 is a schematic diagram showing aspects of an example modular quantum processing unit.

[0020] FIG.16 is a schematic diagram showing aspects of an example quantum processor module.

[0021] FIG.17 is a schematic diagram showing aspects of an example quantum processor module.

[0022] FIG.18 is a schematic diagram showing a portion of an example process for performing a modular graph state processing.

[0023] FIG.19 shows an example triangular magnetic lattice.

[0024] FIG.20 is a table showing resource estimation for the Transverse-Ising model on the triangular lattice of side length 10 shown in FIG.19.

[0025] FIG.21A is a plot showing the number of fault tolerant compiled logical qubits as a function of the number of T-states for three instance types.

[0026] FIG.21B is a plot showing the bus size (e.g., the number of physical, non-T state distillation qubits) as a function of fault tolerant runtime in second for three instance types.

[0027] FIG.22 is a plot showing the normalized fault tolerant runtime as a function of the number of inter-module connections.

[0028] FIGS.23A-23C are plots showing the number of physical qubits allocated for the quantum bus and the T-state distillation factories in the same quantum processor module as a function of instance size.

[0029] FIGS.24A-24C are plots showing the execution time in seconds as a function of instance size.

[0030] FIG.25 shows an example T-distillation factories lookup table.

[0031] FIG.26 is an example algorithm for resource estimation.

[0032] FIG.27 is a plot showing logical error as a function of physical error rate.Attorney Docket No.: RIGET-125WO1 DETAILED DESCRIPTION

[0033] In some aspects of what is described here, a quantum program can be segmented into multiple quantum circuit widgets representing multiple time slices of the quantum program. In some examples, the quantum program can be segmented based on a tree structure, with different levels of the tree structure representing different decomposition levels of the quantum program. In some cases, the tree structure can be obtained by decomposing the quantum program to a sequence of quantum logic gates, each of which is either a single-qubit or a two-qubit quantum logic gate. In some examples, quantum programs can be segmented into quantum circuit widgets in another manner. In some quantum computing systems, the quantum circuit widgets are applied to logical qubits. The quantum computing system can be an error corrected quantum computing system, a fault tolerant quantum computing system, or another class of quantum computing system.

[0034] In some implementations, the quantum program can be executed by executing the quantum circuit widgets on respective quantum processor modules of a modular quantum processing unit of a quantum computing system. For example, a first quantum circuit widget can be executed on a first quantum processor module during a first time period to generate first output quantum states. The first output quantum states can be teleported from the first quantum processor modules to a second quantum processor module, where a second quantum circuit widget can be executed during a second time period to generate second output quantum states based on the received first output quantum states and the second quantum circuit widget. In some instances, the sequence of quantum circuit widgets is executed alternatively on two or more quantum processor modules in an interleaved manner until all the quantum circuit widgets are executed. In some instances, sub-sequences when executing the first or the second quantum circuit widgets on the first and second quantum processor modules may occur simultaneously.

[0035] In some instances, each quantum circuit widget is compiled into hardware specific instructions by operation of a fault-tolerant compiler (e.g., a graph state compiler). The graph state compiler can convert each quantum circuit widget to a compiled quantum circuit widget which includes an equivalent graph state representation. A graph stateAttorney Docket No.: RIGET-125WO1 representation includes two sub-sequences, e.g., a graph state preparation schedule to prepare a graph state and a consumption schedule to obtain output quantum states. The execution of sub-sequences associated with the quantum circuit widgets can be coordinated. The quantum circuit widgets can be stitched together at respective interfaces between quantum processor modules reducing the overhead of connectivity of hardware modules.

[0036] This work has also enabled research towards assuring that real quantum computing platforms can be engineered to provide the espoused benefits of fault-tolerant operation. This includes addressing issues such as very low error rate T-state distillation widgets, but more broadly provides a software testbed for evaluating the impact of algorithmic, compilation, decoding, and physical-layer intrinsic or system architecture proposals. Rapid iteration in a simulated space is a proven methodology to accelerate technology growth.

[0037] In some implementations, the systems and techniques described here can provide technical advantages and improvements. For example, the systems and methods provide a way to split an algorithm into widgets, schedule execution onto a modular quantum processing unit, thereby reducing the overall hardware requirements. In some cases, a combination of these and potentially other advantages and improvements may be obtained. The systems and techniques presented here facilitate the development of fault- tolerant quantum computers (FTQCs) allowing error correction and the use of a large number of qubits. The systems and techniques presented here can be used to estimate the physical resources required to execute specific quantum algorithms, power consumption, and execution time associated with the execution of the quantum algorithms according to explicit assumptions about the system’s physical layout, thermal load, and modular connectivity. The systems and techniques presented here can be used to understand the impact of trade-offs, inter-module connectivity, latency, and resource requirements.

[0038] FIG.1 is a block diagram of an example computing environment 100, according to an example embodiment. The example computing environment 100 shown in FIG.1 includes a computing system 101 and user devices 110A, 110B, 110C. A computing environment may include additional or different features, and the components of aAttorney Docket No.: RIGET-125WO1 computing environment may operate as described with respect to FIG.1 or in another manner.

[0039] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, 110B, 110C (referred to collectively as “user devices 110”). The computing system 101 shown in FIG.1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109, and other resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, and the components of a computing system may operate as described with respect to FIG.1 or in another manner.

[0040] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109, or otherwise).

[0041] The user devices 110 shown in FIG.1 may include one or more classical processors, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets, or other types of computer devices. In the example shown in FIG.1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in another manner, and the computing system 101 may expose computing resources in another manner.Attorney Docket No.: RIGET-125WO1

[0042] In the example shown in FIG.1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. For instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, the user device 110A communicates with the servers 108 through a local data connection.

[0043] The local data connection in FIG.1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B, and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computing systems 103A, 103B (or to one or more of the elements of the quantum computing systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0044] In the example shown in FIG.1, the remote user devices 110B, 110C operate remotely from the servers 108 and other elements of the computing system 101. For instance, the user devices 110B, 110C may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG.1, each of the user devices 110B, 110C communicates with the servers 108 through a remote data connection.

[0045] The remote data connection in FIG.1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connectionAttorney Docket No.: RIGET-125WO1 (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0046] The example servers 108 shown in FIG.1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B, and the other resources 107.

[0047] As shown in FIG.1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115, and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server, or a combination of these and other types of servers. The servers 108 may include additional or different features and may operate as described with respect to FIG.1 or in another manner.

[0048] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The memory 112 can include various forms of volatile or non-volatile memory, media, and memory devices, etc.Attorney Docket No.: RIGET-125WO1

[0049] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum simulators, or both) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0050] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B, or any of the other resources 107. The programs may include classical programs, quantum programs, hybrid classical / quantum programs, and may include any type of function, code, data, instruction set, etc.

[0051] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computer system, a simulator, a digital microprocessor, co- processor or other classical data processing apparatus, or another type of computing resource.

[0052] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication “A Practical Quantum Instruction SetAttorney Docket No.: RIGET-125WO1 Architecture,” arXiv:1608.03355v2, dated Feb.17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or simulators. In some cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form. In some cases, a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.). In some cases, a program may be expressed in another form or format. In some cases, a program may utilize Quil-T, described in the publication “Gain deeper control of Rigetti quantum processing units with Quil-T,” available at https: / / medium.com / rigetti / gain-deeper-control-of-rigetti-quantum-processors-with- quil-t-ea8945061e5b dated Dec.10, 2020, which is hereby incorporated by reference in the present disclosure.

[0053] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101. For example, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.

[0054] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise); the parametric update can be performed without further compilation. In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.Attorney Docket No.: RIGET-125WO1

[0055] In some implementations, the servers 108 generate a schedule for executing programs, allocate computing resources in the computing system 101 according to the schedule, and delegate the programs to the allocated computing resources. The servers 108 can receive, from each computing resource, output data from the execution of each program. Based on the output data, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action.

[0056] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical / quantum programs that include instructions for execution by one or more quantum computing resources (e.g., the quantum-based algorithms) and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.

[0057] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.Attorney Docket No.: RIGET-125WO1

[0058] Each of the example quantum computing systems 103A, 103B shown in FIG.1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in, and represented by, an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0059] In some implementations, a quantum computing system can operate using gate- based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation.

[0060] In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting codes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems mayAttorney Docket No.: RIGET-125WO1 operate in non-fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small- scale or non-scalable architectures.

[0061] The example quantum computing system 103A shown in FIG.1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system 103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG.1 or in another manner.

[0062] In some instances, all or part of the quantum processing unit 102A functions as a quantum processing unit, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102A includes a superconducting quantum circuit system. The superconducting quantum circuit may include data qubit devices, stabilizer qubit devices, coupler devices, readout devices, and possibly other devices that are used to store and process quantum information. In some cases, multiple data qubit devices are operatively coupled to a single stabilizer-check qubit device through respective coupler devices. In some implementations, the quantum processing unit 102A is implemented utilizing aspects designed or generated from the components and processes shown in FIGS. 2-4, or in another manner. In certain examples, the qubit devices and the coupler devices are implemented as superconducting quantum circuit devices that include Josephson junctions, for example, in Superconducting QUantum Interference Device (SQUID) loops or other arrangements, and are controlled by radio-frequency signals, microwave signals, and bias signals delivered to the quantum processing unit 102A.

[0063] In some instances, the quantum processing modules can include a superconducting quantum circuit that includes one or more quantum circuit devices. For instance, a superconducting quantum circuit may include qubit devices, readout resonatorAttorney Docket No.: RIGET-125WO1 devices, Josephson junctions, or other quantum circuit devices. In some implementations, quantum circuit devices in a quantum processing unit can be collectively operated to define a single logical qubit. A logical qubit includes a quantum register, for instance multiple physical qubits or qudits, and associated circuitry, that supports physical operations which can be used to detect or correct errors associated with logical states in a quantum algorithm. Physical operations supported by the quantum register associated with a logical qubit may include single-qubit or multi-qubit quantum logic gates and readout mechanisms. Error detection or correction mechanisms associated with a logical qubit may be based on quantum error correction schemes such as the surface code, color code, Bacon- Shor codes, low-density parity check codes (LDPC), some combination of these, or others.

[0064] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0065] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.Attorney Docket No.: RIGET-125WO1

[0066] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a room- temperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems, or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0067] The control systems 105A, 105B may be implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computing system may include multiple quantum processing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.

[0068] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102A. For example, the signal hardware 104A can be configured to operate in a particular frequency range, configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0069] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations, or other types of operations. As an example, the signal hardware 104A may include arbitraryAttorney Docket No.: RIGET-125WO1 waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radiofrequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices, or other types of components in the quantum processing unit 102A.

[0070] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The received signals can be generated by the execution of a quantum program on the quantum computing system 103A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radiofrequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A.

[0071] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A. For example, the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers, and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning, or other operations on readout signals received from the quantum processing unit 102A.Attorney Docket No.: RIGET-125WO1

[0072] The example controllers 106A communicate with the signal hardware 104A to control the operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interfaces with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0073] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in one or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0074] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.Attorney Docket No.: RIGET-125WO1

[0075] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitstrings from multiple shots may be analyzed to compute quantum state probabilities.

[0076] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above. For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical / quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0077] The other quantum computing system 103B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B, and controllers 106B) can be implemented as described above with respect to the quantum computing system 103A; in some cases, the quantum computing system 103B and its components may be implemented or may operate in another manner.

[0078] In some implementations, the quantum computing systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computer system 101 may include both an adiabatic quantum computing system and a gate-based quantum computer system. As another example, the computer system 101 mayAttorney Docket No.: RIGET-125WO1 include a superconducting circuit-based quantum computing system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.

[0079] The systems and techniques presented here can be used to understand the resources needed to execute large-scale quantum algorithms on an exemplar superconducting qubit architecture. The systems and techniques presented here can be used for superconducting fault-tolerant hardware resource estimation based on graph- state compilation of a quantum program. In some instances, the quantum processing unit 103 is a modular quantum processing unit with quantum processor modules each including a grid of logical qubits. In some instances, quantum processor modules in a modular quantum processing unit with fixed native connectivity and faster gate speed can be interconnected more sparsely with reduced fidelity, bandwidth, or entangling gate speed. In some instances, a modular quantum processing unit includes inter-module connections (e.g., pipes) between quantum processor modules of code distance ^. An interaction time between quantum processor modules can be defined as the inter-module tock.

[0080] In some instances, the quantum computing system 103 can be used for distributed fault-tolerant quantum computing based on inter-connected quantum processor modules. The computational power of each module has been constrained by yield. These operational (thermal) or manufacturing constraints limit the number of qubits that can be fabricated into a single quantum processing unit (QPU) hosted in a single quantum processor module.

[0081] In some instances, one or more classical processors (e.g., the servers 108 or the control system 105) of the computing system 101 can be operated to receive a quantum program, decompose the quantum program into a sequence of quantum logic gates that are compatible with a compilation process, segmenting the sequence of quantum logic gates into multiple quantum circuit widgets that consists of a set of single and two-qubit quantum logic gates, computing the graph properties of these quantum circuit widgets, and scheduling the preparation and consumption of these quantum circuit widgets on a specificAttorney Docket No.: RIGET-125WO1 hardware architecture. In some instances, one or more components of the computing system 101 shown in FIG.1 are configured to perform the operations of the example processes 200, 300, 600, 800, 1000, 1800 shown in FIGS.2, 3, 6, 8, 10, 18 or in another manner.

[0082] In some instances, a quantum logic circuit in a respective quantum circuit widget can be compiled into a graph-state resource (e.g., an algorithm-specific graph-state ^) to be consumed by a schedule of measurements. Using an algorithm-specific graph-state ^, the original unitary / quantum logic operations defined by and received from a user can be implemented deterministically by applying only single qubit measurements with classical feedforward. This describes a Measurement-Based Quantum Computing (MBQC) pattern which can be used for distributed Fault-tolerant quantum computing (FTQC) since only an algorithmic specific resource (e.g., a graph-state) and measurements on logical qubits must be specified. In some instances, the graph-state resource can be prepared via entangling operations on a single rail of ancilla logical qubits. Clifford operations are abstracted away, classically simulated, and converted into the graph-state resource.

[0083] In some instances, a graph state representation of a quantum logic circuit is defined by a set of vertices and a set of edges. The graph state corresponding to the graph state representation can be constructed by associating each vertex to a qubit and each edge to an entangling operation between the qubits represented by the edge’s vertices. The nodes will be assigned measurements on a non-Clifford basis corresponding to the non- Clifford gates in the initial quantum logic circuit of the quantum program. A set of schedules for preparing the graph state, performing non-Clifford measurements, and tracking Pauli corrections are required to execute the circuit fully. A nested set of stabilizer measurement schedules that prepares the graph for computation is denoted as ^^^^^^. The other nested set of non-Clifford measurement schedules “consumes” the graph state and is denoted as ^^^^^^^^^. Both schedules contain a list of subsets specifying the order of measurements, where each subset hosts the list of nodes meant to be measured simultaneously.Attorney Docket No.: RIGET-125WO1

[0084] In some instances, execution of the graph state representation naturally leads toa two-stage execution of the fault-tolerant quantum program. Preparing the graph per^^^^^, then performing s ^^^^^^^^ ingle qubit measurements to consume the graph per ^^ ,while accounting for the tracked Pauli corrections on the software, will essentially execute the complete algorithm. Furthermore, the essential distillation of non-Clifford ^ / magic states and decoding can be performed or delayed at any of the two stages as required.

[0085] FIG.2 is a flow chart showing aspects of an example process 200. In some instances, the example process 200 can be used for executing quantum programs on a quantum computing system that includes a modular quantum processing unit with multiple quantum processor modules. In some instances, the quantum computing system is a fault-tolerant quantum computing system, an error-corrected quantum computing system or another type of quantum computing system. In some instances, the quantum processor modules may be implemented as the quantum processor modules 704A / 704B, 812A / 812B, 904-1A / 904-2A / 904-3A / 904-1B / 904-2B / 904-3B, 1100, 1200, 1300, 1400, 1504A / 1504B / 1504C, 1600, 1700, 1812A / 1812B shown in FIGS.7-9, 11-18.

[0086] The modular quantum processing unit includes discrete, physical qubit devices which store quantum information, as well as components that manipulate, and readout, this information according to a set of instructions, typically compiled from a sequence of operations described in a quantum logical circuit. In some implementations, patches of physical qubits can be collectively used to define a logical qubit. In some implementations, the quantum processing unit can be configured to perform fault-tolerant quantum computing during which error correction can be carried out on logical qubits so that if the information on a physical qubit is corrupted, the integrity of the total computation is not adversely impacted. In some instances, the quantum computing system allows robust operations and readout of these logical qubits to a reasonable amount of corruption of the information stored by the physical qubits, thus, “fault tolerant.” In some implementations, the example process 200 may be performed by the computing system 101 shown in FIG.1 or in another manner. The example process 200 may include additional or different operations, including operations to fabricate additional or different components, and the operations may be performed in the order shown or in another order. In some cases,Attorney Docket No.: RIGET-125WO1 operations in the example process 200 can be combined, iterated, or otherwise repeated or performed in another manner.

[0087] The systems and techniques described here in this application can enhance the efficiency of the operation of a quantum computing system containing multiple superconducting physical qubits.

[0088] At 202, a quantum program is received. It is to be appreciated that the term “received,” as used herein, shall include receiving the quantum program remotely from another entity (e.g., as may be transmitted over the internet or some other network communicated) and also receiving the quantum program locally from a user interface element (e.g., as may be provided by a development environment or file system user interface). In some instances, the quantum program may be obtained in another manner. In some implementations, a quantum program can be represented, for example, as a quantum Hamiltonian, a sequence of quantum logic gates, a set of quantum machine instructions, or otherwise. The quantum program may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations. In some instances, a quantum program includes a sequence of quantum logic operations, e.g., single-qubit quantum logic gates, two-qubit quantum logic gates, multi-qubit quantum logic gates, identity gates, and other quantum logic gates. In some instances, the quantum program can be an Quil program generated by a user device (e.g., the user device 110 as shown in FIG.1), another computer resource outside the local environment of the quantum computer system 103, or in another manner; and received by a quantum computing system (e.g., the control system 105 of the quantum computing system 103 in FIG.1).

[0089] In some instances, the quantum program may include an initial quantum logic circuit, ^, which implements a unitary operator, ^, acting on ^^^^^^algorithmic qubits. That is, |output: = ^′^, ^′!, ⋯ , ^′#$%&'()!〉 = ^|input: = ^^, ^!, ⋯ , ^#$%&'()!〉(1)

[0090] In some nested hierarchy of layers of subcircuits representing different decompositions of theAttorney Docket No.: RIGET-125WO1 initial quantum logic circuit. For example, the initial quantum logic circuit may include a Quantum Fourier Transfer (QFT) gate, acting on ^ − 1 qubits. In some instances, a QFT gate can be defined as other gates, acting on subsets of the ^ − 1 qubits.

[0091] In some instances, during operation 202, a known and fixed description of the logical and hardware architecture can be also received by the computing system. For example, the description of the logical and hardware architecture may be denoted by a set of system architecture configuration parameters, { / 0^12^}. In some instances, the configuration parameters may include one or more of the following parameters: physical error rate, cycle times, and the desired total failure rate budget for a quantum error correction process. In some instances, the user may select a set of pre-configured parameters and their values. In some instances, the user can customize the values and add new parameters (e.g., via a YAML file). In some instances, the configuration parametersmay include values for the parameters. For example, physical error rate, all quantum ops4=0.001; characteristic cycle time, intra quantum ops t=200 ns; Characteristic TN decodingtime 56^^^6^^7=1 ms; number of inter-modular pipes connecting fridge pairs ^^^^^^)^^^^^=1; and failure rate budget, full algorithm 4897^):8^9=5%. In some instances, other information may be received by the quantum computing system.

[0092] In some implementations, the user inputs a widgetized logical algorithm converted from a cirq circuit. The user also can input a unified system architectural configuration, {config}, containing important parameters such as the total failure rate budget, p897^):8^9, and p9^7^^99-to-p^>?^^^89scaling coefficients. In some instances, if no widgetization (e.g., decomposition and segmentation operations 204, 206) is desired standard OpenQASM 2.0 circuit input can be used.

[0093] At 204, the received quantum program is decomposed. In some implementations, one or more classical processors of the quantum computing system (e.g., the classical processors 111 of the servers 108, or the control system 105 of the quantum computing system 103 shown in FIG.1) can be operated to decompose the sequence of quantum logic operations of the quantum program into one or more equivalent intermediate sequences of quantum logic sub-operations. In some implementations, theAttorney Docket No.: RIGET-125WO1 intermediate sequence of quantum logic sub-operations can be further decomposed into a sequence of quantum logic gates equivalent to the sequence of quantum logic operations in the initial quantum program. The sequence of quantum logic operations can be decomposed into a sequence of quantum logic gates, which only includes simple single- or two-qubit quantum logic gates that are compatible with and can be processed by a compiler in a later operation. For example, the decomposed quantum logic circuit may include one or more of the following: single-qubit Clifford gates, H gates, XY gates, two- qubit Clifford gates, CNOT gates, CZ gates, RX gates, RY gates, arbitrary rotation gates, and CU gates. In some instances, the decomposition of the quantum program may be performed by executing operations 304 in the example process 300 shown in FIG.3 or in another manner. In some instances, the sequence of quantum logic gates may include quantum logical gates that are not compatible with the compiler. In this case, additional processes can be performed, e.g., transpilation. In some cases, a 3-qubit logical operation (e.g. Toffoli) can be enacted and then the decomposition could stop there. The key is that decomposition stops with leaf nodes in the tree that are physically realizable by the fault-tolerant control plan of the fault-tolerant quantum computer. In some instances, a quantum circuit widget may include Toffoli (CCNOT) gates.

[0094] At 206, the decomposed quantum logic circuit ^ is segmented into multiple quantum circuit widgets ^@^67^^^. In some implementations, each quantum circuit widget represents a time slice of the quantum program, including quantum logic gates that are executed during a time period. Each quantum circuit widget includes a subcircuit of ^^^^^^- width, a portion of the decomposed quantum logic circuit, with a user-defined limit (e.g., a maximum allowed logical circuit depth of ^^8A). In some implementations, the segmentation process of a quantum program is performed by executing operations in the example process 300 in FIG.3 according to a tree structure (e.g., the tree structure 400 shown in FIG.4). After segmentation of the decomposed quantum logic circuit, there are no entangling gates connecting immediately neighboring quantum circuit widgets; and the quantum program can be represented by an equivalent sequence of quantum circuit widgets, e.g., ^ = [^^, … , ^#D$EFG(H)!] whereAttorney Docket No.: RIGET-125WO1 ^JstateJ= stateJN!for 2 ∈ {0, ⋯ , ^@^67^^^− 2}(2)where state^is the input state, and state#D$EFG(H)!is the output state of the complete quantum logic circuit representing the quantum program. In some implementations, the systems and techniques presented here can avoid the memory overheads associated with decomposing the complete circuit to elementary operations.

[0095] After the generation of the sequence of multiple quantum circuit widgets, an approximate version of ^^^^(e.g., a set of key characteristic parameters output by the compiler) can be constructed. In some instances, the set of parameters includes a total number of logical qubits, a level of error correction (^) for each logical qubit, an algorithmic error tolerance (how likely the algorithm is to complete successfully with one circuit execution), etc. In some instances, this set of parameters is sufficient to correctly and efficiently allow the execution or resource estimation based on the original quantum program. A widgetization-based set ^S^^^below can be used as a good approximation of ^^^^for resource estimation purposes, ^S^^^ : =(3) {^, T, ^^U^^^ , ^V^^W^^ , ^XY9^7^^89 , ^S^Y^^^ , ^S^Y^^^^^^ , ^S^Y^8^ }≈ ^^^^ .

[0096] In this widgetization-based estimation procedure, estimation primitives for each quantum circuit widget can be obtained based on its graph state representation and then define the full circuit resources estimates as, ^XY ^9^7^^89 : = m^a^x (^ ^9^7^^89 ) ≈ ^Y9^7^^89 ,(4) where ^J is the graph- highlights the critical assumptions made while generating all the resource estimates. The individual graphs and scheduling lists can be stitched together to approximate the complete Y, ^^Y^^^, ^^Y^^^^^^, and ^^Y^8^. Note that while stitching of the quantum circuitAttorney Docket No.: RIGET-125WO1 widgets (e.g., the interleaved execution of quantum circuit widgets on distinct quantum processor modules as shown in FIGS.7-10) would be required to execute the quantum program on an FTQC system, it is not necessary for resource estimation purposes. The computational requirements needed for obtaining resource estimates can thus be reduced by calculating the “widgetized" quantities above by operation of a software on the one or more classical processors.

[0097] In some instances, the received QASM strings can be parsed, for example, translating the QASM strings to a computer representation by operation of a control system of the quantum computing system to extract the quantum logic gates and their attributes such as angles, qubit indices, etc.; counting initial T and non-Clifford angle rotation gates in the received quantum program as required for later steps; and identifying any unitary not supported by downstream compilers in the input and determining whether a transpilation is needed. In response to an identification of a non-supported quantum logic gates and a necessary transpilation operation, the quantum circuit widgets can be transpiled according to the fault-tolerant compiler used later for executing a compilation process. To prepare for the compilation during operation 208, each quantum circuit widget can be processed to only contain logical Clifford+^+ef(g) using exact gate equivalences, where g’s are non- Clifford angles. In some instnaces, when single qubit logical measurements are performed, for example, at the end during the consumption stage, each ef(g) node needs to be decomposed into a chain of Clifford+^ itself through gate syntheses. In some instances, the transpilation to the logical Clifford+^+^h+ef(g) is also performed. Performing gate synthesis including decomposing a non-Clifford rotation gate, e.g., ef(g), to a sequence of Clifford+^+^hfor the quantum computing system to execute consumption measurements, at the end allows generating, caching, and reusing subgraphs {^^, … , ^#D$EFG(H)!} independent from logical and hardware-level configurations, {config}. In someimplementations, the quantum computing system cannot directly consume and processe (g) gates and nee hf d those to be decomposed to a chain of Clifford+^+^ gates.

[0098] In some instances, the initial quantum logic circuit can be expressed solely in terms of logical Clifford gates, ^, ^hgates, and non-Clifford arbitrary-angle rotation eigates, e.g., ^{Clifford, ^, ^h, efIn some instances, a "non-Clifford angle" g refers to aAttorney Docket No.: RIGET-125WO1 rotation or phase that does not belong to the Clifford group, a set of quantum gates essential for basic quantum computations and stabilizer codes. The Clifford group consists of operations like the Pauli-X, Y, Z, Hadamard, and S (π / 2 phase) gates, as well as the CNOT gate. In some instances, the Clifford group is configured to perform specific operations that preserve the stabilizer states and are efficient to simulate classically. A π / 8 or T-gate corresponds to a rotation of π / 4 around the Z-axis. Non-Clifford angles are also crucial in fault-tolerant quantum computing, often requiring special handling such as magic state distillation to implement them accurately in error-corrected quantum systems. In some instances, the non-Clifford angle g may have a value in a range equal to or less than π / 4.

[0099] In some instances, when the fault-tolerant compiler is another type of compiler,the transpilation may result in quantum logic gates of another type. The number of logical^ and ^h gates, excluding those implicitly residing in the non-Clifford arbitrary angleas ^^U^^^. ^V^^W^^denote the number of non-Clifford arbitrary angle efgates in ^ including the ones that resided implicitly in pre-transpilation logical gates. FT execution of the quantum program ^ is assumed to use rotated surface code patches with distance ^. In some instances, the decomposition of non-Clifford arbitrary-angle rotation ei gates can be performed after compilation in the consumption stage of the graph state, a process sometimes referred to as gate synthesis. The diamond norm precision for gate syntheses is denoted by T.

[0100] At 208, the quantum circuit widgets are compiled. In some instances, the quantum circuit widgets are compiled by operation of a fault-tolerant compilation process, e.g., a graph state compilation by operation of a graph state compiler of a classical processor. In some implementations, a quantum graph state is a quantum state which can be described by a graph. Specifically, given a set of vertices and edges, a graph state is created in a quantum computing system by mapping one qubit to each vertex, and performing control-Z (CZ) operation between qubits whenever their respective vertices have an edge between them. This puts the qubits into a “graph state.” Using this graph state one can carry out circuit operations by scheduling measurements on specific qubits in a specific order. By compiling a quantum circuit widget into a graph state and measurement schedules, one can carry out the computation prescribed by the quantum circuit widget byAttorney Docket No.: RIGET-125WO1 using a reduced number of physical resources since the graph structure provides a natural way to “split” a computation into subgraphs to be carried out on separate quantum processor modules or separate quantum processing units; and at any moment in time, only a portion of the graph needs to be executed on the quantum computing system. This allows one to continually create and consume (e.g., perform measurements) portions of the graph “on the fly”, minimizing the number of logical and physical qubits required.

[0101] During operation 208, the graph state compilation is performed by operation of a fault-tolerant compiler which can be used to convert each subcircuit {^J} of a respective quantum circuit widget containing compatible quantum logic gates into an equivalent graph state representation. In some implementations, a graph state representation is equivalent to a corresponding subcircuit of a quantum circuit widget. The graph state representation includes a set of quantities (graph states {^}), schedules includingpreparation schedules, consumption schedules, and measurement schedules {^^^^^^ },{^^^^^^^^^ }, and {^^^^8^ }, and other quantities. In some instances, a graph state compiler maybased “Jabalizer” FT-compiler or another type of compiler for performing a measurement-based quantum computing (MBQC). The stabilizer-tableau- based Jabalizer FT-compiler is described in publications such as Vijayan et al, “Compilation of algorithm-specific graph states for quantum circuits, Quantum Science and Technology 9, 025005 (2024);” Paler et al., “Fault tolerant, high-level quantum circuits: form, compilation and description, Quantum Science and Technology 2, 025003 (2017).” In someimplementations, Jabalizer v0.5.2 is invoked to compile the transpiled subcircuits into{^, {^mno}, {^^^^^^^^^ }, {^^:^8^^^ }, {^^^^8^ }}. In some implementations, the MBQC-formattedcircuit is extracted from the corresponding subgraph, Pauli corrections, and the consumption schedule. In some instances, the MBQC-formatted circuit can map the larger space of all graph qubits to the smaller space of |stateJ^^stateJ| (e.g., equivalent to the execution of ^J∈ [^^, … , ^#D$EFG(H)!]).In some implementations, the MBQC-formatted circuit contains logical r, Phase and st gates, as well as mid-circuit measurements.

[0102] Based on a subcircuit ^Jof a quantum circuit widget, containing only compatible quantum logic gates, for example Clifford gates, ^ gates, or ef(g) gates for a graph stateAttorney Docket No.: RIGET-125WO1 compiler, the graph-state compiler (e.g., Jabalizer) during operation 208 can generate a graph state representation containing the following set of quantities, hu8v89^w^^(5) ^J({Clifford, ^, ^ , ef^(g)}) x¾^^¾¾¾¾z^^ ^ ^^^ ^^^where ^^^is a setat the end of each consumption step during the execution of eachquantum circuit widget, for example, after performing the scheduled initializations and consumption measurements on selected logical qubits . ^^^^^ ^^^^^and ^^^^^^^denotes the set (or map) of output and input nodes (e.g., logical qubits on a quantum processor module configured to receive input quantum states and output quantum states) in the graph state, respectively. In some implementations, the number of intermediate input and output nodes are the same. ^^9^^7^^89is the quantum memory needed to process the quantum circuit module ^J. ^^^^^^^^^^is the graph consumption schedule to perform individual logical qubitis the list identifying which rotational basis are used for consumption-stage measurement. Finally, ℰu8v89^w^^o|}nis the MBQC-formatted circuit extracted from the previous outputs, which effectively maps the current portion of the logical algorithm to the output qubits. For the quantum circuit widget in step 2, this correspondence can be written as ℰu8v89^w^^o|}n,^|stateJ, 00 … 0^ = |stateJN!, 00 … 0^.

[0103] The operation 208 is^@^67^^^, providing the user with the information required for the approximate estimation set, excluding the preparation schedules, {^^^^^^}.

[0104] In some implementations, Pauli Tracker v0.4.1 described in J. Ruh and Pauli tracker, https: / / github.com / taeruh / pauli_tracker.git (2024) and MBQC Scheduling v0.1.0 described in J. Ruh, Mbqc scheduling, https: / / pypi.org / project / mbqc-scheduling / (2024) are invoked to process Jabalizer’s outputs to Pauli corrections, consumption schedule, and other required sets. Each graph object and Pauli frame information are reusable and cached as a .json file. Even if the architecture was altered, this portable graph object couldAttorney Docket No.: RIGET-125WO1 estimate resources for the algorithm, ^, without requiring further graph state processing. The default configurations for Pauli Tracker and MBQC Scheduling for all reported results, which includes generating the trivial "time-optimal" consumption sub-schedules and initializing all circuits in 00 … 0.

[0105] In some implementations, a preparation schedule for the respective subcircuits is generated. A preparation schedule can create the schedule of stabilizer measurements needed to prepare the input graph state. This encodes some aspects of the quantum circuit widget that are not input-state-dependent. In some instances, the preparation schedule needs to be compatible with the bi-linear bus; each stabilizer measurement occupies a contiguous portion of the quantum bus, e.g., if the first and last logical qubits on the quantum bus are involved, the whole bus needs to be involved. The preparation schedule tries to allocate the logical qubits used by the quantum circuit widget in such a way so as to reduce / optimize the time to run all of the stabilizer measurements.

[0106] In some instances, a Substrate Scheduler, an open-source tool, can be used to generate the graph preparation schedule, {^^^^^^}, based on the fixed architecture of bi- linear quantum bus and the graph states {^}. In some instances, other tools to map the graph states {^}, calculated by the fault-tolerant compiler, to the set of graph initialization schedules {^^^^^^} can be used. In some instances, these preparation schedules can be optimized for the quantum bus in the superconducting hardware layout, for example to maximize or otherwise increase the parallelism between the stabilizer measurement so as to reduce the total preparation time. The Substrate Scheduler v0.2.0 described in S. Liu, et. al., Substrate scheduler, graph-state-generation, https: / / github.com / sfc-aqua / gosc-graph- state-generation, 2023 is used to produce a preparation schedule of stabilizer measurements to initialize each (sub)graph states.

[0107] In some implementations, the modular quantum processing unit includes two or more quantum processor modules. Each quantum processor module includes a dual-rail quantum bus containing linear arrangements of surface code data logical qubits to storethe subgraphs and ancilla logical qubits. The dual-rail quantum bus is of fixed size^X : = max ( ^^9^7^^89 ^^ ^9^7^^89 ) per rail to validate an assumption that there are no memoryAttorney Docket No.: RIGET-125WO1 constraints for executing preparation and consumption stages back-to-back. The quantum bus is laid out in comb-like patterns in the cryogenic modules, facilitating the measurements. The Substrate Scheduler currently finds an optimum schedule based on an input of individual ^ mapping to this layout. The operation of the scheduler can be improved by including additional information on node types (e.g., input nodes: quantum logic qubits configured to receive quantum states from other quantum processor modules, output nodes: quantum logic qubits configured to output quantum states to other quantum processor modules, and intermediate nodes: quantum logic qubits configured to perform scheduled T and Rz measurements) and adding support for customized bus architectures.

[0108] Parts of the graph-state that need to be present at a particular time slice of the quantum program (e.g., in a quantum circuit widget) can be specified by using three schedules, including a schedule for graph-state preparation (^S^Y^^^), a schedule for graph- state consumption (^S^Y^^^^^^), and a related schedule identifying measurement bases to be used for the consumption stage (^S^Y^8^). In some instances, the three schedules can efficiently approximate the sets ^^Y^^^, ^^Y^^^^^^, and ^^Y^8^, which belong to the entire Y when no time-sliced segmentation of the initial quantum program is performed.

[0109] ^S^Y^^^and ^S^Y^^^^^^can be written as nested sets, where sub-schedules list the set of nodes required to be measured at each step. The following is a hypothetical example of a preparation schedule for a three-step decomposition of ^ with an entire graph of 56 logical qubits (e.g., nodes): ^SY^^^^ = [(6) [[(10, (9,10))], [(1, (1,51)), (23, (3,23))], [(20, (19,34))]],[[(24, (1,24))]],[[(30, (7,31))], [(12, (12,25))], [(35, (2,55))]]].

[0110] Here, to create the subgraph for the first quantum circuit widget at the first time step, the fault-tolerant quantum computing requires three sub-steps, and so on. The different elements of any sub-step can be performed simultaneously and are permutable. Each sub-sub-element is a tuple of the form (2^, (2^^^^, 2^^8A)) identifying patch labels for multi-Pauli product operator measurements containing first an ^ stabilizer and a pair ofAttorney Docket No.: RIGET-125WO1 minimum to maximum positions of t stabilizers. As another example, a related three-step consumption schedule may look like ^SY^^^^^^^ = [(7) [[18,6,3], [27,13,14,17,23,22], [20,1]],[[0,10,6], [24,35,16], [38,25,37,51], [40,26]],[[0,14,8], [11,13,55,10]]].where at the first time step, the algorithm requires a measurement of [18,6,3], then[27,13,14,17,23,22], and lastly [20,1] before moving to the set of operations needed,similarly, for the second time step and so on. There are no repeated nodes in the sub- schedules at each time step. For any given time step, the nodes inside the sub-sublists canbe measured simultaneously and are permutable. Here, the largest sub-schedule in^SY^^^^^^^ (at the second time step) determines the maximum quantum memory needed forthe FTQC to perform any sub-step unrestricted. Finally, ^S^^^8^is a nested list identifying which rotational basis (^ or effor non-Clifford arbitrary angles) may be used for single- qubit logical measurements of each node in the sub-step of ^S^Y^^^^^^to consume the graph using distilled resources. Considering graph consumption, this provides a natural separation between two distinct node types: nodes requiring ^ states and the ones requiring ef-basis measurements.

[0111] Note that the number of nodes in the graph produced from the graph state compilation process comprising the graph, ^, is typically much larger than the number of input logical qubits; that is, ^ ≫ ^^^^^^. This is because ancilla logical qubits are always added for an MBQC realization of a given quantum program. However, due to the scheduling mentioned above, only a relatively small subset of logical qubits representing each node is required at any step to execute the quantum program ^. The maximum number of logical qubits required in any time step is denoted ^XY9^7^^89. This is also referred to as the maximum quantum memory. Typically, ^Y9^7^^89< ^. The number of nodes in the graph is never less than the total number of algorithmic input qubits. Using the MBQC framework at the logical level simplifies the Clifford and non-Clifford compilation of the circuit.Attorney Docket No.: RIGET-125WO1

[0112] One should also be aware that distinct graph states with similar attributes can be constructed from different input states and the same ^; however, for resource estimation purposes, the graph state constructed from 00 ⋯ 0 may be considered. Arbitrary inputs to algorithmically specific graphs can be generated by first compiling the graph assuming an all-zero input and then attaching appropriate ancilla logical qubits to perform teleportation into the particular input nodes of one graph from the output nodes of another.

[0113] In some instances, resource estimations can be performed according to a set of resource estimation primitives for the non-widgetized single-timestep input algorithm, ^^^^ (^, {config}): = (8)^U VW Y Y Y Y^^^^ ^^^^^ ^^^^^ ^^^^^^^^where the userof primitives used for resource estimation shown on the right-hand side. It is inefficient to directly compile a utility-scale ^ with tens of millions of gates and considerable circuit depth for resource estimation or hardware execution; it becomes highly challenging to construct ^^^^exactly for such enormous utility-scale circuits. In certain examples, the resource estimation set, ^^^^, can be constructed approximately and verified robustly.

[0114] At 210, the quantum program is executed based on the executing of the set of compiled quantum circuit widgets. In some implementations, the compiled quantum circuit widgets are executed on at least two distinct quantum processor modules in an interleaved manner. In some implementations, executing a compiled quantum circuit widget includes an execution of a preparation schedule to prepare a graph state a consumption schedule to obtain an output quantum state based on the prepared graph state. In some instances, the execution of a compiled quantum circuit widget may be implemented as the operation shown in FIGS.8, 10, 18 or in another manner. In some instances, the execution of a compiled quantum circuit widget may include other operations.

[0115] In some instances, executing a preparation schedule includes performing quantum logical operations to construct a graph state. including performing measurements such as Pauli measurement, stabilizer measurement, etc. In some instances, executing a preparation schedule may not involve T-states.Attorney Docket No.: RIGET-125WO1

[0116] In some instances, executing a consumption schedule includes preparing T- states (e.g., generation and distillation of T-states, transferring T-states and performing measurement on nodes where measurements are scheduled. In some instances, T-states prepared can be teleported within the same quantum processor module or via inter- module connections from a distinct quantum processor module which can be dedicated as T-state distillation factories. In some instances, executing a consumption schedule includes performing a consumption measurement, e.g., π / 2 rotation measurements, T measurements, or other types of measurements involving T states.

[0117] In some instances, the space-time volume requirements for graph state processing parts can be formulated based on {config}, ^S^^^, and an architecture with spatially optimal size of the quantum bus and time-optimal compilation strategies (given the spatial configurations) creating a “middle-of-the-way" design.

[0118] In some instances, the modular quantum processing unit is a superconducting quantum processing unit that has a low syndrome extraction cycle and can benefit from minimizing physical footprint and interleaving graph preparation and consumption operations as described in the example processes 800, 1000 shown in FIGS.8 and 10. In some implementations, each quantum processor module includes a square grid of logical qubits (e.g., patches). The edge size is set to ^^^67^= ⌊^(&^^H^^^)⌋, and every (rotated surface code) patch contains 2^^physical qubits. ^^>?^isof physical qubits available to each quantum processor module. In some implementations, physical qubits and logical qubits in a quantum processor module may be allocated for performing respective functions; and some physical qubits or logical qubits may be unallocated. In some instances, the unallocated physical qubits or logical qubits may be used for other ancillary operations. In some implementations, a quantum processor module includes a first set of logical qubits configured as a bi-linear quantum bus which includes a rail of ancilla logical qubits and a distinct rail of data logical qubits. Each rail of logical qubits includes ^X9^7^^89surface code patches or logical qubits. This is laid out in a comb or snake- like pattern to fill in a full-edge side of the quantum processor module. The quantum processor module includes a second distinct set of logical qubits configured as a linear ^-Attorney Docket No.: RIGET-125WO1 transfer bus, and a third set of logical qubits configured as ^-distilleries, also known as ^- state factories. Upon allocating the quantum bus, the ^-transfer bus sandwiches as many ^- state factories as possible on the remaining unfilled part of the module and is laid out in a comb-like pattern again – two columns or more from the ^-transfer bus may be communicably connected to the second rail of the ancilla logical qubits. In some implementations, the ^ transfer bus actively stores magic states from the T-state distillation factories and queues them during all sub-schedules. In some instances, the ^- transfer-bus is configured to service at least ^6^^^^99^^^^^logical qubits of the quantum bus in parallel with T states during the subgraph consumptions (there are at most ^X9^7^^89at any given time). An equal number of logical qubits configured for T-state distillation factories (^6^^^^99^^^^^) per module may exist. In some implementations, quantum processor modules in the modular quantum processing unit may have an architecture that contains a ladder- style structure with ^^^^^^6)^9^9^7^of quantum processor modules, e.g., the example modular quantum processing unit 900 as shown in FIG.9.

[0119] In some implementations, a quantum processor module includes T-state distillation factories or distilleries which include a subset of logical qubits configured to perform ^-state generation and distillation. In some instances, the type of distilleries can be selected from an extended list of T-state distillation factories derived from a method proposed in D. Litinski, “Magic State Distillation: Not as Costly as You Think”, Quantum 3, 205 (2019) (incorporated by reference herein) or in another manner. Furthermore, a superconducting homogeneous physical error rate of 4 = 10)^is assumed for all quantum operations or, at least, for the dominant error rates – whether from measurements, single, or two-qubit quantum logical gates applied on physical qubits. In some instances, a T-state distillation factory lookup table to determine configurations of quantum logical qubits is shown in FIG.26, which can be recursively used to locate a suitable T-state distillation factory type. In some instances, a widget lookup table may be part of {config} that the user provides. In some instances, a T-state distillation factory includes logical qubit configuration, physical resources, and other information.

[0120] In some instances, the output probability, 4^^^, sets the error rate for the ancillary state and bounds the error rate on any ^-gate implemented using the ancillaAttorney Docket No.: RIGET-125WO1 logical qubits. The number of logical qubits, 2D patch dimensions, and physical cycle sweeps depend on the T-state distillation factories construction. The T-state distillation factory configured for performing the magic state generation and distillation ignoring any entries for sst in the original table can be selected. The number of distilleries (T-state distillation factories) per module is defined as (9)^^ ^^^^ − 1¦^^^^ ^^^^ ^^ = ^ ¥ ^^≥ 1,

[0121] In somedirectly as shown in the example quantum processor module in FIG.13. In certain instances, the T-state distillation factories can service the quantum bus through a T transfer bus as shown in the example quantum processor module in FIG.14. This T-transfer bus can guarantee the same number of parallel T-states that are available for performing measurements at any given time. The number of distillation columns (e.g., a set of T-state distillation factories for generating and distilling magical states) in a quantum processormodule can be defined as ^^^9 ^= ⌊ GEFG)^¨©'H)! #X⌋ a «¯F$°±«6^^^^99 ª«G%F( nd ^­v^^ = ⌈ ² c^ ⌉ ≥ 3. Moreover,^ ^ GEFG  and  @^6^>

[0122] In some instances, resource estimation can be performed based on the received quantum program and hardware architecture.

[0123] In some instances, the space-time volume of the complete graph creation on the bi-linear quantum bus before each single qubit logical measurement can be defined as, µY= 2^X9^7^^89¶^^^^^,(10)where ¶^^^^(^S^^^^) = ∑^^v∈ S¸&¹G&  ^^v is the sum of the sub-schedule lengths,  ^^v, for set^S^^^^. In other words,  ^^v is the number of distinct measurement steps for the graphpreparation.

[0124] Resource cost for the gate synthesis decomposition to Clifford+^ executed at each graph node’s single-qubit measurement step, consuming the distillation factories’ output resources through the buses and at the end of subgraph processing. In someAttorney Docket No.: RIGET-125WO1 instances, graph nodes (e.g., the data logical qubits of the quantum bus) are either of the type requiring arbitrary e^-basis measurements or a single ^-basis one. Measurements that require t-axis rotations are decomposed into ^-gate sequences of a fixed worst-case length of  º= ⌈ / ^log(1 / T) + / !⌉ as instructed by the gate synthesis method. T is known as the diamond-norm error for decompositions to quantum logic gates selected from a group consisting of Clifford gates and ^ gates.

[0125] For each distilled ^-state, s cycles are needed to prepare the state, and one tock (^ cycles) is required to interact the prepared state with the graph node and measure it in the ^ or t-basis. In some instances, the time cost of all operations requiring ½(1) cycles (e.g. shuffling some surface code patches) can be ignored, assuming that they can be performed at the same time sub-steps for free. Hence, for each node measurement, assuming an ef-basis measurement, the space-time volume increases as 2^X9^7^^89¶^^^^^ → 2^X9^7^^89¶^^^^^ + (11)

[0126] In (^^67^ − ^­v^^ − ^^^96^^^^99 ¿À«G%F(^√^^ Á)^^67^ + ^^^96^^^^99 ¿À«G%F(^√^^ Á. In equation (11), the second termscomebus consumption and logical qubits used as the T-state distillation factories occur over a space of 2^X9^7^^89+  ^^8^^:^^)v^^. Hence, for all nodes of both types ^ and efthat need to be measured sequentially, the space-time volume can be defined as µ^^­^^^^^89= 2^X(12) ^^^89 9^7^^89¶^^^^^ +

[0127] Thestage as described in the operation 210 of the example process 200 shown in FIG.2 can be efined as ^ = ^#Â^#ÃWd^^­ $%$( $%$(¤; note only distinct ^ and e nodes canconsumed in parallel. =$%$(#E$H($««G¹$GH¤ can be defined as the number sequential ^ states required forand injection operations (whether theyAttorney Docket No.: RIGET-125WO1 happen over the graph preparation or graph consumption stages). ^6^^^^99^^^^^is the numberof T-state distillation factories on the quantum processor module allowing a generation of^6^^^^99^^^^^ simultaneous magic states. The total number of required T states, regardless ofparallelization considered above, can be written as ^^U^^= ^V^^W^^ º+ ^^U^^^, which is used for determining the total number oy f ^ gates, ^- much largerthan ^Y. Finally, when T-state distillation e.g., table 2500 in FIG. 25 are chosen to have a second (20-to-4) layer (the second and third T-state distillation factories), ^6^^^^99^^^^^should be replaced by 4^6^^^^99^^^^^in all space-time equations as the T- state distillation factories can now produce four outputs simultaneously.

[0128] In some instances, a single cycle time of the surface code has a failure probability governed by the following physical-to-logical rates scaling: (^N!) / ^4Å = Æ Ç4È ,(13)where the coefficients, Æ andMatching (MWPM) decoder simulations and device modeling. In particular, decoder simulations provide logical and physical probabilities. Consequently, a single unit cell containing ^ cycles fail with probability 49^7)^^99 = 1 − (1 − 4Å)^,(14)and failure rate of a total volume^^^894897^):8^9 > 1 − (1 − 49^7)^^99)ÊHG¨'G%($±«(¯(±«,(15)where 4897^):8^9represents the total algorithm failure rate / budget for the execution of thefull circuit, ^, and includes the entire space-time volume, which can be received as part of{ / 0^12^}. Assuming that 4 ^Å ≪ 1 then (1 − 4Å) ≈ 1 − 4Å^, and thus 49^7)^^99 ≈ 4Å^ and,4897^) ≳ 1 − (1 − 4Å^)ÊHG¨'G%($±«(¯(±«.(16)

[0129] Subtracting each side logÍ1 − 4897^):8^9Î ≲ µ^^­^^^^^89log(1 − 4Å^) ≲ −µ^^­^^^^^894Å^.(17)Attorney Docket No.: RIGET-125WO1

[0130] In some implementations, the required precision and code distance are determined iteratively: Given 4897^):8^9, the graph, and the schedules, loop through a T-state distillation factory lookup table (e.g., the table 2500 shown in FIG.25), iteratively find T, ^, the most optimum widget that satisfies T < 49^7)^^99and 4^^^< 49^7)^^99. T sets the length of the Clifford+^ chain,  º, for arbitrary angle transformations required at the measurement points in the end.

[0131] If µ^^­^^^^^89^^^89from equation (12) is inserted, the main logarithmic inequality to be solved can as4(^ N!) / ^(18) Æ^ Ç4 È (2^X9^7^^89¶^^^^^ +^>^^^>(2^X +   )(^^^­ ^ ^^­9^7^^89 ^^8^^:^^)v^^ ^^^^^^^ + ^6^^^^99 s)) < −Ð!where Ð!= log(1 − 4897^):8^9). The minimum code distance required is the smallest ^- that satisfies equation (18). The only free variables above are the distillation widget’s cycle time s, and T. Note ¶^^^^and ^X9^7^^89were previously extracted from the Jabalizer and Substrate Scheduler.

[0132] In some instances, to determine s and T, nested loops can be performed to iterate through the sequence of quantum circuit widgets and then gate synthesis’ T. Theinner loop feeds back into the Clifford+^ decomposition as the failure rate of a unit cell,49^7)^^99, sets the approximation error as T < 49^7)^^99. By choosing a particular T-factory, scan be fixed, which also fixes the output error rate of the distilled state, 4^^^.

[0133] In a compiled quantum circuit widget, the implemented ^-gates may have precisely the same error rate as any other gates in the compiled quantum circuit widget. A Pauli initialization or measurement takes a single unit cell in the space-time volume. Hence, its failure rate is governed by equation (14). This error rate must be dominant. Consequently, the error output, 4^^^, from the T-state distillation factory should be less than the failure rate of this cell. In some instances, the distillation output is at least as good as a unit cell in the space-time volume. Hence, the smallest value of s can be selected from the table 2500 shown in FIG.25 and solve equation (16) for ^. Then, with a physical error rate of 4 = 10)^and the solution for ^, whetherAttorney Docket No.: RIGET-125WO1 49^7)^^99 = 1 − (1 − 4Å)^> 4^^^(19)is satisfied for theperforming T-state distillation factory can be selected in the outer loop. The next entry in the T-state distillation factory lookup table (e.g., the table 2500 shown in FIG.25) can be considered; and the process can be repeated until a T-state distillation factory that performs at least as well as the failure of a logical qubit is located.

[0134] In some implementations, space complexity is identified. For example, the total physical qubit number that hardware would require can be identified. In some implementations, the total physical qubit number scales with ^9^7^^89, the number of required logical qubits provided by Pauli Tracker outputs. Once a particular T-state distillation factory is selected, as per the above, the total number of required physical qubits over all quantum processor modules at any given time and total intra-modular runtime (including the initial subgraph preparation time at the first time step, all consumption operations, and delays) can be calculated respectively as, ^^^Ñ)Ò^ÓÔ^= 4^X^^^J¦Ó^^^+ ^ÒÕ^^^^)^^^^^^^Í^^J^^J^^^^J^^Ö + 2^^ ^^Ó#^×^^)Ø^^Î, (20) where ^unit shown in FIG.9, thus 2^^^^^^6)^9^9^7^quantum processor modules in total.5 is the characteristic gate time, which sets the architecture’s quantum tock of all intra-modular operations. The factor-8 comes from the fact that in the physical architecture, every surface code sweep for syndrome extraction circuits requires one initialization, two Hadamard gates, four entangling gates, and one measurement, all assumed to take a duration of 5. The temporal cost of initializing the first subgraph ^^ with ^^^^^ (^^^^^^ ) is always nonzero and can be explicitly added. In some instances, theremaining graph preparations and ^-state distillation operations on one quantum processor module can be performed in parallel with consumption operations on a distinct quantum processor module. There might exist overall delays accumulated over all time as 56^98?= 56^^^^99)6^98?and 56^98?= 5^^^^)6^98?.Attorney Docket No.: RIGET-125WO1

[0135] To execute every consumption sub-schedule 2 of a compiled quantum circuit widget, a certain number of distilled magic states should be stored in a T-state reservoir (e.g., the ^-transfer bus) on the same leg of the macro-architecture. In some instances, adelay can be added if more magic states are required than those already accumulated in the^-state reservoir (e.g., T-transfer bus) during the previous preparation step 2 − 1. Thenumber of ^ states per quantum processor module at the end of a preparation step is ^^^^^6^^^ 5(21) ^U)^^^)^^6^9^= ^99^^^^^ JJ max(⌊85s ⌋,  ^8^^:^^)v^^)for 2 ∈ {0, … , ^@^67^^^ − 1}.

[0136] As shown above, the hybrid (intra- and inter-modular) time to prepare thesubgraph for the preparation step 2 can be defined as 5^^^^ ^^^^8)^^^^^J = 8^(^J 5 +^J#^^^)Õ^^^^^J 5J#^^^)Here, ^^^^^8)^^^^^J =^,Ú for ^^^6^9^^^^^)9^7 > 1 isthe number of intra-module∑ܱÝÛ∈ &¹G& ⌊^^,Ú,Û / #X«¯F$°±«⌋operations, ^J#^^^)Õ^^^^^ ª∑&^¹G&Þ^,Ú ^^6^9^^#$%(G¹c&$&GHß for ^^^^)> 1 is the number inter-sub-schedule 2 of a corresponding compiledquantum circuit widget (only in the vertical direction of a ladder leg). In some instances,5^^^^^ ≫ 5 is the characteristic physical timescale for all inter-module communications.Furthermore, ^^8AJ,Ù,à is the maximum distance between any pairs of graph nodes in the tupleá of sub-list â of the preparation sub-schedule 2 and ^^^^^^)^^^^^ is the number of inter-modular connections (e.g., pipes) connecting every pair of quantum processor modules inthe macro-architecture. In some instances, the distillation delay for step 2 ∈{0, … , ^@^67^^^ − 2} can be defined as ^8A)^^­ U)^^^)^^6^9^^^^^^^^, − ^(22) ⌈J⌉,5^8A)^^­>U)^^^^^^^,JotherwiseAttorney Docket No.: RIGET-125WO1 where  ^8A)^^­^^^^^^^,J= ^J^8A)U+  º^^8A)VJéis the maximum sequential ^-length per-module 2; ^^8A)U U ^^8^J = max(^J,Ù ) for 2 ∈ ^J , â ∈…, ^^^)9^7 − ma of ^-type node existing in all quantumfor the measurement sub-schedule ^^^8^ ^8A)VéJ . Similarly, ^J =max for 2 ∈ ^^^8^, â ∈ {0 ^^6^9^^J,Ù J , … , ^^^^)9^7 − 1}.be added if the graph preparation operation on a first quantum processor module of the next subgraph 2 + 1 is not yet finished (which runs parallel across the interleaving quantum processor modules in the other leg of the ladder) by the time that the graph consumption operation on a second distinct quantum processor module during step 2 is completed. One can write down an upper bound to the individual time solely for the intra-modular consumption’s of step 2 as #Ü^±Ýc Ü^±ÝcÃW5^^^^^^^)^^^^8J = 85^(⌈#E$H($««G¹$GH⌉ +  º⌈ ##E$H($««G¹$GH⌉). Therefore, the preparation delay for step2∈ {0, …5^^^^− ^^^^^^^)^^^^8 6^^^^99)6^98?(23) ^^^^ JN! 5J − 5^ ,5 )6^98?if 5^^^^ ^^^^^^^)^^^^8 6^^^^99)6^98?JN!> 5J+ 5^

[0138] In somethe overall time required on the real FTQC to stitch the output logical qubits of the graph 2 at step 2, living across one leg of the ladder, to the input logical qubits of the graph 2 + 1 at step 2 + 1, living across the other leg of the ladder, for 2 ≠^@^67^^ − 1 can be accounted. In practice, this hand-over process can be performed byteleporting output quantum states (e.g., data-qubit Bell pairs) across the quantum processor modules in the horizontal direction, which involves the addition of logical CNOT / CZ gates, or for small-sized problems, some equivalent SWAP operations. Notice the graph nodes cannot be teleported vertically across the same leg for free through ½(1) operations. Therefore, an upper-bound for this quantity can be written as ^^^^^)^^6^9^)mî=85^ í(24)^^^^^⌈^^^^)^} ^^)D$EFG(Attorney Docket No.: RIGET-125WO1 where the overall number of inter-module communications required to hand over output nodes of graph 2 to 2 + 1 is ^J^^^^^)^^6^9^)mî=∑^X∈¸^ ^ñd ¯'(&'( ,ï̃∈ $¸%&'(^J^X,ï̃, and ^^JX,ï̃is the number of crossing 0X of graph 2to the input −

[0139] In sometime can be defined as 5>^^8^^Ó6^@8^^ = 5^^^^^^^889+ 5>^^8^^869^ì^^)^^^^^ + 56^^^^^8^96^)6^98? .(25)where 56^^^^^8^96^)6^98?for all QEC cycles. An algorithm for estimating 56^^^6^)6^98?^^^based on tensor network decoders can be found in FIG.26, in which an example algorithm based on the space-optimal-bus architecture of FIG.10.

[0140] The graph state processing naturally leads to an architecture where the hardware is divided into two sets of quantum processor modules; these are arranged on two legs of a ladder structure and handle the processing of these quantum circuit widgets in an interleaved fashion. In some implementations, execution of a compiled quantum program based on an interleaved execution of the compiled quantum circuit widgets through three major steps: 1) graph preparation, 2) graph handover: teleportation or “stitching” of output nodes (e.g., the quantum logic qubits on a first quantum processor module where output quantum states are obtained during a respective graph consumption) to input nodes (e.g., the quantum logic qubits on a second quantum processor module where output quantum states are received from the first quantum processor module) and 3) graph consumption. The T distillations are performed inside the quantum processor modules in both steps as required (filling in the T-state reservoir, e.g., dedicated T transfer buses), and the T states are applied to the measurements in the graph preparation and the graph consumption as shown in FIG.10.

[0141] In some implementations, the multiple quantum processor modules in the modular quantum processing unit include an equal number of magic state distillation factories to provide the required magical states (T-states). The quantum bus will be shared equally between all the modules on the same leg of the ladder at any time. Here, the fasterAttorney Docket No.: RIGET-125WO1 native connectivity of a lattice of superconducting qubits can be exploited within a quantum processor module, where reduced connectivity or slower interaction can be scheduled in the teleportation to connect output nodes from IO graph state widgets in one leg of the ladder to the other one.

[0142] In some implementations, stitching includes teleportation of output quantum states from one quantum processor module to another quantum processor module. In some instances, stitching also could include establishment of a correspondence between the output nodes of the first quantum processor module and the input nodes of the second quantum processor module. In some instances, the node correspondence can be obtained from the compiler where the compiled quantum circuit widgets are formed and assigned.

[0143] In some instances, portions of a single quantum circuit widget can be segmented and run only on distinct quantum processor modules in the same set with high connectivity and fast gate times. These quantum processor modules communicate with one another using a respective coherent link over at a reduced rate, with lower connectivity, only for graph preparation and handover.

[0144] In some implementations, the quantum program is broken into time-sliced quantum circuit widgets and interleaved across two or more quantum processor modules or two or more sets of quantum processor modules in time direction. A quantum processor module or a set of quantum processor modules can be configured to handle graph preparation and consumption, and generation and purification of magic states of a graph state representation of a quantum circuit widget. The two quantum circuit widgets are stitched together through teleportation of output nodes from a previous quantum circuit widget to input nodes of a following quantum circuit widget.

[0145] In some implementations, a modular quantum processing unit for performing a modular graph state processing includes multiple quantum processor modules including lattice of rotated surface code qubits, a first quantum bus, and a second quantum bus. The modular quantum processing unit includes inter-module connections between the multiple quantum processor modules to enable connections along the quantum bus. The first quantum bus includes a first rail of logical qubits and a second rail of logical qubits. TheAttorney Docket No.: RIGET-125WO1 first rail of the first quantum bus includes data logical qubits configured to register logical qubits for graph preparation and consumption. The second rail of the first quantum bus includes ancilla logical qubits configured to connect data logical qubits (or graph state logical qubits) and teleport distilled magic states (T-states) for consumption. The second quantum bus is a T-state transfer bus, which includes ancilla logical qubits configured to queue and store T-states. In some implementations, the second quantum bus has a wide enough connection to the second rail of the first quantum bus to teleport T-states to the first quantum bus on demand. The quantum processor module includes magic state distillation factories configured to generate and purify magic states.

[0146] In some implementations, a quantum program is processed on an MBQC by a sequence of measurements and rotations of logical qubits facilitated by a rail of a quantum bus of ancilla logical qubits. As a result, such an architecture requires cryostat modules only to have connections along the rail of ancilla logical qubits. This drastically simplifies the hardware as dense, long-range connectivity between modules is unnecessary. The bare minimum requirement is that the number of coherent links along this rail of the quantum bus may be equal to the code distance; however, adding additional connections will accelerate the overall computation.

[0147] To perform physically grounded, device-specific resource estimations, an error scaling pipeline can be used to incorporate the impact of device properties into resource estimations. This pipeline translates a device-level noise model into the physical to logical error scaling law used in resource counts. As part of the pipeline, the square planar iSWAP surface code or other types of error correction code can be implemented. To produce input noise models for the QEC simulations, device physics-inspired two-qubit correlated noise models can be generated for iSWAP gates. The resulting terms can be used in a Pauli error model to simulate the noise process in a standard Clifford Tableau simulator, for example, described in the publication by C. Gidney, “Stim: a fast stabilizer circuit simulator,” Quantum 5, 497 (2021). For simplicity of this initial workflow, a Minimum Weight Perfect Matching (MWPM) decoder can be implemented in pymatching as described in Oscar Higgott, “PyMatching: A Python package for decoding quantum codes with minimum-Attorney Docket No.: RIGET-125WO1 weight perfect matching,” ACM Transactions on Quantum Computing 3.3 (2022), pp.1–16 (incorporated by reference herein) or in another manner.

[0148] In some instances, a power-law type physical error is assumed to logical error scaling law, equation (13), where 4Åwas the per cycle logical error rate, 4 was the physical error rate, ^ was the code distance, and Æ and 4^>^^^>were fitting parameters.

[0149] Given ^ and characteristic timescales set in the system architectural configuration, {5­^8^^^^^^^ó, 56^^^6^^7^^^ó, 5^^^^^^^ó^)^^6^9^} can be identified. Use the tocks, schedule, and other proprietary architectural configurations from the YAML (fridge sizes, line, coupler, power dissipation details, etc.) to fully identify an FT hardware object, PhysResources, including number of couplers, number of inter-modular pipes, areas, memory, energy usage, etc. PhysResources fully identifies all outputs including total FT hardware time, decoding core numbers, and total power and energy consumption. Hardware execution times are calculated based on the intra and inter-modular operations on the ancilla bus. In some instances, tabulate and print resource estimation outputs to the console and a CSV file as requested. In some instances, other types of output can be produced.

[0150] To generate the data used to determine the coefficients in Eq.30, decoder simulations can be performed using the method described in C. Gidney, sinter, https: / / pypi.org / project / sinter / (2023) or another method. These simulations use combinations of twenty physical error rates and four different code distances for 80 different experiments. For each experiment the square planar iSWAP error correction circuit is simulated for 1 million shots. For each shot, the error correction circuit is repeated 10^ times. To fit the parameters, multivariable least squares fitting is implemented in the scipy numerical package described in publication by Virtanen et al., “SciPy 1.0: Fundamental Algorithms for Scientific Computing in Python,” Nature Methods, 17, 261, 2020. Data points that involved logical error rates that were lower than 10)ôwere removed from the final data set due to the rarity of observing errors. This resulted in a final data set of 69 experiments, which are plotted in FIG.27. The resulting scaling law is given by,Attorney Docket No.: RIGET-125WO1 Å4 !^(^N!) (26)4 = 0.00795980 õ0.0154732ö

[0151] In some implementations, the andoutput one or more of the following parameters which specify properties of logical architecture and hardware. In some instances, the example process 200 can output other parameters. For example, custom classes of quantities to estimate can be added.

[0152] Parameter 1: Number of distillation widget qubits, ÷. The number of total physical qubits that exist in each ^-distillation widget. This is extracted from the example table 2500 shown in FIG.25 after selecting a factory type.

[0153] Parameter 2: Code distance, ø. ^ is the surface code distance that forms the logical patches of 2^2 size, which are the building blocks of all space-time components for the FT hardware. The minimal viable ^ must be calculated precisely and iteratively according to the algorithm shown in FIG.26, which involves satisfying a logarithmic inequality in Step 6, also stated in equation (16).

[0154] Parameter 3: Number of required logical qubits, ùúûüýþ^^û. ^X9^7^^89is the maximum number of logical nodes required to process the complete graph state Y according to a widgetization-based set ^S^^^at any given time. In other words, this is the maximum quantum memory required. A maximum memory of ^X9^7^^89can be applied to all modules and steps of the schedules to avoid any quantum memory bottleneck and delay; there are likely more efficient methods of assigning hybrid quantum bus spaces. Note that the maximum quantum memory required for the entire ^ is a different quantity, ^9^7^^89. For widgetized circuit input, this quantity calculated from the subgraphs can be expressed ^ as ^X9^7^^89= max(^^9^^7^^89, ⋯ , ^^D$EFG(Hcd9^7^^89) ≈ ^9^7^^89. Pauli Tracker can efficiently output each ^^

[0155] Parameter 4: Number of ^-distilleries (^-factories), ù^þ^^þûû^^þ^^. The number of Litinski’s ^-state distillation widgets inside every module. These send purified magic states to T-tranfer and ancillae buses required for the parity measurements on the logical qubits at the consumption stage. This is calculated as ^^ )!6^^=²Attorney Docket No.: RIGET-125WO1

[0156] Parameter 5: Number of required physical qubits for T-distilleries per module, ù^^^þ^^^)þû^û^^^^þ^^^. The total number of physical qubits required for all T-distilleries per module, = ^6^^^^99^^^^^Ö. of QPU modules per leg of the ladder architecture,ù^^^)û^ý^ü^^û^^. ^^^^)9^7^^6^9^^is the number of QPU modules that exist on each leg of the ladder structure in the macro-architecture in FIG.10; in other words, this is the height of the ladder structure.

[0158] Parameter 7: Number of required physical qubits, ù^^^)^^^^. The total number of physical qubits required in the FT computer at any time given the architecture. This is calculated as ^^^­)^>?^= 4^9^7^^89^^+ ^^^^)9^7^^6^9^^(^6^^^^99^^^^^Ö + 2^^^^)^^8^^:^^).

[0159] graph state methodology, the total T-count, ^U^^^, is the total number of T-basis measurements required after the arbitrary-angle ef’s are synthesized at the measurement points of the distillation stage. Therefore, T-count can be written as ^U^^^= ^^V^f^^ º+ ^^U^^^= ^^V^f^^⌈ / ^log^(1 / T) + / !⌉ + ^^U^^^.of available physical qubits, ù^^^^^)^^^^. Total number of physical qubits available in all 2^^^^)9^7^^6^9^^modules of the FTQC.

[0161] Parameter 10:of IO nodes, ù^^^^^. Maximum number of output, or equivalent input, considering all subgraphs. In other words, ^^8Amî =max({ ^ #D$EFG )!^^^^^^^ , … ,   (H^^^^^^^ }), where  ^^^^^^^ is the length of set ^^^^^^^^ as usual. For thein the example processes 200, 300 in FIGS.2 and 3, perform on the input algorithm, for example as shown in FIG.5, all quantum circuit widgets have the same output and input nodes, equal to this reported maximum.

[0162] Parameter 11: Decoder tock, ^^^^^^!^^^. Time required for the assumed TN decoder to perform ^ QEC sweeps sequentially and Parameter 11 below for further details.

[0163] Parameter 12: Intra-module quantum tock, ^þ^ù^^#!^. Time required for subcircuit widgets to perform ^ QEC sweepsis calculated as 5^#^^Ó= 8^5.Attorney Docket No.: RIGET-125WO1

[0164] Parameter 13: Inter-module quantum tock, ^þ^ù^^"!#. Time required for inter- module pipes to transfer ^ or Bell states sequentially in ^ sweeps, 5^^#^¦^^à^= ^5^#^^^.

[0165] Parameter 14: Number of concurrent decoding cores at the distillation stage, ^^#"^^^^^^^^^^^^^^^^. A method of adding some decoding timescales to improve the temporal estimations can be added. Until more efficient decoding approaches can be solved for large surface code sizes ^, an existing scalable candidate: the TN decoder described in Christopher T. Chubb. General tensor network decoding of 2D Pauli codes, 2021. doi:10.48550 / ARXIV.2101.04125 and Piveteau et al., Tensor Network Decoding Beyond 2D arXiv:2310.10722 [quant-ph], 2023 can be selected (incorporated here by reference). Unlike MWPM candidates, this Matrix Product State (MPS) based decoder scales efficiently for different errors and offers clear scaling relations, helping us estimate costs.

[0166] Many assumptions are required for a TN decoder to work with a real-world FTQC, and more research is essential for the viability of such tools. In some instances, TN decoders (well-established for 2D codes) are still work-in-progress and offer no systematic method to generalize them to measurement errors. In certain instances, the same MPS structure is still used for time evolution steps; the contraction is bounded, and scales in the presence of other error types.

[0167] Resources for an embedded reference classical unit, such as a CPU or ASIC core or group of cores, can be calculated. that performs one complete cycle of decoding: these receive the syndrome and output possible corrective operations, which can be, for example, performed through parity measurements at the ends. Here, a reference decoding core is used with a few TFLOPS performance and 100 Watt Thermal Design Power (TDP) consistent with cluster-grade CPU or consumer-grade GPU units. For an MPS bonddimension of % = 20, ^ = 96, and best-case noise scenario, decoding takes 56^^^6^^7^^^ó =0.1 ms to the nearest order of magnitude. In some instances, an updated scaling pattern as% = ⌊0.1^^.&⌋ + 8 or another scaling pattern can be used.

[0168] Since quantum operations do not need to wait for decoders to finish their cycles until corrective measurements are performed, there will always be a staggered type of architecture when considering classical and quantum units working together at each stage.Attorney Docket No.: RIGET-125WO1 Moreover, since decoder tocks for us are longer than quantum tocks, the best strategy is to let many concurrent decoding cores complete the cycles. This way, the decoding process only adds an overall delay to FT hardware time on top of purely quantum gate operations.

[0169] Hence, cores6^^^6^^76^^^^99can be defined as the number of concurrent decoding cores EG°¯E$% required at the distillation stage. This was calculated as cores6^^^6^^7^ F (¯°'6^^^^99= ⌈^¨'±%('Ü⌉. (¯°'

[0170] Parameter 15: Total consumption time, ^^^^^^^^^^^. The cumulative time to consume the subgraphs given all scheduling steps, including all delays necessary to distillmore ^-states or prepare the subgraphs. This is calculated as 5^^^ ^^^#^^ÕÒ = 85^( ^^^^ +^^^­ 6^98? 6^9^ ) + 56^^^^99 + 8?^^^^^^ 5^^^^ .

[0171] Parameter 16: Overall distillation delay, 56^^^^99)6^98? 6^^^^99)6^98?^^^.5^^^is the overall delay included in the total consumption time, 5^^^^^#^^ÕÒ, to distill additional T-states in the same module, which is required to complete the parity measurements.

[0172] Parameter 17: Overall preparation delay, 5^^^^)6^98? ^^^^)6^98?^^^.5^^^is the overall delay included in the total consumption time, 5^^^^^#^^ÕÒ, to create the next subgraph in the schedule. The FT pipeline cannot proceed from the current consumption stage until the next subgraph is prepared in the next set of the quantum processor modules.

[0173] Parameter 18: Overall decoding delay, 56^^^6^)6^98? 6^^^6^)6^98?^^^.5^^^is the overall decoding delay accumulated from all graph distillation and consumption stages and is added to the total FT hardware time. The overall decoding delay, assuming 56^^^6^^7^^^ó> 5­^8^^^^, can be calculated as6^^^6^)6^98? 6^^^6^^7 ­^8^^^^^^^ó5^^^= ^^^^ó(5^^^ó^− 5^^^ó), where ^^^^ó^was given in the example algorithm 2600 shown in FIG.26.

[0174] Parameter 19: Total inter-modular handover operation time, 5>^^8^^6^ì^^)^^^^^. The cumulative inter-modular time for Bell-state teleportation operations to handover, “stitch”, subgraphs for all scheduling steps. This is calculated as 5>^^8^^6^ì^^)^^^^^=∑Jb^,…,À&¹G&)!5>J8^6^ì^^)^^^^^.Attorney Docket No.: RIGET-125WO1

[0175] Parameter 20: Power dissipation at 4K stage, POW-.. Power dissipation for the 4-Kelvin stages of all fridges.

[0176] Parameter 21: Power dissipation at MXC stage, POW^^^. Power dissipation for the MXC stages of all fridges.

[0177] Parameter 22: Number of available logical qubits, ^8ì8^9)9^7^^89. The total number of logical qubits available per module of the FTQC and can be allocated to quantum operations, ^8ì8^9)9^7^^89= ^^^67^.

[0178] Parameter 23: Number of unallocated logical qubits, ^^^899^^)9^7^^89. The minimum number of left-over, or unallocated, logical qubits in each module given the complete set of FTQC operations, ^^^899^^)9^7^^89= ^^^67^− 2^X9^7^^89− ^^)^^8^^:^^− ^6^^^^99^^^^^⌈^«G%F(^√^^⌉⌈^D$E(^√^^⌉.Number of input logical qubits, ^^^^^^. The total number of logical qubits in the input algorithm, ^.

[0180] Parameter 25: Diamond-norm precision for gate synthesis, 0. Extensive theoretical and numerical studies established that a non-Clifford angle1Q rotation gate can be systematically approximated as a chain of Clifford+^. Here, T-length maximally scales as  º= ⌈ / ^log^(1 / T) + / !⌉. The diamond-norm precision, T, denotes the rate used in the gate synthesis of non-Clifford angle unitaries (for example, only ei gates) at the measurement points of the distillation stage. The state-of-the-art decomposition approach of mixed- fallback can be used, which offers / ^= 0.57, / != 8.83 improving over the previously employed GridSynth method with / ^= 3.0, / != 0.

[0181] In some instances, the non-angle decompositions can be processed internally, meaning the graph does not depend on T. The diamond-norm precision must be found precisely and iteratively, according to the algorithm 2600 shown in FIG.26, which naturally involves solving a logarithmic equation in Step 6.

[0182] In some instances, T parameter should not be left for the user to set by default (although the methods and systems presented here allow users to force a fixed value if required). Utmost care is needed here because precisions are, in fact, equivalent to the FTAttorney Docket No.: RIGET-125WO1 resources: if T was selected too large, then the rate condition in Step 7 above is not satisfied, and too small means space-time resources will become wasteful and unnecessarily large.

[0183] Parameter 26: ^-depth, 1^.2Uis the estimated ^-depth for the input logical algorithm, ^. This is calculated as 2U= ⌈^^U^^ / ^X9^7^^89⌉.

[0184] Parameter 27: Number of 34-gate in the input circuit, ^V^^f^^. The number of ei-gates in the input algorithm, ^, whether written explicitly or live inside other logical gates. All ei-gates must undergo decomposition to Clifford+^ at the distillation- consumption stage.

[0185] Parameter 28: Number of ^,^h-gates in the input circuit, ^U^^^^. The number of ^,^h-gates in the input algorithm, written explicitly or live inside otherlogical gates.

[0186] Parameter 29: Number of Clifford gates in the input circuit, ^n^^9^^:^:^^6. The number of Clifford gates in the input algorithm, ^.

[0187] Parameter 30: Number of graph state logical qubits, ^. ^ is the number of total logical nodes in the complete graph state, 5, i.e., graph degree. For widgetized circuits, this quantity calculated from subgraphs can be expressed as ^6= ∑Jb^,...,#D$EFG(H)!^J+ ∑Jb^,...,#D$EFG(H)^^^^^^^^^J ≈ ^, where ^^^^Ò^^^J is the number of output nodes at step 2 which needs to be added to the complete graph to facilitate Bell pair transfer stitching subgraphs.

[0188] Parameter 31: Number of distinct measurement steps at the graph- consumption stage, ¶^^^^^^^. The total number of distinct and sequential measurement steps of the consumption schedule governing the operations at the consumption- distillation stage. In other words, the total number of distinct sets inside nested sets in the schedule derived from Pauli Tracker described in https: / / github.com / taeruh / pauli_tracker.git (2024) and https: / / pypi.org / project / mbqc- scheduling / (2024).

[0189] Parameter 32: Number of distinct measurement steps at the graph- preparation stage, ¶^^^^. The total number of distinct and sequential measurement stepsAttorney Docket No.: RIGET-125WO1 of the preparation schedule governing the operations to initialize the subgraphs. In other words, the total number of distinct sets inside nested sets in the schedule derived from the publication, Liu et al., Substrate scheduler, graph-state-generation, https : / / github.com / sfc- aqua / gosc-graph-state-generation.

[0190] Parameter 33: Decoding memory at the consumption stage, mem6^^^6^^76^^^^99. mem6^^^6^^76^^^^99is the maximally required random access memory for all concurrent decoding cores at the consumption stage. In some instances, the decoding units store and manipulate ^-MPS-matrices in the dense form for each step. Given that each element requires 8 Bytes for double precision storing and the scaling relations given in the Publication C. T. Chubb,General tensor network decoding of 2d Pauli codes (2021). a memory of mem6^^^6^^7^^^^^^^ =8cores6^^^6^^7(^ + ^%^^^^^^^^ √ ) in Bytes for this stage.QPU area, area^>^^. area^>^^is the total area occupied by QPUs from all modules on both legs of the ladder macro-architecture.

[0192] Parameter 35: Number of couplers, ^^^^^^^^9^^^. ^^^^^^^^9^^^is the total number of adjustable couplers required for all modules on both legs of the ladder macro-architecture (as shown in FIG.8).

[0193] Parameter 36: Decoding power at consumption stage, POW^^^^^^^. The Decoding power used during the distillation-consumption stage is based on 100W reference decoding units. Therefore, POW^^^^^^^= 100cores^6^^^^^^^6^^^.

[0194] Parameter 37: Total FT-hardware time, 5^>^8^^6@8^^.5^>^8^^6@8^^is the estimated upper-bound on total FT hardware time accumulated from all its non-simultaneous components running in two legs of modules and inter-connects of the architecture. This includes all the inter and intra tocks required at the consumption stages, delays required for the graph creation and ^-distillation, subgraph handover time, and the decoding delay. In other words, this is the overall time cost. This can be formulated as 5>^^8^^Ó6^@8^^= 5^^^^^^^889+ 5>^^8^^869^ì^^)^^^^^+ 56^^^^^8^96^)6^98?.Attorney Docket No.: RIGET-125WO1

[0195] Parameter 38: Total energy consumption, 7^^^. Estimates for 7^^^, can determine the upper-bound on the total energy usage of the FT hardware, considering all quantum and decoding operations. In some instances, three dominant power-consuming units dissipating energy during FT computations can be considered. These include decoding cores with the TDP of 8^6^^^^)^^6^^^^^7= 100W during distillation-consumption stage (taking around 56^^^6^^7)^^^^6^^^^998^^^^= (Å^ + 1)^^U^^56^^^6^^7^^^óper core).4K units can be included with a total TDP of 8-^.^^and a efficiency factor assumed to be 9-.= 500, and finally,lower- units with a total TDP of 8^^^^^^ and a cooling efficiency factorassumed to be of 9^^^ = 10:. Each unit contains several power-consuming stages, and these values can be established by thermal analysis of the signal chain. Overall, 7^^^= 8^6^^^^)^^6^^^^^7cores6^^^6^^76^^^^99566^^^^^^^9698^^)^^^^^^^+ 9-.8-^.^^5^>^8^^6@8^^+ 9o / n8o^^ / ^n 5^>^8^^6@8^^.The example process 300 allows segmenting a quantum program into a set of quantum circuit widgets each representing a time slice of the quantum program and executing the quantum program based on the set of quantum circuit widgets. In some instances, the methods presented here allow segmenting a large quantum logic circuit without unrolling and offer an improved efficiency in compilation and execution of the quantum program. For example, segmenting a large quantum logic circuit without decomposing the complete circuit to the lowest-level quantum logical operations supported by the fault tolerant quantum computer in all cases; by recognizing repetition in the tree structure of the input circuit repeated decompositions can be avoided. The example process 300 may include additional or different operations, including operations to fabricate additional or different components, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 300 can be combined, iterated, or otherwise repeated or performed in another manner.

[0197] At 302, a quantum program is received. In some implementations, a quantum program can be represented, for example, as a quantum Hamiltonian, a sequence of quantum logic gates, a set of quantum machine instructions, or otherwise. The quantum program may correspond to a computational task, a hardware test, a quantum errorAttorney Docket No.: RIGET-125WO1 correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations. In some instances, a quantum program includes a sequence of quantum logic operations, e.g., single-qubit quantum logic gates, two-qubit quantum logic gates, multi-qubit quantum logic gates, identity gates, and other quantum logic operations. In some instances, the quantum program can be an Quil program generated by a user device (e.g., the user device 110 as shown in FIG.1), another computer resource outside the local environment of the quantum computer system 103, or in another manner; and received by a quantum computing system (e.g., the control system 105 of the quantum computing system 103 in FIG.1). In some implementations, operation 302 may be implemented as the operation 202 in the example process 200 or in another manner.

[0198] At 304, the received quantum program is decomposed. In some implementations, one or more classical processors of the quantum computing system (e.g., the classical processors 111 of the servers 108, or the control system 105 of the quantum computing system 103 shown in FIG.1) can be operated to decompose the sequence of quantum logic operations of the quantum program into an equivalent sequence of first- layer quantum logic sub-operations applied to the qubits. Using the example shown in FIG. 4, the sequence of quantum logic operations 402 in the received quantum program is first decomposed into four subcircuits of quantum logic sub-operations 404A (vertex A), 404B (vertex G), 404C (vertex H), 404D (vertex K), which represent four time slices of the decomposed quantum program. The four time slices form a first layer of quantum logic sub-operations. Each subcircuit may include one or more quantum logic sub-operations. As shown in FIG.4, the example quantum program with a circuit depth of 8 of the first layer 412A is decomposed into subcircuits of the second layer 412B. The first subcircuit 404A of the second layer 412B has a circuit depth of 4; the second subcircuit 404B of the second layer 412B has a circuit depth of 1; the third subcircuit 404C of the second layer 412B has a circuit depth of 1; and the fourth subcircuit 404D of the second layer 412B has a circuit depth of 2. Since the subcircuit 404B has a circuit depth of 1 and include a quantum logic gate compatible with the graph state compiler, the subcircuit 404B is not decomposed further; and the vertex G is a leaf node.Attorney Docket No.: RIGET-125WO1

[0199] In some implementations, at least one of the quantum logic sub-operations (e.g., the sub-circuits) in the second layer is decomposed into an equivalent sequence of quantum logic sub-operations applied to the qubits. Continuing with the example shown in FIG.4, after the received quantum program in the first layer is decomposed into four subcircuits of the second layer, one or more subcircuits in the second layer can be further decomposed into subcircuits forming a third layer. For example, the first subcircuit 404A of the second layer 412B with a circuit depth of 4 can be decomposed into three subcircuits 406A (vertex B), 406B (vertex C), 406C (vertex D) each representing a time slice of the received quantum program. The first subcircuit 406A of the third layer 412C has a circuit depth of 1; the second subcircuit 406B of the third layer 412C has a circuit depth of 1; and the third subcircuit 406C of the third layer 412C has a circuit depth of 2. Since each of the first and second subcircuits 406A, 406B of the third layer 412C has a circuit depth of 1, the first and second subcircuits 406A, 406B are not decomposed further; and the vertices B and C are leaf nodes.

[0200] In some implementations, the third subcircuit 404C (vertex H) of the second layer 412B is decomposed to a fourth subcircuit 406D (vertex J). In this case, the decomposition of the third subcircuit 404C does not change the number of quantum logic gates, e.g., the numbers of quantum logic gates in the third and fourth subcircuit are equal. In some instances, a decomposition may increase the number of quantum logic gates that are compatible with the graph state compiler. In some instances, decomposition of the third subcircuit 404C to the fourth subcircuit 406D includes a transpilation process to convert the quantum logic gate to one or more quantum logic gates that are supported by the graph state compiler. In some instances, such transpilation process does not change the depth. For example, a CNOT gate can be rewritten as a H gate, a CZ gate and a H gate on the same qubit; and a QFT(3) can be decomposed into multiple CNOT gates that share qubits and the depth can be increased. The fourth subcircuit 406E of the third layer 412C has a circuit depth of 1. The fourth subcircuit 404D of the second layer 412B is decomposed into a fifth subcircuit 406E (vertex L) and a sixth subcircuit 406F (vertex M). Each of the fifth and sixth subcircuits 406F, 406G has a circuit depth of 1, the fifth and sixth subcircuits 406E, 406F are not decomposed further; and the vertices L and M are leaf nodes.Attorney Docket No.: RIGET-125WO1

[0201] In some instances, a “depth first” approach can be implemented. For example, with all of the children vertices identified for a first parent vertex (vertex A), the decomposition can be continued with a second parent vertex (vertex G), followed by decomposing the vertices H and K. Note that the depth values for each vertex (in the parenthesis) are the sums of the depths of their children and exactly match the number of leaf nodes below it. In some instances, other heuristics can be used such as a total T-gate count can be used to determine the formation of quantum circuit widgets.

[0202] As shown in FIG.4, the third subcircuits 406C of the third layer 412C is decomposed into a first subcircuit 408A (vertex E) and a second subcircuit 408B (vertex F) forming a fourth layer 412D. Each of the first and second subcircuits 408A, 408B has a circuit depth of 1, the first and second subcircuits 408A, 408B are not decomposed further; and the vertices E and F are leaf nodes.

[0203] In some implementations, after decomposition, all subcircuits at the leaf nodes includes only single-qubit quantum logic gates or two-qubit quantum logic gates.

[0204] At 306, a tree structure is constructed. The tree structure is a graph representing subcircuit dependency of a quantum program. A tree structure includes quantum logic sub- operations arranged in multiple layers. The multiple layers correspond to multiple decomposition levels of the quantum program. Each layer includes multiple subcircuits of quantum logic sub-operations.

[0205] In some implementations, in a tree structure, vertices represent time slices of a quantum program. A directed edge connects a parent vertex to a child vertex if the child vertex represents a time slice that was created by decomposing the time slice represented by the parent. The creation of a tree structure is accomplished by recursively decomposing time slices (e.g., performing operations 304), on a level at a time, and stopping when a time slice cannot be further decomposed (called a leaf node). When a leaf node is reached, one returns to the parent vertex and decomposes the next time slice in the temporal sequence. If no time slices remain to decompose, move up to the subsequent parent vertex, and so forth.Attorney Docket No.: RIGET-125WO1

[0206] These depths are aggregated up in a tree structure, where a parent vertex has a depth equal to the sum of the depths of its children. This has the effect of allowing one to know how many time slices a fully decomposed circuit would be. When a tree structure is constructed, a running cache of time slices is maintained, and if a time slice is encountered which has already been decomposed, it is not decomposed again.

[0207] At 308, the decomposed quantum program is segmented into multiple quantum circuit widgets. In some implementations, the decomposed quantum program is segmented to form multiple quantum circuit widgets based on the tree structure. At least one anchor node and at least one leaf node from the constructed tree structure can be identified. In some instances, if a concatenation in time of fully decomposed time slices belonging to a vertex in a temporal order, with a circuit depth of less than or equal to a predefined circuit depth (e.g., a maximum circuit depth that can be handled by a compiler), can reconstruct a subcircuit corresponding to the vertex, this vertex is an anchor node. For example, vertices for example, 404B, 404C, 404D are anchor nodes in the tree structure 400. In some instances, if a vertex includes a subcircuit that can’t be further decomposed, the vertex is a leaf node. In some implementations, a quantum logic sub-operation included in a quantum circuit widget is either a single-qubit quantum logic gate or a two-qubit quantum logic gate. The depth of an anchor vertex is less than or equal to the maximum depth, but the depth of its parent vertex is greater than the maximum depth.

[0208] If the user specifies a maximum subcircuit size (according to the circuit depth, number of qubits, gates, etc.), anchor nodes can be identified from the tree structure. In some implementations, an anchor node is a vertex with two important properties: the full circuit (e.g., the quantum program) can be reconstructed from the subcircuits at anchor nodes only; and the fully decomposed subcircuits at anchor node are smaller than the user defined maximum size.

[0209] In some implementations, subcircuits at the leaf nodes are concatenated in a temporal order until the number of subcircuits reaches a threshold value (e.g., a maximum circuit depth). Assume that the user has set a maximum circuit depth of 3, the starting circuit 402 on the first layer 412A can be considered as a single, monolith time slice, with gates acting on ^ qubits. This circuit corresponds to the anchor node 402 in the exampleAttorney Docket No.: RIGET-125WO1 tree structure 400. Continuing with the example tree structure 400 shown in FIG.4, the leaf nodes 406A, 406B of the third layer 412C and the leaf node 408A of the fourth layer 412D are concatenated together to form a first quantum circuit widget with a circuit depth of 3. Similarly, the leaf node 408B of the fourth layer 412D, the leaf node 404B of the second layer 412B, and the leaf node 406D of the third layer 412C are concatenated together to form a second quantum circuit widget with a circuit depth of 3. Finally, the leaf nodes 406E, 406F of the third layer 412C are concatenated together to form a third quantum circuit widget with a circuit depth of 2. After all the leaf nodes are concatenated, the segmentation of the quantum program is completed, and the quantum circuit widgets are formed.

[0210] In some instances, the concatenation of leaf nodes can ensure quantum circuit widgets are "large enough" which makes the execution of the quantum program based on the quantum circuit widgets more efficient while still being small enough to be performant. while the above procedure ensures no subcircuit is larger than the user requires, it’s possible that the subcircuits may be too small, making downstream execution inefficient on hardware that can run larger circuits. To avoid this, the fully decomposed subcircuits from anchor nodes may be recombined (if determined) in execution order to increase their size, while remaining below the user defined limit (e.g., maximum circuit depth).

[0211] FIG.4 is a schematic diagram showing aspects of an example tree structure 400. In some instances, the tree structure 400 can be used for segmenting a quantum program into multiple quantum circuit widgets. For example, the example tree structure 400 can be obtained by performing operations in the example process 300 and used in operations for performing a modular graph state processing in the example process 200. Each quantum circuit widget can be compiled using a fault tolerant compiler, e.g., a graph state compiler. As shown in FIG.4, the example tree structure 400 includes multiple anchor nodes and multiple leaf nodes.

[0212] In some implementations, the quantum circuit widgets in the sequence may have different circuit depth values. Operations such as re-segmentation can be performed to ensure the quantum circuit widgets have comparable circuit depth values. In some implementations, executing the quantum circuit widgets in order, reconstructs the execution of the original sequence of quantum logic operations in the quantum program,Attorney Docket No.: RIGET-125WO1 and each quantum circuit widget has maximum depth less than or equal to a threshold value (e.g., a user defined limit).

[0213] In some instances, the systems and techniques presented here allow the user to limit the size of the subcircuits used for algorithm execution; maintain a faithful representation of the quantum program; and represent these subcircuits as atomic subcircuits, which leads to easier compilation to machine instructions downstream. In some instances, the techniques described here can produce cached subcircuits allowing for scalable, memory efficient processing in other, downstream procedures (for example, graph state compilation). In some instances, a cache of decomposed subcircuits can be carried so that if a circuit has already been decomposed before, it is not decomposed, but rather indexed and skipped.

[0214] FIG.5 is a schematic diagram showing aspects of an example quantum logic circuit 500. As shown in FIG.5, a complete quantum program, ^, is segmented into multiple quantum circuit widgets 502, ^@^67^^^[^^, … , ^#D$EFG(H)!] each representing a time slice of the complete logical algorithm with exact same ^^^^^^width (applied on qubits 504) and almost equal circuit depths of ^^8A. The decomposed quantum program can include repeated structures, the methods and systems presented here can select a subset of qubits and gates (shown in purple in FIG.3). The union of all quantum circuit widgets, some possibly repeated, reconstructs the circuit. As shown in FIG.5, a first quantum circuit widget 502A includes single-qubit quantum logical gates or two-qubit quantum logical gates applied on the qubits during a first time period 5^; a second quantum circuit widget 502B includes single-qubit quantum logical gates or two-qubit quantum logical gates applied on the qubits during a second time period 5!; a third quantum circuit widget 502C includes single-qubit quantum logical gates or two-qubit quantum logical gates applied on the qubits during a third time period 5^; and an (n-1)-th quantum circuit widget 502C includes single-qubit quantum logical gates or two-qubit quantum logical gates applied on the qubits during an (n-1)th time period 5#)!. In some implementations, neighboring quantum circuit widgets are not assigned to the same quantum processor module. In some instances, at least two quantum processor modules can be used to execute the quantum logic circuit 500. In some instances, the quantum circuit widgets 502A, 502B, 502C can beAttorney Docket No.: RIGET-125WO1 compiled, for example using a fault tolerant compiler, by performing operations shown in FIGS.8, 10, or in another manner. In some instances, some of the single- and two-qubit quantum logic gates can be regrouped together to form a bigger block with possible identity operation on some qubits just to make plotting and writing of the quantum circuit widgets cleaner.

[0215] FIG.6 is a schematic diagram showing aspects of an example process 600. The example process 600 is a verification protocol to robustly test and verify individual MBQC- formatted circuits (corresponding to ℰu8v89^w^^o|}n’s), graphs, consumption schedules, and Pauli tracking information as outputted by the Jabalizer library described in a publication by Madhav Krishnan Vijayan et al., Jabalizer, https: / / github.com / QSI-BAQS / Jabalizer.jl. The robust verification of the compilation and estimation methodology at different layers was a priority. A verification protocol can be used to precisely check the correctness of individual subgraphs {^} as long as the widgets originated from small circuits with 10’s of logical qubits.

[0216] The input logical unitary, ^ (e.g. a small algorithm or a subcircuit of a bigger one in the qasm format) of the quantum program, is provided to the test module. A fault- tolerant compiler, e.g., a graph-state compiler (e.g., Jabalizer) on the input logical unitary to output a unified JSON containing the graph state, consumption schedule, and Pauli tracking information. The MBQC-formatted circuit for the input logical unitary ^ is particularly relevant to the verification protocol, which is labeled as ℰu8v89^w^^o|}nin the figure to highlight the correspondence discussed earlier. Now,of the fault- tolerant compiler, one can build the inverse of the original algorithm for small-size cases, i.e. ^h. For example, if ^ is unitary for a logical QFT4, then ^his InverseQFT4 manually generated. A quantum simulator software is used to run noiseless simulations of the circuit instructions shown in the lowest panel of FIG.6 with the input state of the verification protocol set, as an example, to ^^= 0, ^!= 0, ⋯ , ^#$%&'()!= 0,00 ⋯ 0. By the unitarity principles, if the ℰu8v89^w^^o|}nwas valid (which implies the validity of the graph state and the rest of Jabalizer outputs), then simulation output counts must exactly correspond to 00 ⋯ 0 for the example input.Attorney Docket No.: RIGET-125WO1

[0217] In some instances, graphs produced for several small-size input circuits containing QFT, single TOFFOLI, and Clifford instructions (where some were widgetized from larger algorithms) with all possible input states as inputstates ∈ {(27) |^^ = 0, ^! = 0, ⋯ , ^#$%&'()! = 0,00 ⋯ 0^|^^ = 1, ^! = 0, ⋯ , ^#$%&'()! = 0,00 ⋯ 0^ ⋯ ,|^^ = 1, ^! = 1, ⋯ , ^#$%&'()! = 1,00 ⋯ 0^}.can be simulated and verified.

[0218] FIG.7 is a schematic diagram showing aspects of an example modular quantum processing unit 700. As shown in FIG.7, the modular quantum processing unit 700 includes two quantum processor modules 704A and 704B. The quantum processor modules 704A and 704B are communicably connected via a coherent link 706. The modular quantum processing unit 700 may be enclosed in in a cryostat 702 of a cryogenic system, in which the example modular quantum processing system 700 is exposed to a cryogenic environment of very low temperature (e.g., T < 120 K).and very low pressure (e.g., in the range of 10-3mbar to 10-9mbar) in the cryostat 702. The cryogenic system may include thermal stages, and refrigeration systems thermally coupled to the thermal stages. In some instances, the modular quantum processing system 700 resides on the lowest-temperature thermal stage and can receive control signals and transmit readout signals to devices and systems residing outside of the cryostat 702. In some instances, the example modular quantum processing unit 700 may include additional or different features, and the components may be arranged in another manner. For example, the example quantum processing unit 700 may include more than two quantum processor modules.

[0219] In some instances, each quantum processor module 704A, 704B includes multiple quantum processor chips on a substrate. Each quantum processor chip includes a superconducting quantum circuit with multiple quantum circuit devices (e.g., qubit devices) connected in an error check pattern and provides the functionality of a logical qubit. In some implementations, a qubit device may be a data qubit device, a stabilizer / ancilla qubit device, or other types of qubit devices. Each quantum processor chip also includes intra-chip circuit connections (e.g., coupler devices 1214 in the exampleAttorney Docket No.: RIGET-125WO1 quantum processor module 1200 in FIG.12) which provides couplings between qubit devices on the same chip to apply multi-qubit quantum logic gates or types of operations to qubits defined by the qubit devices. Quantum logic gates mediated by intra-chip circuit connections can be used to create entanglement between qubits defined by qubit devices within the respective quantum processor chip.

[0220] Each quantum processor chip includes boundary qubit devices also communicably connected to boundary qubit devices from neighboring quantum processor chips via inter-chip circuit connections (e.g., the inter-chip coupler devices 1216 in the example quantum processor module 1200 shown in FIG.12). Each logical qubit is coupled with its nearest neighbors. In some instances, the logical qubits may be configured on the quantum processor module in a square lattice or in another manner. In some instances, qubit devices from different quantum processor chips can be connected in an error check pattern and can support a single logical qubit. In some instances, the quantum processor module may be implemented as the example quantum processor module 1200 shown in FIG.12 or in another manner.

[0221] In some implementations, each quantum processor module 704A, 704B includes multiple quantum buses, each of which includes multiple interconnected quantum processor chips or logical qubits to facilitate communication of quantum information within the quantum processor module. In some implementations, each quantum bus is designed to transfer quantum states or entangle logical qubits across different sections of the quantum processor module. In some implementations, quantum processor chips of each quantum processor module are parsed; control signals for performing quantum logic operations are applied to qubit devices and inter-chip coupler devices to form the respective quantum buses. In other words, a subset of quantum processor chips in a quantum processor module are arranged in a bus-like structure enabling the modular graph state processing. For example, each quantum processor module 904 may be configured as the quantum processor module 1300, 1400, 1600 shown in FIGS.13-14, 16, or in another manner.

[0222] In some instances, the quantum processor modules 704A, 704B may be identically configured having the same architecture. In particular, the quantum processorAttorney Docket No.: RIGET-125WO1 modules 704A, 704B may have the same number of logical qubits; the same number and layout of ancilla logical qubits in first quantum buses; and the same number and layout of data logical qubits in second quantum buses. In some instances, when each quantum processor module includes T-state distillation factories, the quantum processor modules 704A, 704B may have the same number and layout of logical qubits for T-state distillation factories. In some instances, when each quantum processor module includes a T-state transfer bus, the quantum processor modules 704A, 704B may have the same number or layout of logical qubits for T-state transfer buses.

[0223] As shown in FIG.7, the logical qubits from the first quantum processor module 704A can be configured to execute a first compiled quantum circuit widget, which includes schedules of a first graph state representation produced from a graph state compilation process of a first quantum circuit widget; and the logical qubits from the second quantum processor module 704B can be configured to execute a second compiled quantum circuit widget, which includes schedules of a second graph state representation produced from a graph state compilation process of a second quantum circuit widget. Each quantum processor modules 704A, 704B is configured to handle a respective portion of the graph state processing. In other words, the logical qubits defined in the first quantum processor module 704A are used to execute the schedules graph state creation, consumption, and magic state distillation, and transfer for local T-state processing associated with the first compiled quantum circuit widget. The logical qubits defined in the second quantum processor modules 704B are used to execute the schedules graph state creation, consumption, and magic state distillation, and transfer for local T-state processing associated with the second compiled quantum circuit widget. For example, the modular quantum processing unit 700 may be used to perform the modular graph state processing shown in FIG.8 or in another manner.

[0224] FIG.8 is a schematic diagram showing a portion of an example process 800 for performing a modular graph state processing. In some instances, the example process 800 includes operations that can be performed in a timely manner from right to left as indicated by the X-axis. Operations occur during the same time period can be performed in parallel on separate quantum computing resources. In some implementations, the example processAttorney Docket No.: RIGET-125WO1 800 is used to execute three compiled quantum circuit widgets in a compiled quantum program obtained from a graph state compilation process. In some instances, the example process 800 may be implemented as the operation 210 in the example process 200 shown in FIG.2. In some instances, the example process 800 can be performed by operations of a modular quantum processing unit with multiple quantum processor modules. The compiled quantum program contains a sequence of compiled quantum circuit widgets. Each compiled quantum circuit widget includes a graph state representation of a corresponding to a quantum circuit widget obtained from a segmentation process of a quantum program. Each compiled quantum circuit widget can be assigned to and executed by operation of a quantum processor module. In some instances, neighboring compiled quantum circuit widgets are not assigned to or executed on the same quantum processor module.

[0225] As shown in FIG.8, the first compiled quantum circuit widget represented by a first graph state representation 822A is assigned to and to be executed on a first quantum processor module 812A (e.g., the quantum processor module 704A in FIG.7) and a second compiled quantum circuit widget represented by a second graph state representation 822B is assigned to and to be executed on a second quantum processor module 812B (e.g., the quantum processor module 704B in FIG.7). The sequence also includes a third compiled quantum circuit widget represented by a third graph state representation 822C. The third graph state representation 822C is assigned to and to be executed on the first quantum processor module 812A.

[0226] As shown in FIG.8, executing each of the first, second, and third graph state representations 822A, 822B, 822C includes performing a measurement-based quantum computing (MBQC) process. This framework allows quantum computation to be carried out by performing a series of single-qubit measurements on the graph state, rather than directly manipulating the qubits through quantum gates. As shown in FIG.8, a MBQC process associated with the execution of the first graph state representation 822A includes a first graph preparation operation 802A and a first graph consumption operation 804A. A MBQC process associated with the execution of the second graph state representation 822B includes a second graph preparation operation 802B and a second graph consumptionAttorney Docket No.: RIGET-125WO1 operation 804B. A MBQC process associated with the execution of the third graph state representation 822C includes a third graph preparation operation 802C and a third graph consumption operation 804C.

[0227] In some implementations, during a graph preparation operation 802A, 802B, 802C, a respective graph state is prepared. For example, each physical qubits within a logical qubit can be initialized in a defined state, e.g., |0^state. After initalization, a single- qubit qunatum logic gate, e.g., a Hadamard gate, can be aplied ot each initialized logical qubit to create a superposition of |0^ and |1^ states on each qubit. In some instances, the state graph is built by applying a CZ gate between pairs of logical qubits to create entanglements based on the desired graph topology. In some instances, on the physical qubit level, quantum logic operations such as single-qubit operations including Pauli X, Y or Z rotations, stabilizer measurements, two-qubit operations such as CZ gates, and other quantum logical operations can be performed.

[0228] In some implementations, each graph preparation operation 802A, 802B, 802C is accomplished through intra -module operations performed on the first quantum processor module 812A. Each processor module 812A, 812B has an intra-module architecture of a continuous comb-shape layout of bilinear quantum buses of data logical qubits and ancilla logical qubits as the quantum buses. In some instances, a full bi-linear quantum bus of data logical qubits or ancilla logical qubits has the logical size of ^X9^7^^89(e.g., 2^X9^7^^89patches in total). In some instances, each quantum processor module 812A / 812B can host 2⌈^X9^7^^89⌉ patches of logical qubits of the quantum bus. Each portion of the quantum bus is allocated to an entire edge of a quantum processor module (e.g., the quantum buses 1402, 1404 of the quantum processor module 1400 in FIG.14) and may take up as much of the quantum processor module as required to consistently execute the graph state processing for ⌈^X9^7^^89⌉ patches of logical qubits originated from the input quantum program. In some instances, each quantum processor module 812A / 812B may include the same intra-chip architecture.

[0229] In some implementations, the MBQC process performed on each quantum processor module 812A / 812B applies measurements to each logical qubit on one rail of theAttorney Docket No.: RIGET-125WO1 bi-linear bus (e.g., the quantum bus 1302, 1402 of data logical qubits as shown in FIGS.13- 14) mediated by the logical qubits on the other rail (e.g., the quantum bus 1304, 1404 of ancilla logical qubits as shown in FIGS.13-14). In some implementations, the quantum bus pattern is at least 3-tile wide to support the graph state processing; the logical width of the bi-linear bus inside each quantum processor module can be calculated as  ­v^^= ⌈#X«¯F$°±«ª c^⌉. In some instances, the layout for embedding this pattern depends on the ^⌊GEFG³ ⌋N!

[0230] In some implementations, during a graph consumption operation 804A, 804B, 804C, since the quantum circuit widget before compilation requires the application of non- Clifford gates (such as the T-gate), T-states are generated and injected in the graph consumption operation. In some instances, T-states can be prepared, transferred and consumed locally on the same quantum processor module (e.g., the quantum processor module 1300, 1400 in FIGS.13, 14) or remotely from a distinct quantum processor module (e.g., the quantum processor module 1502C, 1700 shown in FIGS.15 and 17) and teleported through a coherent link. In some instances, T-states are used to inject the non- Clifford gates into the computation. In some instances, non-Clifford gates are not directly applied to the qubits in graph state. Instead, a non-Clifford gate is applied through a process of magic state injection or state distillation. For example, during the state distillation process, raw T-states for implementing non-Cliford gates, can be generated by operation of a T-state distillation factory. The raw T-states can then be processed by running distillation protocols, e.g., taking multiple raw T-states and combining them through a series of quantum operations, producing distilled and purified T-states with higher fidelity which are ready to be used in quantum logical operations, e.g., the non- Clifford gates. The distilled T-states can then be transferred from the T-state distillation factories to the bi-linear quantum bus for processing. In particular, the distilled T-states can be transferred through a series of quantum operations by operation of logical qubits in a T-state transfer bus (e.g., the T-state transfer bus 1406) connecting the T-state distillation factories and a quantum us of ancilla logical qubits.Attorney Docket No.: RIGET-125WO1

[0231] In some instances, the bi-linear quantum bus is also the end-point for executing the graph consumption operations 804A, 804B, 804C. For example, T-states generated by local T-state distillation factories on the same quantum processor module (e.g., the T-state distillation factories 1306, 1408 as shown in FIGS.13-14) can be only locally consumed during a graph consumption operation. For example, when T-states are generated outside the quantum processor module (e.g., the quantum processor module 1504, 1700 shown in FIGS.15, 17), T-states can’t be shared or reused between different quantum processor modules. In some cases, T-states can be generated non-locally (e.g., on a separate quantum processor module) and teleported in a similar way as teleporting the quantum states between input and output nodes of different quantum processor modules. Magic states or T states can be used to serve all ^ and ei-type nodes (at most there are ⌈^X9^7^^89⌉ of the T and Rz-type node in a bi-linear quantum bus) in at last portion of the quantum bus inside of a quantum processor module, which needs to be measured according to a consumption schedule of the graph consumption operation 804A, 804B, 804C. To facilitate this process, a subgroup of logical qubits can be used to form a T-transfer bus to facilitate the storage, queueing and transferring of the T states. The T-transfer bus queues up to  ^^8^^:^^)v^^= (^^67^− ^­v^^− ^6^^^^9^^99^^^^^¿^«G%F(^√^^Á)^^67^+ ^6^^^^9^^99^^^^^¿^«G%F(^√^^Á distilled magic states, which arefactory at the or previous graphThe T-transfer bus has a ^ buffer area of at least width-2 which communicates with the ancilla logical qubits of the bi-linear quantum bus on an entire edge of the quantum processor module, guaranteeing at worst ^6^^^^99^^^^^that the T states can be sent to the ancilla logical qubits in the rail (e.g., the rail 1304, 1404 as shown in FIGS.13, 14) through ½(1) operations.

[0232] As discussed, T-states are provided locally by ^6^^^^99^^^^^magic state distillation factories laid out among the remaining physical qubits in a comb-like pattern continuously touching the T-transfer bus. There will be ^6^^^^9^^99^^^^^= ⌊ÀGEFG)À¨©'H)!² ⌋ and  ­v^^= ⌈#X«¯F$°±«⌉ columns of T factories, which feed theat all stepsto the quantum program and widget accuracy, the suitable magic stateAttorney Docket No.: RIGET-125WO1 distillation factory (T-state distillation factory) can be selected from the options outlined in the example table 2500 shown in FIG.25.

[0233] In some implementations, during a graph consumption operation, Bell states can be prepared between the T-states from the T-state distillation factories or the T-state transfer bus and the data logical qubits via the ancilla logical qubits by performing T-gate operations. The ancilla logical qubits can be measured by performing single-qubit measurements in different basis (e.g., Pauli-X, Pauli-Y or rotated bases) depending on the quantum program; and based on the output, conditional logical operations such as Pauli corrections can be performed on the data logical qubits to correct for any introduced phase shifts. In some instances, the measurement basis for each qubit might need to be adjusted based on the outcomes of previous measurements. In some instances, measurements on each qubit effectively enact a specific quantum logical gate on the remaining unmeasured qubits. In some instances, the graph consumption operation 804A, 804B, 804C can produce output Bell pairs, which can be teleported to the next quantum processor module via the coherent links during teleportation operations 806A, 806B for processing. In some instances, the graph consumption operation 804A, 804B, 804C may be implemented as the graph consumption operation 1802 and the teleportation operations 1806 shown in FIG. 18.

[0234] As shown in FIG.8, the first quantum processor module 812A can prepare a first graph state for a first compiled quantum circuit widget while the second quantum processor module 812B can consume a second graph state of a second compiled quantum circuit widget immediately prior to the first compiled quantum circuit widget. In some implementations, after graph consumption operation on the second quantum processor module, output nodes of the second graph state can be teleported to input nodes of the first graph state for consumption. In some instances, a set of output Bell pairs are transferred during the teleportation operations 806A, 806B. These operations can be repeated until all compiled quantum circuit widgets are processed and the quantum program is executed.

[0235] FIG.9 is a schematic diagram showing aspects of an example modular quantum processing unit 900. As shown in FIG.9, the modular quantum processing unit 900 includes six quantum processor modules 904-1A, 904-2A, 904-3A, 904-1B, 904-2B, and 904-3B. TheAttorney Docket No.: RIGET-125WO1 quantum processor modules 904-1A, 904-2A, 904-3A are communicably connected via respective coherent links 908-1A, 908-2A. The quantum processor modules 904-1B, 904- 2B, and 904-3B are communicably connected via respective coherent links 908-1B, 908-2B. The modular quantum processing unit 900 may be enclosed in a cryostat 902 of a cryogenic system, in which the example modular quantum processing system 900 is exposed to a cryogenic environment of very low temperature (e.g., T < 120 K).and very low pressure (e.g., in the range of 10-3mbar to 10-9mbar) in the cryostat 902. The cryogenic system may include thermal stages, and refrigeration systems thermally coupled to the thermal stages. In some instances, the modular quantum processing system 900 resides on the lowest-temperature thermal stage and can receive control signals and transmit readout signals to devices and systems residing outside of the cryostat 902. In some instances, the example modular quantum processing unit 900 may include additional or different features, and the components may be arranged in another manner. For example, the example quantum processing unit 900 may include more than six quantum processor modules; and the quantum processor modules may be connected with one another in a different manner.

[0236] In some instances, each quantum processor module 904 includes multiple quantum processor chips on a substrate. Each quantum processor chip includes a superconducting quantum circuit with multiple quantum circuit devices (e.g., qubit devices) connected in an error check pattern and provides the functionality of a logical qubit. In some implementations, a qubit device may be a data qubit device, a stabilizer / ancilla qubit device, or other types of qubit devices. Each quantum processor chip also includes intra-chip circuit connections (e.g., coupler devices 1214 in the example quantum processor module 1200 in FIG.12) which provides couplings between qubit devices on the same chip to apply multi-qubit quantum logic gates or types of operations to qubits defined by the qubit devices. Quantum logic gates mediated by intra-chip circuit connections can be used to create entanglement between qubits defined by qubit devices within the respective quantum processor chip.

[0237] Each quantum processor chip includes boundary qubit devices also communicably connected to boundary qubit devices from neighboring quantum processorAttorney Docket No.: RIGET-125WO1 chips via inter-chip circuit connections (e.g., the inter-chip coupler devices 1216 in the example quantum processor module 1200 shown in FIG.12). Each logical qubit is coupled with its nearest neighbors. In some instances, the logical qubits may be configured on the quantum processor module in a square lattice or in another manner. In some instances, qubit devices from different quantum processor chips can be connected in an error check pattern and can support a single logical qubit. In some instances, the quantum processor module may be implemented as the example quantum processor module 1200 shown in FIG.12 or in another manner.

[0238] In some implementations, each quantum processor module 904 includes multiple quantum buses, each of which includes multiple interconnected quantum processor chips or logical qubits to facilitate communication of quantum information within the quantum processor module. In some implementations, each quantum bus is designed to transfer quantum states or entangle logical qubits across different sections of the quantum processor module. In some implementations, quantum processor chips of each quantum processor module are parsed; control signals for performing quantum logic operations are applied to qubit devices and inter-chip coupler devices to form the respective quantum buses. In other words, a subset of quantum processor chips in a quantum processor module are arranged in a bus-like structure enabling the modular graph state processing. For example, each quantum processor module 904 may be configured as the quantum processor module 1300, 1400, 1600 shown in FIGS.13-14, 16, or in another manner.

[0239] In some instances, all six quantum processor modules 904-1A, 904-2A, 904-3A, 904-1B, 904-2B, and 904-3B may be identically configured to have the same architecture. In particular, all six quantum processor modules 904-1A, 904-2A, 904-3A, 904-1B, 904-2B, and 904-3B may have the same number of logical qubits; the same number and layout of ancilla logical qubits in first quantum buses; and the same number and layout of data logical qubits in second quantum buses. In some instances, when each quantum processor module includes T-state distillation factories, all six quantum processor modules 904-1A, 904-2A, 904-3A, 904-1B, 904-2B, and 904-3B may have the same number and layout of logical qubits for T-state distillation factories. In some instances, when each quantumAttorney Docket No.: RIGET-125WO1 processor module includes a T-state transfer bus, all six quantum processor modules 904- 1A, 904-2A, 904-3A, 904-1B, 904-2B, and 904-3B may have the same number or layout of logical qubits for T-state transfer buses.

[0240] As shown in FIG.9, the logical qubits from the quantum processor modules 904- 1A, 904-2A, 904-3A can be configured to execute a first compiled quantum circuit widget, which includes schedules of a first graph state representation produced from a graph state compilation process of a first quantum circuit widget; and the logical qubits from the quantum processor modules 904-1B, 904-2B, and 904-3B can be configured to execute a second compiled quantum circuit widget, which includes schedules of a second graph state representation produced from a graph state compilation process of a second quantum circuit widget. Each quantum processor modules 904 is configured to handle a respective portion of the graph state processing. In other words, the logical qubits defined in the quantum processor modules 904-1A, 904-2A, 904-3A are used to execute the schedules graph state creation, consumption, and magic state distillation, and transfer for local T- state processing associated with the first compiled quantum circuit widget. The logical qubits defined in the quantum processor modules 904-1B, 904-2B, 904-3B are used to execute the schedules graph state creation, consumption, and magic state distillation, and transfer for local T-state processing associated with the second compiled quantum circuit widget. In some instances, entangled quantum logic gates and measurement can be achieved by the corresponding coherence links 908-1A, 908-2A allowing a fully connection of logical qubits in different quantum processor modules 904-1A, 904-2A, 904-3A; and entangled quantum logic gates and measurement can be achieved by the corresponding coherence links 908-1B, 908-2B allowing a fully connection of logical qubits in different quantum processor modules 904-1B, 904-2B, 904-3B. For example, the modular quantum processing unit 900 may be used to perform the modular graph state processing shown in FIG.10 or in another manner.

[0241] FIG.10 is a schematic diagram showing a portion of an example process 1000 for performing a modular graph state processing. In some instances, the example process 1000 includes operations that can be performed in a timely manner from right to left as indicated by the X-axis. Operations occurring during the same time period can be performed inAttorney Docket No.: RIGET-125WO1 parallel on separate quantum computing resources. In some implementations, the example process 1000 is used to execute three compiled quantum circuit widgets in a compiled quantum program obtained from a graph state compilation process. In some instances, the example process 1000 may be implemented as the operation 210 in the example process 200 shown in FIG.2. In some instances, the example process 1000 can be performed by operations of a modular quantum processing unit with multiple quantum processor modules. The compiled quantum program contains a sequence of compiled quantum circuit widgets. Each compiled quantum circuit widget includes a graph state representation of a corresponding to a quantum circuit widget obtained from a segmentation process of a quantum program. Each compiled quantum circuit widget can be assigned to and executed by operation of a quantum processor module. In some instances, neighboring compiled quantum circuit widgets are not assigned to or executed on the same quantum processor module.

[0242] As shown in FIG.10, the first compiled quantum circuit widget represented by a first graph state representation 1022A is assigned to and to be executed on a first set of quantum processor modules (e.g., the quantum processor modules 904-1A, 1B, 1C in FIG. 9) and a second compiled quantum circuit widget represented by a second graph state representation 1022B is assigned to and to be executed on a second set of quantum processor modules (e.g., the quantum processor modules 904-2A, 2B, 2C in FIG.9). The sequence also includes a third compiled quantum circuit widget represented by a third graph state representation 1022C. The third graph state representation 1022C is assigned to and to be executed on the first set of quantum processor modules (e.g., the quantum processor modules 904-1A, 1B, 1C in FIG.9).

[0243] As shown in FIG.10, executing each of the first, second, and third graph state representations 1022A, 1022B, 1022C includes performing a measurement-based quantum computing (MBQC) process. This framework allows quantum computation to be carried out by performing a series of single-qubit measurements on the graph state, rather than directly manipulating the qubits through quantum gates. As shown in FIG.10, a MBQC process associated with the execution of the first graph state representation 1022A includes a first graph preparation operation 1002A and a first graph consumptionAttorney Docket No.: RIGET-125WO1 operation 1004A. A MBQC process associated with the execution of the second graph state representation 1022B includes a second graph preparation operation 1002B and a second graph consumption operation 1004B. A MBQC process associated with the execution of the third graph state representation 1022C includes a third graph preparation operation 1002C and a third graph consumption operation 1004C.

[0244] In some implementations, during a graph preparation operation 1002A, 1002B, 1002C, a respective graph state is prepared. For example, each physical qubits within a logical qubit can be initialized in a defined state, e.g., |0^ state. After initalization, a single- qubit qunatum logic gate, e.g., a Hadamard gate, can be aplied ot each initialized logical qubit to create a superposition of |0^ and |1^ states on each qubit. In some instances, the state graph is built by applying a CZ gate between pairs of logical qubits to create entanglements based on the desired graph topology. In some instances, on the physical qubit level, quantum logic operations such as single-qubit operations including Pauli X, Y or Z rotations, stabilizer measurements, two-qubit operations such as CZ gates, and other quantum logical operations can be performed.

[0245] In some implementations, each graph preparation operation 1002A, 1002B, 1002C is accomplished through hybrid intra and inter-module operations performed on the first set of quantum processor modules (e.g., the quantum processor modules 904-1A, 904-2A, 904-3A of the quantum processing unit 900 shown in FIG.9). Each quantum processor module has an intra-module architecture of a continuous comb-shape layout of bilinear quantum buses of data logical qubits and ancilla logical qubits as the quantum buses. In some instances, a full bi-linear quantum bus of data logical qubits or ancilla logical qubits has the logical size of ^X9^7^^89(e.g., 2^X9^7^^89patches in total); it is shared in-between all ^^^^)9^7^^6^9^^modules on one leg of the macro-architecture communicating through ^-wide inter-module connections (e.g., the coherent links 908-1A, 908-2A). In some instances, each quantum processor module of the first set can host 2⌈^X9^7^^89 / ^^^^)9^7^^6^9^^⌉ patches of logical qubits of the quantum bus except the last quantum processor module of the first set (e.g., the quantum processor module 904-3A in FIG.9) which may host the remaining 2(^X9^7^^89− (^^^^)9^7− 1)^^^)9^7⌉) patches of logical qubits. Each portion of theAttorney Docket No.: RIGET-125WO1 quantum bus is allocated to an entire edge of a quantum processor module (e.g., the quantum buses 1402, 1404 of the quantum processor module 1400 in FIG.14) and may take up as much of the quantum processor module as required to consistently execute the graph state processing for ⌈^X9^7^^89 / ^^^^)9^7^^6^9^^⌉ patches of logical qubits originated from the input quantum program. In some instances, all quantum process modules may include the same intra-chip architecture. For example, the last module (e.g., the quantum processor module 904-3A) with potentially fewer patches is kept the same for consistency.

[0246] In some implementations, the MBQC process performed on each quantum processor module applies measurements to each logical qubit on one rail of the bi-linear bus (e.g., the quantum bus 1302, 1402 of data logical qubits as shown in FIGS.13-14) mediated by the logical qubits on the other rail (e.g., the quantum bus 1304, 1404 of ancilla logical qubits as shown in FIGS.13-14). In some implementations, the quantum bus pattern is at least 3-tile wide to support the graph state processing; the logical width of the bi- linear bus inside each quantum processor module can be calculated as  ­v^^= ⌈#Xª«¯F$c°±^«⌉. ^⌊ GEFG³ ⌋N!In some instances, the layout for embedding this pattern depends on therequirements.

[0247] In some implementations, during a graph consumption operation 1004A, 1004B, 1004C, since the quantum circuit widget before compilation requires the application of non-Clifford gates (such as the T-gate), T-states are generated and injected in the graph consumption operation. In some instances, T-states can be prepared, transferred and consumed locally on the same quantum processor module (e.g., the quantum processor module 1300, 1400 in FIGS.13, 14) or remotely from a distinct quantum processor module (e.g., the quantum processor module 1502C, 1700 shown in FIGS.15 and 17) and teleported through a coherent link. In some instances, T-states are used to inject the non- Clifford gates into the computation. In some instances, non-Clifford gates are not directly applied to the qubits in graph state. Instead, a non-Clifford gate is applied through a process of magic state injection or state distillation. For example, during the state distillation process, raw T-states for implementing non-Cliford gates, can be generated by operation of a T-state distillation factory. The raw T-states can then be processed byAttorney Docket No.: RIGET-125WO1 running distillation protocols, e.g., taking multiple raw T-states and combining them through a series of quantum operations, producing distilled and purified T-states with higher fidelity which are ready to be used in quantum logical operations, e.g., the non- Clifford gates. The distilled T-states can then be transferred from the T-state distillation factories to the bi-linear quantum bus for processing. In particular, the distilled T-states can be transferred through a series of quantum operations by operation of logical qubits in a T-state transfer bus (e.g., the T-state transfer bus 1406) connecting the T-state distillation factories and a quantum us of ancilla logical qubits.

[0248] In some instances, the bi-linear quantum bus is also the end-point for executing the graph consumption operations 1004A, 1004B, 1004C. For example, T-states generated by local T-state distillation factories on the same quantum processor module (e.g., the T- state distillation factories 1306, 1408 as shown in FIGS.13-14) can be only locally consumed during a graph consumption operation. For example, when T-states are generated outside the quantum processor module (e.g., the quantum processor module 1504, 1700 shown in FIGS.15, 17), T-states can’t be shared or reused between different quantum processor modules. Magic states or T states can be used to serve all nodes labeled with T-measurement for consumption schedule (at most there are ⌈^X9^7^^89 / ^^^^)9^7^^6^9^^⌉ of the such nodes) in at last portion of the quantum bus inside of a quantum processor module, which needs to be measured according to that consumption schedule. To facilitate this process, a subgroup of logical qubits can be used to form a T-transfer bus to facilitate the storage, queueing and transferring of the T states. The T-transfer bus queues up to  ^^8^^:^^)v^^= (^^67^− ^­v^^− ^6^^^^9^^99^^^^^¿^«G%F(^Á)^^67^+ ^6^^^^9^^99^^^^^¿^«G%F(^Á distilledat the current or previous graphThe T-transfer bus has ^ buffer area of at least width-2, displayed in FIG.14, which meets the ancilla logical qubits of the quantum bus on an entire edge of the fridge, guaranteeing at worst ^6^^^^99^^^^^that the T states can be sent to the ancillae rail through ½(1) operations.

[0249] As discussed, T-states are provided locally by ^6^^^^99^^^^^magic state distillation factories laid out among the remaining physical qubits in a comb-like pattern continuouslyAttorney Docket No.: RIGET-125WO1 touching the T-transfer bus. There will be ^6^^^^9 À^^99^^^^^= ⌊GEFG)À¨©'H)!²«G⌋ and  ­v^^= ^%F(^√^¤N!⌈#X«¯F$°±«ªGE c^⌉ columns of T factories, which feed the at all steps as ^⌊FG³ ⌋N!to the total algorithm and widget accuracy, the suitable magic statefactory can be selected from the options outlined in the example table 2500 shown in FIG.25.

[0250] In some implementations, during a graph consumption operation, Bell states can be prepared between the T-states from the T-state distillation factories or the T-state transfer bus and the data logical qubits via the ancilla logical qubits by performing T-gate operations. The ancilla logical qubits can be measured by performing single-qubit measurements in different basis (e.g., Pauli-X, Pauli-Y or rotated bases) depending on the quantum program; and based on the output, conditional logical operations such as Pauli corrections can be performed on the data logical qubits to correct for any introduced phase shifts. In some instances, the measurement basis for each qubit might need to be adjusted based on the outcomes of previous measurements. In some instances, measurements on each qubit effectively enact a specific quantum logical gate on the remaining unmeasured qubits. In some instances, the graph consumption operation 1004A, 1004B, 1004C can produce output Bell pairs, which can be teleported to the next quantum processor module via the coherent links during teleportation operations 1006A, 1006B for processing.

[0251] In some implementations, the quantum processor modules in the same set are interconnected using ancilla logical qubits. In some instances, the systems and techniques presented here can allow the architecture scalable to quantum programs or algorithms that may require more quantum computing resources and time resources.

[0252] In some instances, the widgetization of the logical algorithm may allow for some degree of parallelization between quantum processor modules in different sets. As shown in FIG.10, quantum processor modules in a first set can prepare a first graph state for a first compiled quantum circuit widget while quantum processor modules in a second distinct set can consume a second graph state of a second compiled quantum circuit widget immediately prior to the first compiled quantum circuit widget. In some implementations,Attorney Docket No.: RIGET-125WO1 after graph consumption operation on the second quantum processor module, output nodes of the second graph state can be teleported to input nodes of the first graph state for consumption. These operations can be repeated until all compiled quantum circuit widgets are processed and the quantum program is executed.

[0253] In some implementations, the time required to execute the schedules of compiled quantum program on a quantum processing unit including multiple quantum processor modules and operated as shown in the example processes 200, 800, 1000 shown in FIGS.2, 8, 10 can be estimated. To do this, the teleportation interaction between quantum processor modules can be abstracted as a single time described as an inter- module handover time, which is assumed to be 1 ;s or another value. In some instances, timing required for any schedule operations cross a cryostat boundary is also assumed to be 1 ;s or another value. In some instances, the total handover time depends on the code distance required for the algorithm.

[0254] In addition to algorithmic execution times and logical qubit resources, other hardware resources required to execute a given quantum program can be estimated, including signal line counts, functional chip area, number of amplifiers, etc. For superconducting qubits that operate at millikelvin temperatures, heat loads are a primary concern, and power consumption to operate the computer can be estimated.

[0255] In some implementations, cryogenic energy consumption calculations for this architecture are based on per-line thermal loads. These are calculated to assume a signaling solution with all-superconducting input and output lines below 4K, with conventional dispersive readout using a Traveling Wave Parametric Amplifier (TWPA) and High-Electron-Mobility Transistors (HEMT). Each physical qubit device is assumed to require a microwave line for XY control and a flux bias line for tuning qubit frequency (e.g., the signal lines 1106A, 1106B of the qubit device 1102 as shown in FIG.11). Each pair of physical qubit devices has a tunable coupler device that requires a single flux line (e.g., the signal line 1108 of the coupler device 1104 as shown in FIG.11). Dispersive readout is assumed to read out 10 physical qubit devices multiplexed in parallel. In some instances, heat loads that are dominated by HEMT dissipation, static heat loads and other heat load, can be considered. The power consumed by the general system is scaled by roughAttorney Docket No.: RIGET-125WO1 estimates for the power required to operate 4K cryo-plants (e.g., 500 kW of power for 500 W of cooling in 4 K) and dilution refrigerators (e.g., 1 kW of power for 1 ;W of cooling at 20 mK).In certain examples, these estimates may change over time, as they depend on detailed designs of the signal chain.

[0256] FIG.11 is a schematic diagram of a top view of an example superconducting quantum processing unit 1100. The example superconducting quantum processing unit 1100 includes superconducting circuitry with quantum circuit devices. As shown in FIG.11, the quantum circuit devices in the example superconducting quantum processing unit 1100 include qubit devices 1102 communicably coupled to a qubit device 1102 through respective coupler devices 1104.

[0257] In some examples, the qubit devices 1102 and the coupler devices 1104 may be implemented as tunable-frequency qubit devices, and the features and components represented in FIG.11 can be extended in a larger two-dimensional or three-dimensional array of devices. For example, each of the qubit devices 1102 may be further coupled to a distinct qubit device through a distinct coupler device. In some implementations, the example superconducting quantum processing unit 1100 represents a 4-qubit system in a device array with a square lattice. The example superconducting quantum processing unit 1100 may include additional or different features and components, which may be configured in another manner. For example, the quantum processing unit 1100 may include respective readout resonator devices associated with the qubit devices 1102 for performing readout operations.

[0258] Each of the qubit devices 1102 and the coupler devices 1104 may include a SQUID loop that has two Josephson junctions connected in parallel. In some implementations, each of the SQUID loops can be inductively coupled to (has a mutual inductance with) a respective signal line 1106, 1108, which can individually tune a magnetic flux in a respective superconducting circuit loop. The control lines 1106A, 1106B, 1108 are connected to an external control system (e.g., the control system 105 in FIG.1) which is configured to generate respective flux control signals. In some instances, each of the qubit devices 1102 and the coupler devices 1104 may include a pair of qubit electrodes. In some instances, the qubit devices 1102 and the coupler devices 1104 may includeAttorney Docket No.: RIGET-125WO1 additional or different features and may operate as described with respect to FIG.11 or in another manner.

[0259] In some instances, the signal lines 1106A / 1106B, 1108 receive control signals from a control system (e.g., the control system 105 shown in FIG.1) to respective qubit devices 1102 and respective coupler devices 1104 (e.g., to activate or deactivate coupling between a pair of tunable-frequency qubit devices). The signal lines 1106, 1108 may be flux bias control lines and / or XY qubit control lines that control signals and perform two- qubit quantum logic gates, or other types of quantum control operations. In particular, the quantum processing unit 1100 includes qubit control lines 1106 for respective qubit devices 1102; and coupler control lines 1108 for respective coupler devices 1104.

[0260] In some instances, each control line 1106, 1108 is inductively coupled to a respective SQUID loop of the respective quantum circuit device. In some instances, each control line 1106, 1108 may be also capacitively coupled to each of the two electrodes from the same quantum circuit device. In certain instances, each of the two electrodes may be also capacitively coupled to nearby control lines associated with neighboring quantum circuit devices, e.g., through parasitic capacitance.

[0261] The qubit devices 1102 and the coupler devices 1104 shown in FIG.11 resides on the top surface of a substrate. In certain instances, the substrate may be implemented as the substrate of the quantum processor chip 1104 in FIG.11. The superconducting circuitry of the superconducting quantum processing unit 1100 includes superconductive materials and can be formed by patterning one or more superconductive (e.g., superconducting metal) layers or other materials on the surface of the substrate. The control lines 1106, 1208 may reside on a surface of a different substrate separated from the substrate.

[0262] To determine the number of qubits built into a single module and the overall size of the QPU in that module, the pitch of the qubits is needed. In this tunable coupled transmon architecture, each qubit and coupler require a minimum of 1 control line each, plus an additional microwave line shared among qubits for multiplexed readout. While most quantum processors use perimeter wire bonding for individual control lines, many proposals and demonstrations address qubits individually using through-substrate vias (TSVs). Using this approach, QPUs require a via per qubit and a one per tunable coupler.Attorney Docket No.: RIGET-125WO1 Each signal line requires at least one ground line for return currents. As shown schematically in FIG.11, a sufficient number of signal and ground connections can be applied if the qubit pitch 8Ñis 4x the via pitch 8<. Ultimately, the tunable qubit devices, the tunable coupler devices, and TSVs can all be made with less than 100 ;m pitch, however, the bottleneck is in the input / output: each signal via needs to be interfaced to some kind of wiring and ultimately control electronics. Any significant fanout near the qubit chip itself would be costly, therefore a compliant joint to form a re-usable interconnect with a printed circuit board can be assumed. Under this assumption, a 8<= 250 ;m interposer would result in a 8Ñ= 1 mm. This results in a qubit density of 1 million qubits / m^in the architectural model.

[0263] FIG.12 is a block diagram showing a top view of an example modular quantum processing unit 1200. The modular quantum processing unit 1200 includes a quantum processor module 1222. The quantum processor module 1222 includes an array of quantum processor chips 1204 on a substrate 1202. Each quantum processor chip 1204 includes a superconducting quantum circuit with an array of qubit devices. As shown in FIG.12, qubit devices 1212A / 1212B at the edges of neighboring pairs of quantum processor chips 1204 are connected to each other through inter-chip coupler devices 1216. The inter-chip coupler devices 1216 may be capacitive, inductive, galvanic, or combinations of these. The inter-chip coupler devices 1216 are provided by circuitry on the substrate 1202, which is operably connected to ports, leads, bonds or other types of hardware interfaces on the respective quantum processor chips 1204. Couplings provided by the inter-chip coupler devices 1216 can be used to apply multi-qubit quantum logic gates or other types of operations to qubits in distinct quantum processor chips. The quantum logic gates mediated by the inter-chip coupler devices 1216 may be used to provide entanglement between qubit devices in distinct quantum processor chips 1204; in some cases, other schemes such as remote multi-qubit measurement can be used to entangle qubit devices in distinct quantum processor chips 1216.

[0264] The quantum processor chips 1204 of the quantum processor module 1222 can be arranged on the substrate 1202 as an array in a two-dimensional or three-dimensional lattice structure. Eleven of the quantum processor chips 1204 in the quantum processorAttorney Docket No.: RIGET-125WO1 module 1222 are shown in FIG.12, but the quantum processor module 1222 is scalable to include many more quantum processor chips 1204 (e.g., tens, hundreds, thousands, etc.). In some instances, the modular quantum processing unit 1200 includes multiple quantum processor modules 1222, where each of the multiple quantum processor modules 1222 includes a substrate 1202 supporting a subset of quantum processor chips 1204 of the modular quantum processing unit 1200. In this case, qubit devices 1212 residing at the edges of the quantum processor chips 1204 that reside at the edges of neighboring quantum processor modules 1222 may be communicably coupled to each other through inter-module coupler devices 1216. In some implementations, the multiple quantum processor modules 1222 may be supported on a common carrier substrate which includes superconducting circuitry. The inter-module coupler devices 1206 may be part of the superconducting circuitry of the common carrier substrate. In some implementations, the example modular quantum processing unit 1200 may include additional and different features or components and components of the example modular quantum processing unit 1200 may be implemented in another manner.

[0265] In the example shown in FIG.12, the quantum processor chips 1204 are arranged in a rectilinear (e.g., rectangular, or square) array on the substrate 1202 that extends in two spatial dimensions (e.g., along the X-Y plane) on a surface of the substrate 1202. In some implementations, the quantum processor chips 1204 can be arranged in another type of ordered array. In some instances, the rectilinear array also extends in a third spatial dimension (e.g., along the Z axis), for example, to form a cubic array or another type of three-dimensional module assembly.

[0266] In some implementations, each of the quantum processor chips 1204 in the quantum processor module 1222 of the modular quantum processing unit 1200 includes a superconducting quantum circuit. In some implementations, a superconducting quantum circuit of the quantum processor chips 1204 includes one or more qubit devices 1212 that can operate collectively as a logical qubit, or as multiple logical qubits. In certain instances, the superconducting quantum circuit of a quantum processor chip 1204 includes quantum circuit devices, such as fixed-frequency qubit devices, tunable-frequency qubit devices, coupler devices, readout resonators, or other types of quantum circuit devices. In someAttorney Docket No.: RIGET-125WO1 examples, each of the qubit devices in a quantum processor chip 1204 can be encoded with a single bit of quantum information.

[0267] Typically, each of the qubit devices in a quantum processor chip 1204 has two eigenstates that are used as computational basis states (e.g.,|0^and|1^), and each qubit device 1212 can transition between its computational basis states or exist in an arbitrary superposition of its computational basis states. In some examples, the two lowest energy levels (e.g., the ground state and first excited state) of each qubit device are defined as a qubit and used as computational basis states for quantum computation. In some examples, higher energy levels (e.g., a second excited state or a third excited state) can be used to define a qubit, a qutrit, or a multi-level quantum computational device in some instances. Quantum states (e.g., qubits) are defined by respective qubit devices in a single quantum processor chip 1204 can be manipulated by control signals, or read by readout signals, generated by a control system, e.g., the control system 105 in FIG.1. The qubit devices in a single quantum processor chip 1204 can be controlled individually, for example, by delivering control signals from a control system to the respective qubit devices in the quantum processor chip 1204. In some cases, readout devices can detect the states of the qubit devices, for example, by interacting directly with the respective qubit devices.

[0268] Although each individual qubit device defines a single qubit, a lattice of qubit devices in a quantum processor chip 1204 may operate collectively as a single logical qubit. For example, a stabilizer code or another type of quantum error correction scheme can be applied to the lattice of qubit devices. In some cases, one of the qubit devices operates as a data qubit, other qubit devices in the lattice operate as ancilla qubits, and a quantum error correction scheme is applied to the lattice. The ancilla qubits may be used to detect an error syndrome, which can be used to correct errors on the data qubit. Examples of stabilizer codes include surface codes, color codes and other types of quantum error correcting codes. Accordingly, a quantum processor chip 1204 may include qubit devices, connections among the qubit devices, and potentially other hardware features that define an appropriate lattice for one or more quantum error correction codes to be applied.

[0269] In some instances, all of the quantum processor chips 1204 may include the same superconducting quantum circuit with the same circuit design and the same functionality. For example, two quantum processor chips 1204 in the quantum processorAttorney Docket No.: RIGET-125WO1 module 1222 may include identical circuit design, e.g., the same number of qubit devices, arrangements of signal lines, etc. In this case, two quantum processor chips 1204 in the quantum processor module 1222 may be fabricated through the same fabrication process.

[0270] In certain instances, the quantum processor chips 1204 may include different superconducting quantum circuits with distinct circuit designs and distinct functionalities. For example, two quantum processor chips 1204 in the quantum processor module 1222 have different numbers of qubit devices, different connections (e.g., different intra-module connections) between qubit devices, different arrangements of signal lines, etc. In this case, two quantum processor chips 1204 in the quantum processor module 1222 are fabricated using different fabrication processes. In some cases, multiple different fabrication processes are used to produce a batch of quantum processor chips 1204. In certain instances, design and fabrication processes of superconducting quantum circuit of different quantum processor chips 1204 may be separately optimized.

[0271] In some instances, after fabrication, the quantum processor chips 1204 may be evaluated, for example, using qubit frequency testing, optical micrograph analysis, gate performance testing, coherence time testing, and other types of testing. The evaluations can be used to characterize the quantum processor chips 1204 according to their design specifications. In some cases, the quantum processor chips 1204 may be categorized based on the evaluation results. For example, quantum processor chips 1204 may be sorted into multiple categories based on pre-determined criteria for each category. In some cases, the categories are indicative of a relative quality of a quantum processor module. In some cases, the categories are indicative of the functionality of a quantum processor chip 1204, the number of working qubit devices in a quantum processor chip 1204, the connectivity of the qubit devices at the edges of a quantum processor chip 1204, or a combination of these and other criteria. A subset of the quantum processor chips 1204 may be selected from appropriate categories based on a specified performance level for the modular quantum processing unit 1200.

[0272] The superconducting QuIC in a quantum processor chip 1204 shown in FIG.12 is fabricated on a substrate. In certain instances, the substrate supporting the superconducting QuIC in a quantum processor chip 1204 may be an elemental semiconductor, for example silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), orAttorney Docket No.: RIGET-125WO1 another elemental semiconductor. In some instances, the substrate may also include a compound semiconductor such as aluminum oxide (sapphire), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GaInP), or another compound semiconductor. In some instances, the substrate may also include a superlattice with elemental or compound semiconductor layers. In certain instances, the substrate includes an epitaxial layer. In some examples, the substrate may have an epitaxial layer overlying a bulk semiconductor or may include a semiconductor-on-insulator (SOI) structure.

[0273] The superconducting quantum circuit in a quantum processor chip 1204 may include superconductive materials and can be formed by patterning one or more superconductive (e.g., superconducting metal) layers or other materials on the surface of the substrate 1202. In some implementations, each of the one or more superconductive layers include a superconducting metal, such as aluminum (Al), niobium (Nb), tantalum (Ta), titanium (Ti), rhenium (Re), vanadium (V), tungsten (W), zirconium (Zr), or another superconducting metal. In some implementations, each of the one or more superconductive layers may include a superconducting metal alloy, such as molybdenum-rhenium (Mo / Re), niobium-tin (Nb / Sn), or another superconducting metal alloy. In some implementations, each of the superconductive layers may include a superconducting compound material, including superconducting metal nitrides and superconducting metal oxides, such as titanium-nitride (TiN), niobium-nitride (NbN), zirconium-nitride (ZrN), hafnium-nitride (HfN), vanadium-nitride (VN), tantalum-nitride (TaN), molybdenum-nitride (MoN), yttrium barium copper oxide (Y-Ba-Cu-O), or another superconducting compound material. In some instances, the superconducting quantum circuit in a quantum processor chip 1204 may include multilayer superconductor-insulator heterostructures.

[0274] In some implementations, the superconducting quantum circuit in a quantum processor chip 1204 is fabricated on the top surface of a substrate and patterned using a microfabrication process or in another manner. For example, quantum circuit devices in a superconducting quantum circuit of a quantum processor chip 1204 may be formed by performing at least some of the following fabrication steps: using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-onAttorney Docket No.: RIGET-125WO1 coating, and / or other suitable techniques to deposit respective superconducting layers on the substrate; and performing one or more patterning processes (e.g., a lithography process, a dry / wet etching process, a soft / hard baking process, a cleaning process, etc.) to form openings in the respective superconducting layers.

[0275] In the example shown in FIG.12, a superconducting quantum circuit in each quantum processor chip 1204 can operate as a logical qubit. The respective qubit devices in the quantum processor chip 1204 are communicably coupled with associated signal hardware and local controllers (e.g., the signal hardware 104 and the local controllers 106 shown in FIG.1 or another control system). In certain instances, logic qubit errors at the boundary of quantum processor chips 1204 can be decoded, incorporating specific properties of the inter-chip coupler devices 1216 and intra-chip connections 1214. For example, a weighted graph decoder can assign higher weight values to connections corresponding to inter-chip syndrome extraction which may have higher error rates due to more error prone inter-chip connections. This may result in an overall higher effective physical error threshold, with the decoding task having the limiting case of decoding 2D syndrome graphs for perfect intra-chip syndrome extraction. In some instances, decoding logical qubit errors allows for correlated error processes localized to one quantum processor chip 1204.

[0276] In some cases, each quantum processor chip 1204 is physically attached, bonded, or connected to the substrate 1202. As shown in FIG.12, the quantum processor chips 1204 are bonded or attached to the substrate 1202, for example, using bonding bumps. In some implementations, each of the bonding bumps may include conductive or superconductive materials, such as copper or indium bumps. In some implementations, the bonding bumps can provide electrical communication between the superconducting quantum circuit on the quantum processor chips 1204 and circuitry on the substrate 1202. In some instances, quantum circuit devices in a superconducting quantum circuit of a quantum processor chip 1204 may be communicably coupled, e.g., galvanically, capacitively, or inductively, to the circuitry on the substrate 1202. The substrate 1202 can provide functional connections (e.g., inter-chip coupler devices 1216) between distinct quantum processor chips 1204 in the quantum processor module 1222 as well as connections between quantum processor chips 1204 and the control system. In someAttorney Docket No.: RIGET-125WO1 examples, the substrate 1202 includes circuitry or other types of structures that provide control over the interactions between quantum circuit devices (e.g., qubit devices) in distinct quantum processor chips 1204 of the modular quantum processing unit 1200. For example, the substrate 1202 may include superconducting circuit elements, e.g., ancilla qubit devices or other circuit elements.

[0277] In some implementations, the circuitry on the substrate 1202 may include a variety of circuit elements to control or read out the qubit devices of the quantum processor chips 1204. For example, the circuitry may include flux bias lines which can provide magnetic flux locally to tunable-frequency qubit devices to tune their frequencies. The circuitry may include tunable coupler devices, microwave feedlines, and resonator devices which are capacitively coupled to qubit devices on the quantum processor chips 1204 to readout qubits. In some examples, the circuitry may include microwave feedlines which are coupled to one or several of the resonator devices on the quantum processor chips 1204 to allow microwave excitation of the resonator devices used to readout qubits. In this case, the circuitry may include microwave drive lines which are capacitively coupled to qubit devices of the quantum processor chips 1204 to drive qubits. In some implementations, the substrate 1202 includes deterministic, low loss wiring to mediate coherent interactions between qubit devices from different quantum processor modules 1222. In certain instances, the deterministic, low-loss wiring may include, for example, superconducting transmission lines, phononic or photonic waveguides, through-silicon vias, amplifiers, non-reciprocal elements such as circulators or isolators, switches, or another type of structure.

[0278] In some instances, the circuitry on the substrate 1202 may further include one or more electrically conductive vias. In some implementations, the electrically conductive vias include a superconducting material (e.g., Al, In, Ti, Pn, Sn, etc.). In some implementations, the circuitry can be used as a Faraday cage, which can prevent stray electric fields from reaching the quantum circuit devices on the quantum processor chips 1204. In some implementations, the circuitry may also be used to exclude stray magnetic fields from reaching the quantum circuit devices on the quantum processor chips 1204.Attorney Docket No.: RIGET-125WO1

[0279] In some implementations, the circuitry on the substrate 1202 may be formed in one or more electrically conductive layers. In other implementations, each of the one or more electrically conductive layers may include a material that has normal conductance at the operating temperature of the example modular quantum processing unit 1200. In some implementations, the example modular quantum processing unit 1200 can be operated at cryogenic temperatures (e.g., cooled using liquid helium) and each of the one or more electrically conductive layers (or at least a portion) can operate as a superconducting layer at that temperature. In some instances, the substrate 1202 may include recesses which can be used to form an enclosure to a quantum circuit device or an enclosure to a control line.

[0280] In some implementations, a subset of the one or more electrically conductive vias are electrically coupled with external signal lines, which are used to supply control signals to, or retrieve readout signals from, the quantum processor chips 1204 of the example modular quantum processing unit 1200. For example, the control signals can be provided to the quantum processor chips 1204 from a control system (e.g., the control system 105 in FIG.1) or the readout signals can be retrieved from the quantum processor chips 1204 to the control system, directly or through the substrate 1202.

[0281] In some implementations, the quantum circuit devices of the quantum processor chips 1204 include qubit devices (e.g., transmon devices, fluxonium devices, or other types of superconducting qubit devices), coupler devices, readout devices or other types of devices that are used for quantum information processing in the modular quantum processing unit 1200. The quantum circuit devices may include one or more Josephson junctions, capacitors, inductors, and other types of circuit elements.

[0282] The superconducting circuitry at various positions of the substrate 1202 may be connected through conductive pathways. For example, conductive lines including a patterned metal coating that covers a portion of the sidewalls of a recess extending from a recessed surface to the first surface can galvanically connect the circuitry on the two surfaces. For another example, the circuitry on two different surfaces may be electrically coupled through conductive vias. In some implementations, the electrically conductive vias can be used to form a continuous ground plane through the example quantum processing unit 1200, such that a solidly connected ground plane can be maintained across both theAttorney Docket No.: RIGET-125WO1 quantum processor modules 1222 and the substrate 1202. Multiple electrically conductive vias connected to the ground planes located on the first and second surfaces of the substrate 1202, and the recessed surface may be arranged in a regular array to avoid a formation of a chip-mode resonance and to mitigate unwanted modes (e.g., coupled slotline mode, parallel-plate waveguide modes, or resonant patch mode). In some instances, the circuitry at different positions of the substrate 1202 may be coupled in another manner. In some instances, the one or more electrically conductive vias may include another subset that can be used for thermalization. In this case, the substrate 1202 allows better heatsinking of the quantum circuit devices to the refrigeration system using the one or more electrically conductive vias as thermal paths for heat dissipation.

[0283] In some instances, quantum circuit devices on the quantum processor chips 1204 may be coupled via alternative signal routing levels provided by the circuitry and the electrically conductive vias on the substrate 1202. For example, non-neighboring quantum circuit devices on the same quantum processor module 1222 without qubit-to-qubit connections (e.g., direct coupling lines on the quantum processor module 1222) may be provided by the substrate 1202. In some implementations, the circuitry on the substrate 1202 may be coupled to the quantum circuit devices on the quantum processor chips 1204 using capacitive, inductive, or galvanic connections. In some instances, the circuitry on the substrate 1202 may include planar transmission lines, for example coplanar waveguides, substrate integrated waveguides or another type of planar transmission line.

[0284] In some implementations, at least one qubit device in the modular quantum processing unit 1200 is directly connected to at least one other qubit device of another modular quantum processing unit in a separate quantum computer system via a respective coherent interlink, e.g., an inter-module connection. For example, a qubit device may be directly connected to multiple other qubit devices from multiple other quantum computer systems via respective coherent interlinks. In some instances, couplings between the qubit devices and each of the coherent interlinks can be controlled (e.g., enabled or disabled) by supplying control signals from a local control system, which allows the change of the topology of the quantum computer cluster. For example, when the coherent interlink includes a superconducting transmission line and the qubit devices may be coupled to theAttorney Docket No.: RIGET-125WO1 transmission line via a respective coupler device, e.g., a tunable-frequency coupler device that may be controlled by tuning a coupler magnetic flux. In some implementations, the at least one qubit device that is connected to multiple coherent interlinks may reside at an edge of a quantum processor chip, an edge of a quantum processor module, an edge of the modular quantum processing unit, or any other locations of the modular quantum processing unit. In some implementations, a quantum computer system may be communicably coupled to other quantum computer systems in the quantum computer cluster through distinct qubit devices of the modular quantum processing unit 1200. For example, a first qubit device of a first quantum computer system may be coupled to a second quantum computer system via a first coherent interlink; and a second, distinct qubit device of the first quantum computer system may be coupled to a third quantum computer system via a second coherent interlink. In some implementations, other components or devices may be included as part of the modular quantum processing unit or the control system which allows the connection of a quantum computer system to multiple other quantum computer systems in the quantum computer cluster.

[0285] In some instances, a coherent interlink may be configured to coherently interconnect multiple pairs of qubits from the two distinct quantum computer systems by multiplexing. In some instances, a coherent interlink may include superconducting transmission lines, phononic or photonic waveguides, or may be configured in another manner.

[0286] FIG.13 is a schematic diagram showing aspects of an example quantum processor module 1300. The schematic diagram shows an example snapshot of an intra- module architecture of the quantum processor module 1300. The quantum processor module 1300 can be configured to execute a compiled quantum circuit widget during a modular graph state processing. In some instances, the compiled quantum circuit widget is obtained by performing a fault tolerant compilation, e.g., a graph state compilation by operation of a graph state compiler. In some instances, the quantum processor module 1300 can be implemented as the quantum processor modules 704A / 704B, 1100, 1200 shown in FIGS.7, 11, 12 or in another manner.Attorney Docket No.: RIGET-125WO1

[0287] As shown in FIG.13, the example quantum processor module 1300 includes multiple logical qubits; and the logical qubits are arranged in square lattice surface code patches using multiple physical qubits. The logical qubits are parsed into different subgroups configured to serve different functions. The example quantum processor module 1300 includes a first quantum bus 1302 including a first subgroup of logical qubits and a second quantum bus 1304 including a second, distinct subgroup of logical qubits. Logical qubits within the first and second quantum buses 1302, 1304 are arranged in a pattern where components are alternately positioned in a way that resembles the structure of interleaved fingers (like the structure of a comb). In particular, data logical qubits on the first quantum bus 1302 and ancilla logical qubits in the second quantum bus 1304 have a bi-linear structure (e.g., with two linear rails of logical qubits laid out in a snake-like / comb- like pattern). Each data logical qubit in the first quantum bus 1302 has a nearest logical qubit that is an ancilla logical qubit from the second quantum bus 1304. The second quantum bus 1304 directly interfaces with a third subgroup of logical qubits that is configured to function as T-state distillation factories 1306. As shown in FIG.13, the first and second quantum buses 1302, 1304 are allocated in the middle of the quantum processor module 1300 extending from one side to the opposite side of the quantum processor module 1300 along the X axis. The first and second quantum buses 1302, 1304 are configured to host data and ancilla logical qubits for graph preparation, T-state transfer, and graph consumption. The quantum processor module 1300 also includes a third subgroup of logical qubits which are configured to function as T-state distillation factories 1306. The T-state distillation factories 1306 are arranged on either ends of the quantum processor module 1300 along the Y axis. All T-state distillation factories 1306 directly interface with the second quantum bus 1304. As shown in FIG.13, some of the T- state distillation factories 1306 also interface with the first quantum bus 1302. Distilled T- states generated by the T-state distillation factories 1306 can be transferred to the second quantum bus 1304. During operation, control signals and quantum logic operations for graph preparation and consumption, distilling and teleporting T-states are applied to the logical qubits of the first and second quantum buses 1302, 1304, and the T-state distillation factories 1306. As shown in FIG.13, some of the logical qubits of the quantum processorAttorney Docket No.: RIGET-125WO1 module 1300 are not allocated for performing any operations during the modular graph state processing.

[0288] In some implementations, each T-state distillation factory 1306 includes logical qubits that are collectively operated together in a specific process or setup to generate T- state (or magic states) for quantum error correction and fault-tolerant quantum computing. The T-state is a particular quantum state required to perform non-Clifford gates. Multiple T-states generated by the T-state distillation factory 1306 and distilled to purify noisy T-states and reduce errors making them fault tolerant and useful for executing quantum programs. In some implementations, the T-state distillation factory 1306 is configured to generate reliable T-states.

[0289] FIG.14 is a schematic diagram showing aspects of an example quantum processor module 1400. The schematic diagram shows an example snapshot of the proposed intra-module architecture of the quantum processor module 1400. The quantum processor module 1400 can be configured to execute a compiled quantum circuit widget during a modular graph state processing. In some instances, the compiled quantum circuit widget is obtained by performing a fault tolerant compilation, e.g., a graph state compilation by operation of a graph state compiler. The quantum processor module 1400 enables T-state queueing and parallelization. In some instances, the quantum processor module 1300 can be implemented as the quantum processor modules 704A / 704B, 1100, 1200 shown in FIGS.7, 11, 12 or in another manner.

[0290] As shown in FIG.14, the example quantum processor module 1400 includes multiple logical qubits and the logical qubits are arranged in a square lattice surface code patches using multiple physical qubits. The logical qubits are parsed into different subgroups serving different functions. The example quantum processor module 1400 includes a first quantum bus 1402 including a first subgroup of logical qubits and a second quantum bus 1404 including a second, distinct subgroup of logical qubits. Logical qubits within the first and second quantum buses 1402, 1404 are arranged in a pattern where components are alternately positioned in a way that resembles the structure of interleaved fingers (like the structure of a comb). In particular, data logical qubits in the first quantum bus 1402 and ancilla logical qubits in the second quantum bus 1404 have a bi-linearAttorney Docket No.: RIGET-125WO1 structure. Each data logical qubit in the first quantum bus 1402 has a nearest logical qubit that is an ancilla logical qubit from the second quantum bus 1404. The second quantum bus 1404 directly interfaces with a third subgroup of logical qubits that is configured to function as a T-transfer bus 1406. As shown in FIG.14, the first and second quantum buses 1402, 1404 are allocated on one side (e.g., left side) of the quantum processor module 1400 to host data and ancilla logical qubits for graph preparation, T-state transfer, and graph consumption. The T-transfer bus 1406 is continuous and is configured to communicably connect all T-state distillation factories 1408 with the second quantum bus 1404. The T- transfer bus 1406 includes a third subgroup of logical qubits in the extending from each of the T-state distillation factories 1408 continuously to the second quantum bus 1404. In some implementations, the T-transfer bus 1406 is configured to queue and teleport T- states distilled by the T-state distillation factories 1408 on the opposite side of the quantum processor module 1400 to the first and second quantum buses 1402, 1404. The T- state distillation factories 1408 includes a fourth subgroup of logical qubits of the quantum processor module 1400. In some instances, the T-transfer bus 1406 may be configured to function as a T-state reservoir. During operation, control signals and quantum logic operations for graph preparation and consumption, distilling and teleporting T-states are applied to the logical qubits of the first and second quantum buses 1402, 1404, the T-state transfer bus 1406, and the T-state distillation factories 1408. As shown in FIG.14, some of the logical qubits of the quantum processor module 1400 are not allocated for performing any operations during the modular graph state processing.

[0291] In some implementations, each T-state distillation factory 1408 includes logical qubits that are collectively operated together in a specific process or setup to generate T- state (or magic states) for quantum error correction and fault-tolerant quantum computing. The T-state is a particular quantum state required to perform non-Clifford gates. Multiple T-states generated by the T-state distillation factory 1408 and distilled to purify noisy T-states and reduce errors making them fault tolerant and useful for executing quantum programs. In some implementations, the T-state distillation factory 1408 is configured to generate reliable T-states. In some implementations, the number of logicalAttorney Docket No.: RIGET-125WO1 qubits in the T-state transfer bus and specific arrangement of the logical qubits, e.g., shape and pattern of the T-state transfer bus may be configured in another manner.

[0292] FIG.15 is a schematic diagram showing aspects of an example modular quantum processing unit 1500. As shown in FIG.15, the modular quantum processing unit 1500 includes three quantum processor modules 1504A, 1504B, 1504C. The quantum processor modules 1504A, 1504B, 1504C are communicably connected via coherent links 1506. The modular quantum processing unit 1504A, 1504B, 1504C are enclosed in in a cryostat 1502 of a cryogenic system, in which the example modular quantum processing system 1500 is exposed to a cryogenic environment of very low temperature (e.g., T < 120 K).and very low pressure (e.g., in the range of 10-3mbar to 10-9mbar) in the cryostat 1502. The cryogenic system may include thermal stages, and refrigeration systems thermally coupled to the thermal stages. In some instances, the modular quantum processing system 1500 resides on the lowest-temperature thermal stage and can receive control signals and transmit readout signals to devices and systems residing outside of the cryostat 1502. In some instances, the example modular quantum processing unit 1500 may include additional or different features, and the components may be arranged in another manner. For example, the example quantum processing unit 1500 may include more than three quantum processor modules.

[0293] In some instances, each quantum processor module 1504A, 1504B, 1504C includes multiple quantum processor chips on a substrate. Each quantum processor chip includes a superconducting quantum circuit with multiple quantum circuit devices (e.g., qubit devices) connected in an error check pattern and provides the functionality of a logical qubit. In some implementations, a qubit device may be a data qubit device, a stabilizer / ancilla qubit device, or other types of qubit devices. Each quantum processor chip also includes intra-chip circuit connections (e.g., coupler devices 1214 in the example quantum processor module 1200 in FIG.12) which provides couplings between qubit devices on the same chip to apply multi-qubit quantum logic gates or types of operations to qubits defined by the qubit devices. Quantum logic gates mediated by intra-chip circuit connections can be used to create entanglement between qubits defined by qubit devices within the respective quantum processor chip.Attorney Docket No.: RIGET-125WO1

[0294] Each quantum processor chip includes boundary qubit devices also communicably connected to boundary qubit devices from neighboring quantum processor chips via inter-chip circuit connections (e.g., the inter-chip coupler devices 1216 in the example quantum processor module 1200 shown in FIG.12). Each logical qubit is coupled with its nearest neighbors. In some instances, the logical qubits may be configured on the quantum processor module in a square lattice or in another manner. In some instances, qubit devices from different quantum processor chips can be connected in an error check pattern and can support a single logical qubit. In some instances, the quantum processor module may be implemented as the example quantum processor module 1200 shown in FIG.12 or in another manner.

[0295] In some implementations, each quantum processor module 1504A, 1504B, 1504C includes multiple quantum buses, each of which includes multiple interconnected quantum processor chips or logical qubits to facilitate communication of quantum information within the quantum processor module. In some implementations, each quantum bus is designed to transfer quantum states or entangle logical qubits across different sections of the quantum processor module. In some implementations, quantum processor chips of each quantum processor module are parsed; control signals for performing quantum logic operations are applied to qubit devices and inter-chip coupler devices to form the respective quantum buses. In other words, a subset of quantum processor chips in a quantum processor module, thus a subgroup of logical qubits, are arranged in a bus-like structure enabling the modular graph state processing.

[0296] In some instances, the quantum processor modules 1504A, 1504B may be identically configured having the same architecture. In particular, the quantum processor modules 1504A, 1504B may have the same number of logical qubits; the same number and layout of data logical qubits in first quantum buses; and the same number and layout of ancilla logical qubits in second quantum buses. In some instances, the quantum processor modules 1504A, 1504B do not include logical qubits configured to function as T-state distillation factories. In some implementations, the third quantum processor module 1504C includes a first subgroup of logical qubits configured to function as T-state distillation factories, and a second subgroup of logical qubits arranged in a bus-like structure.Attorney Docket No.: RIGET-125WO1

[0297] As shown in FIG.15, the logical qubits from the first and third quantum processor modules 1504A, 1504C can be configured to execute a first compiled quantum circuit widget, which includes schedules of a first graph state representation produced from a graph state compilation process of a first quantum circuit widget; and the logical qubits from the second and third quantum processor modules 1504B, 1504C can be configured to execute a second compiled quantum circuit widget, which includes schedules of a second graph state representation produced from a graph state compilation process of a second quantum circuit widget. Each quantum processor modules 1504A, 1504B, 1504C is configured to handle a respective portion of the graph state processing. In other words, the logical qubits defined in the first quantum processor module 704A are used to execute the schedules graph state creation, consumption, and the third quantum processor module 1504C are used for magic state distillation. The distilled T-states can be transferred from the third quantum processor module 1504C to the first quantum processor module 1504A via the coherent link 1506 for local T-state processing associated with the first compiled quantum circuit widget. The logical qubits defined in the second quantum processor modules 1504B are used to execute the schedules graph state creation, consumption, and the third quantum processor module 1504C can be used for magic state distillation. The distilled T-state can be transferred from the third quantum processor module 1504C to the first quantum processor module 1504A via the coherent link 1506 for local T-state processing associated with the second compiled quantum circuit widget. For example, the modular quantum processing unit 1500 may be used to perform the modular graph state processing 800, 1000, 1800 shown in FIGS.8, 10, 18 or in another manner.

[0298] FIG.16 is a schematic diagram showing aspects of an example quantum processor module 1600. The schematic diagram shows an example snapshot of an intra- module architecture of the quantum processor module 1600. The quantum processor module 1600 can be configured to execute a compiled quantum circuit widget during a modular graph state processing. In some instances, the compiled quantum circuit widget is obtained by performing a fault tolerant compilation, e.g., a graph state compilation by operation of a graph state compiler. In some instances, the quantum processor moduleAttorney Docket No.: RIGET-125WO1 1600 can be implemented as the quantum processor modules 1504A, 1504B in FIG.15 or in another manner.

[0299] As shown in FIG.16, the example quantum processor module 1600 includes multiple logical qubits; and the logical qubits are arranged in square lattice surface code patches using multiple physical qubits. The logical qubits are parsed into different subgroups configured to serve different functions. The example quantum processor module 1600 includes a first quantum bus 1602 including a first subgroup of logical qubits and a second quantum bus 1604 including a second, distinct subgroup of logical qubits. Logical qubits within the first and second quantum buses 1602, 1604 are arranged in a pattern where components are alternately positioned in a way that resembles the structure of interleaved fingers (like the structure of a comb). In particular, data logical qubits on the first quantum bus 1602 and ancilla logical qubits in the second quantum bus 1604 have a bi-linear structure. Each data logical qubit in the first quantum bus 1602 has a nearest logical qubit that is an ancilla logical qubit from the second quantum bus 1604. The first and second quantum buses 1602, 1604 are configured to host data and ancilla logical qubits for graph preparation and graph consumption. During operation, control signals and quantum logic operations for graph preparation. The quantum processor module 1600 can receive distilled T-states from a distinct quantum processor module (e.g., the quantum processor module 1504C, 1700 shown in FIGS.15, 17) via one or more coherent links 1608. As shown in FIG.16, some of the logical qubits of the quantum processor module 1600 are not allocated for performing any operations during the modular graph state processing.

[0300] FIG.17 is a schematic diagram showing aspects of an example quantum processor module 1700. The schematic diagram shows an example snapshot of an intra- module architecture of the quantum processor module 1700. The quantum processor module 1700 can be configured to execute a compiled quantum circuit widget during a modular graph state processing. In some instances, the compiled quantum circuit widget is obtained by performing a fault tolerant compilation, e.g., a graph state compilation by operation of a graph state compiler. In some instances, the quantum processor module 1700 can be implemented as the quantum processor modules 1504C shown in FIG.15 or in another manner.Attorney Docket No.: RIGET-125WO1

[0301] As shown in FIG.17, the example quantum processor module 1700 includes multiple logical qubits; and the logical qubits are arranged in square lattice surface code patches using multiple physical qubits. The logical qubits are parsed into different subgroups configured to serve different functions. The example quantum processor module 1700 includes a quantum bus 1704 including a first subgroup of logical qubits. Logical qubits within the quantum bus 1704 are arranged around the boundary of the quantum processor module 1700. In particular, ancilla logical qubits in the quantum bus 1704.

[0302] The quantum bus 1704 directly interfaces with a second subgroup of logical qubits that are parsed and configured to function as T-state distillation factories 1702. As shown in FIG.17, the T-state distillation factories 1702 are allocated in the center of the quantum processor module 1700. The quantum bus 1704 is configured to host ancilla logical qubits for T-state transfer, and T-state distillation. All T-state distillation factories 1702 directly interface with the quantum bus 1704. Distilled T-states generated by the T- state distillation factories 1702 can be transferred to the quantum bus 1704. During operation, control signals and quantum logic operations for graph preparation and consumption, distilling and teleporting T-states are applied to the logical qubits of the quantum bus 1704, and the T-state distillation factories 1702. As shown in FIG.17, some of the logical qubits of the quantum processor module 1700 are not allocated for performing any operations during the modular graph state processing.

[0303] In some implementations, each T-state distillation factory 1702 includes logical qubits that are collectively operated together in a specific process or setup to generate T- state (or magic states) for quantum error correction and fault-tolerant quantum computing. The T-state is a particular quantum state required to perform non-Clifford gates. Multiple T-states generated by the T-state distillation factory 1702 and distilled to purify noisy T-states and reduce errors making them fault tolerant and useful for executing quantum programs. In some implementations, the T-state distillation factory 1702 is configured to generate reliable T-states.

[0304] FIG.18 is a schematic diagram showing a portion of an example process 1800 for performing a modular graph state processing. In some instances, the example process 1800 includes operations that can be performed in a timely manner from right to left as indicatedAttorney Docket No.: RIGET-125WO1 by the X-axis. Operations occur during the same time period can be performed in parallel on separate quantum computing resources. In some implementations, the example process 1800 is used to execute a compiled quantum circuit widget in a compiled quantum program obtained from a graph state compilation process. In some instances, the example process 1800 may be implemented as part of the operations in the example process 200, 800, 1000 shown in FIGS.2, 8, 10. In some instances, the example process 1800 can be performed by operations of a modular quantum processing unit with multiple quantum processor modules. The compiled quantum program contains a sequence of compiled quantum circuit widgets. Each compiled quantum circuit widget includes a graph state representation of a corresponding to a quantum circuit widget obtained from a segmentation process of a quantum program. Each compiled quantum circuit widget can be assigned to and executed by operation of a quantum processor module. In some instances, neighboring compiled quantum circuit widgets are not assigned to or executed on the same quantum processor module.

[0305] As shown in FIG.18, the graph consumption operation 1802 is part of a graph state processing operation. During the execution of the graph consumption operation 1802, multiple sets of magic state distillation operations 1804 and magic states teleportation operations 1806 are executed. In some implementations, during the graph consumption operation 1802, since the quantum circuit widget before compilation requires the application of non-Clifford gates (such as the T-gate), T-states are generated and injected in the graph consumption operation 1802. In some instances, T-states can be prepared, transferred and consumed locally on the same quantum processor module (e.g., the quantum processor module 1300, 1400 in FIGS.13, 14) or remotely from a distinct quantum processor module (e.g., the quantum processor module 1502C, 1700 shown in FIGS.15 and 17) and teleported through a coherent link. In some instances, T-states are used to inject the non-Clifford gates into the computation. In some instances, non-Clifford gates are not directly applied to the qubits in graph state. Instead, a non-Clifford gate is applied through a process of magic state injection or state distillation. For example, during 1804, raw T-states for implementing non-Cliford gates, can be generated by operation of a T-state distillation factor. The raw T-states can then be processed by running distillationAttorney Docket No.: RIGET-125WO1 protocols, e.g., taking multiple raw T-states and combining them through a series of quantum operations, producing distilled and purified T-states with higher fidelity which are ready to be used in quantum logical operations, e.g., the non-Clifford gates. During operation 1806, the distilled T-states can then be transferred from T-state distillation factories to the bi-linear quantum bus for processing. In particular, the distilled T-states can be transferred through a series of quantum operations by operation of logical qubits in a T-state transfer bus (e.g., the T-state transfer bus 1406) connecting the T-state distillation factories and a quantum us of ancilla logical qubits.

[0306] In some implementations, during 1802, output Bell states can be prepared between the T-states from the T-state distillation factories or the T-state transfer bus and the data logical qubits via the ancilla logical qubits by performing T-gate operations. The ancilla logical qubits can be measured by performing single-qubit measurements in different basis (e.g., Pauli-X, Pauli-Y or rotated bases) depending on the quantum program; and based on the output, conditional logical operations such as Pauli corrections can be performed on the data logical qubits to correct for any introduced phase shifts. In some instances, the measurement basis for each qubit might need to be adjusted based on the outcomes of previous measurements. In some instances, measurements on each qubit effectively enact a specific quantum logical gate on the remaining unmeasured qubits. In some instances, the graph consumption operation 1802 can produce output Bell pairs, which can be teleported to the next quantum processor module via the coherent links during teleportation operations 1806 for processing. In some instances, the graph consumption operation 804A, 804B, 804C may be implemented as the graph consumption operation 1800 shown in FIG.18.

[0307] As shown in FIG.18, the first quantum processor module 1812A is configured to consume a first graph state for a first compiled quantum circuit widget while the second quantum processor module 1812B is configured to produce and purify T-states which are teleported to the first quantum processor module 1812A for processing. In some implementations, prior to the graph consumption operation 1802, a graph preparation operation can be performed; and a teleportation operation may be performed after the graph consumption operation.Attorney Docket No.: RIGET-125WO1

[0308] In some implementations, the graph preparation occurs entirely within a single graph module. A sequence of measurements of graph state logical qubits (e.g., the data logical qubits) is conducted along the rail of ancilla logical qubits. During the graph consumption operation, a series of measurements along the quantum bus, in addition to a number of T-state rotations applied during this process.

[0309] In some implementations, a teleportation operation includes loading the logical qubits into the inter-module Pipe (1 logical qubit per pipe) and an “inter-module tock” which is the time for a lattice surgery operation of d cycles of the native inter-module interaction with sufficient fidelity to be below threshold. This teleportation operation moves logical qubits from the recently completed graph consumption step over to the other graph module. FIG.10 shows an inter-module teleportation example.

[0310] During the consumption step of the first graph module, the other graph module, idle up until this point, will begin its preparation sequence. Once the preparation sequence and the consumption step are complete on any particular graph module, output quantum states on output nodes from the consumption step can be teleported to a distinct graph module in order to begin the consumption step at that module.

[0311] The graph consumption step involves preparation of T-states at the T-factory module, and teleportation of those T-states. The time is governed by the number of T-states required for each graph consumption step and the number of T-states that can be generated and teleported in parallel. An example is shown in FIGS.8, 10.

[0312] The Quantum Fourier Transform (QFT) is a common component of quantum algorithms, including Quantum Phase Estimation. From the perspective of hardware- specific resource analysis, QFTs are likely to feature in application-relevant resource analysis yet can be scaled down to a small handful of logical input gates. QFT circuits can be analyzed on ^ qubits where ^ = 4,10,25,50,75,100, or 250.

[0313] Simulation of lattice-based Hamiltonians covers a family of important applications investigated by researchers in quantum chemistry and condensed matter. Moreover, simulating dynamics may provide utility for smaller hardware system sizes thanAttorney Docket No.: RIGET-125WO1 methods for evaluating static properties such as the ground state. Hamiltonian simulation consists of evolving an initial state =^to a state at time 5, = according to, == >)J?^=^(28)where r is the Hamiltonian of the system of interest.

[0314] Hamiltonians; 2D Transverse-Ising models and 2D Fermi-Hubbard models can be simulated. Resource estimation for simulation of a time-invariant Transverse-Ising Hamiltonian can be performed, r= ítÙ⊗ tà+ 0.1 í^Ù,(29)on a triangular lattice 1900 andZ operators, respectively, acting on lattice site 2, and angle brackets denote lattice sites connected by an edge.

[0315] Resource estimates of simulation of the Hamiltonian in Equation 28 is carried out for a total time of 5 = 1 on a 2D triangular lattice of size ^ × ^ where ^ is an integer between 2 and 10.

[0316] Fermi-Hubbard simulation as a core computational capability towards solving problems related to room temperature superconductivity is investigated. These problems typically involve studying the ground state energy, state configurations, and other observable properties of the system, including time-dependent quantities.

[0317] The Fermi-Hubbard Hamiltonian is given by, r= −Ð íD / h h(30) Ù,C / à,C+ / à,C / Ù,CEAttorney Docket No.: RIGET-125WO1 +; í ^Ù,C, Ù,C where single and double angled the nearest neighbor and next-nearest-neighbor lattice site pairs respectively.,C(annihilation) operators of a spin- I Fermion on the âth lattice site ∈ {↑, ↓}. Ð (primed or unprimed) and ^ capture themagnitudes of the hopping and repulsion energies respectively. ^à,C= / àh,C / à,Cis the number operator, ℎfis an external applied magnetic field, and ; is the chemical potential.

[0318] In some instances, methods for simulating a Fermi-Hubbard system can be broken into two families; stochastic and deterministic. In some instances, deterministic methods may not suffer from numerical issues seen in stochastic simulations when dealing with systems with non-zero chemical potential. Moreover, this instability due to the sign problem becomes prohibitive for moderate ; ∼ 0.3. This suggests separating instances into those with ; = 0, and those with greater than ; > 0.3.

[0319] The time required to run these studies on a CPU varies like, 5nKL∝  N Ô(2%^2-^^+ %^2^^^+ %^2-^-),(31)where % is the truncated bond dimension and ^ the problem dimension. Memory scaled as, 2%^2-^^O^^Õ+ 2^%^2^^O^^Õ.(32)

[0320] Taking these studies as examples of the types of systems of interest to the community it suggests obtaining resource estimates for Fermi-Hubbard Hamiltonian simulations consisting of a 2D square lattice for total time 5 = 1, with Ð = 1, Ð′ = 0, ℎf= 0, ; = 0.5, ^ = 8, and lattice sides of length ^ = 2,3,4,5,6,7,8.

[0321] Given a Hamiltonian r and simulation time 5, Quantum Signal Processing (QSP) as the Hamiltonian simulation algorithm includes performing a sequence of single qubit rotations, parameterized by a sequence of phase angles, interlaced with a quantum walk- like operator. This allows one to apply a polynomial approximation of >)J?^to the input target state. The sequence of phase angles is responsible for the polynomial approximation, and are computed classically offline, according to the error tolerance of the approximation error desired, captured by the user defined parameter P­^^. P­^^is also inversely related toAttorney Docket No.: RIGET-125WO1 the probability of success of the QSP algorithm. Thus, for an accurate simulation, with a high probability of success, P­^^may have to be set quite small.

[0322] For demonstration purposes, the desired probability of success, 48^^^, is set to be equal to 0.95. In real world applications this is typically fixed to meet outcome requirements (such as accuracy, wall clock time, etc.). Denoting the probability of success of a QSP circuit, 4­^Ò, it is required that, 48^^^ ≤ 4­^Ò.(33)

[0323] Since circuit size is inversely related to P­^^, it is prudent to choose P­^^to be as large as possible while still guaranteeing that 4­^Òexceeds the algorithm target of 0.95. In some instances, (1 − 2P­^^) ≤ 4­^Ò. Thus, 1− 2P­^^ = 48^^^ ,(34)and in some instances, P­^^can be selected as 0.025.

[0324] In some implementations, a python library (e.g., the pyLIQTR package v0.3.1) is used to construct the Hamiltonians, calculate the necessary phase angles for QSP simulation, and synthesize the QSP circuits. In some instances, the pyLIQTR also allows the user to request random phase angles rather than solving for the precise values required for an accurate simulation. In certain instances, random phase angles can be used. The correct number of phase angles is used in the circuits, but their numerical values are random. This maintains the accuracy of the resource estimations without incurring the time-consuming step of solving for the phase angles explicitly. In some instances, other tools to construct the Hamiltonian, and synthesize time evolution circuits, such as Trotterization, can be used.

[0325] In some instances, other tools can be used to convert Hamiltonian terms involving Fermionic creation and annihilation operators, like those in Fermi-Hubbard test cases, to coefficient / Pauli string pairs before use in the pyLIQTR package. In certain examples, the Jordan-Wigner Transformation is used due to its simplicity and ease of implementation. Other transformation such as the Bravyi–Kitaev Transformation, and the Parity Transformation may be used.

[0326] FIG.20 is a table 2000 summarizing physical resource requirements for the test cases over various input sizes. The systems and techniques can be used for estimatingAttorney Docket No.: RIGET-125WO1 resources for problem sizes consistent with studies in the literature, but also reveal where the bottlenecks are to help guide future research.

[0327] The systems and methods presented here allow a full accounting for resources for both T counts, but also for executing the Clifford portions of the circuit, a breakdown of physical and temporal resources allocated to portions of the execution of a quantum program, namely: Clifford, T-states and teleportation between quantum processor modules.

[0328] FIG.20 is a table 2000 showing resource estimation for the Transverse-Ising model on the triangular lattice of side length 10 shown in FIG.19. Results are for a superconducting fault-tolerant quantum computing architecture with space-optimized graph-state compilation. All circuits compile to 282 logical qubits.

[0329] FIG.21A is a plot 2100 showing the number of fault tolerant compiled logical qubits as a function of the number of T-states for three instance types: e.g., transverse Ising 2102, Fermi-Hubbard 2104 and QFT 2106. The curve 2102 is the Hamiltonian evolution of the Transverse-Ising model on triangular lattice sizes ranging from 2x2 to 10x10. The curve 2104 are estimates for Hamiltonian simulation of a Fermi-Hubbard model on a square lattice with sizes ranging from 2×2 to 8×8. The curve 2106 indicates QFT results for sizes 4 to 250. The full accounting of both Clifford and T contributions to total resources is shown in FIG 21A for all families of applications. As problems scale, physical qubits need to be allocated to the increased needs of Clifford processing, squeezing out available qubits that could be allocated to magic state distillation. This in turn reduces the number magic state distillation factories that can be applied to a calculation and thus increases runtime in a non-linear fashion.

[0330] FIG.21B is a plot 2110 showing the bus size (e.g., the number of physical, non-T state distillation qubits) as a function of fault tolerant runtime in second for three instance types: e.g., transverse Ising 2112, Fermi-Hubbard 2114, and QFT 2116. The curve 2112 is the Hamiltonian evolution of the Transverse-Ising model on triangular lattice sizes ranging from 2×2 to 10×10. The curve 2214 are estimates for Hamiltonian simulation of a Fermi- Hubbard model on a square lattice with sizes ranging from 2×2to 8×8. The curve 2116 indicates QFT results for sizes 4 to 250. As shown in FIGS.21A-21B, trajectories show anAttorney Docket No.: RIGET-125WO1 increasing trend in resources (e.g., number of logical qubits, T-state count, bus size, and runtime) with increasing problem size.

[0331] FIG.22 is a plot 2200 showing the normalized fault tolerant runtime as a function of the number of inter-module connections (pipes). The number of inter-module pipes varies from 1 to 32. The fault tolerant runtime is normalized to the value with 1 pipe. Curve 2202 indicates Quantum Fourier Transform results of size 250. Curve 2204 is the Hamiltonian evolution of the Transverse-Ising model on triangular lattice of size 10. Curve 2206 captures the estimates for Hamiltonian simulation of a Fermi-Hubbard model on a square lattice with size 8×8.

[0332] FIGS.23A-23C are plots 2300, 2310, 2320 showing the number of physical qubits allocated for the quantum bus (2304, 2314, 2324, e.g., the quantum buses 1302 / 1304, 1402 / 1404, 1602 / 1604 shown in FIGS.13, 14, 16) and the T-state distillation factories (2302, 2312, 2322, e.g., the T-state distillation factories 1306, 1408, 1702 shown in FIGS.13, 14, 17) as a function of logical-level instance size for example applications. N in FIG.23A is the number of original logical qubits in the QFT algorithm. As in one is QFT with 4 original qubits, with 10, and so on. In FIG.23C, there is a 2D square lattice with the size of 2×2, 3×3, and so on.

[0333] FIGS.24A-24C are plots 2400, 2410, 2420 showing the execution time in seconds as a function of logical-level instance size for example applications. Proportion of quantum computer compute time allocated to T state distillation, inter-module communications, and intra-module operations for time evolutions.

[0334] As shown in FIGS.24A-24C, the contribution to runtime of magic state distillation increases dramatically for the largest applications considered. This is because fewer qubits are allocated to the creation of higher precision T-states, doubling the penalty in runtime. The impact of runtime on the teleportation present in the distributed architecture can also be seen in this figure. Here, despite a relatively slow inter module interaction time (5× slower than the native code cycle) the contribution to overall runtime is minor for all applications estimated. This shows that for certain architectures, fault tolerance algorithms can be partitioned in a way to allow distributed computing, with relatively low impact.Attorney Docket No.: RIGET-125WO1

[0335] The sensitivity of runtime to parameters in this architectural model, The impact of the number of inter-module connections (pipes) to runtime. In some implementations, a pipe is defined as the number of connections is equal to the required code distance for a quantum program. In some instances, additional pipes can allow the teleportation of nodes between quantum processor modules to happen in parallel. This is done to quantify the penalty being paid for not having a fully connected lattice of qubits between modules. As shown in FIGS.24A-24C, runtime increases with a reduced number of inter-module connections. It is also shown that there are diminishing returns for approaching additional connections and connections with a single connection only have runtime of 10% more in the worst case.

[0336] Some of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Some of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data-processing apparatus. A computer storage medium can be, or can be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media.

[0337] Some of the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0338] In a general aspect, a quantum program is executed on quantum processor modules.Attorney Docket No.: RIGET-125WO1

[0339] In a first example, a method of executing a quantum program in a quantum computing system includes receiving, by operation of one or more classical processors, a quantum program comprising a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; segmenting, by operation of the one or more classical processors, the sequence of quantum logic gates into an equivalent sequence of quantum circuit widgets, each quantum circuit widget including a subset of the quantum logic gates in the sequence and corresponding to a time slice of the quantum program; and compiling, by operation of the one or more classical processors, the sequence of quantum circuit widgets to produce a set of compiled quantum circuit widgets to be executed on multiple quantum processor modules of the quantum computing system.

[0340] Implementations of the first example may include one or more of the following features. The quantum computing system is a fault-tolerant quantum computing system. The quantum computing system executes the quantum circuit widgets with error correction. The sequence of quantum logic gates includes only single-qubit quantum logic gates and two-qubit quantum logic gates. Compiling the sequence of quantum circuit widgets includes performing quantum graph state compilation on each of the quantum circuit widgets. The method includes, prior to compiling, transpiling at least one quantum circuit widget. The at least one transpiled quantum circuit widget includes a set of quantum logic gates that are compatible with the compilation.

[0341] Implementations of the first example may include one or more of the following features. The set of quantum logic gates in the at least one transpiled quantum circuit widget includes quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non- Clifford angle. The set of compiled quantum circuit widgets are produced by a compiler; and segmenting the sequence of quantum logic gates includes segmenting the sequence according to a quantum logic circuit depth requirement specified by the compiler. The set of compiled quantum circuit widgets are produced by a compiler; and segmenting the sequence of quantum logic gates includes segmenting the sequence according to a number of quantum logic gates specified by the compiler.Attorney Docket No.: RIGET-125WO1

[0342] Implementations of the first example may include one or more of the following features. The sequence of quantum circuit widgets includes first and second quantum circuit widgets corresponding to consecutive time slices of the quantum program, the quantum computing system includes a modular quantum processing unit, the modular quantum processing unit includes a first quantum processor module and a second quantum processor module, and the method includes assigning the first quantum circuit widget to be executed on the first quantum processor module; and assigning the second quantum circuit widget to be executed the second quantum processor module. Producing the set of compiled quantum circuit widgets includes converting each quantum circuit widget to a corresponding equivalent graph state representation.

[0343] Implementations of the first example may include one or more of the following features. The equivalent graph state representations includes a first graph state representation of the first quantum circuit widget, and a second graph state representation of the second quantum circuit widget, and the method includes executing the compiled quantum circuit widgets in an alternating manner on the first and second quantum processor modules. Executing the compiled quantum circuit widgets in an alternating manner includes causing the first quantum processor module to execute a first preparation schedule and to prepare a first graph state, the first preparation schedule associated with the first graph state representation; causing the first quantum processor module to execute a first consumption schedule to obtain a first output quantum state, the first consumption schedule associated with the first graph state representation; while executing the first consumption schedule, causing the second quantum processor module to execute a second preparation schedule and to prepare a second graph state, the second preparation schedule associated with the second graph state representation; after the execution of the first consumption schedule and the second preparation schedule, causing the first output quantum state to be teleported from the first quantum processor module to the second quantum process module; and causing the second quantum processor module to execute a second consumption schedule to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state, the second consumption schedule associated with the second graph state representation.Attorney Docket No.: RIGET-125WO1

[0344] Implementations of the first example may include one or more of the following features. The each of the first and second quantum circuit widgets includes a sequence of quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle. Causing the first quantum processor module to execute the first consumption schedule to obtain the first output quantum state includes receiving a plurality of T-states from a T-state reservoir; causing the first quantum processor module to execute quantum logic gates in the first quantum circuit widget, and performing measurements in T or Rz basis on a subset of logical qubits of the first quantum processor module to generate the first output quantum state according to the received plurality of T-states. The T-state reservoir includes one or more T-state distillation factories defined by multiple logical qubits of the first quantum processor module. The T-state reservoir includes a T-state transfer bus configured to store and transfer T-states received from one or more T-state distillation factories, the T-state transfer bus defined by multiple logical qubits of the first quantum process module, and each T-state distillation factory includes multiple logical qubits of the first quantum processor module. The T-state reservoir includes one or more T-state distillation factories defined on a third, distinct quantum processor module of the modular quantum processing unit, the third quantum processor module is communicably connected to the first quantum processor module via a coherent link, and receiving the plurality of T- states includes teleporting the plurality of T-states from the third quantum processor module to the first quantum processor module via the coherent link.

[0345] The sequence of quantum circuit widgets includes first and second quantum circuit widgets corresponding to consecutive time slices of the quantum program, the quantum computing system includes a modular quantum processing unit comprising a first subset of quantum processor modules and a second subset of quantum processor module communicably connected to the first subset of quantum processor modules, and the method includes assigning the first quantum circuit widget to be executed on the first subset of quantum processor modules; and assigning the second quantum circuit widget to be executed the second subset of quantum processor modules. The method further includes prior to segmenting, constructing a tree structure comprising a plurality of layersAttorney Docket No.: RIGET-125WO1 of anchor nodes and leaf nodes, the plurality of layers corresponding to distinct decomposition levels, each leaf node representing a single-qubit quantum logic gate or a two-qubit quantum logic gate. Segmenting the sequence of quantum logic gates into the sequence of quantum circuit widgets includes using the defined tree structure to segment the sequence of quantum logic gates into the sequence of quantum circuit widgets.

[0346] The quantum computing system includes a modular quantum processing unit, which includes multiple quantum processor modules. Each quantum processor module includes a plurality of quantum processor chips, each of which includes a plurality of superconducting quantum circuit devices collectively operated to define a single logical qubit. Each quantum processor chip is communicably connected to at least one neighboring quantum processor chip via one or more inter-chip connections. The one or more inter- chip connections includes an inter-chip tunable frequency coupler device.

[0347] In a second example, a quantum computing system includes a modular quantum processing unit, and one or more classical processors configured to perform operations in the first example.

[0348] In a third example, a method of segmenting a quantum program to be executed in a quantum computing system includes receiving, by operation of one or more classical processors, a quantum program comprising a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of first-layer quantum logic sub- operations; decomposing, by operation of the one or more classical processors, at least one of the first-layer quantum logic sub-operations into an equivalent sequence of second-layer quantum logic sub-operations; constructing, by operation of the one or more classical processors, a tree structure representing quantum logic sub-operations arranged in a plurality of layers corresponding to decomposition levels of the quantum program, the plurality of layers comprising a first layer representing the first-layer quantum logic sub- operations and a second layer representing the second-layer quantum logic sub- operations; and segmenting, by operation of the one or more classical processors, the quantum program into an equivalent sequence of quantum circuit widgets to be executed on multiple quantum processor modules based on the tree structure, each quantum circuitAttorney Docket No.: RIGET-125WO1 widget including a subset of the quantum logic sub-operations and corresponding to a time slice of the quantum program.

[0349] Implementations of the third example may include one or more of the following features. Segmenting the quantum program into the sequence of quantum circuit widgets includes segmenting the quantum program according to a quantum logic circuit depth requirement specified by a compiler of the quantum computing system. Segmenting the quantum program into the sequence of quantum circuit widgets includes segmenting the quantum program according to a number of quantum logic gates specified by a compiler of the quantum computing system. The second-layer quantum logic sub-operations include quantum logic gates comprising only single-qubit and two-qubit quantum logic gates.

[0350] Implementations of the third example may include one or more of the following features. The one or more classical processors are configured to produce a set of compiled quantum circuit widgets by performing a quantum graph state compilation. The sequence of quantum circuit widgets includes first and second quantum circuit widget that correspond to consecutive time slices of the quantum program, the quantum computing system comprises a modular quantum processing unit, the modular quantum processing unit includes a first quantum processor module and a second quantum processor module connected to the first quantum processor module, and the one or more classical processors are configured to assign the first quantum circuit widget to be executed on the first quantum processor module; and assign the second quantum circuit widget to be executed the second quantum processor module.

[0351] Implementations of the third example may include one or more of the following features. Producing the set of compiled quantum circuit widgets includes converting each quantum circuit widget to a corresponding equivalent graph state representation, the equivalent graph state representations comprises a first graph state representation equivalent to the first quantum circuit widget, and a second graph state representation equivalent to the second quantum circuit widget, and the one or more classical processors are configured to cause the quantum computing systems to alternatively execute the compiled quantum circuit widgets in an alternating manner on the first and second quantum processor modules, and alternatively executing the compiled quantum circuitAttorney Docket No.: RIGET-125WO1 widgets in an alternating manner includes causing the first quantum processor module to execute a first preparation schedule and to prepare a first graph state, the first preparation schedule associated with the first graph state representation; causing the first quantum processor module to execute a first consumption schedule to obtain a first output quantum state, the first consumption schedule associated with the first graph state representation; while executing the first consumption schedule, causing the second quantum processor module to execute a second preparation schedule and to prepare a second graph state, the second preparation schedule associated with the second graph state representation; after the execution of the first consumption schedule and the second preparation schedule, causing the first output quantum state to be teleported from the first quantum processor module to the second quantum process module via the coherent link; and causing the second quantum processor module to execute a second consumption schedule to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state, the second consumption schedule associated with the second graph state representation.

[0352] In a fourth example, a quantum computing system includes one or more classical processors configured to perform operations in the third example.

[0353] In a fifth example, a method of executing a quantum program in a quantum computing system includes representing the quantum program as an equivalent sequence of quantum circuit widgets, each quantum circuit widget corresponding to a time slice of the quantum program; causing a first quantum processor module of the quantum computing system to prepare a first graph state based on a first quantum circuit widget in the sequence of quantum circuit widgets; causing the first quantum processor module to consume the first graph state and to generate a first output quantum state; while causing the first quantum processor module to consume the first graph state, causing a second quantum processor module to prepare a second graph state based on a second quantum circuit widget in the sequence of quantum circuit widgets; teleporting the first output quantum state from the first quantum processor module to the second quantum processor module; and causing the second quantum processor module to consume the second graphAttorney Docket No.: RIGET-125WO1 state and to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state.

[0354] Implementations of the fifth example may include one or more of the following features. The method includes while causing the second quantum processor module to consume the second graph state, causing the first quantum processor to prepare a third graph state; after completing the consumption of the second graph state, teleporting the second output quantum state from the second quantum processor module to the first quantum processor module; and causing the first quantum processor module to consume the third graph state and to generate a third output quantum state based on the prepared third graph state and the teleported second output quantum state.

[0355] Implementations of the fifth example may include one or more of the following features. Representing the quantum program as the equivalent sequence of quantum circuit widgets includes receiving, by operation of one or more classical processors of the quantum computing system, the quantum program including a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; segmenting, by operation of the one or more classical processors, the sequence of quantum logic gates into the equivalent sequence of quantum circuit widgets, each quantum circuit widget including a subset of the quantum logic gates in the sequence.

[0356] Implementations of the fifth example may include one or more of the following features. The method includes, after segmenting, compiling each of the quantum circuit widgets to produce a set of compiled quantum circuit widgets. Producing the set of compiled quantum circuit widgets includes converting each quantum circuit widget into a corresponding equivalent graph state representation. The method further includes prior to compiling, transpiling at least one quantum circuit widget, the at least one transpiled quantum circuit widget comprising a set of quantum logic gates compatible with the compilation. The set of quantum logic gates in the at least one transpiled quantum circuit widget includes quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non- Clifford angle. Causing the first quantum processor module to consume the first graph stateAttorney Docket No.: RIGET-125WO1 and to generate the first output quantum state includes receiving a plurality of T-states from a T-state reservoir; executing the set of quantum logic gates in the at least one transpiled quantum circuit widget, and performing measurements in T or Rz basis on a subset of logical qubits of the first quantum processor module to generate the first output quantum state according to the received plurality of T-states.

[0357] In a sixth example, a quantum computing system for executing a quantum program includes a modular quantum processing unit including first and second quantum processor modules, and one or more classical processors configured to perform operations in the fifth example.

[0358] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[0359] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0360] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

Attorney Docket No.: RIGET-125WO1 CLAIMS What is claimed is:

1. A method of executing a quantum program in a quantum computing system, the method comprising: receiving, by operation of one or more classical processors, a quantum program comprising a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; segmenting, by operation of the one or more classical processors, the sequence of quantum logic gates into an equivalent sequence of quantum circuit widgets, each quantum circuit widget comprising a subset of the quantum logic gates in the sequence and corresponding to a time slice of the quantum program; and compiling, by operation of the one or more classical processors, the sequence of quantum circuit widgets to produce a set of compiled quantum circuit widgets to be executed on multiple quantum processor modules of the quantum computing system.

2. The method of claim 1, wherein the quantum computing system is a fault-tolerant quantum computing system.

3. The method of claim 1, wherein the quantum computing system executes the quantum circuit widgets with error correction.

4. The method of claim 1, wherein the sequence of quantum logic gates comprises only single-qubit quantum logic gates and two-qubit quantum logic gates.

5. The method of claim 1, where compiling the sequence of quantum circuit widgets comprises performing quantum graph state compilation on each of the quantum circuit widgets.

6. The method of claim 1, comprising: prior to compiling, transpiling at least one quantum circuit widget, the at least one transpiled quantum circuit widget comprising a set of quantum logic gates that are compatible with the compilation.Attorney Docket No.: RIGET-125WO1 7. The method of claim 6, wherein the set of quantum logic gates in the at least one transpiled quantum circuit widget comprises quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle.

8. The method of claim 1, wherein: the set of compiled quantum circuit widgets are produced by a compiler; and segmenting the sequence of quantum logic gates comprises segmenting the sequence according to a quantum logic circuit depth requirement specified by the compiler.

9. The method of claim 1, wherein: the set of compiled quantum circuit widgets are produced by a compiler; and segmenting the sequence of quantum logic gates comprises segmenting the sequence according to a number of quantum logic gates specified by the compiler.

10. The method of any one of claims 1 to 9, wherein the sequence of quantum circuit widgets comprises first and second quantum circuit widgets corresponding to consecutive time slices of the quantum program, the quantum computing system comprises a modular quantum processing unit, the modular quantum processing unit comprises a first quantum processor module and a second quantum processor module, and the method comprise: assigning the first quantum circuit widget to be executed on the first quantum processor module; and assigning the second quantum circuit widget to be executed the second quantum processor module.

11. The method of claim 10, wherein producing the set of compiled quantum circuit widgets comprises converting each quantum circuit widget to a corresponding equivalent graph state representation.

12. The method of claim 11, wherein the equivalent graph state representations comprises a first graph state representation of the first quantum circuit widget, and a second graph state representation of the second quantum circuit widget, and the method comprises: executing the compiled quantum circuit widgets in an alternating manner on theAttorney Docket No.: RIGET-125WO1 first and second quantum processor modules, and executing the compiled quantum circuit widgets in an alternating manner comprises: causing the first quantum processor module to execute a first preparation schedule and to prepare a first graph state, the first preparation schedule associated with the first graph state representation; causing the first quantum processor module to execute a first consumption schedule to obtain a first output quantum state, the first consumption schedule associated with the first graph state representation; while executing the first consumption schedule, causing the second quantum processor module to execute a second preparation schedule and to prepare a second graph state, the second preparation schedule associated with the second graph state representation; after the execution of the first consumption schedule and the second preparation schedule, causing the first output quantum state to be teleported from the first quantum processor module to the second quantum process module; and causing the second quantum processor module to execute a second consumption schedule to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state, the second consumption schedule associated with the second graph state representation.

13. The method of claim 12, wherein the each of the first and second quantum circuit widgets comprises a sequence of quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle.

14. The method of claim 13, wherein causing the first quantum processor module to execute the first consumption schedule to obtain the first output quantum state comprises: receiving a plurality of T-states from a T-state reservoir; causing the first quantum processor module to execute quantum logic gates in the first quantum circuit widget, and performing measurements in T or Rz basis on a subset of logical qubits of the firstAttorney Docket No.: RIGET-125WO1 quantum processor module to generate the first output quantum state according to the received plurality of T-states.

15. The method of claim 14, wherein the T-state reservoir comprises one or more T- state distillation factories defined by multiple logical qubits of the first quantum processor module.

16. The method of claim 14, wherein the T-state reservoir comprises a T-state transfer bus configured to store and transfer T-states received from one or more T-state distillation factories, the T-state transfer bus defined by multiple logical qubits of the first quantum process module, and each T-state distillation factory comprises multiple logical qubits of the first quantum processor module.

17. The method of claim 14, wherein the T-state reservoir comprises one or more T- state distillation factories defined on a third, distinct quantum processor module of the modular quantum processing unit, the third quantum processor module is communicably connected to the first quantum processor module via a coherent link, and receiving the plurality of T-states comprises teleporting the plurality of T-states from the third quantum processor module to the first quantum processor module via the coherent link.

18. The method of any one of claims 1 to 9, wherein the sequence of quantum circuit widgets comprises first and second quantum circuit widgets corresponding to consecutive time slices of the quantum program, the quantum computing system comprises a modular quantum processing unit comprising a first subset of quantum processor modules and a second subset of quantum processor module communicably connected to the first subset of quantum processor modules, and the method comprises: assigning the first quantum circuit widget to be executed on the first subset of quantum processor modules; and assigning the second quantum circuit widget to be executed the second subset of quantum processor modules.

19. The method of any one of claims 1 to 9 comprising: prior to segmenting, constructing a tree structure comprising a plurality of layers of anchor nodes and leaf nodes, the plurality of layers corresponding to distinctAttorney Docket No.: RIGET-125WO1 decomposition levels, each leaf node representing a single-qubit quantum logic gate or a two-qubit quantum logic gate.

20. The method of claim 19, wherein segmenting the sequence of quantum logic gates into the sequence of quantum circuit widgets comprises: using the defined tree structure to segment the sequence of quantum logic gates into the sequence of quantum circuit widgets.

21. The method of any one of claims 1 to 9, wherein the quantum computing system comprises a modular quantum processing unit comprising multiple quantum processor modules, each quantum processor module comprises a plurality of quantum processor chips, each quantum processor chip comprises a plurality of superconducting quantum circuit devices collectively operated to define a single logical qubit.

22. The method of claim 21, wherein each quantum processor chip is communicably connected to at least one neighboring quantum processor chip via one or more inter-chip connections.

23. The method of claim 22, wherein the one or more inter-chip connections comprises an inter-chip tunable frequency coupler device.

24. A quantum computing system comprising: a modular quantum processing unit; and one or more classical processors configured to perform operations comprising: receiving a quantum program comprising a sequence of quantum logic operations; decomposing the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; segmenting the sequence of quantum logic gates into an equivalent sequence of quantum circuit widgets, each quantum circuit widget comprising a subset of the quantum logic gates in the sequence and corresponding to a time slice of the quantum program; compiling the sequence of quantum circuit widgets to produce a set ofAttorney Docket No.: RIGET-125WO1 compiled quantum circuit widgets to be executed on multiple quantum processor modules of the quantum computing system.

25. The system of claim 24, wherein the quantum computing system executes the quantum circuit widgets with error correction,, the quantum processor modules each quantum processor module comprises a plurality of quantum processor chips connected to one another in a quantum correction surface code pattern, and each quantum processor chip comprises a plurality of superconducting quantum circuit devices collectively operated to define a single logical qubit.

26. The system of claim 25, wherein each quantum processor chip is communicably connected to at least one neighboring quantum processor chip via one or more inter-chip connections.

27. The system of claim 26, wherein the one or more inter-chip connections comprises an inter-chip tunable frequency coupler device.

28. The system of claim 24, wherein the sequence of quantum logic gates comprises only single-qubit quantum logic gates and two-qubit quantum logic gates.

29. The system of claim 24, wherein compiling the sequence of quantum circuit widgets comprises performing quantum graph state compilation on each of the quantum circuit widgets.

30. The system of claim 24, wherein the operations comprise: prior to compiling, transpiling at least one quantum circuit widget, the at least one transpiled quantum circuit widget comprising a set of quantum logic gates that are compatible with the compilation.

31. The system of claim 30, wherein the set of quantum logic gates in the at least one transpiled quantum circuit widget comprises quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle.

32. The system of claim 24, wherein the quantum computing system comprises a compiler configured to produce the set of compiled quantum circuit widget, andAttorney Docket No.: RIGET-125WO1 segmenting the sequence of quantum logic gates comprises segmenting the sequence according to a quantum logic circuit depth requirement specified by the compiler.

33. The system of claim 24, wherein the quantum computing system comprises a compiler configured to produce the set of compiled quantum circuit widget, and segmenting the sequence of quantum logic gates comprises segmenting the sequence according to a number of quantum logic gates requirement specified by the compiler.

34. The system of any one of claims 24 to 33, wherein the sequence of quantum circuit widgets comprises first second quantum circuit widgets that correspond to consecutive time slices of the quantum program, the modular quantum processing unit comprises a first quantum processor module and a second quantum processor module, and the operations comprise: assigning the first quantum circuit widget to be executed on the first quantum processor module; and assigning the second quantum circuit widget to be executed the second quantum processor module.

35. The system of claim 34, wherein producing the set of compiled quantum circuit widgets comprises converting each quantum circuit widget into a corresponding equivalent graph state representation.

36. The system of claim 35, wherein the equivalent graph state representations comprises a first graph state representation of the first quantum circuit widget, and a second graph state representation of the second quantum circuit widget, and causing the quantum computing system to execute the quantum program comprises executing the compiled quantum circuit widgets in an alternating manner on the first and second quantum processor modules, and executing the compiled quantum circuit widgets in an alternating matter comprises: causing the first quantum processor module to execute a first preparation schedule and to prepare a first graph state, the first preparation schedule associated with the first graph state representation; causing the first quantum processor module to execute a first consumption scheduleAttorney Docket No.: RIGET-125WO1 to obtain a first output quantum state, the first consumption schedule associated with the first graph state representation; while executing the first consumption schedule, causing the second quantum processor module to execute a second preparation schedule and to prepare a second graph state, the second preparation schedule associated with the second graph state representation; after the execution of the first consumption schedule and the second preparation schedule, causing the first output quantum state to be teleported from the first quantum processor module to the second quantum process module; and causing the second quantum processor module to execute a second consumption schedule to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state, the second consumption schedule associated with the second graph state representation.

37. The system of claim 36, wherein the each of the first and second quantum circuit widget comprises a sequence of quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle.

38. The system of claim 37, wherein causing the first quantum processor module to execute the first consumption schedule to obtain the first output quantum state comprises: receiving a plurality of T-states from a T-state reservoir; causing the first quantum processor module to execute quantum logic gates in the first quantum circuit widget, and performing measurements in T or Rz basis on a subset of logical qubits of the first quantum processor module to generate the first output quantum state according to the received plurality of T-states.

39. The system of claim 38, wherein the T-state reservoir comprises one or more T- state distillation factories defined by multiple logical qubits of the first quantum processor module.Attorney Docket No.: RIGET-125WO1 40. The system of claim 38, wherein the T-state reservoir comprises a T-state transfer bus configured to store and transfer T-states received from one or more T-state distillation factories, the T-state transfer bus defined by multiple logical qubits of the first quantum process module, and each T-state distillation factory comprises multiple logical qubits of the first quantum processor module.

41. The system of claim 38, wherein the T-state reservoir comprises one or more T- state distillation factories defined on a third, distinct quantum processor module of the modular quantum processing unit, the third quantum processor module is communicably connected to the first quantum processor module via a coherent link, and receiving the plurality of T-states comprising teleporting the plurality of T-states from the third quantum processor module to the first quantum processor module via the coherent link.

42. The system of any one of claims 24 to 33, wherein the sequence of quantum circuit widgets comprises first and second quantum circuit widgets corresponding to consecutive time slices of the quantum program, the modular quantum processing unit comprising a first subset of quantum processor modules and a second subset of quantum processor module communicably connected to the first subset of quantum processor modules via respective coherent links, and the operations comprise: assigning the first quantum circuit widget to be executed on the first subset of quantum processor modules; and assigning the second quantum circuit widget to be executed the second subset of quantum processor modules.

43. The system of any one of claims 24 to 33, wherein the operations comprise: prior to segmenting, constructing a tree structure comprising a plurality of layers of anchor nodes and leaf nodes, the plurality of layers corresponding to distinct decomposition levels, each leaf node representing a single-qubit quantum logic gate or a two-qubit quantum logic gate.

44. The system of claim 43, wherein segmenting the sequence of quantum logic gates into the sequence of quantum circuit widgets comprises:Attorney Docket No.: RIGET-125WO1 using the defined tree structure to segment the sequence of quantum logic gates into the sequence of quantum circuit widgets.

45. A method of segmenting a quantum program to be executed in a quantum computing system, the method comprising: receiving, by operation of one or more classical processors, a quantum program comprising a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of first-layer quantum logic sub- operations; decomposing, by operation of the one or more classical processors, at least one of the first-layer quantum logic sub-operations into an equivalent sequence of second-layer quantum logic sub-operations; constructing, by operation of the one or more classical processors, a tree structure representing quantum logic sub-operations arranged in a plurality of layers corresponding to decomposition levels of the quantum program, the plurality of layers comprising a first layer representing the first-layer quantum logic sub-operations and a second layer representing the second-layer quantum logic sub-operations; and segmenting, by operation of the one or more classical processors, the quantum program into an equivalent sequence of quantum circuit widgets to be executed on multiple quantum processor modules based on the tree structure, each quantum circuit widget comprising a subset of the quantum logic sub-operations and corresponding to a time slice of the quantum program.

46. The method of claim 45, wherein segmenting the quantum program into the sequence of quantum circuit widgets comprises segmenting the quantum program according to a quantum logic circuit depth requirement specified by a compiler of the quantum computing system.

47. The method of claim 45, wherein segmenting the quantum program into the sequence of quantum circuit widgets comprises segmenting the quantum program according to a number of quantum logic gates specified by a compiler of the quantum computing system.Attorney Docket No.: RIGET-125WO1 48. The method of claim 45, wherein the second-layer quantum logic sub-operations comprise quantum logic gates comprising only single-qubit and two-qubit quantum logic gates.

49. The method of any one of claims 45 to 48, wherein the one or more classical processors are configured to produce a set of compiled quantum circuit widgets by performing a quantum graph state compilation.

50. The method of claim 49, wherein the sequence of quantum circuit widgets comprises first and second quantum circuit widget that correspond to consecutive time slices of the quantum program, the quantum computing system comprises a modular quantum processing unit, the modular quantum processing unit comprises a first quantum processor module and a second quantum processor module connected to the first quantum processor module, and the one or more classical processors are configured to: assign the first quantum circuit widget to be executed on the first quantum processor module; and assign the second quantum circuit widget to be executed the second quantum processor module.

51. The method of claim 50, wherein producing the set of compiled quantum circuit widgets comprises converting each quantum circuit widget to a corresponding equivalent graph state representation, the equivalent graph state representations comprises a first graph state representation equivalent to the first quantum circuit widget, and a second graph state representation equivalent to the second quantum circuit widget, and the one or more classical processors are configured to cause the quantum computing systems to execute the compiled quantum circuit widgets in an alternating manner on the first and second quantum processor modules, and executing the compiled quantum circuit widgets in an alternating matter comprises: causing the first quantum processor module to execute a first preparation schedule and to prepare a first graph state, the first preparation schedule associated with the first graph state representation; causing the first quantum processor module to execute a first consumption schedule to obtain a first output quantum state, the first consumption schedule associated with theAttorney Docket No.: RIGET-125WO1 first graph state representation; while executing the first consumption schedule, causing the second quantum processor module to execute a second preparation schedule and to prepare a second graph state, the second preparation schedule associated with the second graph state representation; after the execution of the first consumption schedule and the second preparation schedule, causing the first output quantum state to be teleported from the first quantum processor module to the second quantum process module via the coherent link; and causing the second quantum processor module to execute a second consumption schedule to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state, the second consumption schedule associated with the second graph state representation.

52. A quantum computing system comprising: one or more classical processors configured to perform operations comprising: receiving the quantum program comprising a sequence of quantum logic operations; decomposing the sequence of quantum logic operations into an equivalent sequence of first-layer quantum logic sub-operations; decomposing at least one of the first-layer quantum logic sub-operations into an equivalent sequence of second-layer quantum logic sub-operations; constructing a tree structure representing quantum logic sub-operations arranged in a plurality of layers corresponding to decomposition levels of the quantum program, the plurality of layers comprising a first layer representing the first-layer quantum logic sub-operations and a second layer representing the second-layer quantum logic sub-operations; and segmenting the quantum program into an equivalent sequence of quantum circuit widgets to be executed on multiple quantum processor modules based on the tree structure, each quantum circuit widget comprising a subset of the quantum logic sub- operations and corresponding to a time slice of the quantum program.Attorney Docket No.: RIGET-125WO1 53. The system of claim 52, wherein segmenting the quantum program into the sequence of quantum circuit widgets comprises segmenting the quantum program according to a quantum logic circuit depth requirement specified by the compiler of the quantum computing system.

54. The system of claim 52, wherein segmenting the quantum program into the sequence of quantum circuit widgets comprises segmenting the quantum program according to a number of quantum logic gates requirement specified by the compiler of the quantum computing system.

55. The system of claim 52, wherein the second-layer quantum logic sub-operations comprise quantum logic gates comprising only single-qubit and two-qubit quantum logic gates.

56. The system of any one of claims 52 to 55, wherein the one or more classical processors are configured to produce a set of compiled quantum circuit widgets by performing a quantum graph state compilation.

57. The system of claim 56, wherein the sequence of quantum circuit widgets comprises first and second quantum circuit widgets corresponding to consecutive time slices of the quantum program, the quantum computing system comprises a modular quantum processing unit, the modular quantum processing unit comprises a first quantum processor module and a second quantum processor module connected to the first quantum processor module, and the one or more classical processors are configured to: assign the first quantum circuit widget to be executed on the first quantum processor module; and assign the second quantum circuit widget to be executed the second quantum processor module.

58. The system of claim 57, wherein producing the set of compiled quantum circuit widgets comprises converting each quantum circuit widget to a corresponding equivalent graph state representation, the equivalent graph state representations comprises a first graph state representation equivalent to the first quantum circuit widget, and a second graph state representation equivalent to the second quantum circuit widget, and the one orAttorney Docket No.: RIGET-125WO1 more classical processors are configured to cause the quantum computing systems to execute the compiled quantum circuit widgets in an alternating manner on the first and second quantum processor modules, and executing the compiled quantum circuit widgets in an alternating matter comprises: causing the first quantum processor module to execute a first preparation schedule and to prepare a first graph state, the first preparation schedule associated with the first graph state representation; causing the first quantum processor module to execute a first consumption schedule to obtain a first output quantum state, the first consumption schedule associated with the first graph state representation; while executing the first consumption schedule, causing the second quantum processor module to execute a second preparation schedule and to prepare a second graph state, the second preparation schedule associated with the second graph state representation; after the execution of the first consumption schedule and the second preparation schedule, causing the first output quantum state to be teleported from the first quantum processor module to the second quantum process module via the coherent link; and causing the second quantum processor module to execute a second consumption schedule to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state, the second consumption schedule associated with the second graph state representation.

59. A method of executing a quantum program in a quantum computing system, the method comprising: representing the quantum program as an equivalent sequence of quantum circuit widgets, each quantum circuit widget corresponding to a time slice of the quantum program; causing a first quantum processor module of the quantum computing system to prepare a first graph state based on a first quantum circuit widget in the sequence of quantum circuit widgets; causing the first quantum processor module to consume the first graph state and toAttorney Docket No.: RIGET-125WO1 generate a first output quantum state; while causing the first quantum processor module to consume the first graph state, causing a second quantum processor module to prepare a second graph state based on a second quantum circuit widget in the sequence of quantum circuit widgets; teleporting the first output quantum state from the first quantum processor module to the second quantum processor module; and causing the second quantum processor module to consume the second graph state and to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state.

60. The method of claim 59, comprising: while causing the second quantum processor module to consume the second graph state, causing the first quantum processor to prepare a third graph state; after completing the consumption of the second graph state, teleporting the second output quantum state from the second quantum processor module to the first quantum processor module; and causing the first quantum processor module to consume the third graph state and to generate a third output quantum state based on the prepared third graph state and the teleported second output quantum state.

61. The method of claim 60, wherein representing the quantum program as the equivalent sequence of quantum circuit widgets comprises: receiving, by operation of one or more classical processors of the quantum computing system, the quantum program comprising a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; and segmenting, by operation of the one or more classical processors, the sequence of quantum logic gates into the equivalent sequence of quantum circuit widgets, each quantum circuit widget comprising a subset of the quantum logic gates in the sequence.Attorney Docket No.: RIGET-125WO1 62. The method of claim 61, comprises: after segmenting, compiling each of the quantum circuit widgets to produce a set of compiled quantum circuit widgets.

63. The method of claim 62, wherein producing the set of compiled quantum circuit widgets comprises converting each quantum circuit widget into a corresponding equivalent graph state representation.

64. The method of claim 62, comprising: prior to compiling, transpiling at least one quantum circuit widget, the at least one transpiled quantum circuit widget comprising a set of quantum logic gates compatible with the compilation.

65. The method of claim 64, wherein the set of quantum logic gates in the at least one transpiled quantum circuit widget comprises quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle.

66. The method of claim 65, wherein causing the first quantum processor module to consume the first graph state and to generate the first output quantum state comprises: receiving a plurality of T-states from a T-state reservoir; executing the set of quantum logic gates in the at least one transpiled quantum circuit widget, and performing measurements in T or Rz basis on a subset of logical qubits of the first quantum processor module to generate the first output quantum state according to the received plurality of T-states.

67. A quantum computing system for executing a quantum program, the system comprising: a modular quantum processing unit comprising first and second quantum processor modules, and one or more classical processors configured to perform operations comprising: representing the quantum program as an equivalent sequence of quantum circuit widgets, each quantum circuit widget corresponding to a time slice of the quantumAttorney Docket No.: RIGET-125WO1 program; causing the first quantum processor module to prepare a first graph state based on a first quantum circuit widget in the sequence of quantum circuit widgets; causing the first quantum processor module to consume the first graph state and to generate a first output quantum state; while causing the first quantum processor module to consume the first graph state, causing the second quantum processor module to prepare a second graph state based on a second quantum circuit widget in the sequence of quantum circuit widgets; teleporting the first output quantum state from the first quantum processor module to the second quantum processor module; and causing the second quantum processor module to consume the second graph state and to generate a second output quantum state based on the prepared second graph state and the teleported first output quantum state.

68. The system of claim 67, wherein the operations comprise: while causing the second quantum processor module to consume the second graph state, causing the first quantum processor to prepare a third graph state; after completing the consumption of the second graph state, teleporting the second output quantum state from the second quantum processor module to the first quantum processor module; and causing the first quantum processor module to consume the third graph state and to generate a third output quantum state based on the prepared third graph state and the teleported second output quantum state.

69. The system of claim 67,wherein representing the quantum program as the equivalent sequence of quantum circuit widgets comprises: receiving, by operation of one or more classical processors of the quantum computing system, the quantum program comprising a sequence of quantum logic operations; decomposing, by operation of the one or more classical processors, the sequence of quantum logic operations into an equivalent sequence of quantum logic gates; segmenting, by operation of the one or more classical processors, the sequence ofAttorney Docket No.: RIGET-125WO1 quantum logic gates into the equivalent sequence of quantum circuit widgets, each quantum circuit widget comprising a subset of the quantum logic gates in the sequence.

70. The system of claim 69, wherein representing the quantum program as the equivalent sequence of quantum circuit widgets further comprises: after segmenting, compiling each of the quantum circuit widgets to produce a set of compiled quantum circuit widgets.

71. The system of claim 70, wherein producing the set of compiled quantum circuit widgets comprises converting each quantum circuit widget into a corresponding equivalent graph state representation.

72. The system of claim 70, wherein representing the quantum program as the equivalent sequence of quantum circuit widgets further comprises: prior to compiling, transpiling at least one quantum circuit widget, the at least one transpiled quantum circuit widget comprising a set of quantum logic gates compatible with the compilation.

73. The system of claim 72, wherein the set of quantum logic gates in the at least one transpiled quantum circuit widget comprises quantum logic gates selected from a group of quantum logic gates, the group consisting of Clifford gates, ^ gates, ^hgates, and ef(g) gates, where g is a non-Clifford angle.

74. The system of claim 73, wherein causing the first quantum processor module to consume the first graph state and to generate the first output quantum state comprises: receiving a plurality of T-states from a T-state reservoir; executing the set of quantum logic gates in the at least one transpiled quantum circuit widget, and performing measurements in T or Rz basis on a subset of logical qubits of the first quantum processor module to generate the first output quantum state according to the received plurality of T-states.

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