Charge pump circuit arrangement

Abstract

The invention suggests charge pump circuit arrangement (70) with enhanced efficiency. According to the invention, the charge pump circuit arrangement (70), comprising: a multitude of capacitors (10, 12, 14, 16) switches (20, 22, 24) that connect one of the capacitors (10, 12, 14, 16) to another one of the capacitors (10, 12, 14, 16); each one of the capacitors (10, 12, 14, 16) comprising a sem- iconductor substrate (38) including a deep well doping region (42) of a first conductivity type and a well doping region (48) of a second conductivity type disposed adjacent to the deep well doping region (42) of the first conductivity type, a portion of the capacitors (10, 12, 14, 16) disposed in the semiconductor substrate (38); each one of the capacitors (10, 12, 14, 16) comprising a top electrode connected to a gate electrode (50); wherein for each of the capacitors (10, 12, 14, 16), its deep well doping region (42) is connected to its gate electrode (50).

Description

[0001] Charge Pump Circuit Arrangement

[0002] DESCRIPTION

[0003] Technical background of the invention

[0004] The invention relates to a circuit arrangement for a charge pump . Speci fically, the present invention relates to a charge pump circuit arrangement wherein a portion of a multitude of capacitors forming the charge pump is reali zed in a substrate that comprises a deep well doping region of a first conductivity type and another doping well of a second conductivity type disposed above the deep well region . Yet more speci fically, the invention relates to a charge pump circuit arrangement , comprising a multitude of capacitors and switches that connect one of the capacitors to another one of the capacitors wherein each capacitor comprises a semiconductor substrate including a deep well doping region of a first conductivity type and a well doping region of a second conductivity type disposed adj acent to the deep well doping region of the first conductivity type , wherein a portion of each capacitor is disposed in the semiconductor substrate , and wherein each capacitor comprises a top electrode connected to a gate electrode .

[0005] Background

[0006] Many applications like time-of- f light ( ToF) , non-volatile memories , LCD drivers , or VCSEL Drivers , in particular in automotive or mobile device technologies , require an input voltage several times higher than the available supply voltage . In such applications , so-called charge pumps are widely used, especially in integrated CMOS semiconductor circuits , to generate such an output voltage that is higher than the input supply voltage .

[0007] In integrated circuits , charge pumps based upon switched capacitors are most commonly used as they are relatively easy to integrate into ICs . In one type , referred to as Dickson type charge pump, a series of capacitors interconnected by switches are controlled by phase-shi fted non-overlapping clock signals . The capacitors may be reali zed as MOS capacitors (MOSCAPs ) wherein one portion of the capacitor is disposed in the semiconductor substrate and the other portion of the capacitor is formed by the gate electrode . Using complementary MOS technology ( CMOS ) , a deep n-well doping region is disposed in a p-substrate . The deep n-well encloses a high voltage p-well which forms the lower plate of the charge pump capacitors . According to conventional CMOS structures , the deep n-well doping region is connected to a fixed voltage such as the supply voltage VDD . The maj or design goals in switched capacitor charge pumps of this type typically are , on the one hand side , ef ficiency (maximi ze power / current efficiency) , and, on the other hand side , area requirements ( in favor of a high package density, the goal is to minimi ze the required silicone area without compromising on current capability) .

[0008] In order to achieve these goals , widespread approaches regarding the design and layout of the charge pumps are : o Minimi ze parasitic capacitors in pump stages o Use multiphases clocking schemes to minimi ze cross conduction currents inside the charge pump stages o Use high density pumping capacitors o Increase switching frequency of pump

[0009] In the design mentioned above , however, the parasitic capacitances between the lower plate of the charge pump capacitors and the deep n-well must be charged and discharged with every clock cycle . Since the parasitic capacitance between the high voltage p-well and the deep n-well is considerably large , the ef ficiency of the charge pump operation is limited . In particular, in many systems a high voltage (HV) MOS is most commonly used as the pumping capacitor in high voltage charge pumps . Large values of the p-well diode parasitic capacitance signi ficantly reduce power / current ef ficiency of the pump as the p-well diode parasitic capacitance is connected to the bottom plate of the pumping capacitor . Further, due to parasitic capacitance at the pumping lower plate , the clock driver output load capacitance is increased, in result requiring larger clock drivers . Pumping capacitors also are main contributors to the required charge pump area . So , by using high density capacitances as pumping capacitor may allow to minimi ze the pump area . In high voltage pumps , however, these high density capacitors cannot be used due to stress and SOA limitation .

[0010] Summary

[0011] The obj ect of the invention is therefore to provide a charge pump of the type identi fied above that has enhanced ef ficiency . In particular, it is another obj ect of the present invention to provide a charge pump that achieves the same output voltage with less input power when compared to conventional solutions . It is yet another obj ect of the present invention to provide a charge pump circuit arrangement that achieves the same ef ficiency with less semiconductor area .

[0012] According to the invention, this obj ect is achieved in that for each of the capacitors , its deep well doping region is connected to its gate electrode .

[0013] Preferred embodiments of the invention are subj ect of the dependent claims .

[0014] The invention is based on the consideration that the ef ficiency of a switch capacitor pump may be maximi zed by consequently reducing parasitic losses . Under the consideration that the lower plate parasitic capacitance is the prime contributor to ef ficiency losses , the lower plate parasitic loss should be minimi zed . For this purpose , in a concept according to the invention, the deep n-well may be connected to the top plate of the pumping capacitor in such a way that the MOS oxide capacitance and the p-well diode capacitance are connected in parallel . In this aspect of the invention, the lower plate parasitic capacitance is signi ficantly reduced, potentially to close to zero . Further, the HV MOS si ze can be reduced proportionally as the p-well diode capacitance in this layout may act as additional pumping capacitance in addition to the actual MOS oxide capacitance . Further, the clock driver si ze may be reduced accordingly, as well , as lesser load capacitance is provided at clock driver output .

[0015] In one aspect of the invention, one or more of the deep n- well implants may be clubbed, and the clubbed p-well diode capacitance may be used as pumping capacitance in some stages instead of HVMOS oxide cap . As the number of HVMOS pumping is less in this setup, the required pump area will be reduced together with the clock driver si ze .

[0016] According to an aspect of the invention, the p-well parasitic diode capacitance may by comparable to the capacitance of the HV MOS capacitor . In accordance with one aspect of the invention, the deep n-well is connected to the upper plate of the pumping capacitor, so that MOS oxide capacitance and the p- well diode capacitance are connected in parallel , and thus in combination may be used as pumping capacitance .

[0017] In a preferred embodiment , the substrate provided for the charge pump circuitry assembly may be a p-doped semiconductor substrate . The deep well doping region may be an n-doped deep well . The high voltage well doping region may be a high voltage p-doped well region enclosed by the n-doped deep well region . N-doped source and drain regions are disposed in the high voltage p-doped well to form one of the MOSCAP capacitors of the charge pump . The n-doped source / drain regions are connected with each other . A gate electrode disposed between the n-doped source / drain regions forms the upper plate of the MOSCAP capacitors of the charge pump .

[0018] The charge pump may comprise N capacitors disposed in a sequence . This means that a switch is provided between the 1 st and the 2nd capacitor, the 2nd and the 3rd capacitor, etc . and between the N-lst capacitor and the N-th capacitor . The capacitors may be controlled by a common clock signal , or the capacitors may be grouped such that various subgroups of the capacitors are controlled by independent clock signals each .

[0019] Main advantages of the present invention may be seen in that the parasitic capacitance of the bottom plate is signi ficantly reduced, potentially even close to zero , as the p-well diode capacitance may be used as pumping capacitor . Thus , charge losses in pumping cycle will be minimal . As a result , the pump power and current ef ficiency is increased signi ficantly as compared to prior systems . Further, the si ze of the HV MOS may be reduced proportionally since oxide capacitance and diode capacitance act in parallel . This leads to signi ficant reduction in the demand for pump area . Yet further, the clock driver may be reduced in si ze as in the embodiment of the invention, the lower plate parasitic capacitance is close to zero .

[0020] As may be shown by calculations and simulations , the ef ficiency of the charge pump is increased since the parasitic capacitances that need to be charged and discharged during the charge pump operation are lower so that less power is needed and, consequently, the power dissipation is lower . On the other hand, it can be veri fied that in terms of current capability the MOS capacitances of the charge pump may be dimensioned smaller in order to achieve the same ef ficiency as a conventional charge pump where the deep well doping regions are tied to a fixed potential . As a result , the area consumption of the integrated circuit is reduced .

[0021] Brief Description of the Preferred Embodiments

[0022] Preferred embodiments and aspects of the invention are described further in connection with a drawing . In this drawing,

[0023] FIG . 1 shows a conventional charge pump circuit ; FIG . 2a, 2b show a cross-section through a semiconductor substrate including a charge pump capacitor and illustrating the parasitic capacitances ;

[0024] FIG . 3 shows an improved charge pump circuit ;

[0025] FIG . 4 shows another charge pump circuit in accordance with one aspect of the invention;

[0026] FIG . 5 shows a graph illustrating the efficiency according to an analytical model representing the charge pump circuits of FIGs . 1 , 3 , and 4 ;

[0027] FIG . 6 shows a graph illustrating the output current according to an analytical model representing the charge pump circuits of FIGs . 1 , 3 , and 4 , and

[0028] FIG . 7 shows yet another charge pump circuit in accordance with one further aspect of the invention .

[0029] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understand the nature and character of the claims . The accompanying drawings are included to provide a further understanding and are incorporated in, and constitute a part of , this description . The drawings illustrate one or more embodiments , and together with the description serve to explain principles and operation of the various embodiments . In the drawings , identical parts are labelled by the same reference numerals .

[0030] Detailed Description of the Preferred Embodiments

[0031] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings showing embodiments of the disclosure . The disclosure may, however, be embodied in many di f ferent forms and should not be construed as limited to the embodiments set forth herein . Ra-

[0032] RECTIFIED SHEET (RULE 91) ISA / EP ther, these embodiments are provided so that the disclosure will fully convey the scope of the disclosure to those skilled in the art . The drawings are not necessarily drawn to scale but are configured to clearly illustrate the disclosure .

[0033] FIG . 1 shows a conventional charge pump circuit 1 , in the embodiment shown according to the so-called Dickson structure . The charge pump 1 generates an elevated output voltage VOUT available at the tank capacitor 2 supplying the load 4 , 6 from the input voltage VDD supplied by input voltage source 8 . According to the Dickson structure , the charge pump comprises a sequence of a multitude of N capacitors of which capacitors 10 , 12 , 14 , 16 are depicted in FIG 1 . Adj acent capacitors such as 10 , 12 are connected through a switch 20 , 22 , 24 , ... which may be a diode . The first capacitor 10 of the sequence of capacitors is connected through a diode or switch 26 to the input voltage source 8 . The uppermost capacitors 14 , 16 are connected through a switch or diode 24 .

[0034] In the embodiment shown, the capacitors of a first group of capacitors such as capacitors 10 , 14 are driven by a first clock signal as indicated by insert 30 . The capacitors of a second group of capacitors such as capacitors 12 , 16 , in contrast , are controlled by a second clock signal as indicated by insert 32 , wherein clock signal 30 and 32 have phase shi fted, non-overlapping pulses . The first and second group of capacitors are interleaved with each other . During the operation of the charge pump 1 , in a first cycle , one of the capacitors is connected across the supply voltage to be charged . In a second cycle , the capacitor is reconfigured to be in series with the adj acently connected capacitor to input its load to that capacitor .

[0035] In the embodiment shown, the capacitors 10 , 12 , 14 , 16 are designed as MOS capacitors (MOSCAPs ) in a CMOS circuit technology so that one portion of the capacitor is reali zed in a well doping region of a substrate close 38 to a gate electrode . The substrate 38 includes also a deep well doping re- gion 42 below the well doping region to form the CMOS structure .

[0036] In FIG . 2 , a CMOS layer representation of the capacitor 12 , in principle representing the other capacitors 10 , 14 , 16 as well , is shown in more detail in cross section . In particular, FIG . 2 shows the capacitor 12 in a triple well CMOS structure . A p-substrate 40 includes a deep n-well region 42 . The deep n-well 42 is connected to high voltage (HV) n-well regions 44 and thereby accessible via terminals 46 at the surface of the substrate 38 . The deep n-well region 42 together with the HV n-well regions 44 encloses a high voltage p-well region 48 in which the capacitor 12 is reali zed, wherein the high voltage p-well region 48 is disposed adj acent to or above the deep n-well region 42 . The lower plate of the capacitor 12 is disposed in the HV p-well region 48 , and the top electrode of capacitor 12 is represented by a CMOS gate electrode 50 .

[0037] The HV p-well region 48 includes n+-doping regions 52 , 54 to which the electrode 56 of the lower plate of capacitor 12 is connected . Further, the HV p-well region 48 includes also a p+-doping region 58 which is also connected to the capacitor bottom electrode 56 . A common deep well doping region and a common HV well doping region 48 may be associated to the first group of capacitors 10 , 14 , and another common deep well doping region and another HV well doping region may be associated with the second group of capacitors 12 , 16 .

[0038] Both, at the interface between the HV p-well region 48 and deep n-well region 42 and at the interface between the p- substrate 40 and the deep n-well region 42 , parasitic capacitances CpWand Cdnware formed . In the schematic diagram of the CMOS layer representation of the capacitor 12 shown in FIG . 2b, these parasitic capacitances are identi fied as parasitic capacitance CPW60 and parasitic capacitance Cdnw62 , respectively, in addition to the actual capacitance CMos of capacitor 12 . As shown in FIG . 2b, the electrode 56 of the lower plate of capacitor 12 is connected to parasitic capacitors CpW60 .

[0039] In the conventional setup of the prior art system 1 shown in FIG . 1 , the nodes 64 between parasitic capacitors 60 , 62 of all capacitors are connected to the positive supply potential VDD according to conventional CMOS technology . This conventional setup, with respect to the various capacitors , may be described by the following observations :

[0040] - In general , the capacitances Cmosand Cpware comparable to each other in si ze whereas Cpwis larger than Cdnw

[0041] - both Cpwand Cdnware proportional to Cmos, i . e . Cpw= a Cmosand Cdnw= £ Cmoswith, normally, a > (3

[0042] - Cpwand Cdnwdo not scale in the same way as MOS capacitor Cmos

[0043] - Normally, a clock driver is connected to the bottom plate and the top plate is connected to pump cell internal switches

[0044] - Cpwand their parasitic capacitances at the internal node of pumps are main contributors to pump ef ficiency loss .

[0045] In consequence , the system 1 as shown in FIG . 1 has the following properties :

[0046] The output voltage is determined by

[0047] And

[0048] IvDD —(N+1)IL+ NVDDf aVDDC with f being the clock frequency of the charge pump driver . As Cpwand CMos are comparable , in every pumping cycle Cpwis charged and discharged . Consequently, the pump system 1 using this architecture will be less power / current ef ficient . This lowered efficiency is considered a disadvantage. Further, due to the direct coupling to VDD via Cpw, generation of noise at VDD supply is expected as deep n-well 42 is connected to VDD.

[0049] In contrast, as an advantage, no direct coupling between VOUT and the clock drivers is provided in this system, and thus voltage rippling is low.

[0050] In contrast, an improved charge pump circuit 1 ' is shown in FIG. 3. In this embodiment, the nodes 64 between parasitic capacitors 60, 62 of all capacitors 10, 12, 14, 16 are connected to the output potential VOUT rather than to the positive supply potential VDD as in system 1. This modified system 1 ' may be described by:

[0051] And

[0052] ^VDD —(N+1)IL+ NVDDf aV0UTC

[0053] Modified system 1 ' , as an advantage, has good efficiency. Since in this setup the p-well diode 60 is reversely biased by the relatively large voltage VOUT, the lower plate parasitic capacitance will be less. Also, no coupling to VDD via Cpw .

[0054] As a disadvantage, however, due to strong coupling between the clock driver and the pump output, a high voltage ripple must be expected.

[0055] In contrast, in an embodiment within the spirit of the present invention, in the charge pump circuit arrangement 70 as is shown in FIG. 4, the nodes 64 between parasitic capacitors 60, 62 of all capacitors 10, 12, 14, 16 are no longer connected to a joint, common potential. Rather or instead, the node 64 of each of the capacitors 10, 12, 14, 16 is connected individually to the CMOS gate electrode 50 and thereby to the top plate of the respective capacitor 10, 12, 14, 16, respectively. In FIG. 4, this connection is represented by connection line 72. In other words: in an aspect of the present invention, for each individual capacitor 10, 12, 14, 16, the actual capacitance CMos of the respective capacitor 10, 12, 14, 16, also referred to as gate oxide capacitance, and the p-well diode capacitance CPW60 are connected in parallel, and in combination jointly act as effective pumping capacitance .

[0056] Thus, in an aspect of the invention, the "parasitic" capacitance 60 is used as an additional contribution to the pumping capacitance. In consequence, the needed MOS pumping size may be reduced accordingly.

[0057] In an aspect of the invention, by connecting the deep n-well region 42 to the CMOS gate electrode 50 and thereby to the upper plate of the pumping capacitance, the MOS oxide Capacitance CMOS and the p-well diode capacitance CPWare connected in parallel and may be used in combination as pumping capacitance. This setup provides the following advantages with respect to prior solutions:

[0058] - The bottom plate parasitic capacitance is significantly reduced (close to zero) as p-well diode capacitance CPWis used as pumping capacitor. Thus, there will be no charge loss in the pumping cycle as the pumping capacitance lower plate parasitic capacitance is almost zero. As a result, the pump power and current efficiency are increased significantly.

[0059] - The HVMOS size may be reduced proportionally as oxide capacitance and diode capacitance act in parallel. The necessary pump area can be reduced accordingly.

[0060] - The clock driver size may be reduced as well as now the lower plate parasitic capacitance is almost zero.

[0061] In this embodiment within an aspect of the present invention, the charge pump circuit arrangement 70 may be described by:

[0062] This arrangement 70 has improved efficiency since the as bottom plate parasitic is reduced significantly, preferably almost to zero. Further it has low voltage ripple, since there is no direct coupling from the clock driver to Vout, and the last stage acts as filter. It also minimizes demand for pump Area since Cmosan Cpwin their parallel combination result in increased effective pumping capacitance, and HVMOS size may be reduced proportionally.

[0063] FIG. 5 shows a chart related to the efficiency of a charge pump. The efficiency is defined as:

[0064] The efficiency has been calculated for the charge pumps of FIG. 1, FIG. 3, and FIG. 4, the latter in accordance with the present invention. Curves 80, 82, and 84 show the efficiency as a function of output voltage of the respective charge pump. Curve 80 represents the system 1 as shown in FIG. 1, curve 82 represents the system 1' as shown in FIG. 3, and curve 84 represents the circuit 70 as shown in FIG. 4 and in accordance with the present invention. It can be concluded that the circuit 70 offer significant improvements as compared to previous systems, the efficiency increasing by up to 70% .

[0065] FIG. 6, in turn, shows a chart related to the output current of a charge pump. The output current as a function of output voltage has been calculated for the charge pumps of FIG. 1, FIG. 3, and FIG. 4, the latter in accordance with the present invention. Curves 90, 92, and 94 show the output current as a function of output voltage of the respective charge pump. Curve 90 represents the system 1 ' as shown in FIG. 1, curve 92 represents the system 1 as shown in FIG. 3, and curve 94 represents the circuit 70 as shown in FIG. 4 and in accordance with the present invention. In the latter, both MOS oxide capacitance and p-well diode capacitance jointly act as pumping capacitor, so almost the same or even enhanced pump current capability can be achieved, while a 20% smaller HVMOS pumping capacitance is used.

[0066] In summary, in the embodiment shown in FIG. 4, a charge pump circuit arrangement 70 is provided, comprising the following aspects and features that in suitable combinations are considered aspects of the present invention:

[0067] - a multitude of capacitors 10, 12, 14, 16;

[0068] - switches 20, 22, 24 that connect one of the capacitors 10, 12, 14, 16 to another one of the capacitors 10, 12, 14, 16;

[0069] - each one of the capacitors 10, 12, 14, 16 comprises a semiconductor substrate 38 including a deep well doping region 42 of a first conductivity type and a well doping region 48 of a second conductivity type disposed adjacent to the deep well doping region 42 of the first conductivity type,

[0070] - a portion of the capacitors 10, 12, 14, 16 is disposed in the semiconductor substrate 38;

[0071] - each one of the capacitors 10, 12, 14, 16 comprises a top electrode connected to a gate electrode 50;

[0072] - for each of the capacitors 10, 12, 14, 16, its deep well doping region 42 is connected to its gate electrode 50;

[0073] - each capacitor 10, 12, 14, 16 has a deep well doping region 42 independent of the deep well doping region 42 of the other capacitors 10, 12, 14, 16;

[0074] - each capacitor 10, 12, 14, 16 has a gate electrode 50 independent of and separate from the gate electrodes 50 of the other capacitors 10, 12, 14, 16;

[0075] - the capacitors 10, 12, 14, 16 are disposed in a sequence, the sequence comprising a first capacitor 10 connected to a terminal 8 for a supply voltage VDD and a last capacitor 16 connected to a terminal for an output voltage VOUT having a voltage higher than the supply voltage VDD; - the capacitors 10, 12, 14, 16 are MOS capacitors comprising a first plate disposed in one of the well doping regions 48, and a second plate forming the gate electrode 50 disposed above the first plate and doping regions 52, 54 of the first conductivity type disposed in the well doping regions 48 adjacent to the gate electrodes 50;

[0076] - a portion of the capacitors 10, 12, 14, 16 is disposed in the well doping region 48 of the second conductivity type;

[0077] - the first conductivity type is n-doped and the second conductivity type is p-doped;

[0078] - a p-doped substrate 40;

[0079] - an n-doped deep well doping region 42 disposed in the substrate 40, the n-doped deep well doping region 42 enclosing a corresponding p-doped well doping region 48 disposed in the substrate 38;

[0080] - n-doped regions 52, 54 disposed in the p-doped well doping regions 48, the n-doped regions 52, 54 short-circuited with each other;

[0081] - gate electrodes 50 disposed between adjacent ones of the n-doped regions 52, 54, wherein the n-doped regions 52, 54 and the gate electrode 50 form a corresponding MOS capacitor 10, 12, 14, 16.

[0082] Further, in another embodiment within the spirit of the present invention, as shown in FIG. 7, a clubbed Pwell may be provided and used as pumping capacitance instead of a HVMOS oxide capacitance. In this embodiment within an aspect of the present invention, the charge pump circuit arrangement 70 may be described by: and (as in previous example) :

[0083] This embodiment will have significant advantages regarding both efficiency and pump area: significant improvement in ef- ficiency will be obtained since the bottom plate parasitic in this setup will be almost zero . The pump area, in turn, will decrease by almost 25% since a number of HVNMOS are provided in separate deep Nwell , and capacitance associated with Pwell and deep Nwell will be used as pumping capacitance instead of the HVNMOS oxide capacitance . The pump stage voltage gain will be reduced by a small amount as the Cdnw diode is connected to the top plate of the pumping capacitance . It will be apparent to those skilled in the art that various modi fications and variations can be made without departing from the spirit or scope of the disclosure as laid down in the appended claims . Since modi fications , combinations , sub-combinations and variations of the disclosed embodiments incorporating the spirt and substance of the disclosure may occur to the persons skilled in the art , the disclosure should be construed to include everything within the scope of the appended claims .

[0084] LIST OF REFERENCE NUMERALS , 1 ' charge pump circuit (prior art), 2 ' tank capacitor , 6 load input voltage source 0, 12, 4, 16 capacitors 0, 22, 4 switch 6 diode 0, 32 insert 8 substrate 0 p-substrate 2 deep n-well region 4 high voltage n-well region 6 terminals 8 high voltage p-well region 0 CMOS gate 2, 54 n+-doping regions 6 bottom electrode 8 p+-doping region 0, 62 parasitic capacitance 4 node 0 charge pump circuit arrangement2 connection line 0, 82, 4 curves 0, 92, 4 curves

Claims

CLAIMS1. A charge pump circuit arrangement (70) , comprising:- a multitude of capacitors (10, 12, 14, 16) ;- switches (20, 22, 24) that connect one of the capacitors (10, 12, 14, 16) to another one of the capacitors (10, 12, 14, 16) ;- each one of the capacitors (10, 12, 14, 16) comprising a semiconductor substrate (38) including a deep well doping region (42) of a first conductivity type and a well doping region (48) of a second conductivity type disposed adjacent to the deep well doping region (42) of the first conductivity type, a portion of the capacitors (10, 12, 14, 16) disposed in the semiconductor substrate (38) ;- each one of the capacitors (10, 12, 14, 16) comprising a top electrode connected to a gate electrode (50) ;- wherein for each of the capacitors (10, 12, 14, 16) , its deep well doping region (42) is connected to its gate electrode ( 50 ) .

2. The charge pump circuit arrangement (70) of claim 1, wherein each capacitor (10, 12, 14, 16) has a deep well doping region (42) independent of the deep well doping region (42) of the other capacitors (10, 12, 14, 16) .

3. The charge pump circuit arrangement (70) of claim 1, wherein each capacitor (10, 12, 14, 16) has a gate electrode (50) independent of and separate from the gate electrodes (50) of the other capacitors (10, 12, 14, 16) .

4. The charge pump circuit arrangement (70) of any one of claims 1 to 3, wherein the capacitors (10, 12, 14, 16) are disposed in a sequence, the sequence comprising a first capacitor (10) connected to a terminal (8) for a supply voltage (VDD) and a last capacitor (16) connected to a terminal for an output voltage (VOUT) having a voltage higher than the supply voltage (VDD) .

5. The charge pump circuit arrangement (70) of any one of claims 1 to 4, wherein the capacitors (10, 12, 14, 16) are MOS capacitors comprising a first plate disposed in one of the well doping regions (48) , and a second plate forming the gate electrode (50) disposed above the first plate and doping regions (52, 54) of the first conductivity type disposed in the well doping regions (48) adjacent to the gate electrodes (50) .

6. The charge pump circuit arrangement (70) of any one of claims 1 to 5, wherein each one of the capacitors (10, 12, 14, 16) comprises a semiconductor substrate (40) of a second conductivity type which includes a deep well doping region (42) of a first conductivity type opposite the second conductivity type and a well doping region (48) of the second conductivity type disposed adjacent to the deep well doping region (42) of the first conductivity type, wherein a portion of the capacitors (10, 12, 14, 16) is disposed in the well doping region (48) of the second conductivity type.

7. The charge pump circuit arrangement of any one of claims 1 to 6, wherein the first conductivity type is n-doped and the second conductivity type is p-doped.

8. The charge pump circuit arrangement (70) of any one of claims 1 to 7, comprising:- a p-doped substrate (40) ;- an n-doped deep well doping region (42) disposed in the substrate (40) , the n-doped deep well doping region (42) enclosing a corresponding p-doped well doping region (48) disposed in the substrate (38) ;- n-doped regions (52, 54) disposed in the p-doped well doping regions (48) , the n-doped regions (52, 54) short- circuited with each other;- gate electrodes (50) disposed between adjacent ones of the n-doped regions (52, 54) , wherein the n-doped regions (52, 54) and the gate electrode (50) form a corresponding MOS capacitor (10, 12, 14, 16) .

Images