Substrate and production method therefor for producing a wide-bandgap bidirectional switch

Abstract

The invention relates to a substrate and the production method therefor for producing a bidirectional switch, the method comprising: - transferring, to the front face of a carrier substrate, a first seed layer (21) made of a wide-bandgap polar semiconductor material; - transferring, to the rear face of the carrier substrate, a second seed layer (22) made of the wide-bandgap polar semiconductor material, wherein these transfers are carried out so as to expose a surface of a first type (F1) of the first seed layer (21) and a surface of the first type (F1) of the second seed layer (22), and wherein a surface of a second type (F2) of the first seed layer (21) and a surface of the second type (F2) of the second seed layer (22) are at the interface with the front face and the rear face of the support substrate, respectively.

Description

[0001] DESCRIPTION

[0002] Substrate and its manufacturing method for the production of a wide bandgap bidirectional switch

[0003] TECHNICAL FIELD

[0004] The field of the invention is that of bidirectional switches made of wide bandgap materials such as gallium nitride (GaN) and silicon carbide (SiC). The invention relates more particularly to a substrate and its manufacturing method for producing a bidirectional switch with vertically back-to-back connected transistors.

[0005] PRIOR ART

[0006] Bidirectional switches are particularly useful in power electronics applications such as electric vehicles, renewable energy generation, vehicle-to-vehicle communication, and energy storage. These switches effectively control the flow of power in both directions, ensuring reliable and safe operation under various operating conditions.

[0007] In the power device market, currently dominated by silicon devices, devices based on wide bandgap materials such as GaN and SiC are gradually increasing their market share. These materials can operate at significantly higher temperatures and voltages while offering higher power levels and lower losses.

[0008] GaN-based bidirectional switches typically have a lateral structure as shown in Figure 15(a) of the article [1] referenced at the end of the description. The separation between the drain and gate electrodes determines the breakdown voltage of these switches. The greater the separation, the higher the voltage that the switch can block. But this then results in a significant chip footprint.

[0009] SiC-based bidirectional switches, as for example shown in Figure 15(b) of the same article [1], typically comprise two transistors with a common drain. These switches have two drift regions, one for each polarity of the blocking voltage. This also results in a large chip footprint.

[0010] One solution to address this space requirement is to connect two MOS transistor cells vertically back-to-back as shown in Figure 15(d) of the same paper [1] so that they share a common flyback region. This connection can be realized in a common-source or common-drain configuration. The common-source configuration allows controlling bidirectional blocking and conduction with a single gate drive. The common-drain configuration requires two separate gate drives.

[0011] As reported in the article [2] referenced at the end of the description, the realization of this vertical back-to-back connection requires the implementation of double-sided lithography processes on a monocrystalline SiC substrate forming the shared migration region. The monocrystalline SiC shared migration region has a thickness of 250 pm and a high resistivity: a differential on-state resistance of 140 mΩ.cm 2 is thus observed.

[0012] Furthermore, the shared migration layer in SiC has, due to its polar character, the characteristic of having, on one side, a surface consisting mainly of silicon atoms (so-called Si-type surface) and, on the other side, a surface consisting mainly of carbon atoms (so-called C-type surface). The MOS transistor cell manufactured on the Si-type surface therefore has different properties from the MOS transistor cell manufactured on the C-type surface.

[0013] Indeed, the surface state of an epitaxially grown layer differs depending on whether the layer is grown on the Si-type surface or on the C-type surface. On the one hand, on the C-type surface, the surface after epitaxy is rather flat without macroscopic steps. On the other hand, on the Si-type surface, the surface after epitaxy has terraces of 200-600nm with steps of 2-8nm.

[0014] Furthermore, the oxidation of SiC occurs with kinetics 8 to 15 times faster on the C-type surface than on the Si-type surface. After oxidation, the band gap height is higher on the Si-type surface (2.7-2.8 eV) than on the C-type surface (2.4-2.5 eV).

[0015] As reported in article [2], a consequence of the different properties is a very different threshold voltage between the two surfaces. This threshold voltage is indeed at room temperature 13.7 V on the C-type surface and 7.3 V on the Si-type surface. Moreover, the difference in trap density at the interface makes the transistor channel prepared on the MOS transistor cell fabricated on the C-type surface much more sensitive to temperature variations than the MOS transistor cell fabricated on the Si-type surface.

[0016] STATEMENT OF THE INVENTION

[0017] The invention aims to propose a solution for the design of a bidirectional switch whose vertically back-to-back connected MOS transistors have similar properties.

[0018] To this end, the invention proposes a method for manufacturing a substrate for producing a bidirectional switch with vertically connected back-to-back transistors, comprising: providing a support substrate having a front face and a rear face; transferring onto the front face of the support substrate a first seed layer made of a polar semiconductor material with a wide band gap, said first seed layer having a surface of a first type and a surface of a second type; transferring onto the rear face of the support substrate a second seed layer made of said polar semiconductor material with a wide band gap, said second monocrystalline layer having a surface of the first type and a surface of the second type.

[0019] The transfers are made so as to expose the surface of the first type of the first seed layer and the surface of the first type of the second seed layer, the surface of the second type of the first seed layer and the surface of the second type of the second seed layer being at the interface with respectively the front face and the back face of the support substrate.

[0020] Some preferred but non-limiting aspects of this method are as follows: the transfer of each of the first and second seed layers onto the front face and the rear face of the support substrate respectively comprises: o the bonding respectively onto the front face and the rear face of the support substrate of a surface of the second type of a donor substrate made of said polar semiconductor material with a wide band gap, the donor substrate having been previously subjected to an implantation of ionic species through its surface of the second type to form a weakening plane there; o the supply of thermal and / or mechanical energy to separate the donor substrate at the weakening plane. it further comprises the growth, on each of the first and second seed layers transferred onto the front face and the rear face of the support substrate respectively, of a migration layer made of a semiconductor material with a wide band gap.the migration layer deposited on each of the first and second seed layers has a thickness of between 5 and 100 pm. the migration layer deposited on each of the first and second seed layers is doped.

[0021] It further comprises the implantation of N-type or P-type impurities into the migration layer deposited on each of the first and second seed layers.

[0022] It further comprises depositing a gate oxide layer on the migration layer deposited on each of the first and second seed layers and forming a gate electrode on the gate oxide layer. The support substrate is made of a material which has an electrical resistivity of less than 20 mΩ.cm. The support substrate is a substrate of silicon carbide, aluminum nitride, diamond or gallium oxide. The support substrate has a thickness of between 100 and 500 μm, preferably between 300 and 400 μm. Each of the first and second seed layers has a thickness of less than or equal to 10 μm. The surfaces of the first type and the second type of each of the first seed layer and the second seed layer are faces perpendicular, within 15°, to opposite crystal directions.each of the first and second seed layers is a SiC layer whose first type surface is a Si type surface. each of the first and second seed layers is a GaN layer whose first type surface is a Ga type surface.

[0023] The invention also relates to a substrate for producing a bidirectional switch with vertically back-to-back connected transistors, comprising: a support substrate having a front face and a rear face; a first seed layer applied to the front face of the support substrate, the first seed layer being made of a polar semiconductor material with a wide band gap and having a surface of a first type and a surface of a second type, the surface of the second type of the first seed layer being at the interface with the front face of the support substrate; a second seed layer applied to the rear face of the support substrate, the second seed layer being made of said polar semiconductor material with a wide band gap and having a surface of the first type and a surface of the second type, the surface of the second type of the second seed layer being at the interface with the rear face of the support substrate.

[0024] The invention also relates to a bidirectional switch with vertically connected back-to-back transistors, integrating a substrate as presented above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which:

[0026] - figure 1 illustrates different stages of manufacturing the substrate according to the invention;

[0027] - figure 2 is a schematic view of a substrate according to the invention;

[0028] - figure 3 is another schematic view of a substrate according to the invention after implementation of a step of forming migration layers;

[0029] - figure 4 is a schematic view of a substrate according to the invention following the production of MOS cells in the migration layers.

[0030] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0031] The invention relates to a substrate and its manufacturing method for realizing a wide bandgap bidirectional switch whose transistors are vertically connected back-to-back.

[0032] With reference to Figure 1(A), such a method comprises providing a support substrate 1 which has a front face and a rear face. This support substrate 1 may be made of a wide band gap material, for example silicon carbide (for example p-SiC type), aluminum nitride, diamond or gallium oxide. By wide band gap, we typically mean a band gap wider than that of silicon, i.e. a band gap typically between 1.5 and 7 eV. The support substrate 1 is preferably a substrate with very low electrical resistivity, i.e. a substrate having an electrical resistivity less than or equal to 20 mΩ.cm. The support substrate is for example polycrystalline, in particular if it is made of silicon, diamond or aluminum nitride.

[0033] The support substrate 1 may have a thickness of between 100 and 500 μm, preferably between 300 and 400 μm. In the case of a substrate with a diameter of 150 mm (for example made of polycrystalline SiC), this thickness corresponds to the SEMI industry standard. In the case of a 200 mm substrate (for example made of polycrystalline SiC), this thickness may require adjustment compared to the current standard of 500 μm. In all cases, beyond the thickness that must be adjusted prior to bonding, it may be advisable to carry out a surface preparation suitable for bonding, for both the front and rear faces of the substrate 1.

[0034] As illustrated in Figure 2, the method further comprises the transfer (or “transfer”) onto the front face of the support substrate 1 of a first seed layer 21 and the transfer onto the rear face of the support substrate 1 of a second seed layer 22. By seed layer is meant a monocrystalline growth seed layer. Each of the first and second seed layers 21, 22 may have a thickness less than or equal to 10 μm, for example a thickness of between 400 and 800 nm.

[0035] The seed layers 21, 22 are made of a polar material with a wide band gap. This material can be SiC (for example 4H-SiC or 6H-SiC) or GaN. It should be noted that seed layers of SiC or GaN can be transferred onto a polycrystalline SiC support substrate.

[0036] Due to their polar character, the seed layers 21, 22 have the characteristic of having, on one face, a surface of a first type F1 and, on the other face, a surface of a second type F2.

[0037] The surfaces of the first type Fl and the second type F2 correspond to faces perpendicular, within 15°, to opposite crystal directions. For example, these crystal directions correspond to the positive direction along the c axis (+c, (0001) plane) and the negative direction along the c axis (-c, (000-1) plane). Thus, the surface of the first type Fl can be defined as a surface whose crystal misorientation with respect to the (0001) axis of the crystal is less than 15°. Similarly, the surface of the second type F2 can be defined as a surface whose crystal misorientation with respect to the (000-1) axis of a crystal is less than 15°. It should be noted that this misorientation is motivated by the need for step-edge growth to promote the growth of a polytype or minimize antiphase walls.

[0038] In the case of SiC, the Si face is the face oriented along the (0001) direction while the C face is the face oriented along the (000-1) direction. The surface of the first type Fl is then a Si type surface made up mainly of silicon atoms while the surface of the second type F2 is then a C type surface made up mainly of carbon atoms.

[0039] In the case of GaN, the Ga face is the face oriented in the (0001) direction while the N face is the face oriented in the (000-1) direction. The surface of the first type Fl is then a Ga type surface consisting mainly of gallium atoms while the surface of the second type F2 is then an N type surface consisting mainly of nitrogen atoms.

[0040] The respective transfers of the first seed layer 21 on the front face of the support substrate and of the second seed layer 22 on the rear face of the support substrate are made so as to expose the surface of the first type Fl of the first seed layer 21 and the surface of the first type Fl of the second seed layer 22. Thus, the surface of the second type F2 of the first seed layer 21 and the surface of the second type F2 of the second seed layer 22 are at the interface with the front face and the rear face of the support substrate respectively. The surface of the first type Fl is preferably the surface of type Si in the case of SiC and the surface of type Ga in the case of GaN. This promotes the production of epitaxy of SiC or GaN respectively on the surfaces of the first type Fl of the seed layers 21, 22.It will be noted in this regard that the surface of the first type Fl of each of the seed layers 21, 22 preferably has a disorientation (off-cut in English) suitable for crystal growth thereon, for example a disorientation of between 4 and 8° in the case of SiC.

[0041] In a preferred embodiment, the transfer of each of the first and second seed layers 21, 22 onto the front face and the rear face of the support substrate respectively is carried out in accordance with the Smart Cut™ method. These transfers then comprise the bonding (see FIG. 1(B)) respectively onto the front face and the rear face of the support substrate 1 of a surface of the second type of a donor substrate 2 made of said wide bandgap polar semiconductor material, the donor substrate having previously been subjected to an implantation of ionic species through its surface of the second type to form a weakening plane 3 there and to a supply of thermal and / or mechanical energy to separate the donor substrate at the weakening plane (see FIG. 1(C)) and thus carry out the transfer of the seed layer from the donor substrate to the support substrate (see FIG. 1(D)).Figures 1(B)-1(D) represent the transfer of the first seed layer 21 onto the front face of the support substrate 1. It is understood that identical steps are implemented to carry out the transfer of the second seed layer 22 onto the rear face of the support substrate 1.

[0042] The bonding can be carried out in accordance with the techniques set out in patents FR 3 117 666 B1 and FR 3 112 240 Bl. It is also possible to carry out direct bonding with surface activation (SAB bonding for “Surface Activated Bonding”) or bonding using a conductive or semiconductive bonding layer (for example in Si or W).

[0043] Optionally, after the transfer of the seed layers 21 and 22, a so-called “finishing” annealing can be provided, making it possible to reinforce the bonding and / or to reactivate the dopants in the seed layers 21 and 22 (since the implantation of ionic species is likely to damage the crystal lattice of these layers and therefore to reduce the level of active dopants).

[0044] In one possible embodiment, the successive transfer of the seed layers 21 and 22 is preceded by the successive performance of surface preparation and transfer processes on both sides of the support substrate 1. For this, two approaches can be considered.

[0045] The first approach comprises the preparation, by transfer of the seed layer 21, of an intermediate substrate combining the support substrate 1 and the seed layer 21, followed, after deposition of a protective layer on the surface of the seed layer 21, by a second sequence of transfer of the seed layer 22. Optionally, a migration layer 31 (described below) is deposited on the seed layer 21 before the transfer of the seed layer 22, in which case it is the surface of the migration layer 31 which is covered with a protective layer before and during the transfer of the seed layer 22.

[0046] This first approach amounts to chaining two sequences of the Smart Cut™ process successively, each time addressing one face of the support substrate 1. It has the advantage of reusing the existing state of the art. It also makes it possible to carry out a new sequence of preparation of the surface of the support substrate 1 before transfer of the seed layer 22, it being understood that the rear face of a support substrate is impacted during the operations linked to the Smart Cut™ process and to the growth of the migration layer 31: roughening under the effect of heat treatments, creation of scratches during handling and installation / deposition on equipment of the support plate type (or “chuck” in English), addition of particles linked to each manufacturing step. This new sequence of preparation of the support substrate 1 before transfer of the seed layer 22 can also include a step of thinning the support substrate 1 if necessary.

[0047] The protection of the surface of the migration layer 31 before initiating the surface preparation and the transfer of the seed layer 22 may for example consist of a deposition of a layer (or “capping”) of carbon.

[0048] The second approach comprises the combined preparation by successive bonding of the donor substrates of the seed layers 21 and 22, before applying a single detachment anneal, leading to the separation of three substrates, one forming the negative having given the seed layer 21 (in other words, the part of the donor substrate remaining after transfer of the seed layer 21), the other substrate formed by the seed layer 21, the support substrate 1 and the seed layer 22, the third the negative having given the layer 22 (in other words, the part of the donor substrate remaining after transfer of the seed layer 22).

[0049] This second approach makes it possible to limit the thermal budget provided for the production and finishing of the substrates illustrated in Figure 3, since it is not necessary to repeat the detachment and / or finishing annealing.

[0050] This second approach, however, has two drawbacks. First, it requires successively handling the substrates from their rear face. It may therefore be advisable to apply / remove protective layers (for example by depositing a carbon resin, potentially annealed) on the rear face to be handled, before applying a treatment (for example polishing or epitaxy) on the opposite face of the substrate. Second, without a protective layer, this second approach requires successively impacting each surface during the treatment of an opposite face. This drawback, particularly noticeable during growth or heat treatment steps, can be limited by rigorous alignment of the substrates at each step, impacting a minimum number of chips.With reference to Figure 3, the method can continue with the growth, on each of the first and second seed layers 21, 22 transferred to the front face and the rear face of the support substrate respectively, of a drift layer 31, 32 made of a wide bandgap semiconductor material (identical or not to that of the underlying seed layers). These can thus be monocrystalline migration layers, for example SiC layers deposited on SiC seed layers or GaN layers deposited on GaN or SiC seed layers.

[0051] The growth of each of the migration layers 31, 32 can be carried out by epitaxy, for example by chemical vapor deposition (or CVD for English Chemical Vapor Deposition).

[0052] The migration layer 31, 32 deposited on each of the first and second seed layers 21, 22 may have a thickness of between 5 and 100 pm depending on the desired blocking voltage.

[0053] The migration layer 31, 32 deposited on each of the first and second seed layers 21, 22 is preferably doped, for example n-type, in particular so as to lower its resistivity. In the case of a SiC migration layer, the latter may have a doping level of between 10 13 and 10 17 atoms / cm 3 .

[0054] In a preferred application, the support substrate 1 is made of a material which has a resistivity lower than that of the material of the migration layers, preferably a resistivity lower than 20 mΩ.cm. Taking the example of a polycrystalline SiC support substrate, this has a resistivity of between 1 and 10 mΩ.cm. Such a resistivity is so low that it can be considered that the two migration layers 31, 32 are connected by a conductive wire. It follows that the equivalent electrical thickness of the support substrate is divided up to 20 times. Considering an optimal configuration for a polycrystalline SiC support substrate (thickness of the support substrate of 100 μm and a resistivity of 1 mΩ.cm), a differential resistance in the on state as low as 0.01 mΩ.cm is observed. 2 , equivalent to that of a 5 pm thick monocrystalline SiC substrate and significantly lower than that (140 mQ.cm 2) observed in article [2] with a shared migration region in the form of a 250 pm thick monocrystalline SiC substrate.

[0055] The method may continue with the production of all or part of the electronic components on each of the sides of the substrate, i.e. in each of the migration regions 31, 32, in particular by means of double-sided lithography steps. In particular, the method may comprise carrying out steps conventionally implemented in the field to form a MOS transistor from each of the migration layers 31, 32.

[0056] The method can thus comprise the implantation of N-type or P-type impurities in the migration layer 31, 32 deposited on each of the first and second seed layers. In the exemplary embodiment shown in FIG. 4, this implantation makes it possible to form P-doped wells 33 and, within these, N+ doped bands 34 and P+ doped bands 35. The implantation also makes it possible to form a region forming a channel 36 of a JFET (Junction Field Effect Transistor) field effect transistor or a CSEL (Charge Storage Layer) charge storage layer.

[0057] The method may also include depositing a gate oxide layer 37 on the migration layer 31, 32 deposited on each of the first and second seed layers and forming a gate electrode 28 on the gate oxide layer 37.

[0058] The invention is not limited to the method previously described but also extends to the substrate thus manufactured (at any manufacturing stage whatsoever) as well as to a bidirectional switch produced from such a substrate, for example in a common source or common drain configuration.

[0059] References

[0060] [1] J. Huber and JW Kolar, “Monolithic Bidirectional Power Transistors,” in IEEE Power Electronics Magazine, vol. 10, no. 1, pp. 28-38, March 2023, doi: 10.1109 / MPEL.2023.3234747 [2] S. Chowdhury, C. Hitchcock, Z. Stum, RP Dahal, IB Bhat and TP Chow, "Experimental Demonstration of High-Voltage 4H-SiC Bi-Directional IGBTs," in IEEE Electron Device Letters, vol. 37, no. 8, pp. 1033-1036, Aug. 2016, doi: 10.1109 / LED.2016.2581419

Claims

CLAIMS 1. A method of manufacturing a substrate for producing a bidirectional switch with vertically back-to-back connected transistors, comprising: providing a support substrate (1) having a front face and a rear face; transferring onto the front face of the support substrate a first seed layer (21) made of a polar semiconductor material with a wide band gap, said first seed layer having a surface of a first type (F1) and a surface of a second type (F2); transferring onto the rear face of the support substrate a second seed layer (22) made of said polar semiconductor material with a wide band gap, said second monocrystalline layer having a surface of the first type (F1) and a surface of the second type (F2);said transfers being made so as to expose the surface of the first type (F1) of the first seed layer (21) and the surface of the first type (F1) of the second seed layer (22), the surface of the second type (F2) of the first seed layer (21) and the surface of the second type (F2) of the second seed layer (22) being at the interface with respectively the front face and the rear face of the support substrate.; 2. Method according to claim 1, in which the transfer of each of the first and second seed layers (21, 22) onto the front face and the rear face of the support substrate respectively comprises: bonding respectively onto the front face and the rear face of the support substrate (1) a surface of the second type of a donor substrate (2) made of said polar semiconductor material with a wide band gap, the donor substrate having previously been subjected to an implantation of ionic species through its surface of the second type to form a weakening plane (3) there; supplying thermal and / or mechanical energy to separate the donor substrate at the weakening plane.

3. Method according to one of claims 1 and 2, further comprising the growth, on each of the first and second seed layers (21, 22) transferred to respectively the front face and the rear face of the support substrate, of a migration layer (31; 32) made of a wide bandgap semiconductor material.

4. Method according to claim 3, in which the migration layer (31, 32) deposited on each of the first and second seed layers (21, 22) has a thickness of between 5 and 100 μm.

5. Method according to one of claims 3 and 4, in which the migration layer (31, 32) deposited on each of the first and second seed layers (21, 22) is doped.

6. Method according to one of claims 3 to 5, further comprising the implantation of N-type or P-type impurities in the migration layer (31, 32) deposited on each of the first and second seed layers.

7. The method of claim 6, further comprising depositing a gate oxide layer (37) on the migration layer (31, 32) deposited on each of the first and second seed layers and forming a gate electrode (38) on the gate oxide layer.

8. Method according to one of claims 3 to 7, in which the support substrate (1) is made of a material which has an electrical resistivity of less than 20 mΩ.cm.

9. Method according to one of claims 1 to 8, in which the support substrate (1) is a substrate of silicon carbide, aluminum nitride, diamond or gallium oxide.

10. Method according to one of claims 1 to 9, in which the support substrate (1) has a thickness of between 100 and 500 μm, preferably between 300 and 400 pm.

11. Method according to one of claims 1 to 10, in which each of the first and second seed layers (21, 22) has a thickness less than or equal to 10 μm.

12. Method according to one of claims 1 to 11, in which the surfaces of the first type (F1) and of the second type (F2) of each of the first seed layer (21) and of the second seed layer (22) are faces perpendicular, to within 15°, to opposite crystalline directions.

13. The method of claim 12, wherein each of the first and second seed layers (21, 22) is a SiC layer whose first type surface (F1) is a Si type surface.

14. The method of claim 12, wherein each of the first and second seed layers (21, 22) is a GaN layer whose first type surface (Fl) is a Ga type surface.

15. Substrate for producing a bidirectional switch with vertically back-to-back connected transistors, comprising: a support substrate (1) having a front face and a rear face; a first seed layer (21) attached to the front face of the support substrate, the first seed layer being made of a polar semiconductor material with a wide band gap and having a surface of a first type (F1) and a surface of a second type (F2), the surface of the second type (F2) of the first seed layer being at the interface with the front face of the support substrate; a second seed layer (22) attached to the rear face of the support substrate, the second seed layer being made of said polar semiconductor material with a wide band gap; band gap and having a surface of the first type (F1) and a surface of the second type (F2), the surface of the second type (F2) of the second seed layer being at the interface with the rear face of the support substrate.

16. Bidirectional switch with vertically connected back-to-back transistors, integrating a substrate according to claim 15.

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