Inverting buck-boost hybrid converter topologies

Abstract

Embodiments of a voltage converter are disclosed. In some embodiments, the voltage converter includes a voltage converting circuit and a charging circuit. The voltage converting circuit includes an output capacitor coupled to an output node, wherein an output voltage is generated at the output node and an output inductor has a first inductor node and a second inductor node, the first inductor node is operably associated with the output node. The charging circuit is coupled to the second inductor node. The charging circuit includes a fly capacitor, a power source node configured to receive an input voltage, and a set of switches, wherein the set of switches is set into at least one switch configuration that charges the fly capacitor and into at least one switch configuration that presents a fly voltage across the fly capacitor as a negative voltage at the second inductor node.

Description

2867-3395-WO1 / P231426-WO-UTL11INVERTING BUCK-BOOST HYBRID CONVERTER TOPOLOGIES Related Applications

[0001] This claims the benefit of provisional patent applicationserial filed April 24, 2024, which claims the benefit of provisional patent application serial number 63 / 594,385, filed October 30, 2023, the disclosures of which are hereby incorporated herein by reference in their entireties. Field of the Disclosure

[0002] This disclosure relates generally to voltage converters and methods of operating the same. Background

[0003] Voltage converters for Radio Frequency (RF) circuits or light emitting diode (LED) displays play a crucial role in ensuring optimal performance and efficiency. Voltage converters are converted from Direct Current (DC) voltages to another DC voltage at a different voltage level. RF circuits and LED displays require precise and stable voltage levels to function correctly, as deviations can lead to signal distortion and performance degradation. By efficiently managing voltage levels within the RF circuits and LED displays, these converters contribute to maintaining signal integrity, minimizing interference, and optimizing overall system reliability.

[0004] One type of design for a voltage converter is an inverting buck boost converter that converts a positive voltage to a negative voltage. In some existing applications, the inverting buck boost converter uses two transistors and an inductor. In some applications, the size of the inductor is constrained (e.g., mobile applications with a height < 1 mm) and / or the transistors suffer from performance efficiencies. For example, in Active Matrix Organic Light-Emitting Diode (AMOLED) display power applications for cell phones, the typical implementation of an inverting buck boost converter converts power at 87%2867-3395-WO1 / P231426-WO-UTL1 2 efficiency in a nominal condition and less than 80% efficiency at a maximum output power. For portable applications, this level of efficiency limits the battery life and thermal performance. Summary

[0005] In some embodiments, a voltage converter includes a voltage converting circuit, which includes: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit includes: a fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches are configurable in at least one switch configuration that charges the fly capacitor and in at least one switch configuration that presents a fly voltage across the fly capacitor as a negative voltage at the second inductor node. In some embodiments, the charging circuit is a first charging circuit, the fly capacitor is a first fly capacitor, and the set of switches is a first set of switches. The voltage converter further includes a second charging circuit coupled to the second inductor node, wherein the second charging circuit includes: a second fly capacitor; the power source node configured to receive the input voltage; and a second set of switches, wherein, in a second switch configuration, the second set of switches are configured to charge the second fly capacitor and, in a first switch configuration, the second set of switches are configured to present a second fly voltage across the second fly capacitor as a negative voltage at the second inductor node. In some embodiments, the first fly capacitor includes a first capacitor node and a second capacitor node; the first set of switches includes a first switch coupled between the power source node and the first capacitor node and a second switch coupled between the first capacitor node and a ground node; the second fly capacitor includes a third capacitor node and a fourth capacitor node; and the second set of switches includes: a third switch coupled between the power source node and the third2867-3395-WO1 / P231426-WO-UTL1 3 capacitor node; and a fourth switch coupled between the third capacitor node and the ground node. In some embodiments, the first set of switches further includes a fifth switch coupled between the second capacitor node and the ground node; and the second set of switches further includes a sixth switch coupled between the fourth capacitor node and the ground node. In some embodiments, the first set of switches further includes a seventh switch coupled between the second capacitor node and the second inductor node; and the second set of switches further includes an eighth switch coupled between the fourth capacitor node and the second inductor node. In some embodiments, the voltage converting circuit further includes a first switch connected between the first inductor node and the output node. In some embodiments, the output capacitor is connected between the output node and a ground node. In some embodiments, the voltage converting circuit further includes a second switch coupled between the power source node and the first inductor node. In some embodiments, the voltage converting circuit further includes a second switch coupled between a ground node and the first inductor node. In some embodiments, the set of switches further includes a first switch coupled between the second inductor node and a ground node. In some embodiments, the set of switches further includes a first switch coupled between the second inductor node and the power source node. In some embodiments, the fly capacitor includes a first capacitor node and a second capacitor node; and the set of switches includes: a first switch coupled between the power source node and the first capacitor node; and a second switch coupled between the first capacitor node and a ground node. In some embodiments, the set of switches further includes a third switch coupled between the second capacitor node and the ground node. In some embodiments, the set of switches further includes a fourth switch coupled between a second capacitor node and the second inductor node. In some embodiments, the fly capacitor is a first fly capacitor having a first capacitor node and a second capacitor node; the set of switches includes a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; the charging circuit further includes a second fly capacitor having a third capacitor2867-3395-WO1 / P231426-WO-UTL1 4 node and a fourth capacitor node; the first switch is coupled between the second inductor node and the first capacitor node; the second capacitor node is coupled to a ground node; the second switch is coupled between the second capacitor node and the third capacitor node; the third switch is coupled between the third capacitor node and the power source node; the fourth switch is coupled between the first capacitor node and the fourth capacitor node; and the fourth capacitor node is coupled to ground. In some embodiments, the set of switches further includes a sixth switch, wherein the sixth switch is coupled between the second inductor node and the ground. In some embodiments, the voltage converting circuit further includes the fifth switch connected between the first inductor node and the output node. In some embodiments, the output capacitor is connected between the output node and the ground node. In some embodiments, the voltage converting circuit further includes a sixth switch coupled between the power source node and the first inductor node. In some embodiments, the voltage converting circuit is configured as an inverting voltage converting circuit.

[0006] In some embodiments, a method of converting an input voltage into an output voltage at an output node includes: receiving the input voltage at a power source node, wherein the output node is operably associated with a first inductor node of an output inductor; setting a set of switches in a switch configuration to charge a fly capacitor; and setting the set of switches in the same switch configuration or in a different switch configuration to present a fly voltage across the fly capacitor as a negative voltage at a second inductor node of the output inductor.

[0007] In some embodiments, a user element includes a voltage converter, wherein the voltage converter includes a voltage converting circuit including: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit including: a fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches are2867-3395-WO1 / P231426-WO-UTL1 5 configurable into at least one switch configuration that charges the fly capacitor and into at least one switch configuration that presents a fly voltage across the fly capacitor as a negative voltage at the second inductor node.

[0008] In another aspect, any of the foregoing aspects individually or together, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] FIG.1 illustrates one embodiment of a voltage converter, in accordance with some embodiments;

[0012] FIG.1A and FIG.1B illustrate the voltage converter shown in FIG.1 with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments;

[0013] FIG.2 illustrates one embodiment of a voltage converter, in accordance with some embodiments;

[0014] FIGs.2A - 2D illustrate the voltage converter shown in FIG.2 with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments;

[0015] FIG.2E illustrates buck circuit states 1 - 4 that are implemented during a switching period for the voltage converter shown in FIG.2, in accordance with some embodiments;2867-3395-WO1 / P231426-WO-UTL1 6

[0016] FIG.2F illustrates boost circuit states 1 - 4 that are implemented during a switching period for the voltage converter shown in FIG.2, in accordance with some embodiments;

[0017] FIG.2G illustrates buck boost circuit states 1 - 3 that are implemented during a switching period for the voltage converter shown in FIG.2, in accordance with some embodiments;

[0018] FIG.3 illustrates an embodiment of a voltage converter, in accordance with some embodiments;

[0019] FIG.3A is voltage and current graphs that illustrate the operation of the voltage converter shown in FIG.3 with an error amplifier and buck comparator activated in a continuous conduction mode (CCM), in accordance with some embodiments;

[0020] FIG.3B is voltage and current graphs that illustrate the operation of the voltage converter shown in FIG.3 with an error amplifier and boost comparator activated in a discrete conduction mode (DCM), in accordance with some embodiments;

[0021] FIG.3C is voltage and current graphs that illustrate the operation of the voltage converter shown in FIG.3 with an error amplifier, boost comparator, and buck comparator activated in a CCM (i.e., second operational mode), in accordance with some embodiments;

[0022] FIG.4 illustrates another embodiment of a voltage converter, in accordance with some embodiments;

[0023] FIG.5 illustrates another embodiment of a voltage converter and five different switch configurations for the voltage converter, in accordance with some embodiments; and

[0024] FIG.6 is a user element, in accordance with some embodiments. Detailed Description

[0025] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following2867-3395-WO1 / P231426-WO-UTL1 7 description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying embodiments.

[0026] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0028] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the2867-3395-WO1 / P231426-WO-UTL1 8 Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may2867-3395-WO1 / P231426-WO-UTL1 9 or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re- described.

[0032] Switches are described throughout this disclosure as being either “open” or “closed.” When a switch is “open,” the switch is in a non-conducting state and / or a high impedance state. For example, if the switch is a field effect transistor (FET), a gate to source voltage applied to a gate of the FET is below a threshold voltage and, thus, no current or very little current (i.e., leakage current) flows between a drain and a source of the FET. The switch is also referred to as being in an “off state” when the switch is “open.” When a switch is “closed,” the switch is in a conducting state and / or a low impedance state. For example, if the switch is a FET, the gate to source voltage applied to a gate of the FET is above a threshold voltage and, thus, current flows between a drain and a source of the FET. The switch is also referred to as being in an “on state” when the switch is “closed.”

[0033] A buck boost converter refers to a voltage converter where a difference in magnitude between an input voltage and an output voltage is less than 5% (where the percentage is calculated with respect to the input voltage, i.e., the difference in magnitude is less than 5% of the input voltage).

[0034] A buck converter refers to a voltage converter where a magnitude of an input voltage is greater than a magnitude of an output voltage, where a voltage difference between the magnitude of the input voltage and the magnitude of the output voltage is more than 5% (where the percentage is calculated with respect to the input voltage, i.e., the difference in magnitude is greater than 5% of the input voltage).

[0035] A boost converter refers to a voltage converter where a magnitude of an output voltage is greater than a magnitude of an input voltage, where a voltage difference between the magnitude of the input voltage and the magnitude of the output voltage is more than 5% (where the percentage is calculated with respect to the input voltage, i.e., the difference in magnitude is greater than 5% of the input voltage).2867-3395-WO1 / P231426-WO-UTL1 10

[0036] Embodiments of a voltage converter are disclosed. The voltage converter includes a voltage converting circuit and at least one charging circuit. In some embodiments, the voltage converting circuit is an inverting voltage converting circuit. The charging circuit or charging circuits may be designed to operate as a charge pump. The voltage converting circuit includes an output inductor and an output capacitor, wherein the output capacitor is coupled to an output node. An output voltage is generated at the output node and, in some embodiments, the output voltage is a voltage with a non-zero magnitude and a negative voltage polarity. The output inductor has a first inductor node operably associated with the output node (e.g., in some embodiments, a switch is connected between the first inductor node and the output inductor) and a second inductor node that is connected to one or more of the charging circuits.

[0037] Each charging circuit includes a different set of switches. The set of switches are operable in at least one switch configuration that charges a fly capacitor and are operable in at least one switch configuration to present a fly voltage across the fly capacitor as a negative voltage at the second inductor node. The presentation of the negative fly voltage at the second inductor node reduces a peak current value and reduces a root mean squared (RMS) current through the output inductor. In some embodiments, the voltage converter increases efficiency at all load ranges, reduces inductor current ripple and output voltage ripple, reduces a saturation current requirement (which leads to a physically smaller inductor and, in some cases, a reduced number of inductors), and leads to better transient performance compared to other previously known designs. In some embodiments, the voltage converter has a power efficiency of 96%.

[0038] FIG.1 illustrates one embodiment of a voltage converter 100, in accordance with some embodiments.

[0039] The voltage converter 100 includes a charging circuit 102 and a voltage converting circuit 104. The charging circuit 102 includes switches S0, S1, S2, S3, S4, S7, and a fly capacitor CFLY. In some embodiments, the switches S1, S2, S3, S4 are FETs, microelectromechanical switches (MEMs),2867-3395-WO1 / P231426-WO-UTL1 11 and / or the like. In some embodiments the fly capacitor CFLY is a Metal- Insulator-Metal (MIM) Capacitor, a Metal-Oxide-Semiconductor (MOS) Capacitor, a poly capacitor, a thin-film capacitor, a varactor, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a varactor, a high-K dielectric capacitor, an array of capacitive devices, a combination of one or more of the capacitors listed, and / or the like.

[0040] The charging circuit 102 includes a power source node 106, a ground node 108, a capacitor node 110, and a capacitor node 112. The charging circuit 102 is connected to an inductor node 114 (also referred to as an output inductor node 114). In alternative embodiments, the switch S4 is not provided and the capacitor node 112 is the same as the output inductor node 114. With respect to the charging circuit 102 shown in FIG.1, the power source node 106 is configured to receive a power source voltage VIN (also referred to as an input voltage VIN), which is a reference voltage with a non-zero voltage magnitude and a positive voltage polarity. The power source voltage VIN is an input voltage and is generally a direct current (DC) voltage. The ground node 108 is configured to receive a ground voltage, which is a reference voltage that defines a zero voltage magnitude and thus has no polarity. The capacitor node 110 is connected to a capacitor terminal at a first side of the fly capacitor CFLY, while the capacitor node 112 is connected to the opposite capacitor terminal on a second side of the fly capacitor CFLY. The output inductor node 114 is connected to an inductor terminal at a first side of an output inductor 116 in the voltage converting circuit 104.

[0041] The switch S0 is optional. In embodiments of the charging circuit 102 that include the switch S0, the switch S0 is connected between the output inductor node 114 and the ground node 108. The switch S7 is optional. In embodiments of the charging circuit 102 that include the switch S7, the switch S7 is connected between the output inductor node 114 and the power source node 106.

[0042] The voltage converting circuit 104 includes switches S5, S6, the output inductor 116, and an output capacitor 118. In some embodiments, the switches2867-3395-WO1 / P231426-WO-UTL1 12 S5, S6 are FETs, MEMs, and / or the like. In some embodiments, the output capacitor 118 is a MIM Capacitor, a MOS Capacitor, a poly capacitor, a thin-film capacitor, a varactor, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a varactor, a high-K dielectric capacitor, an array of capacitive devices, a combination of one or more of the capacitors listed, and / or the like. In some embodiments, the output inductor 116 is a wire-wound inductor, a ferrite bead inductor, a transformer or a portion of a transformer, a multilayer chip inductor, a molded power inductor, an integrated inductor, a shielded inductor, and / or the like. While a load 120 is shown as a part of the voltage converting circuit 104, thae load 120 is generally not a part of the voltage converting circuit 104 and is shown herein for the convenience of explanation. The voltage converting circuit 104 includes an output node 122, wherein an output voltage VOUT is presented by the voltage converting circuit 104 at the output node 122. The load 120 simply refers to a circuit or device that consumes power from the output node 122. For example, one application of the voltage converter 100 is to provide power to radio frequency (RF) circuitry in a user element. Another exemplary application of the voltage convert 100 is for providing power to light emitting diode (LED) displays. Please note that these applications are considered exemplary and are not limiting. Thus, the load 120 refers to RF circuits or LED circuitry, in some embodiments.

[0043] The voltage converting circuit 104 includes the output inductor node 114, an inductor node 124 (also referred to as an output inductor node 124), a voltage node 126, the output node 122, and the ground node 108. The output inductor 116 is connected between the output inductor node 114 and the output inductor node 124. The switch S5 is connected between the output inductor node 124 and the voltage node 126. In some embodiments, the voltage node 126 receives the ground voltage and is thus the same as the ground node 108. In other embodiments, the voltage node 126 receives the power source voltage VIN and is thus the same as the power source node 106.

[0044] The switch S6 is connected between the output inductor node 124 and the output node 122. The output capacitor 118 is connected between the output2867-3395-WO1 / P231426-WO-UTL1 13 node 122 and the ground node 108. In other words, the output capacitor 118 is connected in parallel with the load 120 and in shunt with respect to the output node 122.

[0045] The voltage converting circuit 104 is configured to convert the input voltage VIN into the output voltage VOUT. In this embodiment, the output voltage VOUT has a non-zero magnitude with a negative voltage polarity. Accordingly, this embodiment of the voltage converting circuit 104 is an inverting voltage converting circuit since the input voltage VIN has a positive voltage polarity and the output voltage VOUT has a negative voltage polarity. To do this, the output inductor 116 is magnetized by generating a current with the input voltage VIN that increases the intense magnetic field generated by output inductor 116. The output inductor 116 is then disconnected from the input voltage VIN and demagnetized. During the demagnetization of the output inductor 116, the magnetic energy in the output inductor 116 is released, thereby decreasing the intensity of the magnetic field generated by the output inductor 116.

[0046] The output capacitor 118 acts as an energy reservoir and absorbs and supplies charge so as to reduce periodic amplitude voltage fluctuations (i.e., ripple current) of the output voltage VOUT. The output capacitor 118 and the output inductor 116 are configured as a low-pass filter to reduce voltage ripple and provide a more regulated output voltage VOUT. The output voltage VOUT is considered a DC voltage despite the ripple voltage in the voltage magnitude.

[0047] The charging circuit 102 is configured to charge the fly capacitor CFLY with the input voltage VIN. Once the fly capacitor CFLY is charged, the fly capacitor CFLY is coupled to the output inductor node 114. In this manner, the fly capacitor CFLY is configured to present a voltage -VFLY at the output inductor node 114. By presenting the voltage -VFLY at the output inductor node 114, a peak magnitude of the current through the output inductor 116 is reduced. Furthermore, the RMS current through the output inductor 116 is also further reduced.2867-3395-WO1 / P231426-WO-UTL1 14

[0048] The switches S1 - S6 (and, optionally, the switches S0, S7) are closed and opened in order to magnetize the output inductor 116, demagnetize the output inductor 116, charge the fly capacitor CFLY, and discharge the fly capacitor CFLY. As explained in further detail below, different operating techniques for opening and closing the switches S1 - S6 (and, optionally, the switches S0, S7) will result in different operations. For example, depending on how the switches S1 - S6 are configured, the voltage converter 100 operates as a buck converter, a boost converter, or a buck boost converter.

[0049] The voltage converter 100 has a control circuit 130. The control circuit 130 is configured to generate a control output 132 that is configured to operate the switches S0 - S7. More specifically, the control circuit 130 is configured to generate the control output 132 that opens and closes the switches S0 - S7 in accordance with a switch configuration. As explained below, by switching through different switch configurations, the voltage converter 100 operates as a particular type of voltage converter (i.e., buck, boost, or buck boost converter). In some embodiments, the control circuit 130 is a voltage mode controller, a current mode controller, an average current mode controller, a hysteresis controller, a bang-bang controller, a predictive current controller, a digital controller, an analog controller, an adaptive controller, a voltage feedforward controller, a Proportional- Integral (PI) controller, a Proportional-Integral-Derivative (PID) controller, and / or the like.

[0050] FIG.1A and FIG.1B illustrate the voltage converter 100 shown in FIG. 1 with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments.

[0051] More specifically, FIG.1A and FIG.1B illustrate the voltage converter 100 in five different switch configurations named switch configurations 1 - 5. The lines corresponding to each one of the switch configurations 1 - 5 are closed circuit paths, thereby indicating which of the switches S1 - S6 are closed. For a particular one of the switch configurations 1 - 5, all of the other switches S1 - S6 that are not provided along a particular line in FIG.1A and FIG.1B are2867-3395-WO1 / P231426-WO-UTL1 15 considered open. Table I below indicates the particular switch state of each of the switches S1 - S6 in each configuration.

[0052] The integer X is an integer that corresponds to a particular switch configuration for the switches S1 - S6. Thus, the integer X has a value of 1 - 5 to indicate a particular switch configuration. TABLE I Swit h S1 S2 S3 S4 S5 S6

[0053] With respect to the voltage converter 100 in FIG.1A and FIG.1B, the following sentence is completed for each of the switch configurations 1 - 5 in accordance with Table I.

[0054] In switch configuration X, the control circuit 130 is configured to generate the control output 132 such that: • the switch S1 is (Row X, Column S1 Switch State from Table I); • the switch S2 is (Row X, Column S2 Switch State from Table I); • the switch S3 is (Row X, Column S3 Switch State from Table I); • the switch S4 is (Row X, Column S4 Switch State from Table I); • the switch S5 is (Row X, Column S5 Switch State from Table I); and • the switch S6 is (Row X, Column S6 Switch State from Table I).

[0055] In FIG.1A and FIG.1B, the voltage node 126 is configured to receive the input voltage VIN and, thus, is equivalent to the power source node 106.

[0056] In switch configuration 1, the fly capacitor CFLY is being charged by the input voltage VIN from the power source node 106 and the output node 1222867-3395-WO1 / P231426-WO-UTL1 16 is being connected through the output inductor 116 to ground. If |VFLY| > |VOUT|, the output inductor 116 is demagnetized, the fly capacitor CFLY is recharged, the output capacitor 118 is recharged, and energy is delivered to the output node 122. However, if |VFLY| < |VOUT|, the output inductor 116 is magnetized, the fly capacitor CFLY is recharged, the output capacitor 118 is recharged, and energy is delivered to the output node 122. In alternative switch configurations, the switch S0 is closed and the switch S4 is open.

[0057] In switch configuration 2, the fly capacitor CFLY is recharged by the input voltage VIN. In one implementation, if the voltage node 126 is at ground, the output inductor 116 may also be connected via the switch S5 and the switch S2 (or in an alternative embodiment, through the switch S0 that is closed) to ground to create a voltage close to 0 V across the output inductor 116. In an alternative embodiment, if the voltage node 126 is set to the input voltage VIN, both sides of the output inductor 116 are presented at the input voltage VIN through the switches S5, S7.

[0058] In switch configuration 3, it is assumed that the voltage node 126 is configured to receive the input voltage VIN. In this case, the fly capacitor CFLY recharges, the output inductor 116 magnetizes, and the switch S2 grounds the inductor node 114. Unlike in switch configuration 2, in switch configuration 3, neither of the switches S0, S7 are closed.

[0059] In switch configuration 4, the fly capacitor CFLY discharges. If |VFLY| > |VOUT|, the output inductor 116 magnetizes. If |VFLY| < |VOUT|, the output inductor 116 demagnetizes. Furthermore, energy is delivered to the output node 122.

[0060] In switch configuration 5, the fly capacitor CFLY discharges. If the voltage node 126 is configured to receive the input voltage VIN, the output inductor 116 magnetizes. If the voltage node 126 is configured to receive the ground voltage, the output inductor 116 demagnetizes.

[0061] FIG.2 illustrates one embodiment of a voltage converter 200, in accordance with some embodiments.2867-3395-WO1 / P231426-WO-UTL1 17

[0062] The voltage converter 200 includes a charging circuit 102(1), a charging circuit 102(2), and the voltage converting circuit 104. The voltage converting circuit 104 is described above with respect to FIG.1. In this embodiment, the voltage node 126 is configured to receive the input voltage VIN.

[0063] The charging circuit 102(1) is the same as the charging circuit 102 described above with respect to FIG.1. In this embodiment, the elements of the charging circuit 102(1) have the same elements as those described in FIG.1 and element numbers in the charging circuit 102(1) are the same as those in the charging circuit 102 except that corresponding element numbers include the notation (1) to indicate that the charging circuit 102(1) is a first instance of a charging circuit just like the charging circuit 102 in FIG.1. The charging circuit 102(1) shown in FIG.2 includes the switch S7 but does not include an instance of the switch S0 described above.

[0064] The charging circuit 102(2) is the same as the charging circuit 102 described above with respect to FIG.1. In this embodiment, the elements of the charging circuit 102(2) have the same elements as those described in FIG.1 and element numbers in the charging circuit 102(2) are the same as those in the charging circuit 102 except that corresponding element numbers include the notation (2) to indicate that the charging circuit 102(2) is a second instance of a charging circuit just like the charging circuit 102 in FIG.1. The charging circuit 102(2) shown in FIG.2 includes the switch S0 but does not include an instance of the switch S7 described above.

[0065] The charging circuit 102(1) and the charging circuit 102(2) are connected to the inductor node 114 and are parallel with one another.

[0066] FIGs.2A - FIG.2D illustrate the voltage converter 200 shown in FIG.2 with closed circuit paths demonstrating different switch configuration, in accordance with some embodiments.

[0067] More specifically, FIGs.2A - 2D illustrate the voltage converter 200 in five different switch configurations named switch configurations 1 - 15. The lines corresponding to each one of the switch configurations 1 - 15 are closed circuit paths, thereby indicating which of the switches S1 - S6 are closed. For a2867-3395-WO1 / P231426-WO-UTL1 18 particular one of the switch configurations 1 - 15, all other switches S1 - S6 that are not provided along a particular line in FIGs.2A - 2D are considered open. Table II below indicates the particular switch state of each of the switches S1(1) - S4(1), S5, S6 in each configuration.

[0068] The integer Y is an integer that corresponds to a particular switch configuration, where Y has a value of 1 - 15 to indicate a particular one of the switch configurations 1 - 15. Table II indicates whether a particular one of the switches S1(1) - S4(1), S5, S6 is opened or closed in the charging circuit 102(1) in the switch configurations 1 - 15. Table III indicates whether a particular one of the switches S1(2) - S4(2), S5, S6 is opened or closed in the charging circuit 102(2) in the switch configurations 1-15. TABLE II2867-3395-WO1 / P231426-WO-UTL1 19 15 Closed Closed Open Open Open Openfollowing sentence is completed for each of the switch configurations 1 - 15 in accordance with Table II.

[0070] In switch configuration Y, the control circuit 130 is configured to generate the control output 132 such that: • the switch S1(1) is (Row Y, Column S1(1) Switch State from Table II); • the switch S2(1) is (Row Y, Column S2(1) Switch State from Table II); • the switch S3(1) is (Row Y, Column S3(1) Switch State from Table II); • the switch S4(1) is (Row Y, Column S4(1) Switch State from Table II); • the switch S5 is (Row Y, Column S5 Switch State from Table II); and • the switch S6 is (Row Y, Column S6 Switch State from Table II). TABLE III h d d d2867-3395-WO1 / P231426-WO-UTL1 20 13 Closed Closed Open Closed Open Open 14 Closed Closed Open Open Closed Open, generate the control output 132 such that: • the switch S1(2) is (Row Y, Column S1(2) Switch State from Table III); • the switch S2(2) is (Row Y, Column S2(2) Switch State from Table III); • the switch S3(2) is (Row Y, Column S3(2) Switch State from Table III); • the switch S4(2) is (Row Y, Column S4(2) Switch State from Table III); • the switch S5 is (Row Y, Column S5 Switch State from Table III); and • the switch S6 is (Row Y, Column S6 Switch State from Table III).

[0072] Reciprocal switch configurations are two switch configurations where the corresponding switches in the charging circuit 102(1) are in the same switching state as the corresponding switches in the charging circuit 102(2), and vice versa. In other words, in reciprocal switch configurations, the S1(1) switch state = the S1(2) switch state, the S2(1) switch state = the S2(2) switch state, the S3(1) switch state = the S3(2) switch state, the S4(1) switch state = the S4(2) switch state, the S5 switch state = the S5 switch state, and the S6 switch state = the S6 switch state. As shown in Table II and Table III, switch configuration 1 and switch configuration 8 are reciprocal switch configurations. Switch configuration 2 and switch configuration 9 are reciprocal switch configurations. Switch configuration 3 and switch configuration 10 are reciprocal switch configurations. Switch configuration 4 and switch configuration 11 are reciprocal switch configurations. Switch configuration 5 and switch configuration 12 are reciprocal switch configurations. Switch configuration 6 and switch configuration 13 are reciprocal switch configurations. Switch configuration 7 and switch configuration 14 are reciprocal switch configurations.

[0073] The voltage converter 200 includes the 10 principal switches S1(1), S1(2), S2(1), S2(2), S3(1), S3(2), S4(1), S4(2), S5, S6; the output inductor 116; and two fly capacitors CFLY(1), CFLY(2). The topology of the voltage converting2867-3395-WO1 / P231426-WO-UTL1 21 circuit 104 is of an inverting voltage converting circuit. This means that the input voltage VIN has a non-zero magnitude and a positive voltage polarity and the output voltage VOUT has a non-zero and a negative voltage polarity. The voltage converter 200 shown in FIG.2 is operable to operate as a buck converter, a boost converter, or a buck boost converter, as explained above. However, in some embodiments, the fly capacitor CFLY can run out of charge and, thus, reduce some of the advantages of the topology. In other words, either some portion of a duty cycle, or in some cycles, the fly capacitor CFLY has to be charged. The voltage converter 200 shown in FIG.2 is operable to operate as a buck converter, a boost converter, or a buck boost converter, as explained below. The topology has the two charging circuits 102(1), 102(2). This allows one of the two charging circuits 102(1), 102(2) to operate so as to provide a charge for voltage conversion while the other of the two charging circuits 102(2), 102(1) charges. In alternative embodiments, the voltage converter 200 has more than two charging circuits, like the charging circuits 102(1), 102(2).

[0074] The voltage converter 200 achieves higher efficiency, better transient performance, and, in some cases, a smaller area consumption and corresponding components for the same power output. The charging circuits 102(1), 102(2) allow for the inductor node 114 to be biased to an input voltage - VIN. In some examples, the voltage converter 200 operates as a buck converter, where the inductor node 114 toggles between the input voltage -VIN and a ground voltage to generate a filtered output voltage -VOUT. The different cycles can be switched back and forth between the charging circuit 102(1), 102(2) in a ping-pong fashion to allow for greater recharge times for the fly capacitors CFLY(1), CFLY(2). In this case, one of the charging circuits 102(1), 102(2) can be disabled and the other is enabled when operating in discrete conduction mode (DCM). Providing both of the charging circuits 102(1), 102(2) reduces the RMS current through the switches S1(1), S2(1), S1(2), S2(2). Furthermore, utilizing both of the charging circuits 102(1), 102(2) also increases the average voltage level of voltages VFLY(1), VFLY(2) through the fly capacitors CFLY(1), CFLY(2), which reduces energy losses.2867-3395-WO1 / P231426-WO-UTL1 22

[0075] In this embodiment, the voltage node 126 is configured to receive the input voltage VIN. This allows the inductor node 124 to be biased at a voltage level of the input voltage VIN while the inductor node 114 of the output inductor 116 is biased at a voltage level near the input voltage -VIN or ground. Biasing the inductor node 124 at the voltage level of the input voltage +VIN allows the output inductor 116 to magnetize almost twice as fast, reducing inductor current ripple, DC current, and saturation current requirements. Biasing the inductor node 124 at ground through the switch S5 reduces the voltage stress through the switch S5 (and, optionally, through the switch S7). There are multiple operating regions that are exercised using different sequences of circuit states. Each of the circuit states corresponds to different ones of the switch configurations 1 - 15 from Table II and Table III, as explained below. In the buck region, when |VOUT| < |VIN|, the topology could be operating in a continuous conduction mode (CCM) or a DCM. In the buck boost region, when |VOUT| ~ |VIN|, the voltage converter 200 operates in a pass through mode or using a buck boost region sequence in a CCM or a DCM. In the boost region, when |VOUT| > |VIN|, the voltage converter 200 can operate in a CCM or a DCM.

[0076] As shown in Table II and Table III, there are at least 15 configurations that the control circuit 130 can use to achieve energy transfer in different regions of operation. In switch configuration 1 and switch configuration 8, an inductor current IL flows from the output node 122 to the ground node 108 through the output inductor 116 and the fly capacitor CFLY(1) (for switch configuration 1) or the fly capacitor CFLY(2) (for switch configuration 8). If |VOUT| < |VCFLY(1)| (for switch configuration 1) or |VCFLY(2)| (for switch configuration 8), the fly capacitor CFLY(1) (for switch configuration 1) or the fly capacitor CFLY(2) (for switch configuration 8) decreases in energy while the energy stored in the output inductor 116 increases. In this case, there is an energy transfer to the output node 122. Additionally, the output inductor 116 is magnetized, the fly capacitor CFLY(1) (for switch configuration 1) or the fly capacitor CFLY(2) (for switch configuration 8) loses charge, and the output capacitor 118 is recharged. If |VOUT| > |VCFLY(1)| (for switch configuration 1) or |VCFLY(2)| (for switch2867-3395-WO1 / P231426-WO-UTL1 23 configuration 8), the energy stored by the fly capacitor CFLY(1) (for switch configuration 1) or the fly capacitor CFLY(2) (for switch configuration 8) decreases, the output inductor 116 energy decreases, and there is an energy transfer to the output node 122. Also, the output inductor 116 is demagnetized, the fly capacitor CFLY(1) (for switch configuration 1) or the fly capacitor CFLY(2) (for switch configuration 8) loses charge, and the output capacitor 118 is recharged.

[0077] In switch configuration 2 and switch configuration 9, the output inductor 116 is demagnetized, the fly capacitor CFLY(1) (for switch configuration 2) or the fly capacitor CFLY(2) (for switch configuration 9) is recharged and the output capacitor 118 is recharged. In some cases, the fly capacitor CFLY(1) (for switch configuration 2) or the fly capacitor CFLY(2) (for switch configuration 9) is not recharged.

[0078] In switch configuration 3 and switch configuration 10, the switches S1, S2, S4, S5 (where the switches S1, S2, S4 are referring to the switches S1(1), S2(1), S4(1) for switch configuration 3 and where the switches S1, S2, S4 are referring to the switches S1(2), S2(2), S4(2) for switch configuration 10) are enabled. The switch S0 may also be enabled if available. The switch S4 may be disabled if the switch S0 is available and enabled. In some cases, when a first terminal of the switch S5 is connected to the input voltage VIN through the voltage node 126, the fly capacitors CFLY(1), CFLY(2) are recharged (gain energy) and the output inductor 116 is magnetized (gains energy). In other embodiments, the voltage node 126 is connected to ground (see FIG.4). In this alternate embodiment, the first terminal of the switch S5 is connected to a ground voltage GND. Accordingly, the fly capacitors CFLY(1), CFLY(2) are recharged (gain energy) and the output inductor 116 is slowly demagnetized (leaks energy). In some cases, the switch S1 may be disabled, and the fly capacitors CFLY(1), CFLY(2) are not recharged. In switch configurations 1 - 3, the switches S1(2), S2(2) are enabled and the fly capacitor CFLY(2) is recharged. In switch configurations 8 - 11, the switches S1(1), S2(1) are enabled and the fly capacitor CFLY(1) is recharged.2867-3395-WO1 / P231426-WO-UTL1 24

[0079] In switch configurations 4-7 and reciprocal switch configurations 11-14, the output inductor 116 is demagnetized, the fly capacitor CFLY(1) (in switch configurations 4-7) or the fly capacitor CFLY(2) (in switch configurations 11-14) is recharged and the output capacitor 118 is recharged.

[0080] In switch configuration 5 and switch configuration 12, the fly capacitor CFLY(1) (in switch configurations 4-6) or the fly capacitor CFLY(2) (in switch configurations 11-13) discharges and thereby loses energy, the output inductor 116 is magnetized (gains energy) at a rate approximately proportional to VIN + (|VCFLY(1)| (in switch configuration 5) or VIN + (|VCFLY(2)| (in switch configuration 12), and the voltage node 126 supplies energy with the input voltage VIN.

[0081] In switch configuration 6 and switch configuration 13, the fly capacitor CFLY(1) (in switch configuration 6) and the fly capacitor CFLY(2) (in switch configuration 13) is recharged. In some embodiments, the switch S0 is closed. The switch S4(1) (in switch configuration 6) or the switch S4(2) (in switch configuration 13) maintains one side of the output inductor 116 at low impedance. In switch configuration 6, the switches S4(1), S2(1) connect the inductor node 114 to ground while the switch S5 is open and, thus, the inductor node 124 is floating. In switch configuration 13, the switches S4(2), S2(2) connect the inductor node 114 to ground while the switch S5 is open and, thus, the inductor node 124 is floating.

[0082] In switch configuration 7 and switch configuration 14, the fly capacitor CFLY(1) (in switch configuration 7) and the fly capacitor CFLY(2) (in switch configuration 14) is recharged. In some embodiments, the switch S0 is closed. The switch S5 (in switch configuration 6 and switch configuration 14) maintains one side of the output inductor 116 at low impedance. In switch configuration 7 and switch configuration 14, the switches S4(1), S2(1), S1(2), S2(2) are open so that the inductor node 114 is floating while the switch S5 is closed and, thus, the inductor node 124 is connected to the voltage node 126 to receive the input voltage VIN.2867-3395-WO1 / P231426-WO-UTL1 25

[0083] In switch configuration 15, both the fly capacitor CFLY(1) and the fly capacitor CFLY(2) are recharged with the input voltage VIN through the power source node 106. In switch configurations 1 - 7, the charging circuit 102(1) is being utilized to provide charge to the output inductor 116 and the fly capacitor CFLY(2) is being recharged. Additionally, in switch configurations 8 - 14 the charging circuit 102(2) is being utilized to provide charge to the output inductor 116 and the fly capacitor CFLY(1) is being recharged. Therefore, by using two charging circuits 102(1), 102(2) with reciprocal switch configurations, the power stage efficiency of the voltage converter 200 is increased because there is less current ripple at the output capacitor 118. Switch configuration 15 recharges both of the fly capacitors CFLY(1), CFLY(2). Switch configuration 15 may be used in a DCM operation, where the inductor current IL is zero or close to zero. In switch configuration 15, one may choose to recirculate the inductor current IL of the output inductor 116 by including and closing the switch S7. Not all switch configurations 1 - 15 are necessary for proper operation. Some switch configurations 1- 15 are used and not used depending on whether the voltage converter 200 is used to operate in buck, boost, or buck boost regions of operation. Switch configurations 1- 15 do not have to follow a particular order and some switch configurations 1 - 15 are not utilized during a switching cycle, depending on the mode of operation.

[0084] FIG.2E illustrates buck circuit states 1 - 4 that are implemented during a switching period for the voltage converter 200 shown in FIG.2, in accordance with some embodiments.

[0085] Buck circuit states 1 - 4 operate the voltage converter 200 in the inverting buck region, where |VOUT| is lower than |VIN|. The charging circuits 102(1), 102(2) are operated in ping-pong fashion. When one of the charging circuits 102(1), 102(2) is actively transferring energy between the output node 122, the power source node 106, and the inductor node 126, the other one of the charging circuits 102(2), 102(1) is recharging the fly capacitors CFLY(1), CFLY(2). This allows for at least a full period of capacitor recharge time. When the load impedance of the load 120 is low, only one of the two charging circuits2867-3395-WO1 / P231426-WO-UTL1 26 102(1), 102(2) can be used during every switching period and may be used while one of the other charging circuits 102(2), 102(1) idles every switching period.

[0086] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in a buck circuit state 1 during a first portion of the switching period. In the buck circuit state 1, the voltage converter 200 is in switch configuration 1 from Table II and Table III. As such, the charging circuit 102(1) magnetizes the output inductor 116 by presenting the fly voltage VFLY(1) across the fly capacitor CFLY(1) at the inductor node 114. At the beginning of the buck circuit state 1, the fly voltage VFLY(1) is presented at the inductor node 114 so as to have a negative polarity and a voltage magnitude at or near |VIN|. The charging circuit 102(2) charges the fly capacitor CFLY(2) with the input voltage VIN at the power source node 106.

[0087] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in a buck circuit state 2 during a second portion of the switching period. In the buck circuit state 2, the voltage converter 200 is in switch configuration 2 from Table II and Table III. In some embodiments of the buck circuit state 2, the switch S0 is closed. In the buck circuit state 2, the charging circuit 102(1) demagnetizes the output inductor 116 while transferring energy between the output node 122 and the power source node 106. The charging circuit 102(2) charges the fly capacitor CFLY(2) with the input voltage VIN from the power source node 106.

[0088] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in a buck circuit state 3 during a third portion of the switching period. In the buck circuit state 3, the voltage converter 200 is in switch configuration 8 from Table II and Table III. Switch configuration 8 is a reciprocal switching configuration to switch configuration 1. As such, the charging circuit 102(2) magnetizes the output inductor 116 by presenting the fly voltage VFLY(2) across the fly capacitor CFLY(2) at the inductor node 114. At the beginning of the buck circuit state 3, the fly voltage VFLY(2) is presented at the inductor node 114 so as to have a negative voltage polarity and a voltage2867-3395-WO1 / P231426-WO-UTL1 27 magnitude at or near |VIN|. The charging circuit 102(1) charges the fly capacitor CFLY(1) with the input voltage VIN at the power source node 106.

[0089] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in a buck circuit state 4 during a fourth portion of the switching period. In the buck circuit state 4, the voltage converter 200 is in switch configuration 9 from Table II and Table III. In some embodiments of the buck circuit state 4, the switch S0 is closed. In the buck circuit state 4, the charging circuit 102(2) demagnetizes the output inductor 116 while transferring energy between output node 122 and node 106(4). The charging circuit 102(1) charges the fly capacitor CFLY(1) with the input voltage VIN from the node 106.

[0090] For the next switching period, the control circuit 130 is then configured to generate the control output 132 to go back to the buck circuit state 1, then to the buck circuit state 2, then to the buck state circuit state 3, and then through the buck circuit state 4. The control circuit 130 is configured to operate the voltage converter 200 so as to cycle through the buck circuit states 1 - 4 so long as the voltage converter 200 is configured to operate in the buck region.

[0091] FIG.2F illustrates boost circuit states 1-4 that are implemented during a switching period for the voltage converter 200 shown in FIG.2, in accordance with some embodiments.

[0092] Boost circuit states 1-4 operate the voltage converter 200 in the inverting boost region, where |VOUT| is greater than |VIN|. The charging circuits 102(1), 102(2) are operated in ping-pong fashion. When one of the charging circuits 102(1), 102(2) is actively transferring energy between the output node 122 and the nodes 106, 126, the other charging circuit 102(2), 102(1) is recharging the corresponding one of the fly capacitors CFLY(1), CFLY(2). When the load impedance is low, only one of the charging circuits 102(1), 102(2) may be used.

[0093] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in boost circuit state 1 during a first portion of the switching period. In the boost circuit state 1, the voltage converter2867-3395-WO1 / P231426-WO-UTL1 28 200 is in switch configuration 5 from Table II and Table III. In the boost circuit state 1, the charging circuit 102(1) magnetizes the output inductor 116 without transferring energy between the output node 122 and the power source node 106. Instead, the charging circuit 102(1) magnetizes the output inductor 116 with charge from the input voltage VIN from the voltage node 126. The charging circuit 102(2) is configured to charge the fly capacitor CFLY(2) with the input voltage VIN from the power source node 106.

[0094] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in boost circuit state 2 during a second portion of the switching period. In the boost circuit state 2, the voltage converter 200 is in switch configuration 1 from Table II and Table III. In the boost circuit state 2, the charging circuit 102(1) demagnetizes the output inductor 116 while transferring energy between the output node 122 and the power source node 106. The charging circuit 102(2) is configured to charge the fly capacitor CFLY(2) with the input voltage VIN from the power source node 106.

[0095] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in boost circuit state 3 during a third portion of the switching period. In the boost circuit state 3, the voltage converter 200 is in switch configuration 12 from Table II and Table III. Switch configuration 12 and switch configuration 5 are reciprocal switch configurations. In the boost circuit state 3, the charging circuit 102(2) magnetizes the output inductor 116 without transferring energy between the output node 122 and the power source node 106. Instead, the charging circuit 102(2) magnetizes the output inductor 116 with charge from the input voltage VIN from the voltage node 126. The charging circuit 102(1) is configured to charge the fly capacitor CFLY(1) with the input voltage VIN from the power source node 106.

[0096] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in boost circuit state 4 during a fourth portion of the switching period. In the boost circuit state 4, the voltage converter 200 is in switch configuration 8 from Table II and Table III. In the boost circuit state 4, the charging circuit 102(2) demagnetizes the output inductor 116 while2867-3395-WO1 / P231426-WO-UTL1 29 transferring energy between the output node 122 and the power source node 106. The charging circuit 102(1) is configured to charge the fly capacitor CFLY(1) with the input voltage VIN from the power source node 106.

[0097] For the next switching period, the control circuit 130 is then configured to generate the control output 132 to go back to the boost circuit state 1, then to the boost circuit state 2, then to the boost state circuit state 3, and then through the boost circuit state 4. The control circuit 130 is configured to operate the voltage converter 200 so as to cycle through the boost circuit states 1-4 so long as the voltage converter 200 is configured to operate in the boost region. Arrows indicate current flow. States do not need to be executed in any particular order within a switching period, however, the presented numerical order provides an energy efficient operation. States without current flow are possible and provide a way for a DCM operation. States where the output inductor 116 has a current that recirculates may also provide a way for a DCM operation. Under light load conditions and a low buck duty cycle (e.g., where magnetization time is relatively similar or lower than demagnetization time), a single charging circuit (see FIG.1) can be used. To minimize switching losses, the switches S1(1) - S4(1), S1(2) - S4(2) are switched at a frequency of fsw / 2 (fsw refers to switch frequency) and the switch S6 is switched at a frequency fsw, in some embodiments. In some embodiments, the switch S0 is an optional switch that may be used to further optimize efficiency.

[0098] FIG.2G illustrates buck boost circuit states 1-3 that are implemented during a switching period for the voltage converter 200 shown in FIG.2, in accordance with some embodiments.

[0099] Buck boost circuit states 1-3 operate the voltage converter 200 in the inverting buck boost region, where |VOUT| is approximately equal to |VIN|. The charging circuits 102(1), 102(2) are operated in ping-pong fashion. However, the buck boost circuit states 1-3 are shown only when the charging circuit 102(1) is transferring energy to the output node 122 while the charging circuit 102(2) is charging the fly capacitor CFLY(2). Buck boost circuit states 4-6 are not shown in FIG.2G for the sake of clarity. However, the buck boost circuit states 1-3 and2867-3395-WO1 / P231426-WO-UTL1 30 the buck boost circuit states 4-6 are reciprocal circuit states, as will be explained in further detail below. When one of the charging circuits 102(1), 102(2) is actively transferring energy between the output node 122 and the power source node 106, the other charging circuit 102(2), 102(1) is recharging the corresponding one of the fly capacitors CFLY(1), CFLY(2). When the load impedance is low, only one of the charging circuits 102(1), 102(2) may be used (see FIG.2).

[0100] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in buck boost circuit state 1 during a first portion of the switching period. In the buck boost circuit state 1, the voltage converter 200 is in switch configuration 4 from Table II and Table III. In some embodiments, the switch S0 is closed in the buck boost circuit state 1. In the buck boost circuit state 1, the charging circuit 102(1) demagnetizes the output inductor 116 while transferring energy from the output node 122 to ground. The charging circuit 102(2) is configured to charge the fly capacitor CFLY(2) with the input voltage VIN from the power source node 106.

[0101] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in buck boost circuit state 2 during a second portion of the switching period. In the buck boost circuit state 2, the voltage converter 200 is in switch configuration 5 from Table II and Table III. In the buck boost circuit state 2, the charging circuit 102(1) magnetizes the output inductor 116 by transferring energy from the voltage node 126 to the output inductor 116. The charging circuit 102(2) is configured to charge the fly capacitor CFLY(2) with the input voltage VIN from the power source node 106.

[0102] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in buck boost circuit state 3 during a third portion of the switching period. In the buck boost circuit state 3, the voltage converter 200 is in switch configuration 1 from Table II and Table III. In the buck boost circuit state 3, the charging circuit 102(1) demagnetizes the output inductor 116 in response to |VOUT| > |VIN| and magnetizes the output inductor 116 in response to |VOUT| < |VIN| by transferring energy between the output capacitor2867-3395-WO1 / P231426-WO-UTL1 31 118 and the fly capacitor CFLY(1). The charging circuit 102(2) is configured to charge the fly capacitor CFLY(2) with the input voltage VIN from the power source node 106.

[0103] The buck boost states 4-6 are not shown but are simply reciprocal states to the buck boost states 1-3.

[0104] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in buck boost circuit state 4 during a fourth portion of the switching period. In the buck boost circuit state 4, the voltage converter 200 is in switch configuration 11 from Table II and Table III. In some embodiments, the switch S0 is closed in the buck boost circuit state 4. In the buck boost circuit state 4, the charging circuit 102(2) demagnetizes the output inductor 116 while transferring energy from the output node 122 to ground. The charging circuit 102(1) is configured to charge the fly capacitor CFLY(1) with the input voltage VIN from the power source node 106.

[0105] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in buck boost circuit state 5 during a fifth portion of the switching period. In the buck boost circuit state 5, the voltage converter 200 is in switch configuration 5 from Table II and Table III. In the buck boost circuit state 5, the charging circuit 102(2) magnetizes the output inductor 116 by transferring energy from the voltage node 126 to the output inductor 116. The charging circuit 102(1) is configured to charge the fly capacitor CFLY(1) with the input voltage VIN from the power source node 106.

[0106] The control circuit 130 is configured to generate the control output 132 so as to provide the voltage converter 200 in buck boost circuit state 6 during a sixth portion of the switching period. In the buck boost circuit state 6, the voltage converter 200 is in switch configuration 8 from Table II and Table III. In the buck boost circuit state 6, the charging circuit 102(2) demagnetizes the output inductor 116 in response to |VOUT| > |VIN| and magnetizes the output inductor 116 in response to |VOUT| < |VIN| by transferring energy between the output capacitor 118 and the fly capacitor CFLY(2). The charging circuit 102(1) is configured to2867-3395-WO1 / P231426-WO-UTL1 32 charge the fly capacitor CFLY(1) with the input voltage VIN from the power source node 106.

[0107] The switch S0 is optional and may be used to further optimize efficiency. States do not need to be executed in any particular order within a switching period. However, the suggested numerical order provides one energy efficient way of switching. States without current flow are possible and provide a way for a DCM operation. States where the output inductor 116 has a current that recirculates may also provide a way for a DCM operation. To minimize switching losses, the switches S1(1) - S4(1), S1(2) - S4(2) are switched at a frequency of fsw / 2 and the switches S6, S7 are switched at a frequency of fsw.

[0108] FIG.3 illustrates an embodiment of a voltage converter 300, in accordance with some embodiments.

[0109] The voltage converter 300 includes the voltage converting circuit 104, the charging circuit 102(1), and the charging circuit 102(2), described above with respect to FIG.2. The voltage converter 300 includes a control circuit 302. The control circuit 302 is one embodiment of the control circuit 130 shown in FIG.1 and FIG.2. The control circuit 302 is configured to operate the voltage converting circuit 104, the charging circuit 102(1), and the charging circuit 102(2) in the same manner described above with respect to FIGs.2A - 2G.

[0110] The control circuit 302 includes an inverting voltage amplifier 304, a resistor 306, a resistor 308, a constant-peak-current pulse frequency modulation (PFM) controller 310, a feedback node 312, a resistor 318, a capacitor 320, an error amplifier 321, a capacitor 322, a resistor ladder digital to analog converter (DAC) 324, a boost comparator 325, and a buck comparator 326, a resistor 328, a capacitor 330, and control logic and latch 332. The latch in the control logic and latch 332 is simply a latch used to hold the values of the control logic for the purposes of timing. Thus, this component will simply be referred to as the control logic 332.

[0111] The inverting voltage amplifier 304 is configured to receive the output voltage VOUT and is configured to generate an inverted output voltage VOUT’. The inverted output voltage VOUT’ thus has the same voltage magnitude |VOUT|2867-3395-WO1 / P231426-WO-UTL1 33 as the output voltage VOUT, but has a positive voltage polarity. The resistor 306 is connected between an output of the inverting voltage amplifier 304 and the feedback node 312. The resistor 308 is connected between the feedback node 312 and ground. The resistor 306 has a resistance of R1 and the resistor 308 has a resistance of R2. The resistors 306, 308 thus form a voltage divider that generates a feedback voltage VFB based on the inverted output voltage VOUT’ and, therefore, also based on the output voltage VOUT.

[0112] The constant-peak-current PFM controller 310 is configured to receive the feedback voltage VFB so as to generate a control output C-PFM in a first operational mode. In the first operational mode (which is explained in further detail below), the boost comparator 325 and the buck comparator 326 are deactivated. In a second mode of operation (which is also explained in further detail below), the constant-peak-current PFM controller 310 is deactivated and the boost comparator 325 and the buck comparator 326 are activated.

[0113] The resistor 318 and the capacitor 320 are connected in parallel between the feedback node 312 and an inverting input of the error amplifier 321. A non-inverting input of the error amplifier 321 is configured to receive a reference voltage VREF_P. The resistor ladder DAC 324 (also referred to as the boost ramp generator 324) is configured to receive a reference voltage VREF and generate the reference voltage VREF_P based on the reference voltage VREF. The voltage level of the reference voltage VREF_P is based on an eight bit input VSET, which thereby selects the voltage level of the reference voltage VREF_P. The voltage level of the reference voltage VREF_P varies between 0.5 V - 5.7 V, depending on the value of eight bit input VSET.

[0114] The resistor 328 is connected in series with the capacitor 330. The series connected resistor 328 and the capacitor 330 are connected in parallel with the capacitor 322 between the inverting input of the error amplifier 321 and the output of the error amplifier 321. The error amplifier 321 is configured to generate an error voltage VERR at its output. The error voltage VERR is based on the difference between the feedback voltage VFB and the reference voltage VREF_P.2867-3395-WO1 / P231426-WO-UTL1 34

[0115] The boost comparator 325 is configured to receive the error voltage VERR at an inverting terminal and is configured to receive a boost ramp voltage VBOOST at a non-inverting terminal. In response to receiving the error voltage VERR and the boost ramp voltage VBOOST, the boost comparator 325 is configured to generate an output voltage C-PWM-BOOST based on the difference between the boost ramp voltage VBOOST and the error voltage VERR.

[0116] The buck comparator 326 is configured to receive the error voltage VERR at an inverting terminal and is configured to receive a buck ramp voltage VBUCK (shown as “BUCK RAMP” in FIG.3) at a non-inverting terminal. In response to receiving the error voltage VERR and the buck ramp voltage VBUCK, the buck comparator 326 is configured to generate an output voltage C- PWM-BUCK based on the difference between the buck ramp voltage VBUCK and the error voltage VERR.

[0117] The output voltage C-PWM-BOOST and the output voltage C-PWM- BUCK are received by the control logic 332. Based on the output voltage C- PWM-BOOST and the output voltage C-PWM-BUCK, the control logic 332 is configured to generate a control voltage Φbu, a control voltage Φ’bu, a control voltage Φbo, and a control voltage Φ’bo. In combination, the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo are an example of the control output 132 shown in FIG.2. The switch S1(1), the switch S2(1), and the switch S3(2) are configured to receive the control voltage Φbu. The switch S1(1), the switch S2(1), and the switch S3(2) are thus opened and closed (as described in Table II and Table III) in response to the control voltage Φbu. The switch S1(2), the switch S2(2), and the switch S3(1) are configured to receive the control voltage Φ’bu. The switch S1(2), the switch S2(2), and the switch S3(1) are thus opened and closed (as described in Table II and Table III) in response to the control voltage Φ’bu. The switch S6 is configured to receive the control voltage Φbo. The switch S6 is thus opened and closed (as described in Table II and Table III) in response to the control voltage Φbo. The switch S5 is configured to receive the control voltage Φ’bo. The2867-3395-WO1 / P231426-WO-UTL1 35 switch S5 is thus opened and closed (as described in Table II and Table III) in response to the control voltage Φ’bo.

[0118] In the first mode of operation, the constant-peak-current PFM controller 310 is activated and the boost ladder DAC 324 and the buck comparator 326 are both deactivated. The constant-peak-current PFM controller 310 is configured to receive the feedback voltage VFB and generate the control output C-PFM. The control logic 332 is configured to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo based on the control output C-PFM. In a buck mode, the constant-peak-current PFM controller 310 generates the control output C-PFM so that the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo cycle through the buck circuit states 1 - 4, as described above with respect to FIG.2E. In a boost mode, the constant-peak-current PFM controller 310 generates the control output C-PFM so that the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo cycle through the boost circuit states 1 - 4, as described above with respect to FIG.2F. In a buck boost mode, the constant-peak-current PFM controller 310 generates the control output C-PFM so that the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo cycle through the buck boost circuit states 1 - 6, where the buck boost circuit states 1 - 3 are shown in FIG.2G and the buck boost circuit states 4 - 6 are reciprocal buck boost states. The constant- peak-current PFM controller 310 is configured to detect peak currents. The constant-peak-current PFM controller 310 is advantageous in circumstances where there are light loads and where the inductor current IL cycles to a peak and then stays at a minimum current level for a majority of the switching period where there are very little losses. The constant-peak-current PFM controller 310 is activated in a DCM. The constant-peak-current PFM controller 310 detects a peak current level of the inductor current IL based on the feedback voltage VFB such that the control output C-PFM includes a pulse once the peak current level is detected. The pulse indicates to the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control2867-3395-WO1 / P231426-WO-UTL1 36 voltage Φ’bo in accordance to a subsequent circuit state, which depends on whether the buck, boost, or buck boost operation is being implemented.

[0119] FIG.3A is voltage and current graphs that illustrate the operation of the voltage converter 300 shown in FIG.3 with the error amplifier 321 and the buck comparator 326 activated in a CCM (i.e., second operational mode), in accordance with some embodiments.

[0120] The top graph is a voltage graph that illustrates the output voltage C- PWM-BOOST and the output voltage C-PWM-BUCK versus time (the bottom- most axis is the time axis for all of the graphs in FIG.3A). As shown, the output voltage C-PWM-BOOST remains at the same voltage level because the boost comparator 325 is inactive.

[0121] The next graph from the top is a voltage graph that illustrates the boost ramp voltage VBOOST, the buck ramp voltage VBUCK, and the error voltage VERR. In this embodiment, the error voltage VERR only crosses the buck ramp voltage VBUCK because the voltage converter 300 is operating in the buck region.

[0122] The second graph from the bottom is a current graph that illustrates the inductor current IL versus time.

[0123] The graph at the bottom illustrates the output voltage VOUT at the output node 122 versus time.

[0124] In this embodiment, the input voltage VIN is 4 V and the output voltage VOUT is approximately -2 V. The output inductor 116 is 2.2 microhenries and the output capacitor 118 is approximately 10 microfarads.

[0125] As shown in FIG.3A, at 4.00345 milliseconds, the buck ramp surpasses the error voltage VERR. In response, the output voltage C-PWM- BUCK is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck circuit state 1 described above with respect to FIG.2E. As such, the output inductor 116 is magnetized and the inductor current IL becomes more and more positive.2867-3395-WO1 / P231426-WO-UTL1 37 In response, the magnitude of the output voltage VOUT decreases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck circuit state 1 from 4.00345 milliseconds until 4.00375 milliseconds.

[0126] As shown in FIG.3A, at 4.00375 milliseconds, the buck ramp reaches and then drops below the error voltage VERR. In response, the output voltage C-PWM-BUCK is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck circuit state 2 described above with respect to FIG.2E. As such, the output inductor 116 demagnetizes and the inductor current IL becomes more and more negative. In response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck circuit state 2 from 4.00375 milliseconds until 4.00413 milliseconds.

[0127] As shown in FIG.3A, at 4.00413 milliseconds, the buck ramp surpasses the error voltage VERR. In response, the output voltage C-PWM- BUCK is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck circuit state 3 described above with respect to FIG.2E. As such, the output inductor 116 magnetizes and the inductor current IL becomes more and more positive. In response, the magnitude of the output voltage VOUT decreases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck circuit state 3 from 4.00413 milliseconds until 4.00445 milliseconds.

[0128] As shown in FIG.3A, at 4.00445 milliseconds, the buck ramp reaches and then drops below the error voltage VERR. In response, the output voltage C-PWM-BUCK is received by the control logic 332, which causes the control2867-3395-WO1 / P231426-WO-UTL1 38 logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck circuit state 4 described above with respect to FIG.2E. As such, the output inductor 116 demagnetizes and the inductor current IL becomes more and more negative. In response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck circuit state 4 from 4.00445 milliseconds until 4.00483. The cycle then goes back to the buck circuit state 1 and repeats.

[0129] FIG.3B is voltage and current graphs that illustrate the operation of the voltage converter 300 shown in FIG.3 with the error amplifier 321 and the boost comparator 325 activated in the DCM (i.e., the first operational mode), in accordance with some embodiments.

[0130] The top graph is a voltage graph that illustrates the boost ramp voltage VBOOST, the buck ramp voltage VBUCK, and the error voltage VERR versus time (the bottom-most axis is the time axis for all of the graphs in FIG.3B). In this embodiment, the error voltage VERR only crosses the boost ramp voltage VBOOST because the voltage converter 300 is operating in the boost region.

[0131] The next graph from the top is a voltage graph that illustrates the output voltage C-PWM-BOOST versus time.

[0132] The second graph from the bottom is a current graph that illustrates the inductor current IL versus time.

[0133] The graph at the bottom illustrates the output voltage VOUT at the output node 122 versus time.

[0134] In this embodiment, the input voltage VIN is 4 V and the output voltage VOUT is approximately -6 V. The output inductor 116 is 2.2 microhenries and the output capacitor 118 is approximately 10 microfarads.

[0135] As shown in FIG.3B, at 3.6335 milliseconds, the boost ramp is below the error voltage VERR. In response, the output voltage C-PWM-BOOST is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and2867-3395-WO1 / P231426-WO-UTL1 39 the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the boost circuit state 1 described above with respect to FIG.2F. As such, the output inductor 116 is magnetized and the inductor current IL becomes more and more negative. In response, the magnitude of the output voltage VOUT decreases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck circuit state 1 from 3.6335 milliseconds until 3.6333 milliseconds.

[0136] As shown in FIG.3B, at 3.6333 milliseconds, the boost ramp reaches and surpasses the error voltage VERR. In response, the output voltage C-PWM- BOOST is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the boost circuit state 2 described above with respect to FIG.2F. As such, the output inductor 116 demagnetizes and the inductor current IL becomes more and more positive. In response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the boost circuit state 2 from 3.6333 milliseconds until 3.63375 milliseconds.

[0137] As shown in FIG.3B, at 3.63375 milliseconds, the boost ramp drops below the error voltage VERR. In response, the output voltage C-PWM-BOOST is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the boost circuit state 3 described above with respect to FIG.2F. As such, the output inductor 116 magnetizes and the inductor current IL becomes more and more negative. In response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 1042867-3395-WO1 / P231426-WO-UTL1 40 remain in the boost circuit state 3 from 3.63375 milliseconds until 3.63340 milliseconds.

[0138] As shown in FIG.3B, at 3.63340 milliseconds, the boost ramp reaches and then surpasses the error voltage VERR. In response, the output voltage C- PWM-BOOST is received by the control logic 332, which causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the boost circuit state 4 described above with respect to FIG.2F. As such, the output inductor 116 is demagnetized and the inductor current IL becomes more and more positive. In response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the boost circuit state 4 from 3.63340 milliseconds until 3.6345. The cycle then goes back to the boost circuit state 1 and repeats.

[0139] FIG.3C is voltage and current graphs that illustrate the operation of the voltage converter 300 shown in FIG.3 with the error amplifier 321, the boost comparator 325, and the buck comparator 326 activated in a CCM (i.e., second operational mode), in accordance with some embodiments.

[0140] The top graph is a current graph that illustrates the inductor current IL versus time (the bottom-most axis is the time axis for all of the graphs in FIG. 3C).

[0141] The next graph from the top illustrates the output voltage VOUT at the output node 122 versus time.

[0142] The middle graph illustrates the input voltage VIN versus time.

[0143] The second graph from the bottom illustrates the output voltage C- PWM-BUCK versus time.

[0144] The bottom graph illustrates the output voltage C-PWM-BOOST versus time.2867-3395-WO1 / P231426-WO-UTL1 41

[0145] In this embodiment, the input voltage VIN is 4 V and the output voltage VOUT is approximately -4 V. The output inductor 116 is 2.2 microhenries and the output capacitor 118 is approximately 10 microfarads.

[0146] As shown in FIG.3C, at 3.7324 milliseconds, the output voltage C- PWM-BUCK is triggered into a high voltage state (approximately at ground) while the output voltage C-PWM-BOOST remains in a low voltage state (approximately at -4 V). In response, the control logic 332 causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck boost circuit state 1 described above with respect to FIG.2G. As such, the output inductor 116 is demagnetized and the inductor current IL becomes more and more positive. In response, the magnitude of the output voltage VOUT decreases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck boost circuit state 1 from 3.7324 milliseconds until 3.73245 milliseconds.

[0147] As shown in FIG.3C, at 3.73245 milliseconds, the output voltage C- PWM-BUCK is triggered into a low voltage state while the output voltage C- PWM-BOOST is triggered into a high voltage state. In response, the control logic 332 causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck boost circuit state 2 described above with respect to FIG. 2G. As such, the output inductor 116 is magnetized and the inductor current IL becomes more and more negative. Also, in response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck boost circuit state 2 from 3.73245 milliseconds until 3.73255 milliseconds.

[0148] As shown in FIG.3C, at 3.73255 milliseconds, the output voltage C- PWM-BUCK remains in the low voltage state while the output voltage C-PWM- BOOST is triggered into a low voltage state. In response, the control logic 3322867-3395-WO1 / P231426-WO-UTL1 42 causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck boost circuit state 3 described above with respect to FIG. 2G. As such, the output inductor 116 is demagnetized slowly and the inductor current IL becomes more and more positive slowly. Also, in response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck boost circuit state 3 from 3.73255 milliseconds until 3.73331 milliseconds.

[0149] As shown in FIG.3C, at 3.73331 milliseconds, the output voltage C- PWM-BUCK is triggered into a high voltage state (approximately at ground) while the output voltage C-PWM-BOOST remains in a low voltage state (approximately at -4 V). In response, the control logic 332 causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck boost circuit state 4 described above with respect to FIG.2G. As such, the output inductor 116 is demagnetized and the inductor current IL becomes more and more positive. In response, the magnitude of the output voltage VOUT decreases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck boost circuit state 4 from 3.73331 milliseconds until 3.733315 milliseconds.

[0150] As shown in FIG.3C, at 3.733315 milliseconds, the output voltage C- PWM-BUCK is triggered into a low voltage state while the output voltage C- PWM-BOOST is triggered into a high voltage state. In response, the control logic 332 causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck boost circuit state 5 described above with respect to FIG. 2G. As such, the output inductor 116 is magnetized and the inductor current IL becomes more and more negative. Also, in response, the magnitude of the2867-3395-WO1 / P231426-WO-UTL1 43 output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck boost circuit state 5 from 3.733315 milliseconds until 3.73332 milliseconds.

[0151] As shown in FIG.3C, at 3.73332 milliseconds, the output voltage C- PWM-BUCK remains in the low voltage state while the output voltage C-PWM- BOOST is triggered into a low voltage state. In response, the control logic 332 causes the control logic 332 to generate the control voltage Φbu, the control voltage Φ’bu, the control voltage Φbo, and the control voltage Φ’bo to provide the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 in the buck boost circuit state 6 described above with respect to FIG. 2G. As such, the output inductor 116 is demagnetized slowly and the inductor current IL becomes more and more positive slowly. Also, in response, the magnitude of the output voltage VOUT increases. The charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104 remain in the buck boost circuit state 6 from 3.73332 milliseconds until 3.73339 milliseconds. The voltage converter 300 is then placed again in the buck boost circuit state 1 and the cycle repeats.

[0152] FIG.4 illustrates another embodiment of a voltage converter 400, in accordance with some embodiments.

[0153] The voltage converter 400 includes the charging circuit 102(1), the charging circuit 102(2), and the voltage converting circuit 104, except in this embodiment, the voltage node 126 is configured to receive a ground voltage instead of the input voltage VIN.

[0154] The voltage converter 200 shown in FIG.2 has higher voltage standoff requirements for the switch S5 and the switch S6, but the inductor saturation current requirements, the DC current, and the inductor ripple are reduced compared to the voltage converter 400 in FIG.4. Choosing between the voltage converter 200 and the switch converter 400 depends on process technology figures of merit, available process technology components, and a choice of passive components. The buck, boost, and buck boost circuit states of the2867-3395-WO1 / P231426-WO-UTL1 44 voltage converter 400 in FIG.4 are similar to those of the voltage converter 200 shown in FIG.2.

[0155] FIG.5 illustrates another embodiment of a voltage converter 500 and five different switch configurations for the voltage converter 500, in accordance with some embodiments.

[0156] The voltage converter 500 includes the voltage converting circuit 104 and the control circuit 130 discussed above with respect to FIG.1. However, the voltage converter 500 includes a charging circuit 502 instead of the charging circuit 102 or the charging circuits 102(1), 102(2) shown in FIG.2.

[0157] The charging circuit 502 includes a fly capacitor CFLY(3), a fly capacitor CFLY(4), a switch S10, a switch S11, a switch S12, a switch S13, a switch S14, and a switch S15.

[0158] One side of the fly capacitor CFLY(3) is a capacitor node 507 and an opposite side of the fly capacitor CFLY(3) is a capacitor node 506. One side of the fly capacitor CFLY(4) is a capacitor node 505 and an opposite side of the fly capacitor CFLY(4) is a capacitor node 504. The switch S10 is connected between the power source node 106 and the capacitor node 507. The switch S11 is connected between the ground node 108 and the capacitor node 506. The switch S12 is connected between the capacitor node 507 and the capacitor node 505. The switch S13 is connected between the capacitor node 506 and the capacitor node 504. The capacitor node 505 is connected to the ground node 108. The switch S14 is connected between the capacitor node 504 and the inductor node 114. The switch S15 is connected between the inductor node 114 and the ground node 108. The fly capacitor CFLY(3) is configured to present a fly voltage VFLY(3) at the capacitor node 506. The fly capacitor CFLY(4) is configured to present a fly voltage VFLY(4) at the capacitor node 504.

[0159] FIG.5 illustrates the voltage converter 500 in five different switch configurations named switch configurations 1 - 5.

[0160] The lines corresponding to each one of the switch configurations 1 - 5 are closed circuit paths, thereby indicating which of the switches S5, S6, S10 - S15 are closed. For a particular one of the switch configurations 1 - 5, all other2867-3395-WO1 / P231426-WO-UTL1 45 ones of the switches S5, S6, S10 - S15 that are not provided along a particular line in FIG.5 are considered open. Table IV below indicates the particular switch state of each of the switches S5, S6, S10 - S15 in each of the switch configurations 1 - 5.

[0161] The integer Z is an integer that corresponds to a particular switch configuration, where Z has a value of 1 - 5 to indicate a particular one of the switch configurations. Table IV indicates whether a particular one of the switches S5, S6, S10 - S15 is opened or closed in the charging circuit 502 and the voltage converting circuit 104 in the switch configurations 1 - 5. TABLE IV ch e n n ed n ed

[0162] With respect to the voltage converter 500 in FIG.5, the following sentence is completed for each of the switch configurations 1 - 5 in accordance with Table IV.

[0163] In switch configuration Z, the control circuit 130 is configured to generate the control output 132 such that: • the switch S10 is (Row Z, Column S10 Switch State from Table IV); • the switch S11 is (Row Z, Column S11 Switch State from Table IV); • the switch S12 is (Row Z, Column S12 Switch State from Table IV); • the switch S13 is (Row Z, Column S13 Switch State from Table IV); • the switch S14 is (Row Z, Column S14 Switch State from Table IV); • the switch S15 is (Row Z, Column S15 Switch State from Table IV);2867-3395-WO1 / P231426-WO-UTL1 46 • the switch S5 is (Row Z, Column S5 Switch State from Table IV); and • the switch S6 is (Row Z, Column S6 Switch State from Table IV).

[0164] The charging circuit 502 provides a cascade connection for the fly capacitors CFLY(3), CFLY(4) to provide for a charge pump in a 4-switch configuration. The charging circuit 502 generates the fly voltage VFLY(4) so that the fly voltage VFLY(4) is near or equal to -VIN. The charging of the fly capacitors CFLY(3), CFLY(4) is performed in switch configuration 1 and switch configuration 5. The switches S14, S15, S5, S6 convert the fly voltage VFLY(4) at the capacitor node 504 to the output voltage VOUT at the output node 122, which is a voltage with a negative voltage polarity. The switches S14, S15, S5, S6 are operated by switch configurations 3 - 5.

[0165] In switch configuration 3, the output inductor 116 is magnetized in response to |VOUT| < |VIN| and demagnetizes the output inductor 116 in response to |VOUT| > |VFLY(4)|. Energy is transferred between the fly voltage VFLY(4) and the output voltage VOUT.

[0166] In switch configuration 4, the output inductor 116 is magnetized.

[0167] In switch configuration 5, the output inductor 116 is demagnetized.

[0168] Not all of the switch configurations 1 - 5 are necessary to balance the inductor current IL of the output inductor 116 in one switching cycle. In some embodiments, switch configuration 3 and switch configuration 5 are used to balance the inductor current IL of the output inductor 116 when |VOUT| < |VIN| while switch configuration 4 and switch configuration 3 are used to balance the inductor current IL of the output inductor 116 when |VOUT| > |VIN|. In some embodiments, a switch configuration provides for no inductor flow and can be used during a DCM operation. Note that the operation of switch configuration 1 and switch configuration 5 can be independent from switch configuration 3, switch configuration 4, and switch configuration 5. The advantage of the voltage converter 500 is that a charge pump can provide very high efficiency at a high load. At first impression, the switch configuration 4 seems like a typical 4 switch buck boost operating on a negative voltage environment. However, by connecting one terminal of the switch S5 to the input voltage VIN, a duty cycle of2867-3395-WO1 / P231426-WO-UTL1 47 the boost operation is reduced. This lowers the output inductor 116 ripple, the average current, and increases efficiency when compared to a typical 4 switch buck boost configuration.

[0169] With reference to FIG.6, the concepts described above may be implemented in various types of user elements 600, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 600 will generally include a control system 602, a baseband processor 604, transmit circuitry 606, receive circuitry 608, antenna switching circuitry 610, multiple antennas 612, and user interface circuitry 614. In a non-limiting example, the control system 602 may be a field- programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 602 may include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 608 receives radio frequency signals via the antennas 612 and through the antenna switching circuitry 610 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0170] The baseband processor 604 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 604 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0171] For transmission, the baseband processor 604 receives digitized data, which may represent voice, data, or control information, from the control system2867-3395-WO1 / P231426-WO-UTL1 48 602, which it encodes for transmission. The encoded data is output to the transmit circuitry 606, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and then deliver the modulated carrier signal to the antennas 612 through the antenna switching circuitry 610. The multiple antennas 612 and the replicated transmit and receive circuitries 606, 608 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0172] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0173] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the embodiments that follow.

Claims

2867-3395-WO1 / P231426-WO-UTL1 49 Claims What is claimed is:

1. A voltage converter, comprising: a voltage converting circuit comprising: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; and an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit comprising: a fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches are configurable in at least one switch configuration that charges the fly capacitor and in at least one switch configuration that presents a fly voltage across the fly capacitor as a negative voltage at the second inductor node.

2. The voltage converter of claim 1, wherein the charging circuit is a first charging circuit, the fly capacitor is a first fly capacitor, and the set of switches is a first set of switches, the voltage converter further comprising: a second charging circuit coupled to the second inductor node, wherein the second charging circuit comprises: a second fly capacitor; the power source node configured to receive the input voltage; and a second set of switches, wherein, in a second switch configuration, the second set of switches are configured to charge the second fly capacitor and, in a first switch configuration, the second set of switches2867-3395-WO1 / P231426-WO-UTL1 50 are configured to present a second fly voltage across the second fly capacitor as a negative voltage at the second inductor node.

3. The voltage converter of claim 2, wherein: the first fly capacitor comprises a first capacitor node and a second capacitor node; the first set of switches comprises: a first switch coupled between the power source node and the first capacitor node; and a second switch coupled between the first capacitor node and a ground node; the second fly capacitor comprises a third capacitor node and a fourth capacitor node; and the second set of switches comprises: a third switch coupled between the power source node and the third capacitor node; and a fourth switch coupled between the third capacitor node and the ground node.

4. The voltage converter of claim 3, wherein: the first set of switches further comprises a fifth switch coupled between the second capacitor node and the ground node; and the second set of switches further comprises a sixth switch coupled between the fourth capacitor node and the ground node.

5. The voltage converter of claim 4, wherein: the first set of switches further comprises a seventh switch coupled between the second capacitor node and the second inductor node; and the second set of switches further comprises an eighth switch coupled between the fourth capacitor node and the second inductor node.2867-3395-WO1 / P231426-WO-UTL1 51 6. The voltage converter of claim 1, wherein the voltage converting circuit further comprises a first switch connected between the first inductor node and the output node.

7. The voltage converter of claim 6, wherein the output capacitor is connected between the output node and a ground node.

8. The voltage converter of claim 6, wherein the voltage converting circuit further comprises a second switch coupled between the power source node and the first inductor node.

9. The voltage converter of claim 6, wherein the voltage converting circuit further comprises a second switch coupled between a ground node and the first inductor node.

10. The voltage converter of claim 1, wherein the set of switches further comprises a first switch coupled between the second inductor node and a ground node.

11. The voltage converter of claim 1, wherein the set of switches further comprises a first switch coupled between the second inductor node and the power source node.

12. The voltage converter of claim 1, wherein: the fly capacitor comprises a first capacitor node and a second capacitor node; and the set of switches comprises: a first switch coupled between the power source node and the first capacitor node; and a second switch coupled between the first capacitor node and a ground node.2867-3395-WO1 / P231426-WO-UTL1 52 13. The voltage converter of claim 12, wherein the set of switches further comprises a third switch coupled between the second capacitor node and the ground node.

14. The voltage converter of claim 1, wherein the set of switches further comprises a fourth switch coupled between a second capacitor node and the second inductor node.

15. The voltage converter of claim 1, wherein: the fly capacitor is a first fly capacitor having a first capacitor node and a second capacitor node; the set of switches comprises a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; the charging circuit further comprises a second fly capacitor having a third capacitor node and a fourth capacitor node; the first switch is coupled between the second inductor node and the first capacitor node; the second capacitor node is coupled to a ground node; the second switch is coupled between the second capacitor node and the third capacitor node; the third switch is coupled between the third capacitor node and the power source node; the fourth switch is coupled between the first capacitor node and the fourth capacitor node; and the fourth capacitor node is coupled to ground.

16. The voltage converter of claim 15, wherein the set of switches further comprises a sixth switch, wherein the sixth switch is coupled between the second inductor node and the ground.2867-3395-WO1 / P231426-WO-UTL1 53 17. The voltage converter of claim 15, wherein the voltage converting circuit further comprises the fifth switch connected between the first inductor node and the output node.

18. The voltage converter of claim 17, wherein the output capacitor is connected between the output node and the ground node.

19. The voltage converter of claim 17, wherein the voltage converting circuit further comprises a sixth switch coupled between the power source node and the first inductor node.

20. The voltage converter of claim 1, wherein the voltage converting circuit is configured as an inverting voltage converting circuit.

21. A method of converting an input voltage into an output voltage at an output node, the method comprising: receiving the input voltage at a power source node, wherein the output node is operably associated with a first inductor node of an output inductor; setting a set of switches in a switch configuration to charge a fly capacitor; and setting the set of switches in the same switch configuration or in a different switch configuration to present a fly voltage across the fly capacitor as a negative voltage at a second inductor node of the output inductor.

22. A user element comprising a voltage converter, wherein the voltage converter comprises: a voltage converting circuit comprising: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; and2867-3395-WO1 / P231426-WO-UTL1 54 an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit comprising: a fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches are configurable into at least one switch configuration that charges the fly capacitor and into at least one switch configuration that presents a fly voltage across the fly capacitor as a negative voltage at the second inductor node.

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