Inverting buck-boost hybrid converter topologies

Abstract

Embodiments of a voltage converter are disclosed. In some embodiments, the voltage converter includes a voltage converting circuit and at least one charging circuit. The voltage converting circuit includes an output capacitor and an output inductor. The charging circuit is coupled to inductor nodes of the output inductor. The charging circuit includes at least one fly capacitor and a set of switches. The set of switches is configurable in at least one switch configuration to apply a first fly voltage across the at least one fly capacitor as a negative voltage at the inductor nodes and in at least one switch configuration apply a second fly voltage as a negative voltage at a second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1. The voltage converter thus allows for greater efficiency.

Description

INVERTING BUCK-BOOST HYBRID CONVERTER TOPOLOGIESRelated

[0001] This application claims the benefit of provisional patent application serial number 63 / 638,082, filed April 24, 2024, which claims the benefit of provisional patent application serial number 63 / 594,385, filed October 30, 2023, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] This disclosure relates generally to voltage converters and methods of operating the same.Background

[0003] Voltage converters for Radio Frequency (RF) circuits or light emitting diode (LED) displays play a crucial role in ensuring optimal performance and efficiency. Voltage converters are converted from one Direct Current (DC) voltage to another DC voltage at a different voltage level. RF circuits and LED displays require precise and stable voltage levels to function correctly, as deviations can lead to signal distortion and performance degradation. By efficiently managing voltage levels within the RF circuits and LED displays, these converters contribute to maintaining signal integrity, minimizing interference, and optimizing overall system reliability.

[0004] One type of design for a voltage converter is an inverting buck boost converter that converts a positive voltage to a negative voltage. In some existing applications, the inverting buck boost converter uses two transistors and an inductor. In some applications, the size of the inductor is constrained (e.g., in mobile applications with a height < 1 mm) and / or the transistors suffer from performance efficiencies. For example, in display power applications for cell phones, the typical implementation of an inverting buck boost converter converts power at 87% efficiency in a nominal condition and less than 80% efficiency inmaximum output power conditions. For portable applications, this level of efficiency limits the battery life and thermal performance.Summary

[0005] In some embodiments, a voltage converter includes a voltage converting circuit including: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit including: at least one fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches is configurable in at least one switch configuration to apply a first fly voltage across the at least one fly capacitor as a negative voltage at the second inductor node and in at least one switch configuration to apply a second fly voltage as a negative voltage at the second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 . In some embodiments, the factor is greater or equal to 2. In some embodiments, the at least one fly capacitor includes a first fly capacitor and a second fly capacitor; the power source node is a first power source node; the set of switches includes a first switch, a second switch, and a third switch; the charging circuit further includes a second power source node that is configured to receive the input voltage; the first fly capacitor has a first end and a second end; the second fly capacitor has a third end and a fourth end; the first end of the first fly capacitor is coupled to the second inductor node; the first switch is coupled between the first power source node and the second end of the first fly capacitor; the second switch is coupled between the second end of the first fly capacitor and the third end of the second fly capacitor; and the third switch is coupled between the second power source node and the fourth end of the second fly capacitor. In some embodiments, the set of switches further includes a fourth switch and the fourth switch is coupled between the second inductor node and the first end of the first fly capacitor. Insome embodiments, the set of switches further includes a fourth switch and a fifth switch; the fourth switch is coupled between the first end of the first fly capacitor and ground; and the fifth switch is coupled between the third end of the second fly capacitor and the ground. In some embodiments, the set of switches further includes a fourth switch and a fifth switch; the fourth switch is coupled between the second end of the first fly capacitor and ground; and the fifth switch is coupled between the fourth end of the second fly capacitor and the ground. In some embodiments, the set of switches further includes a sixth switch and the sixth switch is coupled between the first end of the first fly capacitor and the second inductor node. In some embodiments, the set of switches further includes a seventh switch and the seventh switch is coupled between the second inductor node and the ground. In some embodiments, the charging circuit is a first charging circuit, the at least one fly capacitor includes a first fly capacitor, the set of switches is a first set of switches, and the voltage converter further includes: a second charging circuit coupled to the second inductor node, wherein the second charging circuit includes: a second fly capacitor; the power source node is configured to receive the input voltage; and a second set of switches, wherein, in at least one switch configuration of the second set of switches, the second set of switches is configured to charge the second fly capacitor and, in at least one switch configuration of the second set of switches, the second set of switches is configured to present a third fly voltage across the second fly capacitor as a negative voltage at the second inductor node. In some embodiments, the at least one fly capacitor includes a first fly capacitor; the first fly capacitor has a first end and a second end; the first end of the first fly capacitor is coupled to the second inductor node; the power source node is a first power source node; the input voltage is a first input voltage; the charging circuit further includes a second power source node configured to receive a second input voltage; the set of switches includes a first switch and a second switch; the first switch is coupled between the first power source node and the second end of the first fly capacitor; and the second switch is coupled between the second power source node and the second end of the first fly capacitor. In someembodiments, a voltage magnitude of the first fly voltage is equal to a voltage magnitude of the first input voltage and a voltage magnitude of the second fly voltage is equal to a voltage magnitude of the second input voltage. In some embodiments, the charging circuit is a first charging circuit; the set of switches is a first set of switches; and the voltage converter further includes: a second first fly capacitor having a third end and a fourth end; a second set of switches including a third switch and a fourth switch; a third power source node configured to receive the first input voltage; and a fourth power source node configured to receive the second input voltage. In some embodiments, the third end of the second fly capacitor is coupled to the second inductor node; the third switch is coupled between the third power source node and the fourth end of the second fly capacitor; and the fourth switch is coupled between the fourth power source node and the fourth end of the second fly capacitor. In some embodiments, the set of switches further includes a third switch and the third switch is coupled between the first end of the first fly capacitor and the second inductor node. In some embodiments, the set of switches further includes a third switch and the third switch is coupled between the first end of the first fly capacitor and ground. In some embodiments, the set of switches further includes a third switch and the third switch is coupled between the second end of the first fly capacitor and ground. In some embodiments, the power source node is a first power source node, the voltage converting circuit further includes a second power source node configured to receive the input voltage and a switch, wherein the switch is coupled between the second power source node and the first inductor node. In some embodiments, the power source node is a first power source node and the voltage converting circuit further includes a first switch and a second switch, wherein: the first switch is coupled between the output node and the first inductor node; and the second switch is coupled between a second power source node and the first inductor node, wherein the second power source node is configured to receive the input voltage.

[0006] In some embodiments, a method of converting an input voltage into an output voltage at an output node includes: receiving the input voltage at a powersource node, wherein the output node is operably associated with a first inductor node of an output inductor; setting a set of switches in a first switch configuration to apply a first fly voltage across at least one fly capacitor as a negative voltage at a second inductor node of the output inductor; and setting the set of switches in a second switch configuration to apply a second fly voltage as a negative voltage at the second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 .

[0007] In some embodiments, a user element includes a voltage converter, wherein the voltage converter includes a voltage converting circuit including: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit including: at least one fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches is configurable in at least one switch configuration to apply a first fly voltage across the at least one fly capacitor as a negative voltage at the second inductor node and in at least one switch configuration to apply a second fly voltage as a negative voltage at the second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 .

[0008] In another aspect, any of the foregoing aspects individually or together, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] FIG. 1 A illustrates one embodiment of a voltage converter, in accordance with some embodiments;

[0012] FIG. 1 B and FIG. 1 C illustrate the voltage converter shown in FIG. 1A with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments;

[0013] FIG. 2A illustrates one embodiment of a voltage converter, in accordance with some embodiments;

[0014] FIG. 2B and FIG. 2C illustrate the voltage converter shown in FIG. 2A with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments;

[0015] FIG. 3A illustrates one embodiment of a voltage converter, in accordance with some embodiments;

[0016] FIGs. 3B - 3D illustrate the voltage converter shown in FIG. 3A with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments; and

[0017] FIG. 4 illustrates a user element, in accordance with some embodiments.Detailed Description

[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0019] It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0021] It should be understood that, although the terms “upper,” “lower,” “bottom,” “intermediate,” “middle,” “top,” and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed an “upper” element and, similarly, a second element could be termed an “upper” element depending on the relative orientations of these elements, without departing from the scope of the present disclosure.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having meanings that are consistent with their meanings in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently redescribed.

[0025] Switches are described throughout this disclosure as being either “open” or “closed.” When a switch is “open,” the switch is in a non-conducting state and / or a high impedance state. For example, if the switch is a field effect transistor (FET), a gate to source voltage applied to a gate of the FET is below a threshold voltage and, thus, no current or very little current (i.e., leakage current) flows between a drain and a source of the FET. The switch is also referred to as being in an “off state” when the switch is “open.” When a switch is “closed,” the switch is in a conducting state and / or a low impedance state. For example, if the switch is a FET, the gate to source voltage applied to a gate of the FET is abovea threshold voltage and, thus, current flows between a drain and a source of the FET. The switch is also referred to as being in an “on state” when the switch is “closed.”

[0026] A buck boost converter refers to a voltage converter where a difference in magnitude between an input voltage and an output voltage is less than 5% (where the percentage is calculated with respect to the input voltage, i.e., the difference in magnitude is less than 5% of the input voltage).

[0027] A buck converter refers to a voltage converter where a magnitude of an input voltage is greater than a magnitude of an output voltage, where a voltage difference between the magnitude of the input voltage and the magnitude of the output voltage is more than 5% (where the percentage is calculated with respect to the input voltage, i.e., the difference in magnitude is greater than 5% of the input voltage).

[0028] A boost converter refers to a voltage converter where a magnitude of an output voltage is greater than a magnitude of an input voltage, where a voltage difference between the magnitude of the input voltage and the magnitude of the output voltage is more than 5% (where the percentage is calculated with respect to the input voltage, i.e., the difference in magnitude is greater than 5% of the input voltage).

[0029] Embodiments of a voltage converter are disclosed. The voltage converter includes a voltage converting circuit and at least one charging circuit. In some embodiments, the voltage converting circuit is an inverting voltage converting circuit. The charging circuit or charging circuits may be designed to operate as a charge pump. The voltage converting circuit includes an output inductor and an output capacitor, wherein the output capacitor is coupled to an output node. An output voltage is generated at the output node and, in some embodiments, the output voltage is a voltage with a non-zero magnitude and a negative voltage polarity. The output inductor has a first inductor node operably associated with the output node (e.g., in some embodiments, a switch is connected between the first inductor node and the output node) and a second inductor node that is connected to the one or more charging circuits.

[0030] Each of the charging circuits include a different set of switches. The set of switches is operable in at least one switch configuration that charges one or more fly capacitors and is operable in at least one switch configuration to present a fly voltage. More specifically, the set of switches is configurable in at least one switch configuration to apply a first fly voltage across the fly capacitor(s) as a negative voltage at the second inductor node and also is configurable in at least one switch configuration to apply a second fly voltage as a negative voltage at the second inductor node. The second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 across the fly capacitor as a negative voltage at the second inductor node. In some embodiments, the factor is equal to 2. The presentation of the negative fly voltage at the second inductor node reduces a peak current value and reduces a root mean squared (RMS) current through the output inductor. In some embodiments, the voltage converter increases efficiency at all load ranges, reduces inductor current ripple and output voltage ripple, reduces a saturation current requirement (which leads to a physically smaller inductor and, in some cases, the number of inductors can be reduced), and leads to better transient performance compared to other previously known designs. In some embodiments, the voltage converter has a power efficiency of 96%.

[0031] FIG. 1 A illustrates one embodiment of a voltage converter 100, in accordance with some embodiments.

[0032] The voltage converter 100 includes a charging circuit 102(1 ), a charging circuit 102(2), and a voltage converting circuit 104. The charging circuit 102(1 ) includes switches S1 (1 ), S2(1 ), S3(1 ), S4(1 ), and a fly capacitor CFLY(1 ). In some embodiments, the switches S1 (1 ), S2(1 ), S3(1 ), S4(1 ) are FETs, microelectromechanical switches (MEMs), and / or the like. In some embodiments, the fly capacitor CFLY(1 ) is a Metal-Insulator-Metal (MIM) Capacitor, a Metal-Oxide-Semiconductor (MOS) Capacitor, a poly capacitor, a thin-film capacitor, a varactor, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a high-K dielectric capacitor, an array of capacitive devices, a combination of one or more of the capacitors listed, and / or the like.

[0033] The charging circuit 102(1 ) includes a power source node 106(1 ), a ground node 108(1 ), a capacitor node 110(1 ), and a capacitor node 1 12(1 ). The charging circuit 102(1 ) is connected to an output inductor node 114. In alternative embodiments, the switch S4(1 ) is not provided and the capacitor node 1 12(1 ) is the same as the output inductor node 1 14. With respect to the charging circuit 102(1 ) shown in FIG. 1A, the power source node 106(1 ) (also referred to as the input node 106(1 )) is configured to receive a power source voltage VIN (also referred to as an input voltage VIN throughout this disclosure), which is a reference voltage with a non-zero voltage magnitude and a positive voltage polarity. The power source voltage VIN is an input voltage and is generally a direct current (DC) voltage. The ground node 108(1 ) is configured to receive a ground voltage, which is a reference voltage with a zero voltage magnitude and, thus, has no polarity. The capacitor node 110(1 ) is connected to a capacitor terminal at a first side (i.e., first end) of the fly capacitor CFLY(1 ), while the capacitor node 112(1 ) is connected to an opposite capacitor terminal on a second side (i.e., second end) of the fly capacitor CFLY(1 ). The output inductor node 114 is connected to an inductor terminal at a first side of an output inductor 1 16 in the voltage converting circuit 104.

[0034] The switch S1 (1 ) is coupled between the power source node 106(1 ) and the capacitor node 110(1 ). The switch S2(1 ) is coupled between the capacitor node 110(1 ) and the ground node 108(1 ). The switch S3(1 ) is coupled between the capacitor node 1 12(1 ) and the ground node 108(1 ). The switch S4(1 ) is coupled between the capacitor node 112(1 ) and the output inductor node 1 14. Each of the switches S1 (1 ), S2(1 ), S3(1 ), S4(1 ) are configured to open and close a path between the nodes they are coupled between. The charging circuit 102(1 ) is configured to generate a voltage with a negative voltage polarity and a voltage magnitude equal to the voltage magnitude of the input voltage VIN at the output inductor node 114.

[0035] The charging circuit 102(2) includes switches SO, S1 (2), S3(2), S4(2), S1 (3), S2(3), S3(3), S4(3), a fly capacitor CFLY(2), and a fly capacitor CFLY(3). In some embodiments, the switches SO, S1 (2), S3(2), S4(2), S1 (3), S2(3), S3(3),S4(3) are FETs, MEMs, and / or the like. In some embodiments, the fly capacitors CFLY(2), CFLY(3) are each a MIM Capacitor, a MOS Capacitor, a poly capacitor, a thin-film capacitor, a varactor, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a high-K dielectric capacitor, an array of capacitive devices, a combination of one or more of the capacitors listed, and / or the like.

[0036] The charging circuit 102(2) includes a power source node 106(2), a power source node 106(3), a ground node 108(2), a ground node 108(3), a capacitor node 110(2), a capacitor node 110(3), a capacitor node 1 12(2), and a capacitor node 112(3). The charging circuit 102(2) is connected to the output inductor node 114. In alternative embodiments, the switch S4(2) and / or the switch S4(3) is not provided and the capacitor node 112(2) is the same as the output inductor node 114 and / or the capacitor node 112(3) is the same as the capacitor node 110(2). With respect to the charging circuit 102(2) shown in FIG. 1 A, the power source node 106(2) (also referred to as the input node 106(2)) and the power source node 106(3) (also referred to as the input node 106(3)) are both configured to receive the power source voltage VIN. The ground node 108(2) and the ground node 108(3) are both configured to receive the ground voltage.

[0037] The capacitor node 1 10(2) is connected to a capacitor terminal at a first side (i.e., first end) of the fly capacitor CFLY(2), while the capacitor node 1 12(2) is connected to an opposite capacitor terminal on a second side (i.e., second end) of the fly capacitor CFLY(2). The switch S1 (2) is coupled between the power source node 106(2) and the capacitor node 110(2). The switch S3(2) is coupled between the capacitor node 1 12(2) and the ground node 108(2). The switch S4(2) is coupled between the capacitor node 1 12(2) and the output inductor node 114. The switch SO is coupled between the output inductor node 1 14 and the ground node 108(2). In some implementations, the switch SO is not included. In some implementations, the switch SO is provided in the charging circuit 102(1 ) and is coupled between an output node 122 and the ground node 108(1 ). Each of the switches SO, S1 (2), S3(2), S4(2) are configured to open and close a path between the nodes they are coupled between.

[0038] The capacitor node 1 10(3) is connected to a capacitor terminal at a first side (i.e., first end) of the fly capacitor CFLY(3), while the capacitor node 1 12(3) is connected to an opposite capacitor terminal on a second side (i.e., second end) of the fly capacitor CFLY(3). The switch S1 (3) is coupled between the power source node 106(3) and the capacitor node 110(3). The switch S2(3) is coupled between the capacitor node 1 10(3) and the ground node 108(3). The switch S3(3) is coupled between the capacitor node 112(3) and the ground node 108(3). The switch S4(3) is coupled between the capacitor node 112(3) and the capacitor node 110(2). Each of the switches S1 (3), S2(3), S3(3), S4(3) are configured to open and close a path between the nodes they are coupled between. The charging circuit 102(2) is configured to generate a voltage with a negative voltage polarity and a voltage magnitude equal to double the voltage magnitude of the input voltage VIN at the output inductor node 114.

[0039] The voltage converting circuit 104 includes switches S5, S6, the output inductor 1 16, and an output capacitor 1 18. In some embodiments, the switches S5, S6 are FETs, MEMs, and / or the like. In some embodiments the output capacitor 1 18 is a MIM Capacitor, a MOS Capacitor, a poly capacitor, a thin-film capacitor, a varactor, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a high-K dielectric capacitor, an array of capacitive devices, a combination of one or more of the capacitors listed, and / or the like. In some embodiments, the output inductor 116 is a wire-wound inductor, a ferrite bead inductor, a transformer or a portion of a transformer, a multilayer chip inductor, a molded power inductor, an integrated inductor, a shielded inductor, and / or the like. While a load 120 is shown as a part of the voltage converting circuit 104, the load 120 is generally not a part of the voltage converting circuit 104 and is shown herein for the convenience of explanation. The voltage converting circuit 104 includes the output node 122, wherein an output voltage VOUT is presented by the voltage converting circuit 104 at the output node 122. The load 120 simply refers to a circuit or device that consumes power from the output node 122. For example, one application of the voltage converter 100 is toprovide power to radio frequency (RF) circuitry in a user element. Thus, the load 120 refers to RF circuits, in some embodiments.

[0040] The voltage converting circuit 104 includes the output inductor node 1 14, an output inductor node 124, a power source node 126, the output node 122, and a ground node 108. The output inductor 116 is connected between the output inductor node 114 and the output inductor node 124. The switch S5 is connected between the output inductor node 124 and the power source node 126. In some embodiments, the power source node 126 receives a ground voltage and is, thus, the same as the ground node 108. In this embodiment, the power source node 126 receives the power source voltage VIN and is, thus, the same as the power source nodes 106(1 ), 106(2), 106(3).

[0041] The switch S6 is connected between the output inductor node 124 and the output node 122. The output capacitor 1 18 is connected between the output node 122 and the ground node 108. In other words, the output capacitor 118 is connected in parallel with the load 120 and in shunt with respect to the output node 122.

[0042] The voltage converting circuit 104 is configured to convert the input voltage VIN into the output voltage VOUT. In this embodiment, the output voltage VOUT has a non-zero magnitude with a negative voltage polarity. Accordingly, this embodiment of the voltage converting circuit 104 is an inverting voltage converting circuit, since the input voltage VIN has a positive voltage polarity and the output voltage VOUT has a negative voltage polarity. To do this, the output inductor 1 16 is magnetized by generating a current with the input voltage VIN that increases an intensity of a magnetic field generated by the output inductor 116. The output inductor 1 16 is then disconnected from the input voltage VIN and demagnetized. During the demagnetization of the output inductor 1 16, magnetic energy in the output inductor 1 16 is released, thereby decreasing the intensity of the magnetic field generated by the output inductor 1 16.

[0043] The output capacitor 118 acts as an energy reservoir and absorbs and supplies charge so as to reduce periodic amplitude voltage fluctuations (i.e.,ripple current) of the output voltage VOUT. The output capacitor 118 and the output inductor 116 are configured to conduct a low-pass filtering to reduce voltage ripple and provide a more regulated version of the output voltage VOUT. The output voltage VOUT is considered to be a DC voltage despite the ripple voltage in the voltage magnitude.

[0044] The charging circuit 102(1 ) is configured to charge the fly capacitor CFLY(1 ) with the input voltage VIN. Once the fly capacitor CFLY(1 ) is charged, the fly capacitor CFLY(1 ) is coupled to the output inductor node 1 14. In this manner, the fly capacitor CFLY(1 ) is configured to present a voltage -VFLY(1 ) at the output inductor node 1 14. By presenting the voltage -VFLY(1 ) at the output inductor node 114, the peak magnitude of the current that flows through the output inductor 116 is reduced. Furthermore, the RMS current that flows through the output inductor 1 16 is also further reduced.

[0045] The charging circuit 102(2) is configured to charge the fly capacitor CFLY(2) and the fly capacitor CFLY(3) with the input voltage VIN. Once the fly capacitor CFLY(2) and the fly capacitor CFLY(3) are charged, the fly capacitor CFLY(2) and the fly capacitor CFLY(3) are coupled to the output inductor node 1 14. In this manner, the fly capacitor CFLY(2) is configured to present a voltage -VFLY(2) at the output inductor node 114. Also, the fly capacitor CFLY(3) is configured to present a voltage -VFLY(3) at the capacitor node 110(2). As such, the total voltage -VFLY(2) + -VFLY(3) is presented at the output inductor node 1 14. By presenting the total voltage -VFLY(2) + -VFLY(3) at the output inductor node 114, the peak magnitude of the current that flows through the output inductor 1 16 is even further reduced. Furthermore, the RMS current that flows through the output inductor 116 is also further reduced.

[0046] The switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO) are closed and opened in order to magnetize the output inductor 116, demagnetize the output inductor 116, charge the fly capacitor CFLY(1 ), discharge the fly capacitor CFLY(1 ), charge the fly capacitor CFLY(2), discharge the fly capacitor CFLY(2), charge the fly capacitor CFLY(3), and discharge the fly capacitor CFLY(3). As explained in further detail below,different operating techniques for opening and closing the switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO) will result in different operations. For example, depending on how the switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO) are opened and closed, the voltage converter 100 will operate as either a buck converter, a boost converter, or a buck boost converter.

[0047] The voltage converter 100 has a control circuit 130. The control circuit 130 is configured to generate a control output 132 that is configured to operate the switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO). More specifically, the control circuit 130 is configured to generate the control output 132 that opens and closes the switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO) in accordance with a switch configuration. As explained below, by switching through different switch configurations, the voltage converter 100 operates as a particular type of voltage converter (i.e., the buck, the boost, or the buck boost converter). In some embodiments, the control circuit 130 is a voltage mode controller, a current mode controller, an average current mode controller, a hysteresis controller, a bang-bang controller, a predictive current controller, a digital controller, an analog controller, an adaptive controller, a voltage feedforward controller, a Proportional-Integral (PI) controller, a Proportional- Integral-Derivative (PID) controller, and / or the like.

[0048] FIG. 1 B and FIG. 1 C illustrate the voltage converter 100 shown in FIG. 1 A with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments.

[0049] More specifically, FIG. 1 B and FIG. 1 C illustrate the voltage converter 100 in five different switch configurations named switch configurations 1 - 5. The lines corresponding to each one of the switch configurations 1 - 5 are closed circuit paths, thereby indicating which of the switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO) are closed. For a particular one of the switch configurations 1 - 5, all of the other switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO)that are not provided along a particular line in FIG. 1 B and FIG. 1 C are considered to be opened. Table I below indicates the particular switch state of each of the switches S1 (1 ) - S4(1 ), S5, S6 in each of the switch configurations 1 - 5. Table II below indicates the particular switch state of each of the switches S1 (2), S3(2), S4(2), S5, S6 in each of the switch configurations 1 - 5. Table III below indicates the particular switch state of each of the switches S1 (3) - S4(3), S5, S6 in each of the switch configurations 1 - 5.

[0050] The integer X is an integer that corresponds to a particular switch configuration for the switches S1 (1 ) - S4(1 ), S1 (2), S3(2), S4(2), S1 (3) - S4(3), S5, S6 (and, optionally, the switch SO). Thus, the integer X has a value of 1 - 5 to indicate a particular switch configuration.

[0051] With respect to the voltage converter 100 in FIG. 1 B and FIG. 1 C, the following sentence is completed for each of the switch configurations 1 - 5 in accordance with Table I.

[0052] In switch configuration X, the control circuit 130 is configured to generate the control output 132 such that:• the switch S1 (1 ) is (Row X, Column S1 (1 ) Switch State from Table I);• the switch S2(1 ) is (Row X, Column S2(1 ) Switch State from Table I);• the switch S3(1 ) is (Row X, Column S3(1 ) Switch State from Table I);• the switch S4(1 ) is (Row X, Column S4(1 ) Switch State from Table I);• the switch S5 is (Row X, Column S5 Switch State from Table I); and• the switch S6 is (Row X, Column S6 Switch State from Table I).

[0053] With respect to the voltage converter 100 in FIG. 1 B and FIG. 1 C, the following sentence is completed for each of the switch configurations 1 - 5 in accordance with Table II.

[0054] In switch configuration X, the control circuit 130 is configured to generate the control output 132 such that: • the switch S1 (2) is (Row X, Column S1 (2) Switch State from Table II);• the switch S3(2) is (Row X, Column S3(2) Switch State from Table II);• the switch S4(2) is (Row X, Column S4(2) Switch State from Table II);• the switch S5 is (Row X, Column S5 Switch State from Table II); and• the switch S6 is (Row X, Column S6 Switch State from Table II).

[0055] With respect to the voltage converter 100 in FIG. 1 B and FIG. 1 C, the following sentence is completed for each of the switch configurations 1 - 5 in accordance with Table III.

[0056] In switch configuration X, the control circuit 130 is configured to generate the control output 132 such that:• the switch S1 (3) is (Row X, Column S1 (3) Switch State from Table III);• the switch S2(3) is (Row X, Column S2(3) Switch State from Table III);• the switch S3(3) is (Row X, Column S3(3) Switch State from Table III);• the switch S4(3) is (Row X, Column S4(3) Switch State from Table III);• the switch S5 is (Row X, Column S5 Switch State from Table III); and• the switch S6 is (Row X, Column S6 Switch State from Table III).

[0057] Note that the voltage converter 100 is configured to charge the output inductor node 114 between 3 voltage levels so as to swing between 0, -VIN, and -2VIN. In one implementation, the voltage converter 100 is operated as an inverting buck converter. This is achieved by keeping the switch S3(2) closed and operating the charging circuits 102(1 ), 102(2) at the 3 voltage levels: 0, -VIN (via the charging circuit 102(1 )), and -2VIN (via the charging circuit 102(2)).

[0058] In switch configuration 1 , the voltage converter 100 uses the fly capacitors CFLY(2), CFLY(3) in series to magnetize the output inductor 116 in response to |VOUT| < |2VIN| and demagnetize the output inductor 116 in response to |VOUT| > |2VIN|.

[0059] In switch configuration 2, the voltage converter 100 demagnetizes the output inductor 116 (by not using the fly capacitors CFLY(1 ), CFLY(2), CFLY(3)).

[0060] In switch configuration 3, the voltage converter 100 uses the fly capacitors CFLY(2), CFLY(3) in series to magnetize the output inductor 116.

[0061] In switch configuration 4, the voltage converter 100 connects the fly capacitor CFLY(1 ) to magnetize the output inductor 116 in response to |VOUT| < |VIN| and demagnetize the output inductor 1 16 in response to |VOUT| > |VIN|.

[0062] In switch configuration 5, the voltage converter 100 connects the fly capacitor CFLY(1 ) to magnetize the output inductor 116.

[0063] The switch configurations 1 - 5 do not have to follow a particular order and some of the switch configurations 1 - 5 may not be entered in certain switch cycles.

[0064] FIG. 2A illustrates one embodiment of a voltage converter 200, in accordance with some embodiments.

[0065] The voltage converter 200 includes a charging circuit 202 and the voltage converting circuit 104. The voltage converting circuit 104 was discussed above with respect to FIGs. 1 A - 1 C. The charging circuit 202 includes switches S1 , S2, S3, S4, S8 as well as the switch SO and a fly capacitor CFLY. In some embodiments, the switches S1 , S2, S3, S4, S8 are FETs, MEMs, and / or the like. In some embodiments the fly capacitor CFLY is a MIM Capacitor, a MOS Capacitor, a poly capacitor, a thin-film capacitor, a varactor, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a high-K dielectric capacitor, an array of capacitive devices, a combination of one or more of the capacitors listed, and / or the like.

[0066] The charging circuit 202 includes a power source node 206, a ground node 208, a capacitor node 210, a capacitor node 212, and a power source node 220. The charging circuit 202 is connected to the output inductor node 1 14. In alternative embodiments, the switch S4 is not provided and the capacitor node 212 is the same as the output inductor node 114. With respect to the charging circuit 202 shown in FIG. 2A, the power source node 206 (also referred to as an input node 206) is configured to receive the power source voltage VIN, which is a reference voltage with a non-zero voltage magnitude and a positive voltage polarity. The power source voltage VIN is an input voltage and is generally a DC voltage. The ground node 208 is configured to receive a ground voltage, which is a reference voltage that defines a zero voltage magnitude and, thus, has nopolarity. The capacitor node 210 is connected to a capacitor terminal at a first side of the fly capacitor CFLY, while the capacitor node 212 is connected to an opposite capacitor terminal on a second side of the fly capacitor CFLY. The output inductor node 114 is connected to an inductor terminal at the first side of the output inductor 1 16 in the voltage converting circuit 104.

[0067] Also, with respect to the charging circuit 202 shown in FIG. 2A, the power source node 220 (also referred to as an input node 220) is configured to receive a power source voltage VIN2 (also referred to as an input voltage VIN2), which is a reference voltage with a non-zero voltage magnitude and a positive voltage polarity. The power source voltage VIN2 is an input voltage and is generally a DC voltage. The power source node 220 is also coupled to the capacitor node 210. The magnitude of the power source voltage VIN2 is equal to the magnitude of the power source voltage VIN times a factor, wherein the factor is greater than 1 . In some embodiments, the factor is equal to 2. In this manner, the magnitude of a fly voltage VFLY across the fly capacitor CFLY can be equal to the magnitude of the power source voltage VIN and can also be equal to the magnitude of the power source voltage VIN2, depending on how the switches S1 - S6, S8 are operated by the control circuit 130.

[0068] The switch SO is optional. In embodiments of the charging circuit 202 that include the switch SO, the switch SO is connected between the output inductor node 114 and the ground node 208.

[0069] The charging circuit 202 is configured to charge the fly capacitor CFLY with the input voltage VIN. Once the fly capacitor CFLY is charged, the fly capacitor CFLY is coupled to the output inductor node 1 14. In this manner, the fly capacitor CFLY is configured to present a fly voltage -VFLY. In this case, the magnitude of the fly voltage -VFLY is equal to the magnitude of the input voltage VIN at the output inductor node 114. By presenting the fly voltage -VFLY at the output inductor node 114, the peak magnitude of the current that flows through the output inductor 1 16 is reduced. Furthermore, the RMS current that flows through the output inductor 116 is also further reduced.

[0070] The charging circuit 202 is configured to charge the fly capacitor CFLY with the input voltage VIN2. Once the fly capacitor CFLY is charged, the fly capacitor CFLY is coupled to the output inductor node 1 14. In this manner, the fly capacitor CFLY is configured to present the fly voltage -VFLY (in this case, the magnitude of the fly voltage -VFLY is equal to the magnitude of the input voltage VIN2) at the output inductor node 114. By presenting the fly voltage -VFLY at the output inductor node 114, the peak magnitude of the current that flows through the output inductor 1 16 is reduced. Furthermore, the RMS current that flows through the output inductor 116 is also further reduced.

[0071] The switch S1 is coupled between the power source node 206 and the capacitor node 210. The switch S2 is coupled between the capacitor node 210 and the ground node 208. The switch S3 is coupled between the capacitor node 212 and the ground node 208. The switch S4 is coupled between the capacitor node 212 and the output inductor node 1 14. The switch S8 is coupled between the power source node 220 and the capacitor node 210.

[0072] The switches S1 - S6, S8 (and, optionally, the switch SO) are closed and opened in order to magnetize the output inductor 116, demagnetize the output inductor 116, charge the fly capacitor CFLY, and discharge the fly capacitor CFLY. As explained in further detail below, different operating techniques for opening and closing the S1 - S6, S8 (and, optionally, the switch SO) will result in different operations. For example, depending on how the switches S1 - S6, S8 (and, optionally, the switch SO) are opened and closed, the voltage converter 200 operates as either a buck converter, a boost converter, or a buck boost converter.

[0073] The voltage converter 200 has the control circuit 130. The control circuit 130 is configured to generate the control output 132 that is configured to operate the switches S1 - S6, S8 (and, optionally, the switch SO). More specifically, the control circuit 130 is configured to generate the control output 132 that opens and closes the switches S1 - S6, S8 (and, optionally, the switch SO) in accordance with a switch configuration. As explained below, by switching through different switch configurations, the voltage converter 200 operates as aparticular type of voltage converter (i.e., the buck, the boost, or the buck boost converter). In some embodiments, the control circuit 130 is a voltage mode controller, a current mode controller, an average current mode controller, a hysteresis controller, a bang-bang controller, a predictive current controller, a digital controller, an analog controller, an adaptive controller, a voltage feedforward controller, a PI controller, a PID controller, and / or the like.

[0074] FIG. 2B and FIG. 2C illustrate the voltage converter 200 as shown in FIG. 2A with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments.

[0075] More specifically, FIG. 2B and FIG. 2C illustrate the voltage converter 200 in six different switch configurations named switch configurations 1 - 6. The lines corresponding to each one of the switch configurations 1 - 6 are closed circuit paths, thereby indicating which of the switches S1 - S6, S8 (and, optionally, the switch SO) are closed. For a particular one of the switch configurations 1 - 6, all of the other switches S1 - S6, S8 (and, optionally, the switch SO) that are not provided along a particular line in FIG. 2B and FIG. 20 are considered to be opened. Table IV below indicates the particular switch state of each of the switches S1 - S6, S8 in each of the switch configurations 1 - 6.

[0076] The integer Y is an integer that corresponds to a particular one of the switch configurations 1 - 6 for the switches S1 - S6, S8 (and, optionally, the switch SO). Thus, the integer Y has a value of 1 - 6 to indicate a particular one of the switch configurations.

[0077] With respect to the voltage converter 200 in FIG. 2B and FIG. 2C, the following sentence is completed for each of the switch configurations 1 - 6 in accordance with Table IV.

[0078] In switch configuration Y, the control circuit 130 is configured to generate the control output 132 such that:• the switch S1 is (Row Y, Column S1 Switch State from Table IV);• the switch S2 is (Row Y, Column S2 Switch State from Table IV);• the switch S3 is (Row Y, Column S3 Switch State from Table IV);• the switch S4 is (Row Y, Column S4 Switch State from Table IV);• the switch S5 is (Row Y, Column S5 Switch State from Table IV);• the switch S6 is (Row Y, Column S6 Switch State from Table IV); and• the switch S8 is (Row Y, Column S8 Switch State from Table IV).

[0079] In switch configuration 1 , the switches SO, S1 , S3, S4, S6 are closed and the output inductor 116 is demagnetized while recharging the fly capacitor CFLY.

[0080] In switch configuration 2, the switches S4, S6, S8 are closed. Thus, the current flows from the output node 122 to the power source node 220. In response to |VOUT| < |VIN2|, the fly capacitor CFLY is discharged, the output inductor 1 16 is magnetized, and energy is transferred to the output node 122, thereby increasing the magnitude of the output voltage VOUT. In response to |VOUT| > | VI N2| , the fly capacitor CFLY is discharged, the output inductor 1 16 is demagnetized, and energy is transferred to the output node 122, thereby increasing the magnitude of the output voltage VOUT.

[0081] In switch configuration 3, the switches S2, S4, S6, are closed. In this case, the current flows from the output node 122 to the ground node 208 through the output inductor 1 16 and the fly capacitor CFLY. If |VOUT| < |VIN2|, the fly capacitor CFLY is discharged, the energy of the output inductor 1 16 increases, and there is an energy transfer to the output node 122. Additionally, the outputinductor 1 16 is magnetized, the fly capacitor CFLY is discharged, and the output capacitor 1 18 is recharged, thereby increasing the magnitude of the output voltage VOIIT. In response to |VOUT| > |VIN2|, the fly capacitor CFLY is discharged, the output inductor 1 16 is demagnetized, and energy is transferred to the output node 122. Similarly, the output inductor 116 is magnetized, the fly capacitor CFLY loses charge, and the output capacitor 118 is recharged.

[0082] In switch configuration 4, the switches S1 , S3, S4, S5 are closed. In this case, in response to the capacitor node 210 being connected to the power source node 206, the fly capacitor CFLY is recharged (i.e., gains energy) and the output inductor 116 is magnetized (i.e., gains energy). In embodiments where the power source node 126 is connected to ground, the fly capacitor CFLY is recharged (i.e., gains energy) and the output inductor 116 is slowly demagnetized (i.e., leaks energy).

[0083] In switch configuration 5, the switches S2, S4, S5 are closed. In some cases, where the power source node 126 is connected to ground, the fly capacitor CFLY is discharged (i.e., loses energy) while the output inductor 1 16 is magnetized (i.e., gains energy) at a rate approximately proportional to the power source voltage VIN. In an embodiment where the power source node 126 is configured to receive the power source voltage VIN2, the fly capacitor CFLY discharges (i.e., loses energy) and the output inductor 1 16 is magnetized (i.e., gains energy) at a rate approximately proportional to VIN + VIN2. In an embodiment where the power source node 126 is configured to receive the power source voltage VIN, the fly capacitor CFLY is discharged (i.e., loses energy) and the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to 2 * VIN.

[0084] In switch configuration 6, the switches S4, S5, S8 are closed. In an alternative embodiment where the power source node 126 is configured to receive the ground voltage GND, the fly capacitor CFLY is discharged (i.e., loses energy) and the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to (VIN - VIN2). In an embodiment where the power source node 126 is configured to receive the power source voltage VIN2, the flycapacitor CFLY discharges (i.e., loses energy), the power source voltage VIN2 is magnetized (i.e., gains energy), and the output inductor 1 16 is magnetized (i.e., gains energy) at a rate approximately proportional to the power source voltage VIN. In some cases, where the power source node 126 is connected to the power source voltage VIN, the fly capacitor CFLY is discharged (i.e., loses energy) and the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to 2VIN - VIN2.

[0085] FIG. 3A illustrates one embodiment of a voltage converter 300, in accordance with some embodiments.

[0086] The voltage converter 300 includes a charging circuit 202(1 ), a charging circuit 202(2), and the voltage converting circuit 104. The voltage converting circuit 104 is described above with respect to FIG. 2A. In this embodiment, the power source node 126 is configured to receive the input voltage VIN.

[0087] The charging circuit 202(1 ) is the same as the charging circuit 202 described above with respect to FIG. 2A. In this embodiment, the elements of the charging circuit 202(1 ) have the same elements as those described in the charging circuit 202 of FIG. 2A and all element numbers in the charging circuit 202(1 ) are the same as those in the charging circuit 202, except that the corresponding element numbers include the notation (1 ) to indicate that the charging circuit 202(1 ) is a first instance of a charging circuit, just like the charging circuit 202 in FIG. 2A. The charging circuit 202(1 ) shown in FIG. 3A includes the switch SO as described above. In other embodiments, the switch SO is not included in the charging circuit 202(1 ).

[0088] The charging circuit 202(2) is the same as the charging circuit 202 described above with respect to FIG. 2A. In this embodiment, the elements of the charging circuit 202(2) have the same elements as those described in the charging circuit 202 of FIG. 2A and all element numbers in the charging circuit 202(2) are the same as those in the charging circuit 202, except that the corresponding element numbers include the notation (2) to indicate that the charging circuit 202(2) is a second instance of a charging circuit, just like thecharging circuit 202 in FIG. 2A. The charging circuit 202(2) in FIG. 3A does not include an instance of the switch the switch SO as described above. In other embodiments, the charging circuit 202(2) in FIG. 3A does include an instance of the switch SO.

[0089] The charging circuit 202(1 ) and the charging circuit 202(2) are connected to the output inductor node 114 and are parallel with one another.

[0090] FIGs. 3B - 3D illustrate the voltage converter 300 shown in FIG. 3A with closed circuit paths demonstrating different switch configurations, in accordance with some embodiments.

[0091] More specifically, FIGs. 3B - 3D illustrate the voltage converter 300 in nine different switch configurations named switch configurations 1 - 9. The lines corresponding to each one of the switch configurations 1 - 9 are closed circuit paths, thereby indicating which of the switches S1 (1 ), S2(1 ), S3(1 ), S4(1 ), S1 (2), S3(2), S4(2), S5, S6 as well as new switches S8(1 ), S2(2), S8(2) are closed. For each particular one of the switch configurations 1 - 9, all of the other switches S1 (1 ), S2(1 ), S3(1 ), S4(1 ), S8(1 ), S1 (2), S2(2), S3(2), S4(2), S8(2), S5, S6 that are not provided along a particular line in FIGs. 3B - 3D are considered to be open.

[0092] The integer Z is an integer that corresponds to a particular switch configuration, where Z has a value of 1 - 9 to indicate a particular one of the switch configurations 1 - 9. Table V indicates whether a particular one of the switches S1 (1 ), S2(1 ), S3(1 ), S4(1 ), S8(1 ), S5, S6 is opened or closed in one of the switch configurations 1 - 9. Table VI indicates whether a particular one of the switches S1 (2), S2(2), S3(2), S4(2), S8(2), S5, S6 is opened or closed in one of the switch configurations 1 - 9.

[0093] With respect to the voltage converter 300 in FIGs. 3A - 3D, the following sentence is completed for each of the switch configurations 1 - 9 in accordance with Table V.

[0094] In switch configuration Z, the control circuit 130 is configured to generate the control output 132 such that:• the switch S1 (1 ) is (Row Z, Column S1 (1 ) Switch State from Table V);• the switch S2(1 ) is (Row Z, Column S2(1 ) Switch State from Table V);• the switch S3(1 ) is (Row Z, Column S3(1 ) Switch State from Table V); • the switch S4(1 ) is (Row Z, Column S4(1 ) Switch State from Table V);• the switch S8(1 ) is (Row Z, Column S8(1 ) Switch State from Table V);• the switch S5 is (Row Z, Column S5 Switch State from Table V); and• the switch S6 is (Row Z, Column S6 Switch State from Table V).

[0095] With respect to the voltage converter 300 in FIGs. 3A - 3D, the following sentence is completed for each of the switch configurations 1 - 9 in accordance with Table VI.

[0096] In switch configuration Z, the control circuit 130 is configured to generate the control output 132 such that:• the switch S1 (2) is (Row Z, Column S1 (2) Switch State from Table VI);• the switch S2(2) is (Row Z, Column S2(2) Switch State from Table VI);• the switch S3(2) is (Row Z, Column S3(2) Switch State from Table VI);• the switch S4(2) is (Row Z, Column S4(2) Switch State from Table VI);• the switch S8(2) is (Row Z, Column S8(2) Switch State from Table VI);• the switch S5 is (Row Z, Column S5 Switch State from Table VI); and• the switch S6 is (Row Z, Column S6 Switch State from Table VI).

[0097] In switch configuration 1 , the switches SO, S1 (1 ), S3(1 ), S4(1 ), S6 are closed. In this embodiment, the output inductor 1 16 is demagnetized, the fly capacitor CFLY(1 ) is charged, and the output capacitor 118 is charged, thereby increasing the magnitude of the output voltage VOIIT. In other embodiments, the switch S1 (1 ) is not closed. In other embodiments, the switch S1 (1 ) is open, preventing the fly capacitor CFLY(1 ) from recharging in this alternative switch configuration. The charging circuit 202(2) is configured to charge the fly capacitor CFLY(2) in switch configuration 1.

[0098] In switch configuration 2, the switches S4(1 ), S6, S8(1 ) are closed. In this embodiment, the current flows from the output node 122 to a power source node 220(1 ). In response to |VOUT| < VIN2, the fly capacitor CFLY(1 ) discharges, the output inductor 1 16 is magnetized, and there is energy transfer to the output node 122 and to the power source node 220(1 ). Accordingly, theoutput voltage VOUT decreases in magnitude. In response to |VOUT| > | VIN2|, the fly capacitor CFLY(1 ) is discharged, the output inductor 1 16 is demagnetized, and there is energy transfer to the output node 122 and to the power source node 220(1 ). The charging circuit 202(2) is configured to charge the fly capacitor CFLY(2).

[0099] In switch configuration 3, the switches the S2(1 ), S4(1 ), S6 are closed. In this embodiment, current flows from the output node 122 to the ground node 108 through the output inductor 116 and the fly capacitor CFLY(1 ). In response to |VOUT| < |VFLY(1 )|, the fly capacitor CFLY(1 ) is discharged, the output inductor 1 16 is magnetized, and there is energy transfer to the output node 122, thereby increasing the magnitude of the output voltage VOUT. Additionally, the output inductor 116 is magnetized, the fly capacitor CFLY(1 ) is discharged, and the output capacitor 118 is charged. In response to |VOUT| > |VFLY(1 )|, the fly capacitor CFLY(1 ) is discharged, the output inductor 1 16 is demagnetized, and there is energy transfer to the output node 122. The charging circuit 202(2) is configured to charge the fly capacitor CFLY(2).

[0100] In switch configuration 4, the switches S1 (1 ), S3(1 ) S4(1 ), S5 are closed. The switch SO may also be closed, if available. In alternative switch configurations, the switch S4(1 ) may be open if the switch SO is included and closed. In some embodiments where the power source node 126 is configured to receive the power source voltage VIN or the power source voltage VIN2, the fly capacitor CFLY(1 ) is recharged (i.e., gains energy) and the output inductor 1 16 is magnetized (i.e., gains energy). In an alternative embodiment where the power source node 126 is connected to receive the ground voltage, the fly capacitor CFLY(1 ) is recharged (i.e., gains energy) and the output inductor 116 is slowly demagnetized (i.e., leaks energy).

[0101] In switch configuration 5, the switches S2(1 ), S4(1 ), S5 are closed. In an alternative embodiment where the power source node 126 is connected to receive the ground voltage, the fly capacitor CFLY(1 ) discharges (i.e., loses energy) while the output inductor 1 16 is magnetized (i.e., gains energy) at a rate approximately proportional to the power source voltage VIN. In an alternativeembodiment where the power source node 1 6 is connected to receive the power source voltage VIN2, the fly capacitor CFLY(1 ) discharges (i.e., loses energy), the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to VIN + VIN2, and the power source node 220(1 ) loses energy. In the embodiments shown in FIGs. 3A - 3D where the power source node 126 is connected to receive the power source voltage VIN, the fly capacitor CFLY(1 ) discharges (i.e., loses energy), the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to 2VIN, and the power source node 126 loses energy.

[0102] In switch configuration 6, the switches S4(1 ), S5, S8(1 ) are closed. In an alternative embodiment where the power source node 126 is connected to receive the ground voltage, the fly capacitor CFLY(1 ) discharges (i.e., loses energy), the power source voltage VIN2 gains energy, and the output inductor 1 16 is magnetized (i.e., gains energy) at a rate approximately proportional to (VIN - VIN2). In an alternative embodiment where the power source node 126 is connected to receive the power source voltage VIN2, the fly capacitor CFLY(1 ) discharges (i.e., loses energy), the power source nodes 126, 220(1 ) gain energy, and the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to the power source voltage VIN. In some cases, when the first terminal of the switch S5 is connected to the power source voltage VIN, the fly capacitor CFLY(1 ) discharges (i.e., loses energy), the power source voltage VIN2 gains energy, and the output inductor 116 is magnetized (i.e., gains energy) at a rate approximately proportional to 2VIN - VIN2.

[0103] In switch configuration 7, the switches SO, S1 (2), S3(2), S4(2), S6 are closed. In this embodiment, the output inductor 1 16 is demagnetized, the fly capacitor CFLY(2) is charged, and the output capacitor 118 is charged, thereby increasing the magnitude of the output voltage VOUT. In other embodiments, the switch S1 (2) is not closed. In other embodiments, the switch S1 (2) is open, preventing the fly capacitor CFLY(2) from recharging in this alternative switch configuration. The charging circuit 202(1 ) is configured to charge the fly capacitor CFLY(1 ) in switch configuration 7.

[0104] In switch configuration 8, the switches S4(2), S6, S8(2) are closed. In this embodiment, the current flows from the output node 122 to a power source node 220(2). In response to |VOUT| < VIN2, the fly capacitor CFLY(2) discharges, the output inductor 1 16 is magnetized, and there is an energy transfer to the output node 122 and to the power source node 220(2). Accordingly, the output voltage VOIIT decreases in magnitude. In response to |VOUT| > | VIN2| , the fly capacitor CFLY(2) is discharged, the output inductor 1 16 is demagnetized, and there is an energy transfer to the output node 122 and to the power source node 220(2). The charging circuit 202(1 ) is configured to charge the fly capacitor CFLY(1 ).

[0105] In switch configuration 9, the switches S2(2), S4(2), S6 are closed. In this embodiment, current flows from the output node 122 to the ground node 108 through the output inductor 116 and the fly capacitor CFLY(2). In response to |VOUT| < |VCFLY(2)|, the fly capacitor CFLY(1 ) is discharged, the output inductor 1 16 is magnetized, and there is an energy transfer to the output node 122, thereby increasing the magnitude of the output voltage VOUT. Additionally, the output inductor 1 16 is magnetized, the fly capacitor CFLY(2) is discharged, and the output capacitor 1 18 is charged. In response to |VOUT| > |VFLY(2)|, the fly capacitor CFLY(2) is discharged, the output inductor 1 16 is demagnetized, and there is an energy transfer to the output node 122.

[0106] With reference to FIG. 4, the concepts described above may be implemented in various types of user elements 400, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 400 will generally include a control system 402, a baseband processor 404, transmit circuitry 406, receive circuitry 408, antenna switching circuitry 410, multiple antennas 412, and user interface circuitry 414. In a non-limiting example, the control system 402 may be a field- programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 402 may include at leastmicroprocessor(s), embedded memory circuit(s), and communication bus interface(s). The receive circuitry 408 receives radio frequency signals via the antennas 412 and through the antenna switching circuitry 410 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC(s)).

[0107] The baseband processor 404 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 404 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0108] For transmission, the baseband processor 404 receives digitized data, which may represent voice, data, or control information, from the control system 402, which it encodes for transmission. The encoded data is output to the transmit circuitry 406, where digital-to-analog converter(s) (DAC(s)) convert the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 412 through the antenna switching circuitry 410. The multiple antennas 412 and the replicated transmit and receive circuitries 406, 408 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0109] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein maybe combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0110] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:

1. A voltage converter comprising: a voltage converting circuit comprising: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; and an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit comprising: at least one fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches is configurable in at least one switch configuration to apply a first fly voltage across the at least one fly capacitor as a negative voltage at the second inductor node and in at least one switch configuration to apply a second fly voltage as a negative voltage at the second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 .

2. The voltage converter of claim 1 , wherein the factor is greater or equal to2.

3. The voltage converter of claim 1 , wherein: the at least one fly capacitor comprises a first fly capacitor and a second fly capacitor; the power source node is a first power source node; the set of switches comprises a first switch, a second switch, and a third switch;the charging circuit further comprises a second power source node that is configured to receive the input voltage; the first fly capacitor has a first end and a second end; the second fly capacitor has a third end and a fourth end; the first end of the first fly capacitor is coupled to the second inductor node; the first switch is coupled between the first power source node and the second end of the first fly capacitor; the second switch is coupled between the second end of the first fly capacitor and the third end of the second fly capacitor; and the third switch is coupled between the second power source node and the fourth end of the second fly capacitor.

4. The voltage converter of claim 3, wherein: the set of switches further comprises a fourth switch; and the fourth switch is coupled between the second inductor node and the first end of the first fly capacitor.

5. The voltage converter of claim 3, wherein: the set of switches further comprises a fourth switch and a fifth switch; the fourth switch is coupled between the first end of the first fly capacitor and ground; and the fifth switch is coupled between the third end of the second fly capacitor and the ground.

6. The voltage converter of claim 3, wherein: the set of switches further comprises a fourth switch and a fifth switch; the fourth switch is coupled between the second end of the first fly capacitor and ground; and the fifth switch is coupled between the fourth end of the second fly capacitor and the ground.

7. The voltage converter of claim 6, wherein: the set of switches further comprises a sixth switch; and the sixth switch is coupled between the first end of the first fly capacitor and the second inductor node.

8. The voltage converter of claim 7, wherein: the set of switches further comprises a seventh switch; and the seventh switch is coupled between the second inductor node and the ground.

9. The voltage converter of claim 1 , wherein the charging circuit is a first charging circuit, the at least one fly capacitor includes a first fly capacitor, the set of switches is a first set of switches, and the voltage converter further comprises: a second charging circuit coupled to the second inductor node, wherein the second charging circuit comprises: a second fly capacitor; the power source node is configured to receive the input voltage; and a second set of switches, wherein, in at least one switch configuration of the second set of switches, the second set of switches is configured to charge the second fly capacitor and, in at least one switch configuration of the second set of switches, the second set of switches is configured to present a third fly voltage across the second fly capacitor as a negative voltage at the second inductor node.

10. The voltage converter of claim 1 , wherein: the at least one fly capacitor comprises a first fly capacitor; the first fly capacitor has a first end and a second end; the first end of the first fly capacitor is coupled to the second inductor node;the power source node is a first power source node; the input voltage is a first input voltage; the charging circuit further comprises a second power source node configured to receive a second input voltage; the set of switches comprises a first switch and a second switch; the first switch is coupled between the first power source node and the second end of the first fly capacitor; and the second switch is coupled between the second power source node and the second end of the first fly capacitor.1 1 . The voltage converter of claim 10, wherein: a voltage magnitude of the first fly voltage is equal to a voltage magnitude of the first input voltage; and a voltage magnitude of the second fly voltage is equal to a voltage magnitude of the second input voltage.

12. The voltage converter of claim 10, wherein: the charging circuit is a first charging circuit; the set of switches is a first set of switches; and the voltage converter further comprises: a second fly capacitor having a third end and a fourth end; a second set of switches comprising a third switch and a fourth switch; a third power source node configured to receive the first input voltage; and a fourth power source node configured to receive the second input voltage.

13. The voltage converter of claim 12, wherein: the third end of the second fly capacitor is coupled to the second inductor node;the third switch is coupled between the third power source node and the fourth end of the second fly capacitor; and the fourth switch is coupled between the fourth power source node and the fourth end of the second fly capacitor.

14. The voltage converter of claim 10, wherein: the set of switches further comprises a third switch; and the third switch is coupled between the first end of the first fly capacitor and the second inductor node.

15. The voltage converter of claim 10, wherein: the set of switches further comprises a third switch; and the third switch is coupled between the first end of the first fly capacitor and ground.

16. The voltage converter of claim 10, wherein: the set of switches further comprises a third switch; and the third switch is coupled between the second end of the first fly capacitor and ground.

17. The voltage converter of claim 1 , wherein the power source node is a first power source node, the voltage converting circuit further comprises a second power source node configured to receive the input voltage and a switch, wherein the switch is coupled between the second power source node and the first inductor node.

18. The voltage converter of claim 1 , wherein the power source node is a first power source node and the voltage converting circuit further comprises a first switch and a second switch, wherein: the first switch is coupled between the output node and the first inductor node; andthe second switch is coupled between a second power source node and the first inductor node, wherein the second power source node is configured to receive the input voltage.

19. A method of converting an input voltage into an output voltage at an output node, the method comprising: receiving the input voltage at a power source node, wherein the output node is operably associated with a first inductor node of an output inductor; setting a set of switches in a first switch configuration to apply a first fly voltage across at least one fly capacitor as a negative voltage at a second inductor node of the output inductor; and setting the set of switches in a second switch configuration to apply a second fly voltage as a negative voltage at the second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 .

20. A user element comprising a voltage converter, wherein the voltage converter comprises: a voltage converting circuit comprising: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; and an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit comprising: at least one fly capacitor; a power source node configured to receive an input voltage; and a set of switches, wherein the set of switches is configurable in at least one switch configuration to apply a first fly voltage across the at least one fly capacitor as a negative voltage at the second inductor node and inat least one switch configuration to apply a second fly voltage as a negative voltage at the second inductor node, wherein the second fly voltage is equal to the first fly voltage times a factor and wherein the factor is greater than 1 .

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