System and method for low-density parity check code (LDPC) with code rate of 5 / 6

Abstract

In some implementations, a device may include a transmitter and one or more processors. These processors may be configured to identify, based on a 5 / 6 encoding rate and a 3888-bit code block size, a first binary parity check matrix for a quasi-cyclic low-density parity check code (QC-LDPC). The first binary parity check matrix may correspond to a first exponent matrix with 96 values. The processors may be configured to encode data using this matrix and then transmit the encoded data.

Description

System and method for low-density parity-checking code (LDPC) with a code rate of 5 / 6. This application claims the benefit of priority for each of US provisional patent application No. 63 / 516,688 filed July 31, 2023, US provisional patent application No. 63 / 516,700 filed July 31, 2023, and US provisional patent application No. 63 / 600,327 filed November 17, 2023. This disclosure relates, in general, to systems and methods for improving an encoding process and / or a decoding process of a communications system using a quasicyclic low-density parity-checking code (QC-LDPC). Error correction codes allow for the reliable exchange of information between a transmitter and a receiver communication system. A transmitter communication system encodes the information to create a codeword. The codeword is the encoded information. The transmitter communication system then transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may not be identical to the transmitted codeword. Encoding the information allows a receiver communication system, with an appropriate decoding process, to recover the information from the received transmission despite this noise. For example, the transmitter communication system transmits parity bits to the receiver communication system.Parity bits allow the receiver's communication system to verify whether the received transmission is a valid codeword and to correct transmission errors if the received transmission is not a valid codeword. In one approach, generating parity bits involves a complex process. US patent 2016 / 380722 A1 discusses relevant prior art. The invention is defined by the attached claims. According to one aspect, a method is provided, which comprises: to identify, by one or more processors of a first device according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check array for a quasicyclic low-density parity check code (QC-LDPC), the first binary parity check array corresponding to a first exponent array of 96 values; encode, by one or more processors of the first device, data using the first binary parity check matrix; and transmit, by one or more processors of the first device, the encoded data. Advantageously, the method also includes: Generate the first exponent matrix by selecting at least 94 values ​​from a second exponent matrix that has the same dimensions as the first exponent matrix. Advantageously, the method also includes: shift one or two values ​​from the first exponent matrix by one or more corresponding positive values ​​from the second exponent matrix by -1 or +1, in which the one or more corresponding positive values ​​of the second exponent matrix are not selected as the at least 94 values. Advantageously, the second exponent matrix comprises the following set of values: [2896161134914915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130 143310.- 112.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 1 5.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10]. Advantageously, the second exponent matrix comprises the following set of values: [2796160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114 130133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. Advantageously, the method also includes: Identifying a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as the first binary parity check matrix; and encoding data using the second binary parity check matrix by one or more processors. Advantageously, the method further comprises: identify a third binary parity checking matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted, the second exponent matrix having the same dimensions as the dimensions of the first exponent matrix; and Encoding data by one or more processors using the third binary parity check matrix. Advantageously, the method also includes: generate the first binary parity check matrix using (1) a matrix product of the first binary parity check matrix and the first exponent matrix, or (2) a matrix product of the first exponent matrix and the first binary parity check matrix. Advantageously, the method also includes: to identify, by a second device, the first binary parity check matrix; to receive, via the second device from the first device, the encoded data; and Decode, by the second device, the encoded data using the first binary parity check matrix. According to one aspect, an apparatus is provided comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify, according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasicyclic low-density parity check code (QC-LDPC), the first binary parity check matrix corresponding to a first exponent matrix having 96 values; encode data using the first binary parity check matrix; and transmit the encoded data. Advantageously, the one or more processors are also configured to: Generate the first exponent matrix by selecting at least 94 values ​​from a second exponent matrix that has the same dimensions as the first exponent matrix. Advantageously, one or more processors are also configured to: shift one or two values ​​from the first exponent matrix by one or more corresponding positive values ​​from the second exponent matrix by -1 or +1, in which the one or more corresponding positive values ​​of the second exponent matrix are not selected as the at least 94 values. Advantageously, the second exponent matrix comprises the following set of values: [2896161134914915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114 130143310.- 112.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 1 5.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10]. Advantageously, the second exponent matrix comprises the following set of values: [2796160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114 130133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. Advantageously, the one or more processors are also configured to: Identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as the dimensions of the first binary parity check matrix; and encode data using the second binary parity check matrix. Advantageously, the one or more processors are also configured to: identify a third binary parity checking matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted, the second exponent matrix having the same dimensions as the dimensions of the first exponent matrix; and encode data using the third binary parity check matrix. Advantageously, the one or more processors are also configured to: generate the first binary parity check matrix using (1) a matrix product of the first binary parity check matrix and the first exponent matrix, or (2) a matrix product of the first exponent matrix and the first binary parity check matrix. According to one aspect, an apparatus is provided comprising: a receiver configured to receive encoded data; and One or more processors are configured to: Identify, based on a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasicyclic low-density parity check code (QC-LDPC), the first binary parity check matrix corresponding to a first exponent matrix having 96 values; and Decode the received encoded data using the first binary parity check matrix. Advantageously, the first exponent matrix comprises the following set of values: [2896161134914915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114 130143310.- 112.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 1 5.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10]. Advantageously, the first exponent matrix comprises the following set of values: [2796160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114 130133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. Brief description of the drawings Various objects, aspects, features, and advantages of the exhibition will become clearer and be better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which similar reference characters identify corresponding elements throughout. In the drawings, similar reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. Figure 1 is a diagram representing an example communication environment with communication systems, according to one or more embodiments. Figure 2 is a schematic block diagram of a computer system, according to one embodiment. Figure 3 is a diagram that represents an example exponent matrix, according to one or more forms of realization. Figure 4 is a diagram representing example shifted identity matrices to generate a parity checking matrix, according to one or more implementations. Figure 5 is a diagram representing an example parity checking matrix, according to one or more implementation forms. Figures 6A and 6B are diagrams that represent an example code design that uses a protograph lifting concept / method, according to one or more embodiments. Figures 7A, 7B, 7C and 7D are diagrams that represent an example code for concurrent decoding, according to one or more implementation forms. Figure 8 is a flowchart showing a process for encoding data using an LDPC code, according to one embodiment. Figure 9 is a flowchart showing a process for encoding and / or decoding data using an LDPC code, according to one embodiment. Figures 10A, 10B, 10C, 10D, 10E and 10F are diagrams that represent example simulation results using QC-LDPC codes, according to one or more embodiments. Details of various ways of implementing the methods and systems are set out in the attached drawings and the description below. Detailed description The following exposition provides many different embodiments, or examples, for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the present exposition. These are, of course, merely examples and are not intended to be exhaustive. For example, a first feature in communication with, or communicatively coupled to, a second feature in the description that follows may include embodiments in which the first feature is in direct communication with, or directly coupled to, the second feature, and may also include embodiments in which additional features are intermediate between the first and second features, such that the first feature is in indirect communication with, or indirectly coupled to, the second feature.Furthermore, this exposition may repeat reference numbers and / or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not, in itself, dictate a relationship between the various forms of implementation and / or configurations analyzed. Various embodiments disclosed herein relate to an apparatus comprising a transmitter and one or more processors. The one or more processors may be configured to determine a quasicyclic low-density parity-check (QC-LDPC) code having a plurality of codebooks embedded therein. The one or more processors may be configured to select a codebook from the plurality of codebooks based on a code block size and code rate. The one or more processors may be configured to generate a parity-check matrix based on the codebook. A parity-check matrix refers to an array that can define relationships (e.g., parity-check equations or constraints) between information bits and parity bits.A binary parity check matrix refers to a parity check matrix in which all entries are either 0 or 1. One or more processors can be configured to encode data using the generated parity check matrix. These processors can then be configured to transmit the encoded data to another device via a transmitter. In some implementations, each codebook in the codebook plurality may include a plurality of integers, the number of integer pluralities being equal to the number of elements in the parity-check matrix divided by z, where z is an integer representing a QC-LDPC code lift size. In some implementations, each codebook in the codebook plurality can represent an array of exponents of the parity-checking matrix. In some implementations, each element of the exponent array can correspond to a cyclic shift value of an identity matrix. One size of the identity matrix is ​​z x z, and the cyclic shift value d is an integer such as -1d. <z, donde Z es un número entero que representa un tamaño de elevación del código QC-LDPC. El valor de desplazamiento cíclico d puede representar una matriz identidad desplazada que se obtiene desplazando hacia la derecha la matriz identidad en d. El valor de desplazamiento cíclico -1 puede representar una matriz nula de la atriz identidad. In some implementations, when generating the parity check matrix based on the selected codebook, one or more processors can be configured to generate an exponent matrix based on the selected codebook. For each element of the exponent matrix, one or more processors can be configured to generate a shifted identity matrix based on a value for each element of the exponent matrix. The one or more processors can then be configured to generate the parity check matrix such that the parity check matrix includes, as the corresponding element for each element of the exponent matrix, the generated shifted identity matrix. In some implementations, the code block size can be 3888 bits, and the code rate can be 5 / 6.The code block size (denoted by n) refers to the total number of bits encoded or transmitted as a result of encoding data using an error-correcting code (e.g., LDPC). The number of information bits (denoted by k) refers to the number of bits that carry the data to be encoded using the error-correcting code. The code rate (denoted by R) refers to the ratio of the number of information bits to the code block size (R = k / n). A plurality of codebooks may include a first codebook and a second codebook. The first codebook may include [2896161134914915611531057512.- 198146631491474.- 12.- 1 -1138 127148114128156114130143310.- 112.- 113618961241095.- 10.- 110432116049528510890 144143181347.- 111.- 15.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146105 2 -1 -10].The second codebook may include [2796160133914815601521057512.- 19814663149 1474.- 12.- 1 -1138126148113128155114130133310.- 112.- 113618961241095.- 10.- 110331 1 16048518410889143143181347.- 111.- 15.- 1107.- 1003358738389113119751004.- 11318 13110.- 1.- 1146105.- 1 -10]. In one respect, a parity-check matrix defines a set of equations that are satisfied by any valid codeword. The parity-check matrix can be used to encode low-density parity-check codes ("LDPCs"), described by Richardson and Urbanke in IEEE Transactions on Information Theory, vol. 47, no. 2 (February 2001). In general, many wired and wireless communication systems use LDPC as a direct coding scheme with error correction. However, the longest block length (in bits) for encoded data supported in the 802.11 standards (e.g., 802.11n–802.11be) is 1944. There may be limited gain in a radio channel (e.g., 2x2 multiple-input multiple-output channels) that can be achieved using a block length of 1944. To address this problem, some of the implementations discussed here relate to a technique for supporting or providing an LDPC code with a block length of 3888 and a code rate of 5 / 6. The block length of 3888 is twice that of the longest code supported in the 802.11n-802.11be standards (e.g., the 1944 block length). In some implementations, the LDPC code features a quasi-cyclic (QC) structure, which facilitates efficient encoding and decoding. In some implementations, QC-LDPC codes can be a type of structured LDPC code, which can be used in many practical applications, including those covered by the IEEE 802.11n, 802.11ac, 802.11ax, and 802.11be standards.In QC-LDPC codes, a parity-check matrix has a cyclic structure that repeats itself in a quasi-cyclic way, which can simplify the encoding and decoding processes, making QC-LDPC codes more efficient. In some implementations, an LDPC encoder can take a block of k bits of information bits and produce n encoded bits (with a code rate of R=k / n). An LDPC decoder can operate on (noisy version of) n received bits and recover (ideally) the k bits of information. In some implementations, the LDPC encoder can take a block of 3240 bits of information bits (k=3240) as input, encode the 3240-bit block to produce a block of 3888 encoded bits (n=3888) with a code rate of 5 / 6 (R=k / n). Generally, a parity-check matrix for a code represents equations that determine whether errors have occurred during transmission. More formally, for all valid codewords (i.e., bits produced by the encoder without errors), the following equation holds: (Equation 1) In equation 1, "H" is the parity-check matrix, "c" is a codeword vector, and "0" is a vector of all zeros. The parity-check matrix, H, is one way to describe a code. A generator matrix for a code G satisfies the following equation: (Equation 2) In equation 2, "s" is a vector of information bits, "G" is a generator matrix, and "c" is the codeword corresponding to "s". In some embodiments, a system (for example, a communication system 108 that includes a decoder 160) can decode the codeword c to obtain the decoded data s using equation 2. The parity-check and generator matrices for a code are related according to the matrix equations above. Generally, if a parity-check matrix is ​​low-density, the corresponding generator matrix will be high-density, and vice versa. Consequently, LDPC codes are characterized by low-density parity-check matrices and high-density generator matrices. The density of a matrix refers to the number of operations that must be performed to implement one of the equations above. Although it was recognized in 1995 that LDPC codes could be used to transmit data with very few errors—that is, with error rates as good as or better than those of turbocodes—a disadvantage of LDPC codes is that their generator matrices were high-density, making encoding computationally demanding and rendering the codes impractical for many applications. In some implementations, a parity-check matrix may have a quasi-cyclic structure, for example, a parity-check matrix for QC-LDPC code (n=3888, k=3240, R=5 / 6). Given a lift size Z, the parity-check matrix may have a plurality of submatrices such that each submatrix is ​​a cyclically shifted version of an identity matrix of size (Z x Z), where Z = 162, for example. A parity-check matrix can be represented in two equivalent forms: (1) a parity-check matrix H and (2) a block matrix or an exponent matrix P=E(H). In some implementations, a parity-check matrix H can be a binary array of size m x n (where m and n are integers). The elements of the parity-check matrix are binary values. Given a block length n and a code rate R, an LDPC code (or QC-LDPC code) LDPC(n, R) satisfies the following equations: (Equation 3) (Equation 4) In some implementations, a block array or an exponent array (QC-LDPC exponent array) can be obtained. Given a lift size Z, the exponent array P=E(H) can have a size of m / Z x n / Z. If n = 24Z (for example, n = 3888, Z = 162), then the size of P=E(H) is 24(1-R) ​​x 24 (= n(1-R) / Z x n / Z). The elements of the exponent array can be integer values ​​corresponding to cyclic shift values ​​of the Z x Z identity array. A parity-check array H can be a sparse binary array derived from an exponent array P=E(H). The generator array G can have a size of n x k in binary form (for example, the elements of the generator array G are binary values). The exponent matrix P=E (H) can have a structure that includes a plurality of submatrices (for example, A, B, C, D, E, T). In some implementations, a binary QC-LDPC code LDPC(n, R) can be characterized by the null space of an n(1-R) ​​x n parity-check matrix H. The parity-check matrix H can be a binary sparse matrix that includes a set of Z x Z circulating matrices. The parity-check matrix H of a QC-LDPC code can be equivalently represented by an exponent matrix P = E(H). This representation can help illustrate the graphical structure of the underlying code as a basis graph, along with the shift coefficient. In some implementations, a plurality of codebooks may be provided to generate parity-checking arrays. For example, the plurality of codebooks might include a first codebook and a second codebook. A codebook refers to a collection of codewords (or code vectors) or error-correcting codes (e.g., LDPC codes) used in error correction and / or data compression. Codewords refer to coded representations generated by applying an error-correcting code to the original data. The first codebook for representing a block matrix P=E (H) may include [2896161134914915 611531057512.- 198146631491474.- 12.- 1 -1; 138127148114128156114130143310.- 112.- 1 13618961241095.- 100-1; 10432116049528510890144143181347.- 111.- 15.- 1107.- 100; 33 58738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10]........ (Codebook 1) The second codebook for representing a block matrix P=E (H) may include [27961601339148 15601521057512.- 198146631491474.- 12.- 1-1; 138126148113128155114130133310.- 112.- 1 13618961241095.- 10.- 1; 10331116048518410889143143181347.- 111.- 15.- 1107.- 100; 33 58738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]........ (Code Book 2) In some implementations, a parity-checking matrix H can be generated from an exponent matrix P=E(H) using a codebook. The exponent matrix P=E(H) can include (as elements) shift values ​​d in the interval 0<=d <Z junto con d=-1. Por ejemplo, si Z=7, los valores de desplazamiento d pueden incluir -1, 0, 1, 2, 3, 4, 5, 6. El valor de desplazamiento d=0 puede corresponder (o mapearse) a una matriz identidad de tamaño Z x Z, indicada por I (Z) . El valor de desplazamiento d=-1 puede corresponder (o mapearse) a una matriz nula (todos los elementos son cero) de tamaño Z x Z, indicada por 0*I (Z) . Cualquier otro valor entero d en [1, Z-1] puede corresponder (o mapearse) a una matriz desplazada cíclicamente hacia la derecha desde I (Z) .The parity checking matrix H can be obtained from the exponent matrix P=E(H) by expanding the exponent matrix P in such a way that each element of the exponent matrix P (as a shift value d) is replaced by a matrix corresponding to the shift value. In some implementations, the exponent matrix P=E (H) may include a plurality of elements P1, 1, P1, 2, P1, 3, ..., P1, ; P2, 1, P2, 2, P2, 3, ..., P2, ;..., P1, 1, P1, 2, P1, 3, ..., P, , which correspond to values ​​( x ) from a codebook where y satisfy the following equations: (Equation 5) (Equation 6) The exponent matrix (or permutation matrix) P=E (H) can be expressed as follows: (Equation 7) The corresponding parity-check matrix H can be obtained by replacing each element of the matrix (as a displacement value d) with a matrix C(d) corresponding to the displacement value as follows: (Equation 8) For example, a matrix C (1) can be expressed as follows: (Equation 9) In some implementations, an encoder can produce codewords using a generator matrix (for example, using Equation 2). In some implementations, an encoder can use the parity-check matrix (instead of the generator matrix) to produce codewords from vectors of information bits. After a parity-check matrix H is obtained (for example, using a codebook), the parity-check matrix H can have submatrices A, B, C, D, T, and E. An upper area O of submatrix T can correspond to an area where the matrix contains all zeros, and the other areas can represent locations that can contain ones. In some implementations, the code word c can be obtained using the following expression: (Equation 10) where "s" is the vector of information bits to be encoded, "p1" is a vector of the first g parity bits and "p2" is a vector of the remaining mg parity bits. The vectors p1 and p2 can be obtained using the following equations: Although various embodiments disclosed herein are described for encoding data for wireless communication (e.g., wireless local area network (WLAN) that conforms to any IEEE 802.11 standard), the principles disclosed herein are applicable to other types of communication (e.g., wired communication) or any process that performs encoding for LDPC codes. In some implementations, a device may include a transmitter and one or more processors. The one or more processors may be configured to generate, at a 5 / 6 code rate, a first binary parity check matrix for a QC-LDPC code using a first matrix that has 96 values. The first matrix comprises at least 94 values ​​selected from the following set of values: [28 96161134914915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130 143310.- 112.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 1 5.- 1107.- 10033 58738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10]. One or more processors can be configured to encode data using the first generated binary parity check matrix. One or more processors can be configured to have the transmitter transmit the encoded data.In some implementations, the first binary parity check array can be generated with a size of 3888 bits. One or more processors are further configured to shift one or two values ​​from the first array by -1 or +1, based on one or more corresponding positive values ​​in the value set. The corresponding positive values ​​in the value set cannot be selected from the at least 94 values. In some implementations, a device may include a transmitter and one or more processors. The one or more processors may be configured to generate, at a 5 / 6 code rate, a first binary parity check matrix for a QC-LDPC code using a first matrix that has 96 values. The first matrix comprises at least 94 values ​​selected from the following set of values: [27 96160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 10033 58738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. One or more processors can be configured to encode data using the first generated binary parity check matrix. One or more processors can be configured to have the transmitter transmit the encoded data.In some implementations, the first binary parity check array can be generated with a size of 3888 bits. One or more processors are further configured to shift one or two values ​​from the first array by -1 or +1, based on one or more corresponding positive values ​​in the value set. The corresponding positive values ​​in the value set cannot be selected from the at least 94 values. The implementations presented here offer at least the following advantages and benefits. First, these implementations can provide useful techniques for delivering significant gains across all modulation schemes. For example, the block length (e.g., 3888 bits) of a QC-LDPC code according to some implementations is at least twice that of the longest code supported in the 802.11n-802.11be standards (e.g., 1994 bits). This QC-LDPC code can deliver a gain of approximately 2 dB in 2x2 MIMO (multiple-input, multiple-output) channels, and the gains are constant across all modulation schemes, with or without beamforming. Second, the implementations presented here can provide useful techniques for delivering significant gains (e.g., 0.5 dB to 1 dB).2 dB in SNR (signal-to-noise ratio) compared to existing codes across all modulation schemes. For example, the block length (e.g., 3888 bits) of a QC-LDPC code according to some implementations is at least twice that of the longest code supported in the 802.11n-802.11be standards (e.g., 1994 bits). This QC-LDPC code can provide a gain of approximately 2 dB in 2x2 MIMO channels, and the gains are constant across all modulation schemes, with or without beamforming. Third, the implementations described here can provide a codebook and methods for constructing the codebook. In some implementations, the QC-LDPC code can be constructed by slightly adjusting (nudging) the cyclic shift values ​​of the parity-checking matrices. Referring to Figure 1, a diagram illustrates an example communication environment 100 that includes communication systems (or communication devices) 105 and 108, according to one or more embodiments. In one embodiment, communication system 105 includes a baseband circuit set 110 and a transmitter circuit set 120, and communication system 108 includes a baseband circuit set 150 and a receiver circuit set 140. In one aspect, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components work together to exchange data (e.g., messages or frames) over a wireless medium.These components are incorporated as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof, in one or more embodiments. In some implementations, the 105, 108 communication systems include more, fewer, or different components than those shown in Figure 1. For example, each of the 105, 108 communication systems includes transceiver circuit assemblies to enable bidirectional communication between the 105, 108 communication systems or with other communication systems. In some implementations, each of the 105, 108 communication systems may have a configuration similar to that of a 2000 computer system, as shown in Figure 2. The baseband circuit set 110 of communication system 105 is a set of circuits that generates baseband data 115 for transmission. Baseband data 115 includes information data (e.g., signal(s)) at a baseband frequency for transmission. In one approach, the baseband circuit set 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. In another aspect, the baseband circuit set 110 (or the encoder 130) obtains a generator matrix or a parity check matrix, or uses a pre-produced generator matrix or a pre-produced parity check matrix, and encodes the information data by applying the information data to the generator matrix or the parity check matrix to obtain a codeword.In some implementations, baseband circuit set 110 stores one or more generator arrays or one or more parity check arrays that conform to any IEEE 802.11 standard for WLAN communication. Baseband circuit set 110 retrieves the stored generator array or parity check array in response to detecting information data to be transmitted, or in response to receiving an instruction to encode the information data. In one approach, baseband circuit set 110 generates the parity bits based on a portion of the generator array or using the parity check array, and appends the parity bits to the information bits to form a codeword.The baseband circuit set 110 generates the baseband data 115 which includes the codeword for communication system 108, and provides the baseband data 115 to the transmitter circuit set 120. The transmitter circuit set 120 of communication system 105 includes or corresponds to a circuit set that receives baseband data 115 from baseband circuit set 110 and transmits a wireless signal 125 based on the baseband data 115. In one configuration, the transmitter circuit set 120 is coupled between the baseband circuit set 110 and an antenna (not shown). In this configuration, the transmitter circuit set 120 upconverts the baseband data 115 from baseband circuit set 110 into a carrier signal to generate the wireless signal 125 at an RF frequency (e.g., from 10 MHz to 60 GHz) and transmits the wireless signal 125 through the antenna. The receiver circuit set 140 of communication system 108 is a circuit set that receives the wireless signal 125v from communication system 105 and obtains baseband data 145 from the received wireless signal 125. In one configuration, the receiver circuit set 140 is coupled between the baseband circuit set 150 and an antenna (not shown). In this configuration, the receiver circuit set 140 receives the wireless signal 125 through an antenna and performs downconversion of the wireless signal 125 to an RF frequency based on a carrier signal to obtain baseband data 145 from the wireless signal 125. The receiver circuit set 140 then provides the baseband data 145 to the baseband circuit set 150. The baseband circuit set 150 of communication system 108 includes or corresponds to a circuit set that receives baseband data 145 from receiver circuit set 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuit set 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain the information data generated by the baseband circuit set 110 of communication system 105. In some implementations, each of the baseband circuit set 110 (which includes the encoder 130), the transmitter circuit set 120, the receiver circuit set 140, and the baseband circuit set 150 (which includes the decoder 160) may be as one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. Figure 2 is a schematic block diagram of a computer system, according to one embodiment. An illustrated example computer system 2000 includes one or more processors 2010 in direct or indirect communication, via a communication system 2040 (e.g., bus), with memory 2060, at least one network interface controller 2030 with a network interface port for connection to a network (not shown), and other components, e.g., input / output ("I / O") components 2050. Generally, the processor(s) 2010 will execute instructions (or computer programs) received from memory. The illustrated 2010 processor(s) incorporates, or is connected to, the 2020 cache memory. In some cases, instructions are read from memory 2060 to cache memory 2020 and executed by the 2010 processor(s) from cache memory 2020.The Computer System 2000 may not necessarily contain all of the components shown in Figure 2, and may contain other components not shown in Figure 2. In more detail, the 2010 processor(s) can be any logic circuit that processes instructions, for example, instructions fetched from the 2060 memory or the 2020 cache. In many implementations, the 2010 processor(s) is / are microprocessor units or special-purpose processors. The 2050 computing device can be based on any processor, or set of processors, that can operate as described herein. The 2010 processor(s) can be single-core or multi-core processor(s). The 2010 processor(s) can be multiple distinct processors. 2060 memory can be any device suitable for storing computer-readable data. 2060 memory can be a fixed-storage device or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, memory media and devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD-ROM, DVD-ROM, or Blu-ray® discs). A 2000 computer system can feature any number of 2060 memory devices. The 2020 cache is generally a form of computer memory placed in close proximity to the 2010 processor(s) for fast read times. In some implementations, the 2020 cache is part of, or on the same chip as, the 2010 processor(s). In some implementations, there are multiple levels of 2020 cache, for example, L2 and L3 cache layers. The 2030 network interface controller manages data exchange across the network interface (sometimes called network interface ports). The 2030 network interface controller handles the physical and data link layers of the OSI model for network communication. In some implementations, some of the network interface controller's tasks are handled by one or more of the 2010 processor(s). In some implementations, the 2030 network interface controller is part of a 2010 processor. In some implementations, the 2000 computing system has multiple network interfaces controlled by a single 2030 controller. In some implementations, the 2000 computing system has multiple 2030 network interface controllers. In some implementations, each network interface is a connection point for a physical network link (for example, a Cat-5 Ethernet link).In some implementations, the 2030 network interface controller supports wireless network connections, and an interface port is a wireless (e.g., radio) receiver or transmitter (for example, for any of the IEEE 802.11, Near Field Communication "NFC", Bluetooth, ANT, or other wireless protocols). In some implementations, the 2030 network interface controller implements one or more network protocols such as Ethernet. Generally, a 2050 computing device exchanges data with other computing devices using physical or wireless links through a network interface. The network interface can connect directly to another device or to another device through an intermediary device, such as a network device like a hub, bridge, switch, or router, which connects the 2000 computing device to a data network such as the Internet. The Computer System 2000 may include, or provide interfaces for, one or more input or output ("I / O") devices. Input devices include, but are not limited to, keyboards, microphones, touchscreens, pedals, sensors, MIDI devices, and pointing devices such as a mouse or trackball. Output devices include, but are not limited to, video displays, speakers, an updatable Braille terminal, lights, MIDI devices, and 2D or 3D printers. Other components may include an I / O interface, external serial device ports, and any additional coprocessors. For example, a Compute 2000 system may include an interface (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., a portable flash drive or external media drive). In some implementations, a Compute 2000 device includes an additional device such as a coprocessor; for example, a math coprocessor may assist the 2010 processor with complex or high-precision calculations. The 2090 components can be configured to connect to external media, a 2070 display element, a 2080 input device, or any other component in the 2000 computing system, or combinations thereof. The 2070 display element can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display element, a flat panel display element, a solid-state display element, a cathode ray tube (CRT) display element, a projector, a printer, or another display device now known or later developed to output specific information. The 2070 display element can act as an interface for the user to view the operation of the 2010 processor(s), or specifically as an interface with software stored in the 2060 memory. The 2080 input device can be configured to allow a user to interact with any of the components of the Computer 2000 system. The 2080 input device can be a plurality pad, a keyboard, a cursor control device such as a mouse, or a joystick. Additionally, the 2080 input device can be a remote control, a touch screen (which can be a combination of the 2070 display element and the 2080 input device), or any other device capable of interacting with the Computer 2000 system, such as any device that acts as an interface between a user and the Computer 2000 system. Figure 3 is a diagram representing an example exponent matrix 300 (QC-LDPC exponent matrix), according to one or more embodiments. Given a lift size Z, the exponent matrix 300 can have a size of m / Z x n / Z. If n = 24Z (for example, n = 3888, Z = 162), then the size of P=E(H) is 24(1-R) ​​x 24 (= n(1-R) / Z x n / Z). The elements of the exponent matrix can be integer values ​​corresponding to cyclic shift values ​​of the Z x Z identity matrix. A parity-check matrix H (see Figure 5) can be a binary sparse matrix that can be derived from an exponent matrix P=E(H). The generating matrix G can have a size of nxk in binary form (for example, the elements of the generating matrix G are binary values).Referring to figure 3, the exponent matrix P=E (H) can have a structure that includes a plurality of submatrices (for example, A 310, B 312, C 316, D 318, E 320, T 314). Figure 4 is a diagram 400 representing example shifted identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity-checking matrix, according to one or more embodiments. A parity-checking matrix H can be generated from an exponent matrix P=E(H) (for example, the exponent matrix 300) using a codebook (for example, codebook 1 or codebook 2). As shown in Equation 7, the exponent matrix P=E(H) can include (as elements) shift values ​​d in the interval 0<=d <Z junto con d=-1. Véase la ecuación, por ejemplo, si Z=7, los valores de desplazamiento d pueden incluir -1, 0, 1, 2, 3, 4, 5, 6 (véase la figura 4) . El valor de desplazamiento d=0 puede corresponder (o mapearse) a una matriz identidad de tamaño Z x Z, indicada por I (Z) (por ejemplo, la matriz 410) .The shift value d=-1 can correspond to (or be mapped to) a null matrix (all elements are zero) of size Z x Z, denoted by 0*I (Z) (for example, the matrix 409). Any other integer value d in [1, Z-1] can correspond to (or be mapped to) a matrix cyclically shifted to the right of I (Z) (for example, the matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity-checking matrix H can be obtained from the exponent matrix P=E (H) by expanding the exponent matrix P such that each element of the exponent matrix P (as a shift value d) is replaced by a matrix corresponding to the shift value. Figure 5 is a diagram representing an example parity-check matrix 500, according to one or more embodiments. In some implementations, an encoder (e.g., the encoder 130) may produce codewords using a generator matrix (e.g., using equation 2). In some implementations, an encoder (e.g., the encoder 130) may use the parity-check matrix (instead of the generator matrix) to produce codewords from vectors of information bits. After a parity-check matrix H is obtained (e.g., using a codebook), the parity-check matrix H (e.g., the parity-check matrix 500) may have submatrices A 510, B 512, C 516, D 518, T 514, E 520.An upper area O 515 of the submatrix T 514 (for example, the white area in Figure 5) can correspond to an area where the matrix contains all zeros, and the other areas (for example, the gray area in Figure 5) can represent locations that can contain ones. The size of the parity-check matrix 500 can be m x n where the size of the submatrix D 518 is g x g, and the size of the submatrix T is (mg) x (mg). In some implementations, given a vector s of information bits to be encoded, the encoder can obtain a codeword c using Equation 10, Equation 11, Equation 12, and Equation 13. In some implementations, a codebook for the LDPC code with R=5 / 6 and a block length of 3888 bits can provide high-performance error correction and / or up to 1.2 dB of gain compared to existing LDPC codes specified in Wi-Fi standards. In some implementations, a collection of LDPC codes with a block length of 3888 bits (2 x 1944) supports all code rates in a Wi-Fi standard (e.g., 802.11be). The code (e.g., the LDPC code with R=5 / 6 and a block length of 3888 bits) can be used directly in existing 64-QAM modulation in the IEEE 802.11be standard and potentially in combination with more QAM size combinations in the IEEE 802.11bn standard. The collection of LDPC codes with a block length of 3888 bits (2x1944) can provide considerable performance improvements in various ultra-high reliability (UHR) communication scenarios while maintaining manageable complexity. Performance comparisons are conducted between these codes and LDPC codes specified in the IEEE 802.11be standards, as well as recently proposed codes with a block length of 4x1944. The results of the performance comparisons show demonstrable across-the-board gains (e.g., channels, PHY bandwidth, MIMO, modulation and coding scheme (MCS), transmission beamforming). For example, LDPC codes with a block length of 3888 bits, according to some implementations, can provide gains of 0.5–1.0 dB over current 802.11 LDPC codes, depending on channel conditions.LDPC codes with a block length of 4x1944 bits can provide an additional gain of 0.0-0.5 dB, depending on channel conditions. The longest LDPC codes specified in the 802.11be standards have a block length of 1944 bits. In terms of performance, the LDPC codes specified in the 802.11be standards are approximately 2.7 dB below optimal random codes (e.g., bit interleaved code modulation (BICM), additive white Gaussian noise (AWGN), and quadrature amplitude modulation (QAM) with R=5 / 6 limits). Longer block-length random codes (e.g., Shannon's limit addresses the asymptotic case when the block length grows infinitely large) can lead to improved coding gains, according to finite-length scaling laws. Deterministic codes, which are suboptimal, can exhibit scaling gains that are significantly higher than those of optimal random codes. For example, a doubling effect is known to occur in AWGN. In some implementations, LDPC codes with a block length of 2 x 1944 = 3888 bits (doubling the maximum supported block length in current 802.11be standards) can support all existing code rates (e.g., R = 1 / 2, 2 / 3, 3 / 4, and 5 / 6). In some implementations, LDPC codes with a block length of 3888 bits can maintain the 802.11be code structure, specifically QC-LDPC, unchanged except for the expanded array size. This adaptation can facilitate the reuse of existing implementations and enable concurrent encoding and decoding capabilities. Figures 6A and 6B are diagrams that represent an example code design that uses a protograph lifting concept / method, according to one or more embodiments. Figure 6A is a diagram 600 depicting the design / generation / creation / definition of an example code design using a protograph lifting concept / method, according to one or more embodiments. A "protograph" can refer to a bipartite graph having two sets of disjoint and independent vertices (e.g., a set of left vertices denoted by circles and a set of right vertices denoted by rectangles in protograph 611) to represent an array (e.g., the parity-checking array 611). A system according to some implementations (e.g., communication system 105 or 108) can use a code with a block length of 1944 as its base code (e.g., a protograph 611 and the corresponding (parity-checking) array 612).The system can elevate (e.g., copy) the base code by 2 (e.g., a protograph 621 and a (parity-checking) matrix 622 corresponding to protograph 621). The system can (1) permute / move / shift / migrate the edges of a protograph (e.g., from protograph 621 to protograph 631; equivalently permute columns of matrix 622 to obtain matrix 632); and / or (2) remove 4 cycles (and possibly all short cycles) from the protograph (for example, protographs 631 and a corresponding (parity-check) array 632 for protographs 631) to obtain a protograph 641. For example, as shown in Figure 6A, the cycle represented by a subarray 633 in a protograph 631 can be removed in the corresponding protograph 641 by array 642 (see subarray 643).Similarly, the cycle represented by a submatrix 634 in the protograph 631 can be eliminated in the protograph 641 corresponding to matrix 642 (see submatrix 644). In some implementations, the system can generate / define / design / create (as a design goal) code that represents a protograph with a waist > 6. The "waist" of an undirected graph can refer to the length of the shortest cycle contained within the graph. In some implementations, the system can generate / define / design / create (as a design goal) code corresponding to a protograph with a waist > 10. For example, as shown in Figure 6A, protograph 631 (and its corresponding (parity-checking) matrix 632) has a waist of 4, while protographs 641 and 651 (and their corresponding (parity-checking) matrix 642) each have a waist greater than 6. In some implementations, the system can add and / or remove edges to increase performance without increasing the waist.For example, edges can be added and / or removed from the parity checking matrix 642, to increase throughput without increasing the waist of the protographs 641, 651 (or the waist of their corresponding (parity checking) matrix 642). Figure 6B is a diagram 650 representing an example parity-check matrix of a QC-LDPC code, according to one or more embodiments. In some implementations, a system according to certain implementations (e.g., communication system 105 or 108) can obtain the parity-check matrix 642 of the new code (see Figure 6), which is the same as the parity-check matrix 762, by embedding 2x2 binary arrays in the original parity-check matrix H (e.g., parity-check matrix 612 as the base code). For example, the system can (1) substitute an element "1" in the original parity-check matrix 612 by a 2x2 binary identity matrix; and / or (2) further modify the substituted identity matrix. For example, after embedding 2x2 binary identity matrices, the system can modify some of the embedded 2x2 binary identity matrices, resulting in the modified binary matrices 651, 652 that correspond to modified edges in the corresponding protograph. In some implementations, a system (e.g., communication system 103, 108) may include one or more processors (e.g., one or more 2010 processors) configured to select, based on a first size (e.g., 1944 bits) and a code rate of 5 / 6, a codebook from a plurality of codebooks for a QC-LDPC code. The first size may be a code block size resulting from encoding a block of information, and the code rate may be a ratio of an information block size to the first size. The one or more processors may be configured to generate a first parity check matrix (e.g., parity check matrix 612 in Figure 6A) based on at least the codebook. For example, the first parity check matrix may correspond to a block length of 1944 bits and a code rate of 5 / 6.One or more processors can generate, using two instances of the first parity check matrix (for example, two instances of parity check matrix 612 in Figure 6A), a second parity check matrix (for example, parity check matrix 642 in Figure 6A) corresponding to a second size and code rate. The second size can be twice the first size. For example, the second parity check matrix might correspond to a block length of 3888 bits and a code rate of 5 / 6. In some implementations, the system can generate the second parity-check matrix using a first protograph corresponding to the first parity-check matrix (e.g., protograph 611). The system can (1) lift (e.g., copy) the first protograph by 2 (e.g., lift protograph 611 by 2 to create protograph 631); and / or (2) permute / move / shift / migrate the edges of the lifted protograph (e.g., protograph 631) to eliminate one or more short cycles of the lifted protograph, resulting in a second protograph (e.g., protograph 651) such that the waist of the second protograph is greater than 6 (or greater than 10). In some implementations, the system can also add one or more edges to the second protograph, or remove one or more edges from it, without increasing the waist of the protograph.The second protograph (or a protograph as a result of further edge addition / removal) may correspond to the second parity check matrix (e.g., parity check matrix 642). In some implementations, the system can generate the second parity check matrix by embedding 2x2 binary matrices in the first parity check matrix. For example, as shown in Figure 6B, the system can replace each element of the first parity check matrix that has a value of "1" with a 2x2 binary matrix (e.g., a 2x2 binary identity matrix), and / or further modify the replaced binary matrix (e.g., modified binary matrices 651, 652), thus obtaining the second parity check matrix (e.g., parity check matrix 642). Figures 7A, 7B, 7C, and 7D are diagrams representing example code for concurrent decoding, according to one or more implementations. Figure 7A is a diagram 700 representing example submatrix structures, according to one or more implementations. There can be four different graph representations (or protographs) 701, 702, 703, 704 and corresponding submatrix structures 711, 712, 713, 714, respectively. In a submatrix structure, an element (i, j) (entry) of the submatrix indicates whether there is an edge between the j-th column (e.g., vertex v1 or v1 in Figure 7A) and the i-th row (e.g., vertex c1 or c1 in Figure 7A). For example, the submatrix structure 712 indicates that (1) there is no edge between v1 and c1; (2) there is no edge between v1 and c1; (2) there is one edge between v1 and c1; and (2) there is one edge between v1 and c1. Figures 7B, 7C, and 7D are diagrams 720, 740, and 760, representing example code for concurrent decoding, according to one or more implementations. LDPC codes, according to some implementations, allow concurrent decoding using two decoders, each processing 1944-bit blocks simultaneously. Figure 7B shows a 720 protograph indicating edges between a first set of vertices (e.g., {v1, v1, v2, v2, v3, v3, v4, v4}) and a second set of vertices (e.g., {c1, c1, c2, c2, c3, c3}). Figure 7C shows a 740 matrix (e.g., the parity-checking matrix) corresponding to the protograph 720. A system according to some implementations (e.g., the 108 communication system) can obtain the 740 matrix from the protograph 720 using the mapping between protographs and corresponding submatrix structures shown in Figure 7A. Referring to Figure 7D, diagram 760 shows an example of concurrent decoding by decoder 1 (761) and decoder 2 (762), such that the two decoders can perform two block runs of 1944 (as two layers) concurrently. In some implementations, the two decoders can be implemented in a single decoder of a communication system (for example, decoder 160 of communication system 108). For example, the first block run might correspond to a first subgraph 770 of protograph 720, indicating edges between the set of vertices {v1, v2, v3, v4} and the set of vertices {c1, c2, c3}. The second block execution may correspond to a second subgraph 780 of the protograph 720, which indicates edges between the set of vertices {v1, v2, v3, v4} and the set of vertices {c1, c2, c3}.In some implementations, the two decoders 761 and 762 can perform interlayer messaging that passes through connected edges between the two subgraphs of the protograph 720 (e.g., connected edges in part 763, connected edges in part 764). The connected edges in parts 763 and 764 correspond to 2x2 circulating matrices 741 and 742 of matrix 740 (see Figure 7C), respectively. In this case, a circulating matrix can refer to a square matrix in which all rows are composed of the same elements and each row is rotated one element to the right relative to the previous row. The system can perform this concurrent decoding because of (or by using) the submatrix structure (e.g., 2x2 circulating matrices 741 and 742).In some implementations, the 2x2 embedding can be changed for performance, without affecting concurrent decoding, since it is a fixed edge mapping between the two decoding layers. Figure 8 is a flowchart showing a process 800 for encoding data using an LDPC code, according to one embodiment. In some implementations, process 800 is performed by one or more processors (for example, communication system 105, encoder 130, or processor 2010). In other embodiments, process 800 is performed by other entities. In some implementations, process 800 includes more, fewer, or different stages than those shown in Figure 8. In stage 802, one or more processors may determine a QC-LDPC code that has a plurality of codebooks (e.g., codebook 1 or codebook 2) embedded within it. In some implementations, each codebook in the plurality of codebooks may include a plurality of integers (e.g., P1, 1, P1, 2, P1, 3, ..., P1, ; P2, 1, P2, 2, P2, 3, ..., P2, ;..., P1, 1, P1, 2, P1, 3, ..., P, as shown in Equation 7), the number of integers in the plurality being equal to the number of elements in the parity-check matrix divided by z, where z is an integer representing a QC-LDPC code size elevation (e.g., Z=162). See equation 5 and equation 6. In some implementations, each codebook in the codebook plurality (e.g., codebook 1 or codebook 2) can represent an exponent array (e.g., the array 300) of the parity-checking array (e.g., the array 500). Each element of the exponent array can correspond to a cyclic shift value of an identity array. The size of the identity array can be z x z, and the cyclic shift value d can be an integer such as -1d. <z, donde z es un número entero que representa tamaño de elevación del código qc-ldpc. el valor desplazamiento cíclico d puede representar una matriz identidad desplazada se obtiene desplazando hacia la derecha en (véase figura 4 cuando z="7)" . -1 nula 409 4) . In some implementations, the code block size can be 3888 bits, and the code rate can be 5 / 6. The plurality of codebooks can include a first codebook and a second codebook. The first codebook (codebook 1) may include [2896161134914915611531057512.- 1 98146631491474.- 12.- 1 -1138127148114128156114130143310.- 112.- 113618961241095.- 1 0 0 -110432116049528510890144143181347.- 111.- 15.- 1107.- 100335873838911411975 1014.- 1131813110.- 1.- 1146105.- 1-10]. The second codebook (codebook 2) may include [2796160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114 130133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. In stage 804, one or more processors can select a codebook from a plurality of codebooks based on a code block size (e.g., n=3888) and a code rate (e.g., R=5 / 6). In stage 806, one or more processors can generate a parity check matrix (e.g., parity check matrix 500) based on the codebook (e.g., codebook 1 or codebook 2). In some implementations, when generating the parity check matrix based on the selected codebook, one or more processors can also generate an exponent matrix (e.g., matrix 300) based on the selected codebook.For each element of the exponent matrix, one or more processors can generate a shifted identity matrix from an identity matrix (e.g., matrices 410, 411, 412, 413, 414, 415, 416) based on a value for each element of the exponent matrix (e.g., d=0, 1, 2, 3, 4, 5, 6). The one or more processors can generate the parity check matrix such that the parity check matrix includes, as the corresponding element for each element of the exponent matrix, the generated shifted identity matrix (see Equation 8). In stage 808, one or more processors can encode data using the generated parity check matrix (e.g., using equation 10, equation 11, equation 12, and equation 13). In stage 810, one or more processors can transmit, through a transmitter of the apparatus (for example, the transmitter circuit set 120 of communication system 105), the encoded data to another apparatus (for example, communication system 108). In one approach, an apparatus may include a transmitter (for example, communication system 105 of transmitter circuit set 120) and one or more processors (for example, encoder 130, or communication system 105 of processor 2010). The one or more processors may be configured to identify (for example, identify / select from a codebook), based on a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix (for example, parity check matrix H) for a QC-LDPC code. The first binary parity check matrix may correspond to a first exponent matrix (for example, exponent matrix P=E(H)) having 96 values.One or more processors can be configured to encode data using the first binary parity check matrix (e.g., using equation 10, equation 11, equation 12, and equation 13). One or more processors can then be configured to transmit the encoded data. For example, the first device (e.g., communication system 105) can transmit the encoded data to a second device (e.g., communication system 108). In some implementations, one or more processors may be further configured to generate the first exponent array by selecting at least 94 values ​​from a second exponent array that has the same dimensions as the first exponent array (e.g., 4x24; 4 rows and 24 columns). In some embodiments, the first exponent array may be generated by one or more processors of the first device (e.g., encoder 130 of communication system 105). In some embodiments, the first exponent array may be generated by another device (e.g., a device other than communication system 105) and transmitted to the first device. The one or more processors can further be configured to shift (or perturb) one or two values ​​from the first exponent array by -1 or +1 from one or more corresponding positive values ​​in the second exponent array. The corresponding positive values ​​in the second exponent array cannot be selected as the at least 94 values. In some implementations, the second exponent matrix may include the following set of values: [2896161134914915611531057512.- 198146 631491474.- 12.- 1 -1138127148114128156114130143310.- 112.- 113618961241095.- 10.- 1 10432116049528510890144143181347.- 111.- 15.- 1107.- 1003358738389114119751014.- 1 131813110.- 1.- 1146105.- 1 -10]. The first exponent matrix (for example, the permutation matrix P) can be generated by perturbing one or two values ​​from the second exponent matrix.For example, based on the second matrix of exponents, the first matrix can be generated as [27961601349149 15611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130143310.- 112.- 1 136189612410955-10.- 110432116049528510890144143181347.- 111.- 15.- 1107.- 1003358 738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10] in which the first value 27 and the third value 160 are shifted from 28 and 161, respectively. In some implementations, the second exponent matrix may include the following set of values: [27 96160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 100 33587383 89113119751004.- 1131813110.- 1.- 11461052-1 -10]. For example, based on the second matrix of exponents, the first matrix can be generated as [28961601349148 15601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130133310.- 112.- 1 13618961241095.- 10.- 110331116048518410889143143181347.- 111.- 15.- 1107.- 10033 58738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10] in which the first value 28 and the fourth value 134 are shifted from 27 and 133, respectively. In some implementations, the first binary parity-check matrix (e.g., matrix H) can be generated using the first exponent matrix (e.g., P). For example, the first binary parity-check matrix (e.g., matrix H) can be generated by expanding the exponent matrix P such that each element of the exponent matrix P (as a shift value d) is replaced by a matrix (e.g., a Z x Z matrix; Z = 162) shifted from an identity matrix (e.g., the identity matrix Z x Z; Z = 162) by the shift value. In some implementations, one or more processors can be further configured to identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted. The second binary parity check matrix can have the same dimensions as the dimensions of the first binary parity check matrix. For example, the second binary parity check matrix can be generated by permuting a first and a second column of the first binary parity check matrix. The second binary parity check matrix can have the same dimensions as the dimensions of the first binary parity check matrix (for example, m x n; n = 3888; m = n(1 - 5 / 6) = 648). In some implementations, one or more processors can also be configured to encode data using the second binary parity check matrix. In some implementations, one or more processors can be further configured to identify a third binary parity-check matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted. The second exponent matrix can have the same dimensions as the first exponent matrix (for example, 4x24; 4 rows and 24 columns). For example, the second exponent matrix can be generated by permuting the first and second columns of the first exponent. The one or more processors can be configured to encode data using this third binary parity-check matrix. In some implementations, one or more processors can be further configured to generate the first binary parity-check matrix (e.g., matrix H) using (1) a matrix product of the first binary parity-check matrix and the first exponent matrix (e.g., H x P), or (2) a matrix product of the first exponent matrix and the first binary parity-check matrix (e.g., P x H). For example, matrix H can be generated by multiplying (on the right) the matrix product H x P by an inverse matrix of the first exponent matrix (e.g., P-1). In one approach, a device (e.g., communication system 108) may include a receiver (e.g., receiver circuitry set 140) configured to receive encoded data, and one or more processors (e.g., processor 2010). The one or more processors may be configured to identify (e.g., identify / select from a codebook), based on a 5 / 6 code rate and a 3888-bit code block size, a first binary parity check matrix (e.g., parity check matrix H) for a QC-LDPC code. The first binary parity check matrix may correspond to a first exponent matrix (e.g., exponent matrix P=E(H)) having 96 values. In some implementations, before receiving the encoded data, the second device may identify the first binary parity check matrix.In some implementations, in response to or after receiving the encoded data, one or more processors on the second device can identify (for example, identify / select from a codebook) the first binary parity check array. The processors can then be configured to decode the received encoded data using this first binary parity check array. For example, the encoded data (e.g., the codeword c) can be decoded to obtain information bits s using Equation 1 and Equations 10-13. In some implementations, the first exponent matrix may include the following set of values: [28 96161134914915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130 143310.- 112.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 1 5.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10]. In some implementations, the first exponent matrix may include the following set of values: [27 96160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. In some implementations, the first exponent matrix may include at least 94 values ​​selected from a second exponent matrix that has the same dimensions as the first exponent matrix (e.g., 4x24; 4 rows and 24 columns). The first exponent matrix may include one or two values ​​shifted (or perturbed) from one or more corresponding positive values ​​in the second exponent matrix by -1 or +1. The corresponding positive values ​​in the second exponent matrix cannot be selected as the at least 94 values. In some implementations, the second exponent matrix may include the following set of values: [2896161134 9 14915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130143310.- 1 12.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 15.- 1107.- 10 033 58738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10].The first exponent matrix (for example, the permutation matrix P) may include one or two perturbed values ​​from the second exponent matrix. For example, the first matrix might include the following set of values: [27961601349149 15611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130143310.- 112.- 1 13618961241095.- 10.- 110432116049528510890144143181347.- 111.- 15.- 1107.- 1003358 738389114119751014.- 1131813110.- 1.- 1146105.- 1-10] in which the first value 27 and the third value 160 are shifted from 28 and 161, respectively. In some implementations, the second exponent matrix may include the following set of values: [27 96160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. The first exponent matrix (for example, the permutation matrix P) may include one or two perturbed values ​​from the second exponent matrix. For example, the first matrix might include the following set of values: [28 96160134914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1-10] in which the first value 28 and the fourth value 134 are shifted from 27 and 133, respectively. In some implementations, one or more processors can be configured to identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted. The second binary parity check matrix can have the same dimensions as the first binary parity check matrix. For example, the second binary parity check matrix might correspond to a matrix in which the first and second columns of the first binary parity check matrix are permuted. The second binary parity check matrix can have the same dimensions as the first binary parity check matrix (for example, m x n; n = 3888; m = n(1 - 5 / 6) = 648).In some implementations, one or more processors can be configured to decode the received encoded data using the second binary parity check matrix (e.g., using Equation 1 and Equations 10-13). In certain scenarios, the parity-check matrix H can be created / calculated / computed / generated / obtained through a hierarchical elevation process. This hierarchical elevation process may involve generating smaller matrices by applying a cyclic shift of varying sizes (such as Z / 2, Z / 4, etc.). These smaller matrices can then be selectively grouped together to form the equivalent matrix H. Figure 9 is a flowchart showing a process 900 for encoding and / or decoding data using an LDPC code, according to one embodiment. In some implementations, process 900 is performed by one or more processors (e.g., encoder 130 or processor 2010) of a first device (e.g., communication system 105) or by one or more processors (e.g., decoder 160 or processor 2010) of a second device (e.g., communication system 108). In other embodiments, process 900 is performed by other entities. In some implementations, process 900 includes more, fewer, or different stages than those shown in Figure 9. In stage 902, one or more processors of the first device can identify (for example, identify / select from a codebook), based on a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix (for example, parity check matrix H) for a quasicyclic low-density parity check code (QC-LDPC). The first binary parity check matrix can correspond to a first exponent matrix (for example, exponent matrix P=E(H)) having 96 values. In some implementations, the first exponent array can be generated by selecting at least 94 values ​​from a second exponent array that has the same dimensions as the first exponent array (e.g., 4x24; 4 rows and 24 columns). In some embodiments, the first exponent array can be generated by one or more processors of the first device (e.g., encoder 130 of communication system 105). In some embodiments, the first exponent array can be generated by another device (e.g., a device other than communication system 105) and transmitted to the first device. In some implementations, one or two values ​​in the first exponent matrix can be shifted (or perturbed) from one or more corresponding positive values ​​in the second exponent matrix by -1 or +1. The one or more corresponding positive values ​​in the second exponent matrix cannot be selected as the at least 94 values. In some implementations, the second exponent matrix may include the following set of values: [2896161134914915611531057512.- 198146631491474.- 12.- 1 -1 138127148114128156114130143310.- 112.- 113618961241095.- 10.- 1104321160495285108 90144143181347.- 111.- 15.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146 105 2 -1 -1 0]. The first exponent matrix (for example, the permutation matrix P) can be generated by perturbing one or two values ​​from the second exponent matrix.For example, based on the second matrix of exponents, the first matrix can be generated as [2796160134914915611531057512.- 198 146631491474.- 12.- 1 -1138127148114128156114130143310.- 112.- 113618961241095.- 10 0 -110432116049528510890144143181347.- 111.- 15.- 1107.- 100335873838911411975101 4.- 1131813110.- 1.- 1146105.- 1 -10] in which the first value 27 and the third value 160 are shifted from 28 and 161, respectively. In some implementations, the second exponent matrix may include the following set of values: [27 96160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 100 33587383 89113119751004.- 1131813110.- 1.- 11461052-1 -10]. For example, based on the second matrix of exponents, the first matrix can be generated as [28961601349148 15601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130133310.- 112.- 1 13618961241095.- 10.- 110331116048518410889143143181347.- 111.- 15.- 1107.- 10033 58738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10] in which the first value 28 and the fourth value 134 are shifted from 27 and 133, respectively. In some implementations, the first binary parity-checking matrix (e.g., matrix H) can be generated using the first exponent matrix (e.g., P). For example, the first binary parity-checking matrix (e.g., matrix H) can be generated by expanding the exponent matrix P such that each element of the exponent matrix P (as a shift value d) is replaced by a matrix (e.g., a Z x Z matrix; Z = 162) shifted from an identity matrix (e.g., the identity matrix Z x Z; Z = 162) by the shift value. In some implementations, the first binary parity check matrix (e.g., matrix H) can be generated using (1) a matrix product of the first binary parity check matrix and the first exponent matrix (e.g., H x P), or (2) a matrix product of the first exponent matrix and the first binary parity check matrix. In some embodiments, the first binary parity check matrix can be generated by one or more processors of the first device (e.g., P x H). For example, matrix H can be generated by multiplying (on the right) the matrix product H x P by an inverse matrix of the first exponent matrix (e.g., P⁻¹). In stage 904, one or more processors of the first device can encode data using the first binary parity check matrix (for example, using equation 10, equation 11, equation 12, and equation 13). In some implementations, a second binary parity check matrix can be identified in which one or more columns of the first binary parity check matrix are permuted. For example, the second binary parity check matrix can be generated by permuting a first column and a second column of the first binary parity check matrix. The second binary parity check matrix can have the same dimensions as the dimensions of the first binary parity check matrix (for example, m x n; n = 3888; m = n(1 - 5 / 6) = 648).In some implementations, one or more processors of the first device can encode data using the second binary parity checking array. In some implementations, a third binary parity-check matrix can be identified, corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted. The second exponent matrix can have the same dimensions as the first exponent matrix (for example, 4x24; 4 rows and 24 columns). For example, the second exponent matrix can be generated by permuting the first and second columns of the first exponent. In some implementations, one or more processors of the first device can encode data using the third binary parity-check matrix. In stage 906, one or more processors of the first device can transmit the encoded data. For example, the first device (e.g., communication system 105) can transmit the encoded data to a second device (e.g., communication system 108). In stage 908, one or more processors of the second device (e.g., decoder 160 of communication system 108) can identify the first binary parity check matrix. For example, one or more processors of the second device can identify (e.g., identify / select from a codebook), based on a code rate of 5 / 6 and a code block size of 3888 bits, the first binary parity check matrix (e.g., parity check matrix H) for the QC-LDPC code. The first binary parity check matrix can correspond to the first exponent matrix (e.g., exponent matrix P=E(H)) that has 96 values. In stage 910, one or more processors of the second device may receive the encoded data from the first device. In some implementations, before receiving the encoded data in stage 910, one or more processors of the second device may identify the first binary parity check array in stage 908. In some implementations, in response to or after receiving the encoded data, one or more processors of the second device may identify (for example, identify / select from a codebook) the first binary parity check array. In some implementations, the first exponent matrix may include at least 94 values ​​selected from a second exponent matrix that has the same dimensions as the first exponent matrix (e.g., 4x24; 4 rows and 24 columns). The first exponent matrix may include one or two values ​​shifted (or perturbed) from one or more corresponding positive values ​​in the second exponent matrix by -1 or +1. The corresponding positive values ​​in the second exponent matrix cannot be selected as the at least 94 values. In some implementations, the second exponent matrix may include the following set of values: [2896161134 9 14915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130143310.- 1 12.- 113618961241095.- 10.- 110432116049528510890144143181347.- 111.- 15.- 1107.- 10 033 58738389114119751014.- 1131813110.- 1.- 1146105.- 1 -10].The first exponent matrix (for example, the permutation matrix P) may include one or two perturbed values ​​from the second exponent matrix. For example, the first matrix might include the following set of values: [27961601349149 15611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114130143310.- 112.- 1 13618961241095.- 10.- 110432116049528510890144143181347.- 111.- 15.- 1107.- 10033 58738389114119751014.- 1131813110.- 1.- 1146105.- 1-10] in which the first value 27 and the third value 160 are shifted from 28 and 161, respectively. In some implementations, the second exponent matrix may include the following set of values: [27 96160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -10]. The first exponent matrix (for example, the permutation matrix P) may include one or two perturbed values ​​from the second exponent matrix. For example, the first matrix might include the following set of values: [28 96160134914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155114130 133310.- 112.- 113618961241095.- 10.- 110331116048518410889143143181347.- 111.- 1 5.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1-10] in which the first value 28 and the fourth value 134 are shifted from 27 and 133, respectively. In stage 912, one or more processors of the second device can decode the encoded data using the first binary parity-check matrix. For example, the encoded data (e.g., the codeword c) can be decoded to obtain information bits s using equation 1, and equations 10-13. In some implementations, one or more processors can be configured to identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted. The second binary parity check matrix can have the same dimensions as the first binary parity check matrix. For example, the second binary parity check matrix might correspond to a matrix in which the first and second columns of the first binary parity check matrix are permuted. The second binary parity check matrix can have the same dimensions as the first binary parity check matrix (for example, m x n; n = 3888; m = n(1 - 5 / 6) = 648).In some implementations, one or more processors can be configured to decode the received encoded data using the second binary parity check matrix (e.g., using Equation 1, and Equations 10-13). Figures 10A, 10B, 10C, 10D, 10E, and 10F are diagrams representing example simulation results using QC-LDPC codes at a 5 / 6 code rate, according to one or more implementations. The results were obtained with the following simulation settings. Per-packet error rate (PER) values ​​are averaged across 5,000–10,000 independent channel implementations, referencing gains at PER = 1%. A channel instance spans four orthogonal frequency-division multiplexing (OFDM) symbols. Channel models include (1) "DNLOS," indicating a non-line-of-sight 802.11 Type D MIMO channel model; (2) "BLOS," indicating a line-of-sight 802.11 Type B channel model; and (3) AWGN, indicating a flat channel with additive white Gaussian noise. Radio frequency (RF) degradations are not included.The payload size remains the same; and the number of codewords can therefore scale inversely with q for block length = 1944q. Decoding is performed using a belief propagation (BP)-based decoder (e.g., using layered scheduling, with a maximum of 20 iterations). The 2x2 MIMO channels use a near-optimal maximum probability detector of reduced complexity. The 1x1 SISO (single-in, single-out) channels use a linear detector. Figures 10A, 10C, and 10E are diagrams showing PER for different SNRs; ​​and Figures 10B, 10D, and 10F show the spectral efficiency (SpecEff) for different SNRs, respectively. PER refers to the number of packets with errors divided by the total number of packets received. SpecEff refers to an information rate (or bit rate or effective data transmission rate) over a given bandwidth in a communication system (in the unit of bits / second / Hz). SpecEff can be a normalized transmission rate such that the actual transmission rate (bits / second) = SpecEff x bandwidth (Hz). Figures 10A and 10B show simulation results with a flat (frequency) channel, AWGN. Referring to Figure 10A, lines 1001, 1003, 1005, and 1007 correspond to simulation results (PER vs. SNR) using LDPC codes with a block length of 3888 using 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM modulations, respectively; and lines 1002, 1004, 1006, and 1008 correspond to simulation results using LDPC with a block length of 1944 using 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM modulations, respectively.Referring to Figure 10B, lines 1011, 1013, 1015, 1017 correspond to simulation results (SpecEff vs SNR) using LDPC codes with a block length of 3888 using 64-QAM, 256-QAM, 1024-QAM, 4096-QAM modulations, respectively; and lines 1012, 1014, 1016, 1018 correspond to simulation results using LDPC codes with a block length of 1944 using 64-QAM, 256-QAM, 1024-QAM, 4096-QAM modulations, respectively. Figures 10C and 10D show simulation results for a 2x2 MIMO channel with D-NLOS signal propagation. Referring to Figure 10C, lines 1021, 1023, 1025, and 1027 correspond to simulation results (PER vs. SNR) using LDPC codes with a block length of 3888 using 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM modulations, respectively; and lines 1022, 1024, 1026, and 1028 correspond to simulation results using LDPC with a block length of 1944 using 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM modulations, respectively.Referring to Figure 10D, lines 1031, 1033, 1035, 1037 correspond to simulation results (SpecEff vs SNR) using LDPC codes with a block length of 3888 using 64-QAM, 256-QAM, 1024-QAM, 4096-QAM modulations, respectively; and lines 1032, 1034, 1036, 1038 correspond to simulation results using LDPC codes with a block length of 1944 using 64-QAM, 256-QAM, 1024-QAM, 4096-QAM modulations, respectively. Figures 10E and 10F show simulation results for a 2x2 MIMO channel with BLOS signal propagation. Referring to Figure 10E, lines 1041, 1043, 1045, and 1047 correspond to simulation results (PER vs. SNR) using LDPC codes with a block length of 3888 using 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM modulations, respectively; and lines 1042, 1044, 1046, and 1048 correspond to simulation results using LDPC with a block length of 1944 using 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM modulations, respectively.Referring to Figure 10F, lines 1051, 1053, 1055, 1057 correspond to simulation results (SpecEff vs SNR) using LDPC codes with a block length of 3888 using 64-QAM, 256-QAM, 1024-QAM, 4096-QAM modulations, respectively; and lines 1052, 1054, 1056, 1058 correspond to simulation results using LDPC codes with a block length of 1944 using 64-QAM, 256-QAM, 1024-QAM, 4096-QAM modulations, respectively. References to "or" can be interpreted inclusively, so any term described using "or" can indicate any of a single term, more than one term, or all of the terms described. References to "at least one" from a conjunctive list of terms can be interpreted as an inclusive "or" to indicate any of a single term, more than one term, or all of the terms described. For example, a reference to "at least one of A and B" can include only A, only B, or both A and B. Such references used in conjunction with "comprising" or other open terminology can include additional elements. The term "coupled" and variations thereof include the joining of two elements directly or indirectly to each other. The term "electrically coupled" and variations thereof include the joining of two elements directly or indirectly to each other through conductive materials (e.g., metal or copper traces). Such a joining (for both terms "coupled" and "electrically coupled") may be stationary (e.g., permanent or fixed) or movable (e.g., removable or detachable). Such a joining (for both terms "coupled" and "electrically coupled") may be achieved by the two elements being coupled directly to each other, by the two elements being coupled to each other using a separate intermediate element and any additional intermediate elements coupled together, or by the two elements being coupled to each other using an intermediate element that is formed as a single unitary body with one of the two elements.If "coupled" or variations thereof are modified by an additional term (e.g., directly coupled), the generic definition of "coupled" provided above is modified by the plain language meaning of the additional term (e.g., "directly coupled" means the joining of two elements without any independent intermediate elements), resulting in a more restricted definition than the generic definition of "coupled" provided above. Such coupling may be mechanical, electrical, or fluidic. The foregoing describes features of various embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to accomplish the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not fall outside the scope of this disclosure. It should be noted that certain passages in this discussion may refer to terms such as "first" and "second" in connection with strips, data blocks, data rows, and devices, for the purpose of identifying or differentiating them from one another. These terms are not intended merely to relate entities (e.g., a first device and a second device) temporally or sequentially, although in some cases, these entities may include such a relationship. Nor do these terms limit the number of possible entities that may operate within a system or environment. It should be understood that the systems described above may provide multiples of any or all of these components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system.Furthermore, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embedded on or within one or more manufactured items, such as a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or magnetic tape. The programs may be implemented in any programming language, such as LISP, PERL, C, C++, C#, or any bytecode language such as JAVA. The software programs or executable instructions may be stored on or within one or more manufactured items as object code. Although the preceding written description of the methods and systems enables a person skilled in the art to perform and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the embodiment, method, and specific examples in this document. Therefore, the methods and systems presented herein should not be limited to the embodiments, methods, and examples described above, but rather encompass all embodiments and methods within the scope of this disclosure.

Claims

1. A method comprising: identifying, by one or more processors of a first device according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasicyclic low-density parity check code (QC-LDPC), the first binary parity check matrix corresponding to a first exponent matrix having 96 values; encoding (904), by one or more processors of the first device, data using the first binary parity check matrix; transmitting (906), by one or more processors of the first device, the encoded data; characterized in: generating the first exponent matrix by selecting at least 94 values ​​from a second exponent matrix having the same dimensions as the dimensions of the first exponent matrix; the second exponent matrix comprising the following set of values,writing the set of values ​​by rows in the second exponent matrix: [2796160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155 114130133310.- 112.- 113618961241095.- 10.- 11033111604851841088914314318134 7.- 111.- 15.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -1 0].

2. Method according to claim 1, further comprising: shifting one or two values ​​of the first exponent array from one or more corresponding positive values ​​of the second exponent array by -1 or +1, and / or wherein the one or more corresponding positive values ​​of the second exponent array are not selected as the at least 94 values.

3. Method according to claim 1 or 2,in which the second exponent matrix comprises the following set of values: [2896161134914915611531057512.- 198146631491474.- 12.- 1 -1138127148114128156114 130143310.- 112.- 113618961241095.- 10.- 110432116049528510890144143181347.- 1 11.- 15.- 1107.- 1003358738389114119751014.- 1131813110.- 1.- 1146105.- 1-10].

4. A method according to any preceding claim, further comprising: identifying a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as the dimensions of the first binary parity check matrix; and encoding data using the second binary parity check matrix by one or more processors.

5. A method according to any preceding claim,further comprising: identifying a third binary parity check matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted, the second exponent matrix having the same dimensions as the dimensions of the first exponent matrix; and encoding data using the third binary parity check matrix by one or more processors.

6. A method according to any preceding claim, further comprising: generating the first binary parity check matrix using (1) a matrix product of the first binary parity check matrix and the first exponent matrix, or (2) a matrix product of the first exponent matrix and the first binary parity check matrix.

7. A method according to any preceding claim, further comprising: identifying, by a second device,the first binary parity check matrix; receiving, by the second device from the first device, the encoded data; and decoding, by the second device, the encoded data using the first binary parity check matrix.

8. Apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify, according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasicyclic low-density parity check code (QC-LDPC),the first binary parity check matrix corresponds to a first exponent matrix having 96 values; encoding data using the first binary parity check matrix; transmitting the encoded data; characterized by: generating the first exponent matrix by selecting at least 94 values ​​from a second exponent matrix having the same dimensions as the dimensions of the first exponent matrix; comprising the second exponent matrix the following set of values, the set of values ​​being written by rows in the second exponent matrix: [2796160133914815601521057512.- 198146631491474.- 12.- 1 -1138126148113128155 114130133310.- 112.- 113618961241095.- 10.- 11033111604851841088914314318134 7.- 111.- 15.- 1107.- 1003358738389113119751004.- 1131813110.- 1.- 1146105.- 1 -1 0].

9. Apparatus according to claim 8,wherein the one or more processors are further configured to: shift one or two values ​​of the first exponent array from one or more corresponding positive values ​​of the second exponent array by -1 or +1, and / or wherein the one or more corresponding positive values ​​of the second exponent array are not selected as the at least 94 values.

10. Apparatus according to any one of claims 8 to 9, wherein the one or more processors are further configured to: identify a second binary parity check array in which one or more columns of the first binary parity check array are permuted, the second binary parity check array having the same dimensions as the dimensions of the first binary parity check array; and encode data using the second binary parity check array.

11. Apparatus according to any one of claims 8 to 10,wherein one or more processors are further configured to: identify a third binary parity check matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted, the second exponent matrix having the same dimensions as the dimensions of the first exponent matrix; and encode data using the third binary parity check matrix.

12. System comprising: a transmitter according to any one of claims 8 to 11; a receiver configured to receive encoded data; and one or more processors configured to: identify, according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasicyclic low-density parity check code (QC-LDPC),the first binary parity check matrix corresponds to a first exponent matrix with 96 values; and decode the encoded data received using the first binary parity check matrix.

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