Encoding and decoding an LDPC code

Abstract

This application describes an encoding method, apparatus, communications device, and communications system. The method includes encoding an input bit sequence using a low-density parity LDPC array, where the basis graph of the LDPC array is represented by an array of m rows and n columns, m being an integer greater than or equal to 5 and n being an integer greater than or equal to 27; the basis graph includes at least one submatrix A and one submatrix B; submatrix A is an array of five rows and 22 columns; and submatrix B is an array of five rows and five columns, including a column with weight 3 and a submatrix B' with a bidiagonal structure. According to the encoding method, apparatus, communications device, and communications system described in this application, the encoding requirements for information bit sequences of multiple lengths can be supported.

Description

Encoding and decoding an LDPC code Technical field The products described in this application relate to the field of communications and, in particular, to an information processing method and a communications apparatus. Background Low-density parity-check (LDPC) code is a type of linear block code with a sparse check matrix, characterized by a flexible structure and low decoding complexity. Because LDPC code decoding uses a partially parallel iterative decoding algorithm, it offers superior performance compared to conventional turbo codes. LDPC codes can be used as error-correcting codes in communication systems to improve channel transmission reliability and energy efficiency. LDPC codes could find wider applications in space communications, fiber optic communications, personal communication systems, ADSL, magnetic recording devices, and similar applications. Currently, LDPC is considered one of the channel coding modes used in fifth-generation mobile communications. In real-world applications, LDPC arrays characterized by different special structures can be used. An LDPC array H, characterized by a special structure, can be obtained by expanding a base LDPC array that has a quasi-cycle (QC) structure. QC-LDPC is suitable for hardware with high parallelism and provides higher performance. It is possible to design an LDPC array suitable for channel coding. R1-1704250 discloses a nested family of QC-LDPC codes obtained from a high-rate basis matrix having a quasi-row orthogonal structure. R1-1700518 discloses a matrix structure H for the LDPC code. The matrix form would be as follows: where A represents the high-rate code matrix, O the zero matrix, C and I for the matrix of the SPC code, and I is the identity matrix. Figure 1 shows the conceptual structure of the proposed LDPC code. R1-1701473 discloses a compact LDPC design in the form of a low triangular structure or double diagonal structure. R1-1704457 discloses a compact, multi-codebook integrated QC-LDPC design, wherein the base matrix comprises five submatrices (A, B, C, D, E), A corresponding to the system bits, B being square and corresponding to the parity bits. In addition, row non-orthogonal (non-RO), quasi-RO, and pure RO matrices are integrated into a single base matrix. R1-1705419 discloses a proto-array for code rate 8 / 9, which has 4 rows and 20 columns. Compendium The embodiments of this application provide an information processing method, a communications apparatus, and a communications system, to support the encoding and decoding of information bit sequences of a plurality of lengths and to meet the flexible code length and rate requirements of a system. Aspects of the present invention are defined in the independent claims. Additional embodiments are defined in the dependent claims. Parts of the description and drawings not covered by the claims are presented not as embodiments of the present application, but as useful examples for understanding the present application. According to a first aspect, an encoding method and an encoder are provided, and the encoder encodes an input sequence using a low-density parity-check matrix LDPC. According to a second aspect, a decoding method and a decoder are provided, and the decoder decodes an input sequence using a low-density parity-check matrix (LDPC). In a first implementation of either the first or second aspect, a base graph of the LDPC matrix is ​​represented by a matrix of m rows and n columns, where m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27. The base graph includes at least one submatrix A and one submatrix B. Submatrix A is a matrix of five rows and 22 columns. Submatrix B is a matrix of five rows and five columns, and submatrix B includes a column whose weight is 3 and a submatrix B' with a bidiagonal structure. In submatrix A, one column has a weight of 5, one column has a weight of 4, and the other 20 columns have a weight of 3. In submatrix B, one column has a weight of 3 and three columns have a weight of 2. Building on the previous implementation, submatrix B further includes a column with a weight of 1. In a second implementation of either the first or second aspect, a base graph of the LDPC matrix is ​​represented by a matrix of m rows and n columns, where m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27. The base graph includes at least one submatrix A and one submatrix B. Submatrix A is a matrix of five rows and 22 columns; and submatrix B is a matrix of five rows and five columns. In a matrix that includes submatrix A and submatrix B, one column has a weight of 5, one column has a weight of 4, 21 columns have a weight of 3, three columns have a weight of 2, and one column has a weight of 1. Optionally, in the matrix containing submatrix A and submatrix B, one row has a weight greater than or equal to 1 and less than or equal to 5, and four other rows have weights greater than or equal to 17 and less than or equal to 21. For example, in the matrix containing submatrix A and submatrix B, one row has a weight of 3, and the other four rows have a weight of 19. In this case, the matrix containing submatrix A and submatrix B can include rows or columns in a five-row matrix block comprising row 0 to row 4 and column 0 to column 26 in a 30a base graph. The rows can be interchanged, as can the columns. For example, in the matrix block that includes submatrix A and submatrix B in the 30a base graph, row 3 and row 0, row 2 and row 1, and column 23 and column 25 can be swapped to obtain a central matrix in an 80a base graph. Based on the above implementations, a part that is in a base matrix of the LDPC matrix and that corresponds to submatrix A and submatrix B can be represented, for example, by any of the base matrices 30b-1, 30b-2, 30b-3, 30b-4 and 30b-5, and 30b-6, 30b-7, 30b-8, 30b-9 and 30b-10. A part that is in a basis matrix of the LDPC matrix and that corresponds to submatrix A and submatrix B can be represented by a matrix obtained by performing a permutation of columns, a permutation of rows or a permutation of rows and columns in any of the basis matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9 or 30b-10. For example, the part that is in the base matrix of the LDPC matrix and that corresponds to submatrix A and submatrix B may include rows or columns in any of the base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9 or 30b-10.Based on the previous implementations, a part that lies in a basis matrix of the LDPC matrix and corresponds to submatrices A and B can be represented by any of the basis matrices 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, or 80b-6. 80b-4 is a matrix obtained by performing row and column permutations in 30b-3, 80b-5 is a matrix obtained by performing row and column permutations in 30b-4, and 80b-6 is a matrix obtained by performing row and column permutations in 30b-5. To support different block lengths, an LDPC code requires different Z-lift factors. Based on previous implementations, one possible implementation uses basis arrays corresponding to different Z-lift factors. For example, If the lift factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, a part that lies in a basis matrix of the basis graph 30a and that corresponds to submatrix A and submatrix B may be the basis matrix 30b-1 shown in FIG.3b; or If the lift factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B may be the 30b-2 basis matrix shown in FIG.3b; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B may be the 30b-3 basis matrix shown in FIG.3b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B may be the 30b-4 basis matrix shown in FIG.3b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be the 30b-5 basis matrix shown in FIG.3b. In another possible implementation, If the lift factor Z is one of {24, 26, 28, 30}, a part that lies in a basis matrix of the basis graph 80a and that corresponds to submatrix A and submatrix B may be the basis matrix 80b-1 shown in FIG.8b; or If the lift factor Z is one of {32, 36, 40, 44}, a part that lies in a basis matrix of the basis graph 80a and that corresponds to submatrix A and submatrix B may be the basis matrix 80b-2 shown in FIG.8b; or If the lift factor Z is one of {48, 52, 56, 60}, a part that lies in a basis matrix of the basis graph 80a and that corresponds to submatrix A and submatrix B may be the basis matrix 80b-3 shown in FIG. 8b; or If the lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, a part that lies in a basis matrix of the basis graph 80a and that corresponds to submatrix A and submatrix B may be the basis matrix 80b-4 shown in FIG.8b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that lies in a basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B may be the 80b-5 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that lies in a basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be the 80b-6 basis matrix shown in the figure. In another possible implementation, submatrix A may also include two columns of embedded punch bits. Furthermore, to obtain a flexible code rate, a submatrix C, a submatrix D, and a submatrix E of corresponding sizes can be added depending on a central matrix, to obtain different code rates. The submatrix C is a matrix of zeros with five rows and mD columns; The submatrix D is a matrix of mD rows and 27 columns; the submatrix E is an identity matrix with mD rows and mD columns; and mD is an integer and 0mD41. The submatrix D includes mD rows in a matrix F, the matrix F has 41 rows and 27 columns, and the weights of the rows in the matrix F are respectively 7, 7, 9, 8, 7, 7, 8, 6, 6, 5, 6, 5, 5, 6, 5, 5, 5, 5, 4, 4, 4, 5, 4, 5, 4, 4, 4, 4, 3, 4, 4, 4, 4, 3, 3, 4, 4, 3, 3, 3, 4, 4, 3, 3, 3 and 4. In one possible implementation, the matrix F is a matrix that includes row 5 to row 45 and column 0 to column 26 in the 30a base graph. In a possible implementation, a displacement matrix of the matrix F can be represented by any of the basis matrices 30c-1, 30c-2, 30c-3, 30c-4 or 30c-5. In another possible implementation, rows 17 and 19 of the base-30a graph can be interchanged, and columns 39 and 41 can be interchanged, to obtain the matrix of the base-80a graph shown in Figure 8a. For another example, submatrix D includes mD rows in matrix F. A row permutation may not be performed among the mD rows, or a row permutation may be performed among one or more of the mD rows, and submatrix E still retains a diagonal structure. For example, submatrix D includes mD rows in matrix F, rows 12 and 14 in matrix F are interchanged, and submatrix E still retains a diagonal structure, to obtain the base-80a graph. To support different block lengths, an LDPC code requires different Z-raise factors. Based on previous implementations, one possible implementation uses basis arrays corresponding to different Z-raise factors. For example, in one possible implementation, If the lift factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, the submatrix D in the basis matrix can include mD rows in a shift matrix as shown in 30c-1; or If the lift factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, the submatrix D in the basis matrix can include mD rows in a shift matrix as shown in 30c-2; or If the lift factor Z is one of the following: {60, 64, 72, 80, 88, 96, 104, 112, 120}, the submatrix D of the basis matrix may include mD rows in a shift matrix as shown in 30c-3; or if the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the submatrix D in the basis matrix may include mD rows in a shift matrix as shown in 30c-4; or If the lift factor Z is one of {256, 288, 320, 352, 384}, the submatrix D in the basis matrix can include mD rows in a shift matrix shown in 30c-5. In another possible implementation, a set of lift factors may be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If the lift factor Z is one of {24, 26, 28, 30}, the shift matrix of matrix F can be shown in 80c-1; or If the lift factor Z is one of the following: {32, 36, 40, 44}, the shift matrix of matrix F can be shown in 80c-2; or If the lift factor Z is one of the following: {48, 52, 56, 60}, the shift matrix of matrix F can be shown in 80c-3; or If the lift factor Z is one of the following: {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of matrix F can be shown in 80c-4; or If the lift factor Z is one of the following: {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of matrix F can be shown in 80c-5; or If the lift factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of matrix F can be shown in 80c-6. The base graph and the base matrix of the LDPC matrix in the first implementation can meet the performance requirements of code blocks whose block lengths are from 352 to 8448 bits. Based on any of the above aspects or their possible implementations, the method further includes: determining a lift factor Z. For example, a value for the lift factor Z is determined based on the length K of the input sequence. For example, if the length of the input sequence is K, a minimum value for the lift factors that satisfy 22*ZK can be determined from a plurality of lift factors defined in a system. For a communications device at a transmitting end, encoding an input sequence using an LDPC array includes: encoding the input sequence using an LDPC array corresponding to the Z-raise factor. For a communications device at a receiving end, encoding an input sequence using an LDPC array includes: decode the input sequence using an LDPC matrix corresponding to the Z-raise factor. Based on any of the above aspects or possible implementations thereof, in another possible implementation, the base array of the LDPC matrix may be stored in memory. Based on any of the above aspects or possible implementations thereof, in another possible implementation, the base graph of the LDPC matrix is ​​stored in memory, and the offset values ​​of the non-zero elements in the base array of the LDPC matrix may be stored in memory. Based on the above possible implementations, in one possible design, at least one of a base graph and a base matrix for LDPC encoding or decoding is obtained by performing a row permutation, or a column permutation, or a row and column permutation on at least one of the base graphs and the base matrix of the LDPC matrix. According to a third aspect, a communications apparatus is provided, and the apparatus may include software modules and / or hardware components configured to perform any of the possible implementations of the first aspect in the design of the above method. In one possible design, the communications apparatus provided in the third aspect includes the encoder described in the first aspect, a determination unit, and a processing unit. The determination unit is configured to determine a Z-raise factor required to encode an input sequence. The processing unit is configured to encode the input sequence using an LDPC array corresponding to the Z-raise factor. Optionally, the communications apparatus also includes a transceiver, and the transceiver is configured to send a signal corresponding to encoded information data. According to a fourth aspect, a communications device is provided, and the device may include a module configured to perform any of the possible implementations of the second aspect in the design of the previous method. The module may be software and / or hardware. In one possible design, the communications apparatus provided in the fourth aspect includes the decoder described in the second aspect, an acquisition unit, and a processing unit. The acquisition unit is configured to acquire soft values ​​of an LDPC code and a Z-ratio. The processing unit is configured to decode the soft values ​​of the LDPC code based on a base matrix HB corresponding to the Z-ratio, to obtain a sequence of information bits. The communications apparatus further includes a transceiver, and the transceiver is configured to receive a signal that includes an LDPC code. According to a fifth aspect, a communications apparatus is provided, which includes one or more processors. In one possible design, one or more processors may implement encoder functions from the first aspect. In another possible design, the encoder from the first aspect may be part of the processor, and the processor may implement functions other than those of the encoder from the first aspect. In one possible design, one or more processors may implement decoder functions from the second aspect. In another possible design, the decoder from the second aspect may be part of the processor. Optionally, the communications apparatus may also include a transceiver and an antenna. Optionally, the communications apparatus may also include a component configured to generate a transport block CRC, a component used for code block segmentation and CRC checking, an interleaver used for interleaving, a modulator used for modulation processing, or similar components. Optionally, the communications apparatus may also include a demodulator used for demodulation, a deinterlaceer used for deinterlacing, a component used for speed mismatching, or similar components. The functions of these components may be implemented by one or more processors. In a possible design, the functions of these components can be implemented by one or more processors. According to a sixth aspect, an implementation of the present application provides a communications system, and the system includes the communications apparatus described in the third aspect and the communications apparatus described in the fourth aspect. According to a seventh aspect, an implementation of the present application provides a communications system, and the system includes one or more communications apparatuses described in the fifth aspect. According to another aspect, an embodiment of the present application provides a computer storage medium, wherein the computer storage medium stores a program, and when the program is executed, it causes a computer to perform the methods described in the preceding aspects. According to another aspect of this application, a computer program product is provided that includes an instruction. When the instruction is executed on a computer, it causes the computer to perform the methods described in the preceding aspects. According to the information processing method, the apparatus, the communications device, and the communications system in the embodiments of this application, the requirements of flexible code length and code speed of a system can be met in terms of coding performance and an error floor. Brief description of the drawings FIG. 1 shows schematic diagrams of a base graph, a base matrix, and circular permutation matrices of an LDPC code; FIG.2 is a schematic structural diagram of a base chart of an LDPC code; FIG.3a is a schematic diagram of a base chart of an LDPC code according to an embodiment of the present application; FIG. 3b shows schematic diagrams of basis matrices of an LDPC code according to an embodiment of the present application; FIG. 3c shows schematic diagrams of basis matrices of an LDPC code according to another embodiment of the present application; FIG. 4 is a schematic performance diagram provided by an implementation of the present application; FIG. 5 is a schematic performance diagram provided by another embodiment of the present application; FIG.6 is a schematic block diagram of an information processing apparatus according to an embodiment of the present application; FIG.7 is a schematic block diagram of a communications system according to an embodiment of the present application; FIG. 8a is a schematic diagram of a base chart of an LDPC code according to another embodiment of the present application; FIG. 8b shows schematic diagrams of basis matrices of an LDPC code according to yet another embodiment of the present application; FIG. 8c shows schematic diagrams of basis matrices of an LDPC code according to yet another embodiment of the present application; FIG. 9 is a schematic performance diagram of an LDPC code according to an embodiment of the present application; FIG. 10 is a schematic performance diagram of an LDPC code according to another embodiment of the present application; FIG. 11a is a schematic diagram of a base chart of an LDPC code according to yet another embodiment of the present application; FIG. 11b is a schematic diagram of a base matrix based on the LDPC code base graph provided in FIG. 11a; and Figure 12 is a schematic diagram of a base chart according to another embodiment of the present application. Detailed description of the embodiments To facilitate understanding, some terms used in this application are described below. In this application, the terms "network" and "system" are often used interchangeably, and "apparatus" and "device" are also often used interchangeably. The meaning of these terms is understood by those skilled in the art. A "communication apparatus" may refer to a chip (such as a baseband chip, a digital signal processing chip, or a general-purpose chip, etc.), a terminal, a base station, or any other network device. A terminal is a device that has a communication function. It can be a portable device, a vehicle-mounted device, a wearable device, a computer, or any other processing device connected to a wireless modem and equipped with wireless communication capabilities. The terminal may be called by different names on different networks, such as user equipment, mobile station, subscriber unit, station, cell phone, personal digital assistant, wireless modem, wireless communications device, handheld device, laptop, cordless phone, and wireless local loop station. For simplicity, these devices are referred to simply as terminals in this application. A base station (BS), also called a base station device, is a device deployed in a radio access network to provide wireless communication functions. Base stations may be called by different names in different wireless access systems. For example, a base station in a Universal Mobile Telecommunications System (UMTS) network is called a NodeB, a base station in an LTE network is called an evolved NodeB (eNB or eNodeB), and a base station in a new radio (NR) network is called a transmission reception point (TRP) or next-generation NodeB (gNB). Base stations in other networks may be called by other names. This is not limited to the scope of this application. The following describes technical solutions in the implementations of this application with reference to the attached drawings. An LDPC code can be represented by a parity-check matrix H. The parity-check matrix code H can be obtained using a base graph and a shift value. The base graph is an m x n matrix and includes m x n matrix elements (also called entries). The value of each matrix element is either 0 or 1. An element whose value is 0 is called a zero element, which can be replaced by a Z x Z matrix of zeros (zero matrix). An element whose value is 1 is called a non-zero element, which can be replaced by a Z x Z circular permutation matrix (circular permutation matrix). That is, each element of the base graph represents either a matrix of zeros or a circular permutation matrix.10a in FIG. Figure 1 shows elements of an example base chart of an LDPC code with a QC structure, where m=4 and n=20. It should be noted that, in this descriptive report, the row and column indices of the base charts and matrices are numbered starting from 0, and this is simply for ease of description. For example, column 0 indicates the first column in a base chart or matrix, and column 1 indicates the second column in the base chart and matrix; row 0 indicates the first row in the base chart and matrix, row 1 indicates the second row in the base chart and matrix, and so on. It can be understood that row and column indices can be numbered alternatively starting from 1, and in this case, the row and column indices shown in this specification are incremented by 1 to obtain the corresponding row and column indices. For example, if row or column indices are numbered from 1, column 1 indicates the first column in a base chart and matrix, and column 2 indicates the second column in the base chart and matrix; row 1 indicates the first row in the base chart and matrix, row 2 indicates the second row in the base chart and matrix, and so on. If the value of an element in row i and column j of the base graph is 1, and it is assigned a shift value Pi, j, where Pi, j is an integer greater than or equal to 0, then the element whose value is 1 in row i and column j of the base graph is replaced by a circular permutation matrix Z*Z corresponding to Pi, j. The circular permutation matrix corresponding to Pi, j is equal to a matrix obtained by circularly shifting an identity matrix of size Z*Z to the right Pi, j times. Each element of the base graph whose value is 0 is replaced by a matrix of zeros of size Z*Z, and each element whose value is 1 is replaced by a circular permutation matrix of size Z*Z corresponding to a shift value of the element, to obtain the parity-check matrix of the LDPC code.The positions of the shift values ​​can be indicated on the base graph, and a nonzero element in the base graph corresponds to the shift value. Z is a positive integer, the lifting factor, or sometimes called the lifting size or lifting factor. Z can be determined based on the code block sizes that a system supports and the size of the information data. Note that the parity-checking matrix H has a size of (m*Z) * (n*Z). For example, if the lifting factor Z is 4, each zero element is replaced by a 4*4 array of zeros 11a. If P2, 3 is 2, a nonzero element in row 2 and column 3 of the base graph is replaced by a 4*4 circular permutation matrix 11d, and the matrix 11d is obtained by circularly shifting a 4*4 identity matrix 11b twice to the right.If P2, 4 is 0, a nonzero element in row 2 and column 4 is replaced by the identity matrix 11b. It should be noted that only examples are described in this paper, and that these do not constitute a limitation. The value of Pi,j can depend on the Z-raise factor. For an element in the base graph whose value is 1 in the same position, Pi,j can be different for different Z-raise factors. For ease of implementation, an m × n basis matrix can be defined. The elements of the basis matrix are in one-to-one correspondence with the elements of the base graph. A zero element in the base graph has the same position in the basis matrix, and the element is denoted by -1. A nonzero element in row i and column j, whose value is 1 in the base graph, has the same position in the basis matrix; the element can be denoted by Pi,j, where Pi,j is a positive integer greater than or equal to 0. In this implementation of the application, the basis matrix is ​​sometimes also called the base graph matrix shift matrix. FIG.1 shows a basis 10b matrix corresponding to the basis 10a graph. Typically, the LDPC code base chart or base matrix can also include p columns of embedded punch bits (embedded punch), where p can be an integer from 0 to 2. These columns can be used in the encoding, but the system bits corresponding to the columns are not sent. An LDPC code base matrix code rate is given by R = (nm) / (np). If a base matrix of four rows and 20 columns (4*20) includes two columns of embedded punch bits, the code rate is (20-4) / (20-2) = 8 / 9. An LDPC code used in a wireless communication system is a QC-LDPC code, and a portion of the parity bits in the QC-LDPC code has a bidiagonal or raptor-like structure, simplifying the encoding and supporting hybrid incremental redundancy replay. A QC-LDPC shift network (QSN), a Banyan network, or a Benes network is typically used in a QC-LDPC code decoder to implement cyclic information shifting. A base graph of the QC-LDPC code with the raptor-type structure is a matrix with m rows and n columns, and the base graph can generally include five submatrices: A, B, C, D, and E. The weight of a matrix is ​​determined by the number of nonzero elements. The row weight is the number of nonzero elements in a row, and the column weight is the number of nonzero elements in a column. The following is shown in Figure 2. A submatrix A is a matrix of mA rows and nA columns, and the submatrix A has a size of mA*nA. Each column corresponds to Z system bits in the LDPC code, and a system bit is sometimes called an information bit. A submatrix B is a square matrix of mA rows and mA columns, and the submatrix B has a size of mA*mA. Each column corresponds to the parity bits Z in the LDPC code. The submatrix B includes a submatrix B' with a bidiagonal structure and a matrix column whose weight is 3 (weight 3 column, for short), and the weight 3 column is on the left side of the submatrix B', as shown in 20a in FIG. 2. The submatrix B may further include a matrix column whose weight is 1 (weight 1 matrix column), which may be located in the first or last column of the submatrix B, and a nonzero element in the weight 1 matrix column is located in the last row of the submatrix B, so that the weight of the last row of the submatrix B is 1, as shown in 20b or 20c in FIG.2. Generally, an array generated from subarray A and subarray B is a core array, which can be used to support high code rate coding. A submatrix C is a matrix of zeros and the submatrix C has a size of mA× (n- (mA+ nA) ) . A submatrix E is an identity matrix, and the submatrix E has a size of (m - mA) × (m - mA) . A submatrix D has a size of (m - mA) × (nA+ mA) , and the submatrix D can be used to generate parity bits for a low code rate. It can be understood that the basis graph is expressed mathematically, and because C is a matrix of zeros and E is an identity matrix, in a possible implementation, one can use a matrix that includes submatrix A and submatrix B, or a matrix that includes submatrix A, submatrix B and submatrix D to simply represent a basis graph of a matrix to encode or decode. Because the structures of subarray B, subarray C, and subarray E are relatively specified, the structures of subarray A and subarray D are one of the factors that affect the encoding and decoding performance of the LDPC code. When using a raptor-structured LDPC array for encoding, in one possible implementation, the portion of the array that includes subarrays A and B—that is, the central array—is first encoded to obtain one or more parity bits corresponding to subarray B. Subsequently, the entire array is encoded to obtain one or more parity bits corresponding to subarray E. Since subarray B may include the bidiagonal subarray B' and a matrix column of weight 1, during encoding, one or more parity bits corresponding to the bidiagonal structure are obtained first, and then one or more parity bits corresponding to the matrix column of weight 1. The following is an example of an encoding implementation. Assuming the core matrix containing submatrix A and submatrix B is H_core, a matrix column of weight 1 and a row containing a nonzero element are removed from H_core to obtain a dual-core matrix H_core. The portion of the dual-core H_core for parity bits is represented by He = [He1 He2], where He1 is a matrix column of weight 3 and He2 has a bidiagonal structure. According to an LDPC code matrix definition, dual-core H_core[S Pe]T = 0, where S is an input sequence and is a vector containing information bits, Pe is a vector containing parity bits, and [S Pe]T denotes a transposed matrix containing the input sequence S and Pe. Therefore, the parity bits corresponding to the dual core H can be calculated first based on the input sequence S and the dual core H, where the input sequence S includes all the information bits.Next, the parity bits corresponding to the weight 1 column of submatrix B are calculated based on the parity bit obtained from the dual core H and the input sequence S. In this case, all the parity bits corresponding to submatrix B can be obtained. After that, the parity bits corresponding to submatrix E are obtained by encoding using submatrix D and based on the input sequence S and the parity bits corresponding to submatrix B, to obtain all the information bits and all the parity bits. A sequence comprising all the information bits and all the parity bits obtained by performing the encoding is called an LDPC code sequence. Optionally, LDPC encoding can also include a shortening operation and a puncturing operation. The shortened bits and the punctured bits are not sent. Shortening is generally performed starting from the last bit of information and can be done in different ways. For example, if the number of bits shortened is s0, the last s0 bits in the input sequence S can be set to known bits, such as 0, null, or another value, to obtain an input sequence S', and then the input sequence S' is encoded using an LDPC array. Alternatively, the last (s0 mod Z) bits of the input sequence S can be set to known bits, such as 0, null, or another value, to obtain an input sequence S', and the last S0 Z columns of submatrix A are removed to obtain an LDPC matrix H', and the input sequence S' is encoded using the LDPC matrix H', or the last s0 Z columns of submatrix A do not participate in the encoding of the input sequence S'. After encoding, the shortened bits are not sent. Punching can be performed on one or more built-in punch bits, or on one or more parity bits in an input sequence. Typically, parity bit punching is also performed starting from the last parity bit. Alternatively, punching can be performed based on a punching pattern preset in the system. In one possible implementation, an input sequence is first encoded, and then, based on a number p of bits to be punched, the last p parity bits are selected, or p bits are selected according to the punching pattern preset in the system, where the remaining p bits are not sent. In another possible implementation, p columns in an array can be determined that correspond to punched bits, and p rows in which non-zero elements are found in these columns, and the rows and columns are not used in the encoding and therefore no corresponding parity bits are generated. It should be noted that the encoding implementation described in this document is used merely as an example. Other encoding implementations known to those skilled in the art, based on the base graph and / or base matrix provided in this application, may be used, and the encoding implementations are not limited here. Decoding in this application can be performed using various decoding methods, for example, a least sum (MS) decoding method or a belief propagation decoding method. The MS decoding method is sometimes called the flooding MS decoding method. For example, an input sequence is initialized, and one or more iterations are performed. Hard decision detection is performed after the iteration(s), and the outcome of a hard decision is checked.If the decoding result satisfies a verification equation, the decoding is successful, an iteration ends, and a decision result is generated. If the decoding result does not satisfy a verification equation, another iteration is performed within a maximum number of iterations, and if the verification still fails when the maximum number of iterations is reached, the decoding fails. The MS decoding principle is understood by those skilled in the art, and the details are not described in this document. It should be noted that the decoding method used in this document is simply as an example; other decoding methods known to experts in the art can be used based on the base graph and / or base matrix provided in this application, and the decoding method is not limited in this application. An LDPC code can be obtained based on a base graph and a base matrix, and an upper performance limit for the LDPC code can be determined by performing a density evolution on the base graph or the base matrix. An error floor for the LDPC code is determined based on an offset value in the base matrix. Improving encoding and decoding performance and reducing the error floor are some of the goals of designing the base graph and base matrix. Code length is flexible in wireless communication systems. A code block can have a short block length, such as 40 bits or 1280 bits, or a long block length, such as 5000 bits or 8448 bits. Figures 3a, 3b, and 3c are examples of a base graph and base matrices for an LDPC code, and the examples can meet a code block performance requirement with a block length of up to 8448 bits. Figures 8a, 8b, and 3c are examples of a base graph and base matrices for an LDPC code.Figure 8c provides examples of a base graph and base matrices from another LDPC code. Figures 11a and 11b provide examples of a base graph and base matrix from another LDPC code. For ease of description and understanding, the row indices and column indices are shown on the top and left sides, respectively, in Figures 3a, 3b, and 3c. Figures 4 and 5 provide schematic diagrams of the performance of the LDPC code shown in Figures 3a and 3c at two different coding speeds. Figure 3a shows an example of a 30a base chart of an LDPC code. In the figure, the numbers 0 through 67 in the top row indicate the column indices, and the numbers 0 through 45 in the left column indicate the row indices. More precisely, the base chart has 46 rows and 68 columns. A submatrix A corresponds to the system bits, has five rows and 22 columns, and includes elements from row 0 to row 4 and from column 0 to column 21 in the base 30a graph. A submatrix B corresponds to parity bits, has five rows and five columns, and includes elements in row 0 to row 4 and column 22 to column 26 in the base 30a graph. Submatrix A and submatrix B form a core matrix in the LDPC code base graph and, specifically, form a matrix of five rows and 27 columns, and can be used for high code rate coding. For example, in the core matrix that includes submatrix A and submatrix B, one column has a weight of 5, one column has a weight of 4, 21 columns have a weight of 3, three columns have a weight of 2, and one column has a weight of 1. Submatrix A may include two columns of built-in punch bits and, after punching, a code rate that can be supported by the central matrix is ​​22 / (27-2) = 0.88. In submatrix A, one column has a weight of 5, another column has a weight of 4, and the other 20 columns have a weight of 3. For example, the weights of the two columns of built-in punch bits may be 5 and 4 respectively. Both the weight of the last row (row 4) and the weight of the last column (column 4 of submatrix B, i.e., column 26 of the basis matrix) of submatrix B are 1. Submatrix B includes a column of weight 3; specifically, the weight of column 0 of submatrix B (column 22 of the basis matrix) is 3. Columns 1 to 3 of submatrix B (columns 23 to 25 of the basis matrix) and rows 0 to 3 of submatrix B form a bidiagonal structure. The central matrix of the base-30a graph includes four rows with a weight of 19 and one row with a weight of 3. The weights of the rows in the central matrix that include submatrix A and submatrix B are 19, 19, 19, 19, and 3. It should be noted that the rows of the central matrix can be interchanged; for example, row 0 and row 2 can be interchanged, as can row 1 and row 3. The row with a weight of 3 can be row 4 in columns 0 through 26 in the central matrix of the base-30a graph, and the rows with a weight of 19 can be row 0 and row 3 in columns 0 through 26 in the central matrix of the base-30a graph. These rows and columns can also be interchanged. For example, column 8 and column 25 of the central matrix can be swapped with each other, and column 10 and column 26 can be swapped with each other.For example, row 3 and row 0 of the central matrix can be interchanged, and row 2 and row 1 can be interchanged. To maintain the bidiagonal structure in submatrix B, columns 23 and 25 can be interchanged to obtain a central matrix in a base 80a graph shown in FIG. 8a—that is, a matrix that includes rows 0 through 5 and columns 0 through 26 in 80a. It should be noted that only examples are provided in this document. In a real-world application, the permutation of rows and columns can be flexibly designed according to system requirements. Table 1 shows an example of column permutation for the base 80a graph. For ease of description, a sequence of 27 columns in the central matrix, obtained by column permutation, is provided in this document. The column indices are the column indices of the matrix after the permutation and are numbered starting from 0. The column indices before the permutation are the column indices of the matrix before the permutation. As shown in Table 1, columns 8 and 10 of the matrix before the permutation are swapped with columns 25 and 26, column 9 of the matrix before the permutation is swapped with column 8, columns 11 to 21 of the matrix before the permutation are swapped with columns 9 to 19, and columns 25 and 26 of the matrix before the permutation are swapped with columns 20 and 21. In this way, the performance of a specific code rate and a specific code length can be improved.For example, FIG. 9 is a schematic diagram of the performance based on the base matrix shown in Table 1. Performance improves in a case of a 2 / 3 code rate, a BLER of 1E-2, and a code length ranging from 672 to 960. FIG. 10 is a schematic diagram of the performance based on the base matrix shown in Table 1. Performance improves in a case of a 2 / 3 code rate, a BLER of 1E-2, and a code length ranging from 1952 to 2624. Table 1 It can be understood that, since rows and columns in a matrix can be interchanged, row permutations do not change the column weights, column permutations do not change the row weights, and the number of nonzero elements remains unchanged. The row weights in the base 80a graph after the row and column permutations are unchanged. The performance of a base graph obtained by performing a row permutation, a column permutation, or a row and column permutation is unaffected. It should be noted that in this application, the fact that performance is not affected means that the impact is acceptable and falls within a tolerable range overall. For example, performance is generally unaffected because, while performance degrades within an acceptable range in some scenarios or time intervals, it improves in other scenarios or time intervals. The central matrix in the base 30a graph and the one in the base 80a graph are used as examples. After performing a row permutation in the base 30a graph, the central matrix in the base 80a graph still includes the columns of the central matrix in the base 30a graph; one row has a weight of 3, and the other four rows have a weight of 19, except that the order of the rows is reversed. If a column permutation is performed in the base 30a graph—for example, by swapping columns 5 and 7—a central matrix from the base 30a graph obtained by performing the column permutation can be found to still include the columns of the central matrix in the base 30a graph. One column has a weight of 5, one column has a weight of 4, 21 columns have a weight of 3, three columns have a weight of 2, and one column has a weight of 1, except that the order of the columns is reversed.It should be noted that what is provided in this report only describes examples, and that these do not constitute a limitation. For a given base graph or base array of an LDPC code, the impact of some changes to the array elements on performance is usually acceptable. For example, in one implementation, some changes can be made based on the core array of base graph 30a. For example, one row has a weight greater than or equal to 1 and less than or equal to 5, and four other rows have weights greater than or equal to 17 and less than or equal to 21, respectively. For example, one row has a weight of 2 and four other rows have a weight of 18; or one row has a weight of 4 and four other rows have weights of 17, 18, 19, and 19, respectively. It can be understood that the weights of some rows can be increased or decreased by 1 or 2 with respect to the solutions provided in this request, and this is not a limitation in this request. Subarray A can also include a row in which the elements other than those in the built-in punch bit columns are zero elements. Furthermore, to minimize the weight of a row in the core array or the base graph array, the row is often the same as a row with a weight of 1 in subarray B. For example, there are two built-in punch bit columns, specifically columns 0 and 1, as shown in base graph 30a or 80a. In row 4, the elements in columns 0 and 1 are nonzero, the elements in columns 2 through 25 are zero, the elements in column 26 are nonzero, and the weight of row 4 is 3. Row 4 has the lowest weight in the core array, and even in the entire base graph array. This configuration can improve encoding and decoding performance. To accommodate different block lengths, the LDPC code requires different Z-lift factors. For example, the Z-lift factor can be one or more of the following values: 16, 18, 20, 22, 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, or 384. To ensure the LDPC code's performance with varying block lengths, base arrays corresponding to different Z-lift factors can be used. FIG. 3b shows a plurality of examples of basis matrices of the central matrix in the basis graph 30a. The basis matrices are obtained from the central matrix in the basis graph 30a and the lifting factor Z.A non-zero element in row i and column j in the base 30a graph has a displacement value Pi, j in row i and column j in the basis matrix, and a zero element in the base 30a graph is represented by -1 or zero in a displacement matrix. In a possible implementation, If the lift factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be shown in a 30b-1 basis matrix in FIG.3b; or If the lift factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be shown in a 30b-2 basis matrix in FIG.3b; or If the lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be shown in a 30b-3 basis matrix in FIG.3b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be shown in a 30b-4 basis matrix in FIG.3b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be shown in a 30b-5 basis matrix in the figure. In another possible implementation, a set of lift factors may be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If the lift factor Z is one of {24, 26, 28, 30}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B may be a 30b-6 basis matrix shown in FIG.3b; or If the lift factor Z is one of {32, 36, 40, 44}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-7 basis matrix shown in FIG.3b; or If the lift factor Z is one of {48, 52, 56, 60}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-8 basis matrix shown in FIG.3b; or If the lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, a part that lies in a basis matrix of the 30a basis graph and corresponds to submatrix A, and submatrix B can be a 30b-3 basis matrix shown in FIG.3b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that lies in a basis matrix of the basis graph 30a and that corresponds to submatrix A and submatrix B may be a basis matrix shown in 30b-4 in FIG.3b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that lies in a basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-5 basis matrix shown in the figure. Based on the previous implementations, in another possible implementation, to further improve performance, the base graph can correspond to more base matrices, and the parts that are in the base matrices of base graph 30a and that correspond to submatrix A and submatrix B can correspond to different base matrices. For example, If the lift factor Z is one of {24, 26, 28, 30}, a part that lies in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-6 basis matrix shown in FIG.3b; or If the lift factor Z is one of {32, 36, 40, 44}, a part that lies in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-7 basis matrix shown in FIG.3b; or If the lift factor Z is one of {48, 52, 56, 60}, a part that lies in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-8 basis matrix shown in FIG.3b; or If the lift factor Z is one of {64, 72, 80, 88}, a part that lies in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-9 or 30b-10 basis matrix shown in FIG.3b; or If the lift factor Z is one of {96, 104, 112, 120}, a part that lies in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B may be a 30b-3 basis matrix shown in FIG.3b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that is in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-4 basis matrix shown in FIG.3b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that is in the basis matrix of the 30a basis graph and that corresponds to submatrix A and submatrix B can be a 30b-5 basis matrix shown in the figure. Figure 8b shows a plurality of examples of basis matrices of the central matrix in the basis graph 80a. The basis matrices are obtained from the central matrix in the basis graph 80a and the lift factor Z. A nonzero element in row i and column j in the basis graph 80a has a displacement value Pi, j in row i and column j in the basis matrix, and a zero element in the basis graph 80a is represented by -1 or zero in a displacement matrix. In another possible implementation, a set of lift factors may be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If the lift factor Z is one of {24, 26, 28, 30}, a part that lies in a basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be an 80b-1 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {32, 36, 40, 44}, a part that lies in a basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be a 80b-2 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {48, 52, 56, 60}, a part that lies in a basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be an 80b-3 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, a part that lies in a basis matrix of the 80a basis graph and corresponds to submatrix A and submatrix B can be a 80b-4 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that lies in a basis matrix of the 80a basis graph and corresponds to submatrix A, and submatrix B can be a 80b-5 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that lies in a basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be a 80b-6 basis matrix shown in the figure. Based on the previous implementations, in another possible implementation, to further improve performance, the base graph can correspond to more base matrices, and the parts that are in the base matrices of base graph 80a and that correspond to submatrix A and submatrix B can correspond to different base matrices. For example, If the lift factor Z is one of {24, 26, 28, 30}, a part that lies in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be an 80b-1 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {32, 36, 40, 44}, a part that lies in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B may be an 80b-2 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {48, 52, 56, 60}, a part that lies in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B may be an 80b-3 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {64, 72, 80, 88}, a part that lies in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be an 80b-7 or 80b-8 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {96, 104, 112, 120}, a part that lies in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B may be an 80b-4 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, a part that is in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be an 80b-5 basis matrix shown in FIG. 8b; or If the lift factor Z is one of {256, 288, 320, 352, 384}, a part that is in the basis matrix of the 80a basis graph and that corresponds to submatrix A and submatrix B can be an 80b-6 basis matrix shown in the figure. In another possible implementation, a part that is in a basis matrix of the base graph 80a and that corresponds to submatrix A and submatrix B may be a basis matrix 80b-9 shown in FIG. 8b. Since the Z lift factors can be classified in various ways, a basis matrix used for a group of Z lift factors may be considered in terms of performance accordingly. For example, a lift factor value Z is determined based on a length K of the input sequence. For instance, if the input sequence length is K, a minimum value for the lift factors that satisfy 22*ZK can be determined from a plurality of lift factors defined in the system and used as the lift factor value for the matrix. Furthermore, a corresponding base matrix can be selected based on the determined lift factor. Table 2 shows an example of the correspondence between a base matrix and a lift factor. A plurality of lift factors defined in the system are classified into eight groups, i.e., eight sets, and the set indices are from 1 to 8. Correspondingly, there are eight base matrices PCM 1 through PCM 8. Table 2 For example, the 80b-9 base array can be used as PCM 8, and in this case, when the Z-raising factor is any of 15, 30, 60, 120, or 240, 80b-9 can be used as the base array. Consequently, the base array is raised using the Z-raising factor to obtain an LDPC parity-checking array. Furthermore, when Z is greater than or equal to 24, the 80b-9 base array has relatively high performance. Similarly, rows and columns can be interchanged in a basis matrix. If at least one permutation of rows or columns is performed in a basis graph, the same permutation will also be performed in a corresponding basis matrix. It can be observed that, in the previous implementations, 80b-1 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-6, 80b-2 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-7, 80b-3 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-8, 80b-4 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-3, 80b-5 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-4, 80b-6 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-5, 80b-7 is a basis matrix obtained by performing a permutation of rows and columns on the basis matrix 30b-9, and 80b-8 is a basis matrix obtained by performing a permutation of rows and a permutation of columns in the base matrix 30b-10. Certainly, it can be understood that the part that is in the base matrix of the LDPC matrix and that corresponds to submatrix A and submatrix B can include rows or columns in any of the base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9 or 30b-10, that is, a matrix obtained by performing a permutation of columns, or a permutation of rows, or a permutation of rows and columns, is performed in any of the base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9 or 30b-10. Furthermore, to achieve flexible coding rates, submatrices C, D, and E of corresponding sizes can be added to a central matrix to obtain different coding rates. Since submatrix C is a matrix of zeros and submatrix E is an identity matrix, their sizes are determined by the coding rates, and their structures are relatively fixed. The central matrix and submatrix D primarily affect encoding and decoding performance. Rows and columns are added based on the central matrix to form the corresponding C, D, and E matrices, thus enabling different coding rates.For example, the central matrix can be the central matrix of the 30a base graph or the central matrix of the 80a base graph, and the corresponding submatrices C, D, and E are added to meet the encoding or decoding requirements for different code rates. The column count of submatrix D is the sum of the column counts of submatrix A and submatrix B, and the row count of submatrix D is primarily related to a code rate. The base graph 30a is used as an example. The number of columns mD of the corresponding submatrix D is (nA + mA) = 27 columns. If a code rate supported by an LDPC code is Rm, the sizes of a base graph or base matrix of the LDPC code are m*n, where n = nA / Rm + p, and m = n - nA = nA / Rm + p - nA. If the minimum coding rate Rm is 1 / 3 and a quantity p of embedded punch bit columns is 2, in the example of the base 30a graph, n=68, m=46, a row count mD of the submatrix D can be up to m- mA=46-5=41, and 0mD41. To simplify the description, a matrix F of 41 rows and 27 columns can be defined. In this case, submatrix D can include mD rows in matrix F, and submatrix D, submatrix A, submatrix B, submatrix C, and submatrix E of corresponding sizes form a base graph of an LDPC code whose code rate is 22 / (25+mD). In base graph 30a, mD=41, and submatrix D has 41 rows and 27 columns, respectively. Specifically, submatrix D is matrix F, and a corresponding code rate supported by the LDPC code is 22 / 66=1 / 3. It can be learned that a matrix including rows 5 through 45 and columns 0 through 26 in base graph 30a is matrix F. The row weights of the matrix F shown in FIG.30a as an example are sequentially 7, 7, 9, 8, 7, 7, 8, 6, 6, 5, 6, 5, 5, 6, 5, 5, 5, 5, 4, 4, 4, 5, 4, 5, 4, 4, 4, 4, 3, 4, 4, 4, 4, 3, 3, 4, 4, 3, 3, 3, 4 and 4. Because the submatrix E is an identity matrix, the row weights in the base 30a graph are 8, 8, 10, 9, 8, 8, 9, 7, 7, 6, 7, 6, 6, 7, 6, 6, 6, 6, 5, 5, 5, 6, 5, 6, 5, 5, 5, 5, 4, 5, 5, 5, 5, 4, 4, 5, 5, 4, 4, 4, and 5. In the present application, if there is at most one non-zero element in two adjacent rows in the same column in a base graph, the two rows are mutually orthogonal. In one possible implementation, matrix F can be a matrix with a quasi-orthogonal structure. In a matrix block that includes columns other than the embedded punch bit columns of matrix F, there is at most only one nonzero element in any two adjacent rows in the same column; that is, the matrix block that includes columns other than the embedded punch bit columns of matrix F has an orthogonal structure. In the base-30a graph example, matrix F is a matrix that includes rows 5 through 45 and columns 0 through 26, and columns 0 and 1 are embedded punch bit columns.In a matrix block that includes rows 5 through 45 and columns 2 through 26, rows 5 and 6 are mutually orthogonal, rows 6 and 7 are mutually orthogonal, rows 23 and 24 are mutually orthogonal, rows 32 and 33 are mutually orthogonal, and so on. If mD=15, the submatrix D in the LDPC code base graph has 15 rows and 27 columns. The submatrix D can be a matrix that includes rows 0 to 14 of matrix F in the base 30a chart, that is, rows 5 to 19 of the base 30a chart and columns 0 to 26. A corresponding code rate supported by the LDPC code is 22 / 40=0.55. At this code rate, the base chart of the LDPC code corresponds to a matrix that includes rows 0 to 19 and columns 0 to 41 in the base 30a chart.The submatrix E is an identity matrix of 15 rows and 15 columns, and the submatrix C is a matrix of zeros of five rows and 15 columns. If mD=19, the submatrix D in the LDPC code base graph has 19 rows and 27 columns. The submatrix D can be a matrix that includes rows 0 through 18 of matrix F in the 30a base graph, that is, rows 5 through 23 of the 30a base graph and columns 0 through 26. A corresponding code rate supported by the LDPC code is 22 / 44=1 / 2. At this code rate, the LDPC code base graph corresponds to a matrix that includes rows 0 through 23 and columns 0 through 41 in the 30a base graph. The E submatrix is ​​a 19-row, 19-column identity matrix, and the C submatrix is ​​a five-row, 19-column zero matrix. The same applies if mD is another value, and the details are not described. It should be noted that rows and columns can be interchanged in the LDPC code's base graph and base matrix. For example, rows 17 and 19 of base graph 30a can be interchanged, and columns 39 and 41 can be interchanged, resulting in the base graph matrix 80a shown in Figure 8a. As another example, submatrix D includes mD rows in matrix F; no row permutation may occur between the mD rows, or it may occur between one or more of them. Submatrix E retains its diagonal structure, with no row or column permutation taking place. For instance, if rows 12 and 14 of matrix F are interchanged, submatrix D includes mD rows in submatrix F, and submatrix E retains its diagonal structure, resulting in base graph 80a.Matrix F is a quasi-orthogonal matrix before the row permutation, and matrix F remains a quasi-orthogonal matrix after the permutation. For example, in the base-80a graph, matrix F is a matrix that includes rows 5 through 45 and columns 0 through 26, with columns 0 and 1 being built-in punch bit columns. In a matrix block that includes rows 5 through 45 and columns 2 through 26, rows 5 and 6 are mutually orthogonal, rows 29 and 30 are mutually orthogonal, and so on. It can be understood that if the base graph or base matrix includes submatrix D, when the columns of the central matrix are swapped, the corresponding columns of submatrix D must also be swapped. For example, if column 23 and column 25 of the central matrix are swapped, then column 23 and column 25 of submatrix D must also be swapped accordingly.This report provides only examples, and these do not constitute a limitation. In the embodiments of the present application, the submatrix D has a quasi-orthogonal structure; specifically, in each column, except for the integrated punch bit columns, there are two adjacent orthogonal rows. For example, in the submatrices D provided in base graphs 30a, 80a, and 170a, and in FIG. 12, according to the embodiments of the present application, columns 0 and 1 are integrated punch bit columns, and in each of the other columns there are two adjacent orthogonal rows. It should be noted that the integrated punch bit columns can be other columns. This is not limited herein. In another possible implementation, the matrix F with the quasi-orthogonal structure can also include at least two orthogonal rows, and there is a maximum of only one nonzero element in each of the columns 0 to 26 in any two adjacent rows between the at least two orthogonal rows. For example, if mD > 30, the corresponding encoding rate supported by the LDPC code is less than 2 / 5, and a submatrix that includes the last 11 rows of matrix F (i.e., rows 30 to 40 and columns 0 to 26) can be orthogonal. Specifically, in matrix F, there is at most a single non-zero element in a column that does not contain embedded punch bits in two adjacent rows between row 0 and 29, and at most a single non-zero element in each of columns 0 to 26 in two adjacent rows between row 30 and 40. For another example, a submatrix that includes rows 26 to 40 and columns 0 to 26 of matrix F may be orthogonal.Specifically, in matrix F, there is at most a single nonzero element in a column other than the integrated punch bits column, in two adjacent rows between rows 0 and 25, and there is at most a single nonzero element in each of columns 0 to 26, in two adjacent rows between rows 26 and 40. In the base graph 170a shown in FIG.11a, matrix F is a matrix that includes rows 5 to 45 and columns 0 to 26 of the base graph, matrix F has a quasi-orthogonal structure, rows 26 to 40 of matrix F are orthogonal, and there is a maximum of only one nonzero element in each column in two adjacent rows between rows 26 and 40. A core array in the 170a base graph is the same as the core array in the 80a base graph. For subarray D at each code rate, changes can be made to one or two non-zero elements or to one or two zero elements in each row without affecting the performance of subarray D. For another example, if mD>20, a submatrix that includes the last 21 rows of matrix F, that is, from row 25 to row 45 of matrix F, and from column 0 to column 26, can be orthogonal. Specifically, in matrix F, there is at most a single nonzero element in a column other than the embedded punch bits column, in any two adjacent rows between rows 0 and 19, and there is at most a single nonzero element in each of the columns 0 to 26, in any two adjacent rows between rows 20 and 40. A central matrix in the 170a base graph shown in FIG. 11a is the same as the central matrix in the 80a base graph. Rows 5 to 45 are in a quasi-orthogonal structure, or rows 5 to 25 are in a quasi-orthogonal structure, and rows 25 to 45 are in a quasi-orthogonal structure. A central matrix in a base graph shown in FIG.12 is the same as the central matrix in base graph 80a, and row 5 to row 45 in the central matrix has a quasi-orthogonal structure. A basis matrix 30c shown in FIG. 3c is an example of a basis matrix of the basis matrix 30a. A nonzero element in row i and column j of the basis matrix 30a has the same position in the basis matrix 30c, and a nonzero element value is a shift value Pi, j. The submatrix D includes mD rows in a shift matrix of matrix F. For the basis matrix 30c shown in FIG. 3c, mD = 41, and mD can be selected based on different code rates. The shift matrix corresponding to the submatrix D is the shift matrix of matrix F. In this document, the shift matrix of matrix F is obtained by replacing a nonzero element in row i and column j of matrix F with a shift value Pi, j, and a zero element is represented by -1 or null in the shift matrix.It should be noted that only examples are provided in this document; the base graph may be 80a, 180a, or similar, and the base graphs are not described one by one in this document. In one possible implementation, the shift matrix of matrix F can include rows or columns in any of the matrices 30c-1 to 30c-10. For example, If a lift factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, the shift matrix of matrix F can be the matrix 30c-1 or a matrix obtained by performing a row / column permutation on the matrix; or if a lift factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, the shift matrix of matrix F can be the matrix 30c-2 or a matrix obtained by performing a row / column permutation on the matrix; or if a lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of matrix F can be the 30c-3 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of matrix F can be the 30c-4 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of matrix F can be the matrix 30c-5 or a matrix obtained by performing a row / column permutation on the matrix. A submatrix D in the base matrix 30c is replaced by mD rows in each shift matrix of matrix F, to obtain base matrices that have different coding rates and correspond to the base graph 30a. If mD=41, a matrix including row 5 to row 45 and column 0 to column 26 in the base matrix 30c is replaced by each shift matrix of matrix F, to obtain each 46-row, 68-column base matrix that corresponds to the base graph 30a. In this case, the coding rate is 1 / 3. In another possible implementation, a set of lift factors may be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If a lift factor Z is one of {24, 26, 28, 30}, the shift matrix of matrix F can be the matrix 30c-6 or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {32, 36, 40, 44}, the shift matrix of matrix F can be the matrix 30c-7 or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {48, 52, 56, 60}, the shift matrix of matrix F can be the 30c-8 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of matrix F can be the 30c-3 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of matrix F can be the 30c-4 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of matrix F can be the 30c-5 matrix or a matrix obtained by performing a row / column permutation on the matrix. Based on the above implementations, in another possible implementation, there are more options for the shift matrix of matrix F to further improve performance. For example, the shift matrix of matrix F can be the 30c-9 matrix or a matrix obtained by performing a row / column permutation on the matrix, or the 30c-10 matrix or a matrix obtained by performing a row / column permutation on the matrix. For example, a lift factor can be designed as follows: If the lift factor Z is one of {24, 26, 28, 30}, the shift matrix of matrix F can be the 30c-6 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {32, 36, 40, 44}, the shift matrix of matrix F can be the matrix 30c-7 or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {48, 52, 56, 60}, the shift matrix of matrix F can be the 30c-8 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {64, 72, 80, 88}, the shift matrix of matrix F can be either the 30c-9 matrix or a matrix obtained by performing a row / column permutation on the matrix, or the 30c-10 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {96, 104, 112, 120}, the shift matrix of matrix F can be the 30c-3 matrix or a matrix obtained by performing a row / column permutation on the matrix; or if the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of matrix F can be the 30c-4 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of matrix F can be the 30c-5 matrix or a matrix obtained by performing a row / column permutation on the matrix. In another possible implementation, the shift matrix of matrix F can include rows or columns in any of the matrices 80c-1 to 80c-9. For example, a set of lift factors might be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If a lift factor Z is one of {24, 26, 28, 30}, the shift matrix of matrix F can be the matrix 80c-1 or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {32, 36, 40, 44}, the shift matrix of matrix F can be the matrix 80c-2 or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {48, 52, 56, 60}, the shift matrix of matrix F can be the matrix 80c-3 or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of matrix F can be the matrix 80c-4 or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of matrix F can be the 80c-5 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If a lift factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of matrix F can be the 80c-6 matrix or a matrix obtained by performing a row / column permutation on the matrix. Based on the above implementations, in another possible implementation, to further improve performance, the lift factors Z can be designed with finer granularity, so that there are more options for the shift matrix of matrix F. For example, the shift matrix of matrix F can be the 80c-7 matrix or a matrix obtained by performing a row / column permutation on the matrix, or the 80c-8 matrix or a matrix obtained by performing a row / column permutation on the matrix. For example, a lift factor can be designed as follows: If the lift factor Z is one of {24, 26, 28, 30}, the shift matrix of matrix F can be the matrix 80c-1 or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {32, 36, 40, 44}, the shift matrix of matrix F can be the matrix 80c-2 or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {48, 52, 56, 60}, the shift matrix of matrix F can be the 80c-3 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {64, 72, 80, 88}, the shift matrix of matrix F can be the matrix 80c-7 or a matrix obtained by performing a row / column permutation on the matrix 80c-7, or the matrix 80c-8 or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {96, 104, 112, 120}, the shift matrix of matrix F can be the 80c-4 matrix or a matrix obtained by performing a row / column permutation on the matrix; or if the lift factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of matrix F can be the 80c-5 matrix or a matrix obtained by performing a row / column permutation on the matrix; or If the lift factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of matrix F can be the 80c-6 matrix or a matrix obtained by performing a row / column permutation on the matrix. In another possible implementation, if the lift factor Z is any of 15, 30, 60, 120, or 240, the shift matrix of matrix F can be the 80c-9 matrix or a matrix obtained by performing a row / column permutation on the matrix. Furthermore, when Z is greater than or equal to 24, the performance of the F shift matrix is ​​relatively high when the shift matrix is ​​80c-9. Similarly, rows and columns can be interchanged in a basis matrix. If at least one permutation of rows or columns is performed in a basis graph, the same permutation will also be performed in a corresponding basis matrix. It can be observed that, in the previous implementations, 80c-1 is a matrix obtained by performing a row permutation in the base matrix 30c-6, 80c-2 is a matrix obtained by performing a row permutation in 30c-7, 80c-3 is a matrix obtained by performing a row permutation in 30c-8, 80c-4 is a matrix obtained by performing a row permutation in 30c-3, 80c-5 is a matrix obtained by performing a row permutation in 30c-4, 80c-6 is a matrix obtained by performing a row permutation in 30c-5, 80c-7 is a matrix obtained by performing a row permutation in 30c-9 and 80c-8 is a matrix obtained by performing a row permutation in 30c-10. A submatrix D in a basis matrix 80c is replaced by mD rows in each shift matrix of matrix F, to obtain basis matrices that have different coding rates and correspond to the basis graph 80a. If mD=41, a matrix including row 5 to row 45 and column 0 to column 26 in the basis matrix 80c is replaced by each shift matrix of matrix F, to obtain each 46-row, 68-column basis matrix that corresponds to the basis graph 80a. In this case, the coding rate is 1 / 3. It should be noted that, because rows and columns can be interchanged with each other in a base graph and a base matrix, in one possible implementation, the core matrix of base graph 30a can be used as the core matrix in the base graph, i.e., a part that includes a submatrix A and a submatrix B, and a submatrix D in the base graph can include mD rows in a matrix that includes row 5 to row 45 and column 0 to column 26 in base graph 30a. Consequently, a central matrix in the basis matrix can be one of 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, or 30b-10, and a corresponding submatrix D can include mD rows in any of the following matrices: 30c-3, 30c-4, 30c-5, 30c-6, 30c-7, 30c-8, 30c-9, or 30c-10. The central matrix and the corresponding submatrix D can be selected based on a lift factor.In another possible implementation, the central matrix in the base graph 80a is used as the central matrix in a base graph, i.e., a part that includes a submatrix A and a submatrix B, and a submatrix D in the base graph can include mD rows in a matrix that includes row 5 to row 45 and column 0 to column 26 in the base graph 80a. Consequently, a core matrix in a basis matrix can be one of 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, 80b-6, 80b-7, 80b-8, or 80b-9, and a corresponding submatrix D can include mD rows in any of the following matrices: 80c-1, 80c-2, 80c-3, 80c-4, 80c-5, 80c-6, 80c-7, 80c-8, or 80c-9. The core matrix and the corresponding submatrix D can be selected based on a lift factor. In another possible implementation, the central matrix of the base graph 80a is used as the central matrix in a base graph, i.e., a part that includes a submatrix A and a submatrix B, and a submatrix D in the base graph can include mD rows in a matrix that includes row 5 to row 45 and column 0 to column 26 in the base graph 170a, as shown in the base graph 170a. Accordingly, a base matrix can include mD rows in row 5 to row 45 and row 0 to row 4 in a base matrix 170b-1 in FIG. 17b. In another possible implementation, the central matrix in the base chart 80a is used as the central matrix in a base chart, and a submatrix D in the base chart may include mD rows in a matrix that includes row 5 to row 45 and column 0 to column 26 in the base chart shown in FIG.12, as shown in FIG. 12. It can be understood that in this application, the quasiortogonal structure is not limited to just two adjacent rows; an array that complies with the quasiortogonal structure can be designed to include a plurality of groups, each group including at least two rows, for example, three rows or four rows, and the rows included in each group are quasiortogonal. In the performance curve diagrams shown in FIG. 5a and FIG. 5b, LDPC 1 indicates that the LDPC code is obtained by encoding based on base matrices corresponding to the base 30a graph, and LDPC 2 indicates a common LDPC code for comparison. A horizontal coordinate indicates the length of a sequence of information bits, and a unit of length is the bit. A vertical coordinate is a symbol's signal-to-noise ratio (SNR / NNR). The performance curves indicate the symbol's signal-to-noise ratio performance for LDPC 1 and LDPC 2 for different lengths of information bit sequences when the BLERs are 0, 01 and 0, 0001, respectively. The code rate R is 8 / 9 in FIG. 5a and 1 / 3 in FIG. 5b.It can be observed that, with the same BLER, the symbol signal-to-noise ratio of LDPC 1 is lower than that of LDPC 2 in cases of different information bit sequence lengths; that is, the performance of LDPC 1 is better than that of LDPC 2. In an encoding method provided in an embodiment of this application, an encoder encodes an input sequence using an LDPC array. A base graph of the LDPC array can be any of the base graphs from the preceding examples, including the center matrix of base graph 80a, and a base HB matrix of the LDPC array can be any base matrix from the respective examples. The encoder's input sequence can be a sequence of information bits, or it can be a sequence of information bits obtained after at least one of the following processing: CRC addition or padding bit insertion. The method also includes determining a lift factor Z. A value for the lift factor Z can be determined based on a length K of the input sequence. Sometimes, the information bit sequence is also called a code block and can be obtained by performing a code block split on a transport block. If the length of the information bit sequence is Kc, a minimum value for the lift factors that satisfy 22*ZKc can be determined from a plurality of lift factors defined in the system. For example, if Kc=3800 and the lift factors defined in the system include 16, 18, 20, 22, 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, and 384, then Z can be determined to be 176. It should be noted that only examples are provided in this document, and these do not constitute a limitation. In one possible design, padding can be performed on the information bit sequence to obtain the input sequence, such that the length of the input sequence is K = Kb · Z, i.e., Z = K / Kb. For example, the padding bit values ​​can be null, 0, or other values ​​agreed upon by the system. After encoding, these padding bits can be identified and are not transmitted, which is not a limitation in this application. That the encoder that encodes the input sequence using the LDPC matrix H may be encoding the input sequence using the LDPC matrix corresponding to the Z-raise factor. In one possible implementation, the input sequence is c = {c0, c1, c2 cK-1}, the length of the input sequence c is K, and an output sequence obtained after the encoder encodes the input sequence c is d = {d0, d1, d2 dN-1}. K is an integer greater than 0, and K can be an integer multiple of the raise factor Z. The output sequence d includes K0 bits in the input sequence cy parity bits in a parity sequence w, K0 is an integer greater than 0 and less than or equal to K, the length of the parity sequence w is N- The parity sequence wy and the input sequence c satisfy formula (1): where is a transposed vector of a vector that includes bits in the input sequence, is a transposed vector of a vector that includes bits in the sequence of parity, 0T is a column vector and the values ​​of all elements of 07 are 0. H is an LDPC matrix obtained according to any basis chart described in the above embodiments, and a basis chart of H has m rows and n columns, and can be any basis chart described in the above embodiments, e.g., 30a, 80a, 170a and FIG.12. In a design, the base graph of H includes p columns of embedded punch bits, where p is an integer greater than or equal to 0. The information bits corresponding to the p columns of embedded punch bits are not output, and the output sequence does not include the information bits corresponding to the p columns of embedded punch bits. In this case, K0 = K - p·Z. For example, if p = 2, K0 = K - 2·Z, and the length of the parity sequence w is N + 2·Z - K. If the p columns of embedded punch bits participate in the encoding, K0 = K, and the length of the parity sequence w is N - K. Consequently, H can have M rows and (N + p·Z) columns or M rows and N columns; the base graph of H has M / Z rows and columns. The base graph of the LDPC H matrix can be represented by represents a matrix of zeros of size mc×nc, and represents an identity matrix of size nc×nc. In a possible design, if 0× is the submatrix C in the base graph in the above realizations, and is the submatrix E in the above realizations, where A, B, and D are respectively the submatrix A, submatrix B, and submatrix D in the base graph in the above realizations, mc=5, 0nc41, n row count of HBG is less than or equal to 46 and greater than or equal to 5, and a column count of HBG is equal to 27. In another possible design, given that column 26 is a column of matrix weight 1 and a nonzero element in column 26 is in row 5, 0× can also include the first four rows of column 26 in the base graph of the previous embodiments and the first four rows in submatrix C of the previous embodiments, and I nc× can also include submatrix E in the base graph of the previous embodiments, rows 5 to 46 of column 26, and a final row in submatrix C, where mc=4, 0nc42, HBG is a matrix obtained after removing a final column from a part that includes submatrix A, submatrix B, and submatrix D in the base graph of the previous embodiments, the number of rows of HBG is less than or equal to 46 and greater than or equal to 5, and the number of columns of HBG is equal to 26. Optionally, if it is necessary to further increase the rate of a The code, HBG can have four rows: row 0 to row 3. Consequently, the LDPC matrix H can be represented by H=[H1 H2]. H1 can be obtained by replacing each zero element in HBG with a Z*Z matrix of zeros and each nonzero element with a Z*Z circular permutation matrix hi, j. The circular permutation matrix hi, j is obtained by circularly shifting the Z*Z identity matrix Pi, j times to the right, and is sometimes represented by I(Pi, j), where i is the row index and j is the column index. In a possible design, Pi, j = mod(Vi, j, Z), and Vi, j is a nonzero element value in row i and column j of a basis matrix corresponding to an index of the set of lifting factors corresponding to Z. H2 can be obtained after replacing each zero element in HBG, EXT with a Z*Z matrix of zeros and replacing each nonzero element with a Z*Z identity matrix. The encoder can perform the encoding and output in a plurality of ways. Any of the base charts shown in FIG. 12, base chart 80a, or base chart 170a described in the preceding embodiment is used as an example for the description below. The base chart has a maximum of 46 rows and a maximum of 68 columns and includes two columns of built-in punch bits. For ease of description, in this application, a base chart having the maximum number of rows and columns is sometimes referred to as the full base chart. Way 1: The encoding is performed based on the complete base graph, so that as many parity bits as possible can be obtained. In this case, m=46 and n=68, which correspond from row 0 to row 45 and from column 0 to column 67 in any of the base graphs above. Therefore, M=46·Z for the LDPC matrix H. If the output sequence includes the information bits corresponding to the built-in punch bit columns, N=68·Z; or if the output sequence does not include the 2·Z information bits corresponding to the built-in punch bit columns, N=66·Z. During subsequent processing, one or more information bits and one or more parity bits can be determined to be sent from the output sequence generated by the encoder. Way 2: The encoding is performed based on certain rows and columns of the complete base graph. A row and a column can be selected, depending on the required encoding rate, the number of information bits, the number of parity bits, or similar parameters, from the complete base graph for encoding. For example, the coding rate is 8 / 9, m=5 and n=27, that is, the coding is done from row 0 to row 4 and column 0 to column 26 in any of the above base charts. Therefore, M=5·Z for the LDPC matrix H. If the output sequence includes the information bits corresponding to the built-in punch bit columns, N=27·Z; or if the output sequence does not include the information bits corresponding to the built-in punch bit columns, N=25·Z. For another example, the code rate is 1 / 3, m=46 and n=68. It can be learned that in this way, the size of the base graph of H satisfies 5 m 46 and 27 n 68, and correspondingly, for the LDPC matrix H, 5·ZM 46·Z and 27·ZN 68·Z. In one possible design, the 26th column in any base chart described above is a weight-1 matrix column, and a punch can be made in the weight-1 matrix column of the core matrix, so that the core matrix is ​​reduced by one row and one column accordingly, ym=4 yn=26. That is, the encoding is performed based on row 0 to row 3 and column 0 to column 25 in any base chart described above. In this way, a higher encoding rate can be obtained. Therefore, the size of the base chart satisfies 4m ≤ 46 and 26n ≤ 68, and correspondingly, for the LDPC matrix H, 4·ZM ≤ 46·Z and 26·ZN ≤ 68·Z. In the prior implementations, the basis matrix HB of the LDPC matrix H can be any basis matrix described in the prior embodiments or a basis matrix obtained by performing a row permutation, a column permutation, or both a row and a column permutation on any basis matrix described above. A basis graph of the basis matrix HB includes at least a submatrix A and a submatrix B, and may further include a submatrix C, a submatrix D, and a submatrix E. For the submatrices, see the descriptions in the prior embodiments, and the details are not described again herein. Certainly, the basis matrix HB can be another basis matrix whose basis graph conforms to the basis graph shown in the prior embodiments, and the basis matrix HB is not limited to this in the present application.In one possible implementation, a base matrix HB of an LDPC code can be stored in memory, and the encoder obtains an LDPC matrix corresponding to a Z-raise factor, to encode the input sequence. In another possible implementation, because there is a plurality of HB base arrays of an LDPC code, and a relatively large storage space is occupied if the HB base arrays are stored according to an array structure, a base graph of the LDPC code can be stored in memory, non-zero element offset values ​​can be stored in each base array by row or by column, and then an LDPC array can be obtained based on the base graph and an offset value in a base array corresponding to a Z-lift factor. The basis graph indicates the position of the nonzero element in each basis array. In another possible implementation, storing a basis graph can consist of storing the position of a nonzero element within the basis graph. The position of the nonzero element can be indicated by a row and a column in which the element is located; for example, the position of a column in which a nonzero element is found in each row, or the position of a row in which a nonzero element is found in each column. In yet another possible implementation, storing a basis graph can consist of storing the position of a zero element within the basis graph.Similarly, the position of the zero element can also be indicated by a row and a column in which the zero element is located; for example, the position of a column in which a zero element is found in each row, or the position of a row in which a zero element is found in each row, and a corresponding position of a non-zero element can be obtained by excluding the position of the zero element. It should be noted that only examples are provided in this document, and these do not constitute a limitation in this application. In a design, parameters related to a base chart or base array can be expressed in a table. For example, related parameters or tables can be stored in one or more memory locations. Related parameters, such as the row index of a base chart or base array, or the column containing a nonzero element, are read from memory to obtain the base chart or base array. Optionally, a weight for each row and an offset value for a nonzero element in each row can also be stored. Figure 11a is used as an example for the description below. For other base graphics or base matrices provided in this application, please refer to similar designs. For example, the central matrix in the 80a base graph, the 170a base graph, or FIG.12 can be expressed in Table 3. Table 3 A base chart of an LDPC matrix includes a core matrix portion shown in Table 3. Another portion of the base chart of the LDPC matrix may be shown in base chart 80a, base chart 170a, or FIG. 12, or another structure described in this application, or another array structure, and this is not limited in this application. Base chart 170a is used as another example. The parameters related to the first 24 rows of the base chart can be shown in Table 4. The parameters related to the remaining rows are similar and are not listed in Table 4 due to space limitations. Table 4 It should be noted that only examples are provided in this document, and these do not constitute a limitation. Related parameters from another base chart or base matrix provided in this application may also be expressed in a similar table. It can be understood that base chart 170a, Table 3, and Table 4 are intended to aid in understanding the design of the base chart and base matrix. A representation is not limited to base chart 170a or a representation in Table 3 or Table 4. Other possible variations may be included. In an implementation, you can use a column index, a column weight, and a row in which there is a non-zero element or a row in which there is a zero element, for example, a form like the one in Table 5. Table 5 In one implementation, the "row weight" or "column weight" parameter can be omitted from Table 3, Table 4, or Table 5. The number of non-zero elements in a row or column can be obtained from a column or row containing a non-zero element. Therefore, a row weight or column weight is also learned. In one implementation, the parameter values ​​in "column indices of non-zero elements in the row" in Table 3 or Table 4 or the parameter values ​​in "row indices of non-zero elements in the column" in Table 5 cannot be sorted in ascending order whenever a column containing a non-zero element or a row containing a non-zero element can be retrieved from the parameter values. In one implementation, Table 3 or Table 4 may also include a column for "non-zero element offset values," and the parameter values ​​in the "non-zero element offset values" column are one-to-one with the parameter values ​​in "non-zero element column indices in the row." Table 5 may also include a column for "non-zero element offset values," and the parameter values ​​in the "non-zero element offset values" column are one-to-one with the parameter values ​​in "non-zero element row indices in the column." In a design, to save storage space, the position of a nonzero element in a relatively fixed-structure part of a base chart can be calculated based on a row index or a column index without storing the position. For example, a submatrix E is a diagonal array and includes nonzero elements only on one diagonal of the array. The position of a column in which a nonzero element is found in submatrix E can be calculated based on a row index, or the position of a row in which a nonzero element is found can be calculated based on a column index. In an example of any of the base charts 80a, 170a, or the base chart in FIG. 12, a column index of a nonzero element in row me is me + Kb, where me ≥ 4 and Kb = 22. For example, a column in which a nonzero element is found in row 7 is column 29.For another example, a bidiagonal structure B' in a submatrix B lies in row 0 to row 3 and column 23 to column 25 in any of the base graphs 80a, 170a, or the base graph shown in FIG. 12. A column index of a column containing a nonzero element in the bidiagonal structure B' can be calculated from a row index, or a row index of a row containing a nonzero element can be calculated from a column index. The positions of nonzero elements in row mB include column mB+Kb and column mB+Kb+1, where 0 <mB<3. La posición de un elemento distinto de cero en la fila mB es la columna mB+Ke, donde mB=0 o mB=3. Por otro ejemplo, para una columna de matriz de peso 1 en una submatriz B, es decir, la columna 26 en cualquiera de los gráficos base 80a, 170a o el gráfico base en la FIG.12, a position of a non-zero element in row mB is column mB+Kb, where mB=4. Table 6 shows the parameters related to the rows in FIG. 12. The positions of the columns containing non-zero elements in columns 0 to 25 can be stored, while the positions of the columns containing non-zero elements in columns 26 to 68 are not stored; that is, the columns containing non-zero elements in the columns of the weight matrix 1 in submatrix E and submatrix B are not stored. Table 6 can be used to represent HBG whose column index is 26. Table 6 Table 7 shows the parameters related to the rows in FIG. 12. The positions of the columns containing non-zero elements in columns 0 to 26 can be stored, while the positions of the columns containing non-zero elements in columns 27 to 68 are not stored; that is, the columns containing non-zero elements in submatrix E are not stored. Table 7 can be used to represent HBG whose column index is 27. Table 7 In the previous designs, the "row weight" column is optional. In one possible design, the 1 and 0 values ​​in each row or column of a base chart can be considered binary numbers, and storing these binary numbers in decimal or hexadecimal format saves storage space. Any of the previous base charts is used as an example. The nonzero positions in the first 26 or 27 columns can be stored as four hexadecimal numbers in each row. For example, if the first 26 columns of row 0 are 11110110011111011011111100, the nonzero positions in row 0 can be denoted as 0xF6, 0x7D, 0xBF, and 0x00. Specifically, every eight columns form one hexadecimal number. The last two or three columns can be filled with 0 to obtain eight digits, thus obtaining the corresponding hexadecimal number.The same is true of another row, and the details are not described again in this memoir. When encoding the information bit sequence, the base matrix HB can be raised to a power of Z to obtain the LDPC matrix H used for encoding. A circular permutation matrix hi, j of size Z*Z is determined for each nonzero element corresponding to Pi, j in the base matrix HB, where hi, j is a circular permutation matrix obtained by circularly shifting an identity matrix Pi, j times. A nonzero element corresponding to Pi, j is replaced by hi, j, and a zero element in the base matrix HB is replaced by a matrix of zeros of size Z*Z, to obtain the parity-check matrix H. In a possible design, for the lift factor Z, Pi, j of an element in row iy column j in the basis matrix HB, it can satisfy a relationship shown in (2): where Vi, j can be a displacement value of an element in row i and column j in a basis matrix of a set of lift factors comprising the lift factor Z, or a displacement value of a non-zero element in row i and column j in a basis matrix corresponding to a maximum lift factor in a set of lift factors comprising the lift factor Z. An example is used of a correspondence between a basis matrix index and a set of lifting factors Z shown in Table 2. Z=13, and Pi, j of an element in row iy column j in a basis matrix of Z satisfies (2). Vi, j is a displacement value of a non-zero element in row i and column j in a basis matrix indicated by PCM 7. For Z=13, a modulo operation is performed taking the displacement value Vi, j modulo Z, where Z=13, and Vi, j is a displacement value of the non-zero element in row i and column j in the basis matrix indicated by PCM 7. It should be noted that this report only provides examples, and that these do not constitute a limitation in the present application. The 80a base graph or the 170a base graph is used as an example. Once the base matrix HB is determined, one or more parity bits corresponding to columns 22 to 25 of this matrix are obtained using the input sequence and rows 0 to 3 and columns 0 to 25 (i.e., dual core). From the input sequence and one or more parity bits corresponding to column 26 (i.e., a column of the matrix with weight 1), one or more parity bits corresponding to dual core are obtained. Subsequently, the encoding is performed using the input sequence, the parity bits corresponding to columns 22 to 26, and a submatrix D, to obtain one or more parity bits corresponding to a submatrix E. In this way, the encoding is completed. For a process of encoding an LDPC code, refer to the descriptions in the previous implementations, and the details are not described again in this document. In the communications system, the LDPC code can be obtained after encoding using the method described above. Once the LDPC code is obtained, a communications device can perform one or more of the following operations: perform rate adaptation on the LDPC code; perform, according to an interleaving scheme, interleaving on an LDPC code obtained after rate adaptation; modulate, according to a modulation scheme, an LDPC code obtained after interleaving, to obtain a bit sequence X; or transmit the bit sequence X. In a decoding method provided in another embodiment of this application, a decoder decodes an input sequence using an LDPC array. A base graph of the LDPC array can be any of the base graphs from the preceding examples, including the center matrix of base graph 80a, and a base HB matrix of the LDPC array can be any base matrix from the respective examples. The input sequence to the decoder can be a sequence of smooth values ​​of an LDPC code. The method also includes: determining a Z-raising factor. A communications device at a receiving end can receive a signal that includes an LDPC code, obtain a sequence of smooth values ​​of the LDPC code in the signal, and determine the corresponding Z-raising factor. That the decoder decodes the input sequence using the LDPC matrix H can be to decode the sequence of soft values ​​of the LDPC code using an LDPC matrix H corresponding to the Z-raise factor e. Because decoding is the reverse process of encoding, for descriptions of the LDPC H matrix and the LDPC H matrix base chart, refer to the encoding realization above. Decoding can be performed on the basis of an entire base chart, or on the basis of some rows or some columns of an entire base chart. The basis matrix HB of the LDPC matrix H may be any basis matrix described in the preceding embodiments or a basis matrix obtained by performing a row permutation, a column permutation, or both a row and a column permutation on any basis matrix described above. A basis graph of the basis matrix HB includes at least a submatrix A and a submatrix B, and may further include a submatrix C, a submatrix D, and a submatrix E. For the submatrices, see the descriptions in the preceding embodiments, and the details are not described again herein. Certainly, the basis matrix HB may be another basis matrix whose basis graph conforms to the basis graph shown in the preceding embodiments, and the basis matrix HB is not limited to this in the present application. In a possible design, the HB base matrix of the LDPC code can be stored in a memory, and the soft values ​​of the LDPC code can be decoded after obtaining the LDPC matrix corresponding to the Z-raise factor. In another possible implementation, because there is a plurality of base arrays of an LDPC code, and a relatively large storage space is occupied if the base arrays are stored according to an array structure, a base graph of the LDPC code can be stored in memory, non-zero element offset values ​​can be stored in each base array by row or by column, and then an LDPC array can be obtained based on the base graph and an offset value in a base array corresponding to a Z-lift factor. The base graph can be stored in various ways described in the previous encoding implementation. It should be noted that only examples are provided here, and these do not constitute a limitation. Decoding is the reverse process of encoding, and the base matrix HB used during decoding has the same characteristics as the base matrix in the encoding implementation. To raise the base matrix HB to the power of LDPC matrix H, refer also to the encoding implementation. In the communications system, prior to the decoding method, a communications device may also perform one or more of the following operations: receive a signal that includes an LDPC code; or perform demodulation, deinterlacing, or rate mismatching on the signal to obtain smooth values ​​of the LDPC code. In a possible implementation, one or more of the following elements can be stored: (a) a parameter used to obtain any HB base array described in the above implementations, wherein the HB base array can be obtained as a function of the parameter; for example, the parameter may include one or more of the following: a row index, a row weight, a column index or a column weight of a base graph and / or a base array, a position of a non-zero element in a base graph and / or a base array, an offset value in a base array, an offset value of a non-zero element and a corresponding position, an offset value, a lift factor, a set of lift factors, a base graph of a base array, or a code rate; (b) any basis matrix HB described in the above implementations; (c) a matrix raised to the power of the basis matrix HB; (d) a basis matrix obtained by performing a row / column permutation on any HB basis matrix described in the above implementations, where the row / column permutation is a row permutation, or a column permutation, or a row permutation and a column permutation in this application; or (e) a raised matrix of the base matrix obtained by performing the row / column permutation. In a possible implementation, an input sequence can be encoded or decoded using a low-density parity-check matrix (LDPC) in one or more of the following ways during encoding or decoding: Obtain a base matrix HB based on the parameter described in section (a) above; and perform encoding or decoding based on the obtained base matrix HB; or perform row / column permutation based on the obtained base matrix HB, and perform encoding or decoding based on a base matrix obtained by performing the row / column permutation, wherein the encoding or decoding is performed based on the base matrix in this present memory, and optionally, the encoding or decoding can be performed based on a raised matrix of the base matrix; perform encoding or decoding based on a basis matrix stored in (b) or (d) (a stored basis matrix HB or a stored basis matrix obtained by performing a row / column permutation on a basis matrix HB); or perform a row / column permutation on the stored basis matrix and perform encoding or decoding based on a basis matrix obtained by performing the row / column permutation, wherein the encoding or decoding is performed based on the basis matrix in this present memory, and optionally, the encoding or decoding can be performed based on a raised matrix of the basis matrix; or perform encoding or decoding according to (c) or (e). The raising in this application can consist of obtaining a raised array after an array has been transformed or processed, and this application does not limit one form of raising. In one implementation, the raising process might involve performing offset processing on an array. For example, each offset value greater than or equal to 0 in a basis array is incremented or decremented by an offset value, resulting in an offset array. In another implementation, raising might consist of raising a row and a column of an array to obtain a raised array. In yet another implementation, raising might consist of converting a non-zero value in an array. Storage in this application may be performed in one or more memories. The memories may be separate or integrated into the encoder, decoder, processor, chip, communications equipment, or terminal. Some of the memories may be separate, while others may be integrated into the decoder, processor, chip, communications equipment, or terminal. The memory type may be any form of storage medium, without any limitation in this application. Figure 6 is a schematic structural diagram of a 600 communications apparatus. The 600 apparatus is configured to implement the method described in any of the preceding embodiments. See the descriptions in the preceding embodiments. The 600 communications apparatus may be a chip, a base station, a terminal, or another network device. The 600 communications appliance includes one or more 601 processors. The 601 processor can be a general-purpose processor, a specialized processor, or similar. For example, the 601 processor can be a baseband processor and a central processing unit. The baseband processor can be configured to perform processing on a communication protocol and communication data. The central processing unit can be configured to control the communications appliance (such as the base station, terminal, or chip), execute the software program, and process the software program data. In one possible design, the communications apparatus 600 includes one or more processors 601. One or more processors 601 may implement functions of the encoder mentioned above. In another possible design, the encoder may be part of the processor 601, and the processor 601 may implement functions other than those of the encoder. The 600 communications device encodes an input sequence using an LDPC matrix. A base graph of the LDPC matrix can be any of the base graphs from the preceding examples or a base graph obtained by performing a row permutation, a column permutation, or a row and column permutation on any of the base graphs described above. A base matrix HB of the LDPC matrix H can be any base matrix in the above embodiment or a base matrix obtained by performing a row permutation, a column permutation, or a row and column permutation on any base matrix described above. The encoder's input sequence can be a sequence of information bits. In one possible design, one or more 601 processors can implement functions of the decoder mentioned above. In another possible design, the decoder can be part of the 601 processor. The 600 communications device is configured to decode an input sequence using an LDPC matrix. A base graph of the LDPC matrix can be any of the base graphs from the previous examples or a base graph obtained by performing a row permutation, a column permutation, or a row and column permutation on any of the base graphs described above. A base matrix HB of the LDPC matrix H can be any base matrix from the previous examples or a base matrix obtained by performing a row permutation, a column permutation, or a row and column permutation on any of the base matrices described above. The decoder's input sequence can be a sequence of smooth values. Optionally, in a design, the processor 601 may also include an instruction 603. The instruction can be executed on the processor, to make the communications apparatus 600 perform the method described in the previous method implementation. In another possible design, the 600 communications apparatus may also include a circuit, and the circuit may implement encoder, decoder, or encoder and decoder functions in the embodiment of the above method. Optionally, the communications apparatus 600 may include one or more memories 602. The memory stores an instruction 604, and the instruction can be executed by the processor to cause the communications apparatus 600 to perform the method described in the preceding method embodiment. Optionally, the memory may also store data. Optionally, the processor may also store an instruction and / or data. The processor and memory may be arranged separately or integrated together. Optionally, one or more memories 602 may store a parameter related to a base array, for example, an offset value, a base graph, a raised array of a base graph, rows in the base array, or a raising factor. Optionally, one or more memories 602 may store a base array or a raised array of a base array. Optionally, the communications apparatus 600 may also include a transceiver 605 and an antenna 606. The processor 601 may be called the processing unit and controls the communications apparatus (the terminal or the base station). The transceiver 605 may be called the transceiver unit or transceiver circuit, and is configured to implement a transceiver function of the communications apparatus using the antenna 606. Optionally, the 600 communications apparatus may also include a component configured to generate a transport block CRC, a component used for code block segmentation and CRC checking, an interleaver used for interleaving, a modulator used for modulation processing, or similar components. The functions of these components may be implemented by one or more 601 processors. Optionally, the 600 communications apparatus may also include a demodulator used for demodulation, a deinterlaceer used for deinterlacing, a component used for speed mismatching, or similar components. The functions of these components may be implemented by one or more 601 processors. Figure 7 is a schematic diagram of a communication system 700. The communication system 700 includes a communication device 70 and / or a communication device 71. The communication device 70 and the communication device 71 receive and transmit information data to each other. The communication device 70 and the communication device 71 may each be the communication apparatus 600, or the communication device 70 and the communication device 71 may each include the communication apparatus 600, and receive and transmit information data. For example, the communication device 70 may be a terminal, and correspondingly, the communication device 71 may be a base station. Alternatively, the communication device 70 may be a base station, and correspondingly, the communication device 71 may be a terminal. A person skilled in the art may further understand that various illustrative logical blocks and steps listed in the embodiments of this application may be implemented using electronic hardware, computer software, or a combination thereof. Whether the functions are implemented by hardware or software depends on the particular application and the overall system design requirement. A person skilled in the art may use various methods to implement the described functions for each particular application, but such implementation shall not be deemed to be beyond the scope of the embodiments of this application. The various logic units and illustrative circuits described in the embodiments of this application may implement or operate the described functions using a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or a design of any combination thereof. The general-purpose processor may be a microprocessor. Optionally, the general-purpose processor may be any conventional processor, controller, microcontroller, or state machine.The processor can be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors with a digital signal processor core, or any other similar configuration. Steps in the methods or algorithms described in the embodiments of this application can be directly integrated into hardware, an instruction executed by a processor, or a combination thereof. The memory can be RAM, flash memory, ROM, EPROM, EEPROM, a register, a hard drive, a removable magnetic disk, a CD-ROM, or any other storage medium in the art. For example, the memory can be connected to the processor in such a way that the processor can read information from and write information to memory. Optionally, the memory can be integrated into the processor. The processor and memory can be arranged in an ASIC, and the ASIC can be arranged in the communications apparatus (such as the base station or terminal). Optionally, the processor and memory can be arranged in different components of the communications apparatus. From the descriptions of the preceding implementations, a person skilled in the art can clearly understand that this application can be implemented using hardware, firmware, or a combination thereof. When this application is implemented by software, it can be implemented wholly or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the procedure or functions described in this application are generated, wholly or partially. When this application is implemented by software, the above functions can be stored on a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium.A computer can be a general-purpose computer, a specialized computer, a network of computers, or another programmable device. Computer instructions can be stored on a computer-readable storage medium or transmitted from one computer-readable storage medium to another. The computer-readable medium includes both a computer storage medium and a communication medium, where the communication medium includes any means that allows a computer program to be transmitted from one location to another. The storage medium can be any available medium accessible by a computer.The following provides an example, but does not impose a limitation: computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage or disk storage media or other magnetic storage device, or any other medium that can carry or store the expected program code in the form of an instruction or data structure, and that can be accessed by a computer. Furthermore, any connection can be correctly defined as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, optical cable / fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, optical cable / fiber, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium to which they belong.For example, a disk (Disk) or a disc (disc) used in this application includes a compact disc (CD), a laser disc, an optical disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, where the disk generally copies data by magnetic means and the disc copies data optically by laser means. The above combination should also be included within the scope of protection of the computer-readable medium. In this application, " / " indicates and / or. For example, coding / decoding indicates coding, decoding, or coding and decoding. In summary, the above are merely preferred embodiments of the technical solutions in this application, but are not intended to limit the scope of protection of the present invention as defined in the appended claims.

Claims

1. A coding method, comprising: encoding an input sequence based on a low-density parity-check matrix, LDPC; wherein a basis graph of the LDPC matrix is ​​represented by a matrix comprising at least a central matrix of 5 rows and 27 columns, and each element of the basis graph is either a non-zero element or a zero element, wherein each non-zero element in the basis graph represents a circular permutation matrix of size Z*Z in the LDPC matrix, and each zero element in the basis graph represents a matrix of zeros of size Z*Z in the LDPC matrix, wherein Z is a lift factor; characterized in that the central matrix comprises non-zero elements in the following positions: i=0, j = 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23; i=1, j = 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24; i=2, j = 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18,19, 20, 24, 25; i=3, j = 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25; yi=4, j = 0, 1, 26; wherein i represents a row index and j represents a column index, and the central matrix comprises zero elements in any other position.

2. The method according to claim 1, wherein the circular permutation matrix Z*Z is equal to a matrix obtained by circularly shifting an identity matrix of size Z*Z to the right Pi, j times, wherein Pi, j is a shift value for the nonzero element of row i and column j in the base graph.

3. The method according to claim 2, wherein the displacement value Pi,j depends on the lift factor Z.

4. The method according to any of claims 1 to 3, wherein the base chart comprises two columns of embedded punch bits.

5. The method according to any of claims 1 to 4,wherein the LDPC matrix is ​​obtained from the base chart and a displacement value in a base matrix corresponding to the lift factor Z.

6. The method according to any of claims 1 to 5, wherein the base chart further comprises a submatrix C, a submatrix D, and a submatrix E, wherein the submatrix C is a matrix of zeros of 5 rows and mD columns, the elements of the submatrix C represent row indices i = 0, , 4 and column indices j = 27, , 27 + mD - 1; the submatrix D is a matrix of mD rows and 27 columns, the elements of the submatrix D represent row indices i = 5, , 5 + mD - 1 and column indices j = 0, , 26; The submatrix E is an identity matrix of mD rows and mD columns, whose elements represent the row indices i = 5, , 5 + mD - 1 and the column indices j = 27, , 27 + mD - 1; and mD is an integer and 0 < mD 41.

7. A decoding method,comprising: decoding an input sequence based on a low-density parity-check matrix, LDPC; wherein a basis graph of the LDPC matrix is ​​represented by a matrix comprising at least a central matrix of 5 rows and 27 columns, and each element of the basis graph is either a non-zero element or a zero element, wherein each non-zero element in the basis graph represents a circular permutation matrix of size Z*Z in the LDPC matrix, and each zero element in the basis graph is represented by a matrix of zeros of size Z*Z in the LDPC matrix, wherein Z is a lift factor; characterized in that the central matrix comprises non-zero elements in the following positions: i=0, j = 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23; i=1, j = 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24; i=2, j = 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25; i=3,j = 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25; yi=4, j = 0, 1, 26; wherein i represents a row index and j represents a column index, and the central matrix comprises zero elements in any other position.

8. The method according to claim 7, wherein the circular permutation matrix Z*Z is equal to a matrix obtained by circularly shifting an identity matrix of size Z*Z to the right Pi, j times, wherein Pi, j is a shift value for the nonzero element of row i and column j in the base graph.

9. The method according to claim 8, wherein the displacement value Pi,j depends on the lift factor Z.

10. The method according to any of claims 7 to 9, wherein the base chart comprises two columns of embedded punch bits.

11. The method according to any of claims 7 to 10,wherein the LDPC matrix is ​​obtained from the base chart and a displacement value in a base matrix corresponding to the lift factor Z.

12. The method according to any of claims 7 to 11, wherein the base chart further comprises a submatrix C, a submatrix D, and a submatrix E, wherein the submatrix C is a matrix of zeros of 5 rows and mD columns, the elements of the submatrix C represent row indices i = 0 4 and column indices j = 27 27 + mD - 1; the submatrix D is a matrix of mD rows and 27 columns, the elements of the submatrix D represent row indices i = 5 5 + mD - 1 and column indices j = 0 26; The submatrix E is an identity matrix of mD rows and mD columns, whose elements represent the row indices i = 5 5 + mD - 1 and the column indices j = 27 27 + mD - 1; and mD is an integer and 0 < mD 41.

13. A computer storage medium that stores a program and,14. A computer program product comprising one or more instructions, and when the program is executed on one or more processors, causing one or more processors to perform the method according to any of claims 1 to 6, or to perform the method according to any of claims 7 to 12.

15. An apparatus comprising one or more processors, configured to perform the method according to any of claims 1 to 6, or to perform the method according to any of claims 7 to 12.

16. The apparatus according to claim 15, wherein the apparatus further comprises one or more memories configured to store the base graph.

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