Low current consumption non-coherent sampling receiver with one sample per bit

Abstract

Exemplary embodiments provide a data receiver, wherein the data receiver is configured to receive a signal having a sequence of N bits, to obtain a received signal, where N is a natural number greater than or equal to eight, N ≥ 8, wherein the data receiver is configured to sample the received signal at a sampling frequency corresponding to one sample per bit of the sequence of N bits with an intentional deviation of up to 2 / N, to obtain a received bit sequence, wherein the data receiver is configured to correlate the received bit sequence with K different sequences of N-1 reference bits, to obtain K partial correlation results, where K is less than or equal to N-1 and greater than or equal to three, N-1 ≥ K ≥ 3, wherein the K different sequences of reference bits are different dotted versions of the same basic sequence of N reference bits,wherein the data receiver is configured to detect the N-bit sequence when at least one of the K partial correlation results exceeds a detection threshold.

Description

Low current consumption sampling receiver with non-coherent sampling with one sample per bit. Examples of embodiments of the present invention relate to a data receiver and, in particular, to a low current consumption sampling receiver with non-coherent sampling with one sample per bit. Low-current receivers are known, often implemented as detector-receivers or superregenerative receivers. Current consumption is around 100 µA. In [1] a diode detector with an upstream LNA (LNA = low noise amplifier) ​​is presented. The current consumption amounts to 100 µA. In [2], a superregenerative receiver with a relatively high current consumption of 570 µA is described. In [3], a sampling PLL-based receiver ("PLL subject to duty cycle") is presented, which operates synchronously with the transmitter. Its current consumption, at 346 µA, is also relatively high. In [4], a sampling receiver with a constant sampling rate and constant on-time is described. The receiver consists of an analog and a digital part. Radio frequency sampling is performed when the entire receiver is switched on or off. In this respect, the analog and digital parts are always switched on during the "on phases" and switched off during the "off phases." Figure 1 shows a diagram of power consumption in µW versus sensitivity in dBm for conventional ultra-low power receivers in the UHF frequency range for different modulation procedures (OOK (on-off keying, a type of binary modulation), ASK (amplitude shift keying), PWM (pulse width modulation), FSK (frequency shift keying), PPM (pulse position modulation)). In other words, Figure 1 provides an overview of ultra-low power receivers presented in a power-versus-sensitivity diagram. The diagram shown in Figure 1 is derived from [5] and is slightly modified with the activation receptor contributions from [8] and [9]. The savings due to direct sampling ("OVS 1") instead of oversampling with a factor of corresponds to barely a fraction of a decimal scale (vertical axis). In [6] a 95 µW receiver for the 2.4 GHz band is presented, exhibiting a sensitivity of -72 dBm. The data rate is 62.5 kbps. The 14 nm CMOS design digitizes the internal signal with a 6-bit ADC. The external time base is a 32 kHz oscillator. 95 µW is too high for years of battery operation. [7] describes a superheterodyne receiver with a power consumption of 41 µW, achieving a sensitivity of -78 dBm. Recognition of the triggering sequence and the receiver's direction is performed externally using an LF trigger receiver, rather than internally as in [5]. At 41 µW, battery operation with a coin cell (e.g., AG 13, 130 mAh) is only possible for five months.

[10] , US patent 2007 / 211835 A1, describes a device for recognizing a synchronization time. The device comprises a correlation calculator configured to generate a first correlation value by calculating a cross-correlation between a sampled input signal and a reference signal or an autocorrelation of the sampled input signal. The device also comprises an interpolation processor configured to generate a second correlation value by interpolating several of the first correlation values ​​using different combinations of sampling points from the input signal. Furthermore, the device includes a detector for recognizing a synchronization time based on the first and second correlation values. Therefore, the present invention is based on the objective of creating a concept for a receiver that makes it possible to further reduce the current consumption or power absorbed by the receiver. This objective is achieved through independent claim 1. Advantageous improvements are found in the dependent claims. The embodiment examples constitute a data receiver, the data receiver being configured to receive a signal, which has a sequence of N bits, to obtain a received signal, N being a natural number greater than or equal to eight, N 8, the data receiver being configured to sample the received signal with a sampling rate, which with an intentional deviation of up to 2 / N [e.g. up to 5% [such as e.g. from 3% to 5%]] corresponds to a sampling value per bit of the sequence of N bits, to obtain a received bit sequence, the data receiver being configured to correlate the received bit sequence with K different sequences of N-1 reference bits, to obtain K partial correlation results, K being less than or equal to N-1 and greater than or equal to three, N-1 K 3,where the K different reference bit sequences are selectively disabled versions of the same basic N-bit reference sequence, the data receiver is configured to detect the N-bit sequence when at least one of the K partial correlation results exceeds a detection threshold. Therefore, the embodiments constitute a radio-electric sampling receiver capable of receiving data (e.g., correlation sequences) without synchronization. In this respect, sampling is performed in a non-consistent manner with a sampling rate per bit. Oversampling (e.g., by a factor of 4, 8, or 16) in the radio-electric receiver can be omitted. Consequently, current consumption is reduced by a factor of 4, 8, or 16. The embodiments are based on parallel processing of the correlation sequences with selective blocking at different bit positions. The embodiments operate without time delay; that is, no delay regulation is used. Therefore, data reception occurs continuously.Suppressing oversampling significantly reduces the receiver's current draw; suppressing a synchronization message shortens the transmission time at both the transmitter and receiver. Using the method used in the examples of simple sampling implementation, it is possible to implement radio-electric sampling receivers that consume almost an order of magnitude less power. Examples of embodiments of the present invention are described in more detail with reference to the accompanying figures. They show: Figure 1 shows a diagram of absorbed powers in µW versus sensitivities in dBm of conventional ultra-low power receivers for the UHF frequency range for different modulation procedures (OOK, ASK, PWM, FSK, PPM). Figure 2 shows a schematic view of multiple oversampling as an example of pulses modulated using OOK, Figure 3 is a schematic block diagram of a data receiver (radio receiver), according to an embodiment of the present invention, Figure 4 shows in a tabulated overview in the example of binary bit sequences for OOK modulation of an HF carrier signal, how many bit errors are admissible in the worst case in a binary correlation when corresponding to the sequence length N the best correlation sequence is selected, Figure 5 shows a schematic view of a transmitted bit sequence with a transmission data rate DRTX and a received bit sequence, which results from sampling the transmitted bit sequence with the sampling rate (receiver data rate) DRRX, which is lower than the transmission data rate DRTX. Figure 6 shows a schematic view of a transmitted bit sequence with a transmission data rate DRTX and a received bit sequence, which results from sampling the transmitted bit sequence with the sampling rate (receiver data rate) DRRX, which is higher than the transmission data rate DRTX. Figure 7 shows a schematic view of a transmitted bit sequence with a transmission data rate DRTX and a received bit sequence, which results from sampling the transmitted bit sequence with the sampling rate (receiver data rate) DRRX, which is equal to the transmission data rate DRTX. Figure 8 is a schematic view of a transmitted bit sequence with a transmission data rate DRTX and a received bit sequence, resulting from sampling the transmitted bit sequence with the sampling rate (receiver data rate) DRRX, which is equal to the transmission data rate DRTX, when the sampling times coincide with the bit edges; Figure 9 is a schematic block diagram of a data receiver correlation stage, according to an exemplary embodiment of the present invention; and Figure 10 shows a table with bit error statistics for 30 different cases of bit train compression. In the following description of the embodiment examples of the present invention, the same elements or elements of the same function are given the same reference number in the figures, so that their descriptions are interchangeable. Sampling receivers (or radio transmitters) cyclically sample a signal from the connected antenna. The analog receiver is switched on during a sampling operation for the duration of the ON state. The sampling rate can be derived directly or via frequency division from a digital timing signal. The current draw of the sampling receiver is directly proportional to the sampling rate. The sampling receiver is not synchronized with the radiotelegram transmitted by one or more radio transmitters. This eliminates additional effort at both the transmitter (e.g., synchronization telegrams) and the receiver. This also saves time during transmission and reduces the use of the radio channel, enabling a greater number of radio communication users.A circuit for precisely adjusting the phase for the respective sampling time can be used, for example, a so-called CDR circuit (Clock and Data Recovery). The current draw of such circuits is often well above 1 mA, which is completely contrary to the goal of a "low-current radio receiver with less than 10 µA." If oversampling procedures are used, more samples per bit are obtained. Current draw increases with the oversampling factor. Figure 2 assumes, for example, quadruple oversampling. If the RF carrier signal is modulated using OOK, the transmission current ITX corresponds to the transmitted bit data of width Tb. In this case, four related samples result in the direct image of each respective bit.However, the receiver lacks the temporal association of individual sample values. This can be determined, for example, by an integrator (e.g., with a memory length of four). However, it can also happen that individual sample values ​​are formed on the edges of the OOK signal—that is, on the 0-1 or 1-0 transitions—and are unreliable. In this case, instead of four, five or three sample values ​​may correspond to the respective bit. This uncertainty in the determined bit length can have a particularly disruptive effect in the case of low oversampling (e.g., from two to four) and can lead to erroneous decisions in the reconstruction of the transmitted bits (data errors). Generally speaking, higher oversampling (e.g., eight) is less critical but exhibits a much higher average current draw.Uncertainty on bit edges is made up of several contributions: transmitter phase noise, the type of transmitter envelope in OOK modulation with a modulation degree of 100%, as well as receiver phase noise, and many more. The implementation examples described below enable the receiver to operate without oversampling, i.e., with only 1 sample per bit, to significantly reduce the average current absorption of the radio receiver. Figure 3 shows a schematic block diagram of a data receiver 100 (radio receiver), according to an exemplary embodiment of the present invention. The data receiver 100 is configured to receive a signal 102, which has a sequence of N bits, to obtain a received signal 104, where N is a natural number greater than or equal to eight, N ≥ 8. Furthermore, the data receiver 100 is configured to sample the received signal 104 with a sampling rate DRRX, which, with an intentional deviation of up to 2 / N, for example up to 5% (for example, from 3% to 5%), corresponds to a sampling value per bit of the sequence of N bits (i.e., receiver sampling rate or data rate DRRX, distinct from the transmitting data rate DRTX), to obtain a received bit sequence 106.Furthermore, data receiver 100 is configured to correlate the received bit sequence 106 with K different N-1 reference bit sequences to obtain K partial correlation results 108_1-108_K, where K is less than or equal to N-1 and greater than or equal to three, N-1 ≤ K ≤ 3, the K different reference bit sequences being selectively disabled versions of the same basic N-bit reference sequence. Data receiver 100 is further configured to detect the N-bit sequence 106 when at least one of the K partial correlation results 108_1-108_K exceeds a detection threshold. As shown in Figure 3 according to an example implementation, the data receiver 100 may have a sampler 105, K correlators 107_1-107_K and a detector 109. The sampler 105 can be configured to sample the received signal 104 with a sampling rate, which with an intentional deviation of up to 2 / N, for example up to 5% (for example from 3% to 5%), corresponds to a sampling value per bit of the N-bit sequence, to obtain the received bit sequence 106. The K correlators 107_1-107_K can be configured to correlate the 106 received bit sequence with K different N-1 reference bit sequences to obtain the K partial correlation results 108_1-108_K. In this respect, a k-th correlator of the correlators 107_1-107_K can be configured to correlate the 106 received bit sequence with a k-th N-1 reference bit sequence to obtain a k-th partial correlation result from the K partial correlation results 108_1-108_K, where k is a control variable (natural number) from 1 to K. Detector 109 can be configured to detect the N-bit sequence 106 when at least one of the K partial correlation results 108_1-108_K exceeds a detection threshold. In implementation examples, the received 106 bit sequence can have a length of N-1 bits. In implementation examples, the number K of different sequences of N-1 reference bits may depend as follows on a number F of tolerable errors: where F is a natural number greater than or equal to one and less than or equal to N / 3, N / 3 F 1. In some implementations, the transmitted bit sequence may consist of N bits. For detection, N-1 selectively disabled correlators of length N-1 can be constructed in these implementations (full coverage in the case of a missing bit on the receive side). However, fewer than N-1 selectively disabled correlators of length N-1 can also be constructed in these implementations, but at least three correlators of length N-1, when the recognition of the correlation sequence is error-tolerant. In realization examples, as already mentioned, N is assumed to have at least 8. In implementation examples, a sequence of N bits can also be assumed with a tolerance of at most F randomly distributed bit errors. For example, in the case of a sequence with N = 31 and a maximum of F = 6 tolerable errors, the sequence length N = 31 can be divided by F = 6, so in this case K = 5 partial correlators are sufficient. In general, the minimum number K of partial correlators is equal to N divided by F, but basically at least three. The 31-bit sequence, as an example, can be selectively disabled at the fourth position (6 : 2 + 1, i.e., F : 2 + 1) the first time, so that the first partial correlator has a length of N - 1 = 30 bits. Later, at F = 6 bits, the next selective disabling of the 31-bit code takes place, and so on. That is, the scores occur at the original positions of the 31-bit sequence: 4, 10, 16, 22, 28. In general: F : 2 + 1, F : 2 + F + 1, F : 2 + 2 F + 1, F : 2 + 3 F + 1, F : 2 + 4 F + 1, ..., N - F : 2. Within the five correlators, compression errors can now occur anywhere due to a mismatch in sampling rates (e.g., 3%...5%; 3% = 100% / N). If compression takes place at position 1, 2, 3, or 4, the number of bit errors is generally (!) at most 3, or, in the best-case scenario, 0. After selective nulling, the bits (RX and TX sequences) are reconfigured. If the compression position is at position 5, 6, or 7, the first correlator is also the best. Generally, there are at most 3 bit errors. If compression takes place at position 8, 9, 10, 11, 12, or 13, the third correlator is the best. Comparing the correlation value with a threshold at each correlator results in a binary signal.All the binary signals thus obtained from the correlators can be subjected to a logical OR operation to obtain the total "code match" signal. This naturally depends on how the zeros and ones are arranged. Generally, this is unknown; therefore, there are at most 3 bit errors, and with specific bit sequences, often even fewer. In certain cases, there may even be 0 bit errors. Any additional bit errors due to transmission interference must then be processed by the correlators. No additional compression occurs. In total, in the case of the "most favorable" correlator, there are at most F:2 bit errors due to compression. The table shown in Figure 4 illustrates, in the example of binary bit sequences for OOK modulation of an HF carrier signal, how many bit errors are permissible in the worst case for a binary correlation when the best correlation sequence is selected for sequence length N. This was determined in each case by code search. In this respect, the quality measure was the maximum distance between the primary and secondary peaks of KKF, also in the case of F arbitrarily distributed bit errors. This aims to achieve the property of a pseudorandom sequence (ideal case: AKF or KKF is the Dirac delta function). In implementation examples, the data receiver 100 can be configured to selectively disable the basic sequence of N reference bits at position p, to obtain the k-th sequence of K different sequences of N-1 reference bits: where k is a control variable from 1 to K. In implementation examples, the DRRX sampling rate may be less than a DRTX data rate of the 102 signal, for example in 2 / N, such as from 3% to 5%. In implementation examples, the signal 102 can be modulated by OOK (OOK = on-fff keying, in Spanish a type of binary modulation). Detailed embodiment examples of the present invention are described below. In this regard, the effect of different data rates is explained first. As mentioned previously, in the implementation examples, a sampling procedure without oversampling is used. In these implementation examples, a distinction is made between the transmit data rate (DRTX) and the receive data rate (DRRX), with the transmit data rate (DRTX) and the receive data rate (DRRX) being chosen differently. In implementation examples, the aim is to transmit a specific bit sequence of length L (for example, 31 bits). Four cases are examined below in this regard. In the first case, the transmit data rate DRTX is greater than the receiver data rate DRRX (i.e., DRTX > DRRX), resulting in compression of the bitstream, as shown in Figure 5. Specifically, Figure 5 shows a schematic view of a transmitted 102a bit sequence with a transmit data rate DRTX and a received 106a bit sequence, obtained by sampling the transmitted 102a bit sequence with the sampling rate (receiver data rate) DRRX, which is lower than the transmit data rate DRTX. As can be seen in Figure 5, a transmitted 0 bit is missing from the received 106a bit sequence. That is, when the transmit data rate DRTX is greater than the receiver data rate DRRX, transmitted bits are missing from the receiver's bitstream. The position of these missing bits during operation is generally unpredictable. According to a second case, the transmit data rate DRTX is lower than the receiver data rate DRRX, i.e., DRTX > DRRX, resulting in a bit stream extension, as shown in Figure 6. Specifically, Figure 6 shows a schematic view of a transmitted 102b bit sequence with a transmit data rate DRTX and a received 106b bit sequence, which results from sampling the transmitted 102b bit sequence with the sampling rate (receiver data rate) DRRX, which is higher than the transmit data rate DRTX. As can be seen in Figure 6, a transmitted bit 1 was read twice. That is, when the transmit data rate DRTX is lower than the receiver data rate DRRX, transmitted bits appear multiple times in the receiver bit stream. The repetition position during operation is generally unpredictable. According to a third case, the transmit data rate DRTX is equal to the receiver data rate DRRX, i.e., DRTX = DRRX, as shown in Figure 7. Specifically, Figure 7 shows a schematic view of a transmitted 102c bit sequence with a transmit data rate DRTX and a received 106c bit sequence, which results from sampling the transmitted 102c bit sequence at the sampling rate (receiver data rate) DRRX, which is equal to the transmit data rate DRTX. As can be seen in Figure 7, the transmitted bits are correctly reproduced in the receiver's bit stream. There are no defects. The sampling times do not coincide with the bit edges. This is the desired reception scenario. According to a fourth case, the transmission data rate DRTX is equal to the receiver data rate DRRX, i.e., DRTX = DRRX, with the sampling times coinciding with the bit edges, as shown in Figure 8. Specifically, Figure 8 shows a schematic view of a transmitted 102d bit sequence with a transmission data rate DRTX and a received 106d bit sequence, resulting from sampling the transmitted 102d bit sequence at the sampling rate (receiver data rate) DRRX, which is equal to the transmission data rate DRTX, when the sampling times coincide with the bit edges. As can be seen in Figure 8, many transmitted bits are incorrectly reproduced in the receiver's bit stream. The bit decisions at the receiver are uncertain at the bit edges. This is where the errors occur. For equal transmission and receiver data rates, the third or fourth case may occur. In particular, the fourth case (many RX bit errors) can last for an unpredictably long time, for example, during laboratory testing or in the field with minimal temperature fluctuations. Radio transmission is then no longer possible. Direct sampling, i.e., "without oversampling," is not practical without additional measures. In this case, the relative phase position of the TX and RX data streams is crucial. If compression or broadening of the bit streams at the receiver is acceptable, then the first and second cases are conceivable. If special correlation sequences (e.g., as broadening codes) representing specific data bits are transmitted instead of raw bit data, reconstruction can be achieved even with defects and without oversampling. With the second (DRTX < DRRX), a bitstream expansion occurs. The transmitted bits can appear twice instead of once in the receiver's bitstream. When the transmission data rate is chosen to be lower than the receiver data rate, according to , Therefore, in the case of the equals sign, the received bit sequence L+1 and the transmitted bit sequence L will be the same length. This means that the correlators at the receiver must be lengthened by 1 bit. Since the point of intersection with the duplication ("defect") is not known a priori, it is proposed to implement L correlators, each with a different reference sequence. The L distinct reference sequences can be easily generated by the L distinct cases of bit duplication. In any case, one of the correlators will be successfully triggered because the duplication a priori is reproduced there in the reference code. For more efficient implementation, a smaller number of correlators is typically used, as demonstrated in implementation examples. This saves chip area and reduces dynamic and static digital current consumption. If the correlation sequences are chosen appropriately—that is, if the autocorrelation or cross-correlation functions exhibit a very steep maximum with low secondary maxima, which remain low even in the case of transmission errors (code error tolerance postulate)—a reduced number of correlators can be implemented. The first case is more favorable when the transmit data rate (DRTX) is chosen to be higher than the receive data rate (DRRX). This shortens the length of the correlators rather than lengthening them, resulting in fewer digital memory cells or shorter registers. In this case as well, it is preferable to consider only a selection of possible L-1 correlator implementations, rather than all possible L-1 implementations, based on specific examples. For the first chaos shown in figure 5, the result is 17 possible correlation sequences of length 16 bits: _1010110110011010 1_010110110011010 11_10110110011010 110_0110110011010 1101 _110110011010 11010_10110011010 110101_0110011010 1101011_ 110011010 11010110 _10011010 110101101_0011010 1101011011_011010 11010110110_ 11010 110101101100 _1010 1101011011001_010 11010110110011_10 110101101100110_ 0 1101011011001101 _ If instead a selection of correlation sequences is used assuming error tolerance (e.g., 2 bit errors within the 17-bit sequence), selective disablements can now take place in the 3rd, 6th, 9th, 12th, and 15th positions: 11_10110110011010 11010_10110011010 11010110 _10011010 11010110110_ 11010 11010110110011_10 If the actual compression takes place one or two bits before or after a selective sequence invalidation (_) , then between the compression position and the selective invalidation position, at most two errors can be made, in the best case no bit errors. For example, there can be a true compression ("\") in the third position: 110\ 0110110011010, that is: 1100110110011010 This results in the following number of errors, which follows the reference sequences: 11_10110110011010 1 error 11010_10110011010 2 errors 11010110 _10011010 4 errors 11010110110_ 11010 5 errors 11010110110011_10 7 errors In this case, with an error tolerance of "2 out of 17," the first two reference sequences could yield a positive result in one correlator. This example shows that selecting five correlators instead of 16 is sufficient for selectively recognizing the unused receiver sequence. Which correlator is triggered is not, in principle, decisive. Therefore, the correlator selections can be subjected to a logical OR operation on each other. For implementations with 31-bit sequences and an error tolerance of five arbitrary bit errors, it is therefore proposed to implement five correlators (of length 30 bits) with selective disablements in the following positions (see figure 9): position 3, position 9, position 15, position 21, position 27. The total result of the correlator can be a "match" signal, which is derived from the logical OR operation of the match signals Ma1 to Ma5 of the five selectively disabled correlators, as shown in Figure 9, which illustrates an example of a set of five 30-bit binary correlators with different selective disablement. In detail, Figure 9 shows a schematic block diagram of a correlation stage 120 of the data receiver 100, according to an exemplary embodiment of the present invention. The correlation stage 120 comprises a 30-bit shift register 122, K=5 correlators 107_1-107_K (K=5), which are implemented, for example, in each case as a 30-bit XNOR comparator, and a detector 109, which is triggered when at least one of the K=5 partial correlation results exceeds a detection threshold. Figure 10 presents a table of bit error statistics for 30 different bitstream compression scenarios. The tabulated error statistics in Figure 10 account for the recognition of RX sequences with selectively disabled correlators ("A1-A5"). The true number of errors when reviewing all 30 scenarios for true bitstream compression is shown on the far right. For the equal distribution scenario, the average number of errors is 0.84 bits, with a maximum of 2. In eleven of the 30 scenarios (approximately 36.7%), no bit errors occur within the 30-bit sequences. In approximately 43% of the scenarios, only one bit error occurs within the 30-bit sequence. In other words, during selective disabling, up to two bit errors can be generated, according to the table shown in Figure 10, even if the received bit sequence is error-free. Therefore, during operation, it is necessary to reduce the correlator threshold CORR_A_THRESH by up to two. For generally low threshold values, such as 25, confusion with other correlation codes can sometimes occur. Therefore, the bit errors generated due to selective disabling have a minimal effect on the achievable sensitivity. Practical experience in laboratory measurements shows a sensitivity approximately 1 dB lower. This is a tolerable limitation. The direct sampling procedure described herein, with examples of implementations using selectively disabled correlators, allows for the elimination of separate synchronization methods during radio transmission. This saves transmission time, reduces system latency, and increases the maximum number of radio communication users per second. Furthermore, the radio receiver does not need to include any complex, highly precise local oscillator frequency preparation with integrated phase-locked loops (PLLs) and high-frequency quartz crystals. Instead, inexpensive clock quartz crystals can be used, which also exhibit a current draw of less than 1 µA as a quartz oscillator. This does not apply to high-frequency oscillator circuits; in this case, a current draw of more than 1 mA is required.The method described herein, based on exemplary implementations, requires no feedback from the radio receiver (no radio return channel is necessary) and enables the successful reception and decoding of OOK radio frequency sequences in all cases. Furthermore, the method described herein, based on exemplary implementations, is also suitable for enabling fault-tolerant OOK decoding with correlation. This would be an additional specification for a separate synchronization circuit that must be met both during implementation and during actual radio transmission. Failure to acknowledge a synchronization message would lead to the complete loss of the following radio message. In this case as well, the method described herein, based on exemplary implementations, is clearly advantageous. Although some aspects have been described in relation to a device, it is understood that these aspects also represent a description of the corresponding procedure, so that a block or building element of a device should also be understood as a corresponding procedural step or as a feature of a procedural step. Similarly, the aspects described in relation to or as a procedural step also represent a description of a corresponding block, detail, or feature of a corresponding device. Some or all of the procedural steps may be executed by (or using) a hardware device, such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or several of the most important procedural steps may be executed by such a device.Depending on certain implementation requirements, embodiments of the invention may be implemented in hardware or software. Implementation may be carried out using a digital storage medium, such as a floppy disk, DVD, Blu-ray disc, CD, ROM, PROM, EPROM, EEPROM, or FLASH memory, a hard drive, or other magnetic or optical storage, in which electronically readable control signals are stored that can interact with, or do interact with, a programmable computer system to perform the respective procedure. Therefore, the digital storage medium may be computer readable. That is, some examples of embodiment according to the invention comprise a data carrier that presents electronically readable control signals, which can interact with a programmable computer system in such a way that one of the procedures described in this document is carried out. In general, embodiments of the present invention can be implemented as a computer program product with program code, the program code being effective in the sense of performing one of the procedures when the computer program product is executed on a computer. The program code can also be stored, for example, on a machine-readable medium. Other examples of implementation include the computer program to perform one of the procedures described in this document, the computer program being stored on a machine-readable medium. In other words, an example of implementing the procedure according to the invention is therefore a computer program, which has program code for performing one of the procedures described herein, when the computer program is run on a computer. An example of a further embodiment of the procedures according to the invention is therefore a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the procedures described herein is recorded. The data carrier, digital storage medium, or computer-readable medium is normally physical and / or non-transient or non-temporary. An example of a further embodiment of the process according to the invention is therefore a data stream or a sequence of signals, which represents the computer program for performing one of the processes described herein. The data stream or the sequence of signals may be configured, for example, to be transmitted through a data communication connection, for example, via the Internet. An example of a further embodiment comprises a processing unit, for example a computer or a programmable logic building element, that is configured or adapted to perform one of the procedures described herein. An example of a further embodiment comprises a computer, on which the software program is installed to perform one of the procedures described in this document. An example of a further embodiment of the invention comprises a device or system designed to transfer a computer program for performing at least one of the procedures described herein to a receiver. The transfer may take place, for example, electronically or optically. The receiver may be, for example, a computer, a mobile device, a storage device, or a similar device. The device or system may include, for example, a file server for transferring the computer program to the receiver. In some implementations, a programmable logic device (e.g., a field-programmable gate array, an FPGA) may be used to perform some or all of the functionalities of the procedures described herein. In some implementations, a field-programmable gate array may interface with a microprocessor to perform one of the procedures described herein. In general, the procedures are performed in some implementations by an arbitrary hardware device. This may be universally usable hardware such as a computer processor (CPU) or procedure-specific hardware such as an ASIC. The devices described herein may be implemented, for example, using a hardware device, a computer, or a combination of both. The devices described herein, or any component thereof, may be implemented at least partially in hardware and / or software (computer program). The procedures described herein can be implemented, for example, using a hardware device, a computer, or a combination of hardware and a computer. The procedures described herein, or any component thereof, can be executed at least partially using hardware and / or software. The exemplary embodiments described above are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein may occur to other individuals skilled in the art.Therefore, it is intended that the invention be limited only by the scope of protection of the claims below and not by the specific details that have been presented by means of the description and explanation of the embodiment examples in this document. Literature [1] X. Huang, S. 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Alpman et al., "95µW 802.11g / n compliant fully-integrated wake-up receiver with -72dBm sensitivity in 14 nm FinFET CMOS, " 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) , Honolulu, HI, 2017, págs. 172-175. [7] E. T. Armas, D. Ramos-Valido, S. L. Khemchandani y J. del Pino, "A 40.9 µW high sensitivity wake-up radio for wireless sensor networks using uncertain-IF architecture, " 2015 Conference on Design of Circuits and Integrated Systems (DCIS) , Estoril, 2015, págs.1-6. [8] Documento WO 2013 / 131963 A1 [9] Documento EP 2591557 B1

[10] Documento US 2007 / 211835 A1

Claims

1. Data receiver, the data receiver being configured to receive a signal, which has a sequence of N bits, to obtain a received signal, N being a natural number greater than or equal to eight, N 8, the data receiver being configured to sample the received signal with a sampling rate, which with a deviation of up to 2 / N corresponds to a sampling value per bit of the sequence of N bits, to obtain a received bit sequence, the data receiver being configured to correlate the received bit sequence with K different sequences of N-1 reference bits to obtain K partial correlation results, K being less than or equal to N-1 and greater than or equal to three, N-1 K 3, the K different sequences of reference bits being selectively disabled versions in different ways of the same basic sequence of N reference bits,1. The data receiver is configured to detect the N-bit sequence when at least one of the K partial correlation results exceeds a detection threshold.

2. The data receiver according to the preceding claim, wherein the number K of different N-1 reference bit sequences depends on a number F of tolerable errors: F being a natural number greater than or equal to one and less than or equal to N / 3, N / 3 ≤ F.

3. The data receiver according to the preceding claim, wherein the data receiver is configured to selectively disable the basic N-bit reference sequence at position p to obtain the k-th sequence of the K different N-1 reference bit sequences: k being a control variable from 1 to K.

4. The data receiver according to any one of the preceding claims, wherein the received bit sequence has a length of N-1 bits.

5. The data receiver according to any one of the preceding claims,the sampling rate being less than a data rate of the signal.

6. Data receiver according to any of the preceding claims, the signal being modulated by On-Off Keying, OOK.

7. Data receiver according to any of the preceding claims, wherein N=31 and K=5.

8. Data receiver according to claim 1, the signal being modulated by OOK, wherein N=31 and K=5.

9. Method for detecting an N-bit sequence of a received signal, the method comprising: receiving a signal, which has an N-bit sequence, to obtain a received signal, where N is a natural number greater than or equal to eight, N ≥ 8; sampling the received signal with a sampling rate, which, with a deviation of up to 2 / N, corresponds to a sampling value per bit of the N-bit sequence, to obtain a received bit sequence.The correlation of the received bit sequence with K different N-1 reference bit sequences to obtain K partial correlation results, K being less than or equal to N-1 and greater than or equal to three, N-1 ≤ K ≤ 3, the K different reference bit sequences being selectively disabled versions of the same basic N-bit reference sequence, the detection of the N-bit sequence when at least one of the K partial correlation results exceeds a detection threshold.

10. Computer program for carrying out the procedure according to claim 9.

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