Transistor-based electronic device

Abstract

Transistor Electronic Device This description relates to an electronic device (300) comprising a semiconductor region (312) located on a gallium nitride layer (304), two electrodes (314L, 314R) situated on either side of and insulated from the semiconductor region, the electrodes partially penetrating the gallium nitride layer, and two lateral MOS transistors (T1, T2) formed in and on the semiconductor region. Figure for the abbreviation: Fig. 3

Description

Title of the invention: Electronic transistor device Technical field

[0001] The present description relates generally to electronic devices. The present description relates more particularly to high-electron-mobility transistors (HEMTs), or HEMT transistors, and in particular to normally off HEMT transistors based on gallium nitride (GaN) and to methods for producing such transistors. Prior art

[0002] Normally off HEMT transistors based on gallium nitride are commonly used, for example, in electrical energy conversion applications, for powers typically ranging from a few milliwatts to several tens of watts. There are different types of normally off HEMT transistors, including metal-insulator-semiconductor (MIS) insulated gate HEMT transistors, or MIS-HEMT transistors. Such transistors generally have a low threshold voltage and a high on-resistance, which is detrimental to their performance. Summary of the invention

[0003] There is a need to improve existing gallium nitride-based normally off high electron mobility transistors.

[0004] One embodiment overcomes all or part of the drawbacks of existing gallium nitride-based normally blocked high electron mobility transistors.

[0005] One embodiment provides an electronic device comprising: - a semiconductor region located on a gallium nitride layer; - two electrodes, located on either side and insulated from the semiconductor region, the electrodes partially penetrating the gallium nitride layer; and - two lateral MOS transistors formed in and on the semiconductor region.

[0006] According to one embodiment, each transistor is configured to control the passage of an electric current between one of said electrodes and one or more second electrodes carried by the semiconductor region.

[0007] According to one embodiment, each transistor comprises a gate region located directly above a channel region comprised between source and drain regions formed in the semiconductor region.

[0008] According to one embodiment, the source regions of the transistors are doped with a first type of conductivity and separated by a well formed in the semiconductor region and doped with a second type of conductivity, opposite to the first type of conductivity.

[0009] According to one embodiment, the drain region of each transistor is connected, via a two-dimensional electron gas, to one of said electrodes.

[0010] According to one embodiment, the device further comprises one or more conductive regions contacting the drain regions of the transistors and partially penetrating into the gallium nitride layer.

[0011] According to one embodiment, the device comprises exactly two conductive regions covering opposite sides of the semiconductor region located opposite said electrodes and a single second electrode located between the transistors.

[0012] According to one embodiment, the device comprises exactly two conductive regions comprising conductive vias located on either side of the semiconductor region and a single second electrode located between the transistors.

[0013] According to one embodiment, the device comprises a single conductive region comprising a conductive via passing through the semiconductor region and exactly two second electrodes located on either side of the transistors.

[0014] According to one embodiment, the semiconductor region partially penetrates inside the gallium nitride layer.

[0015] According to one embodiment, a lower portion of the semiconductor region is isolated from the gallium nitride layer.

[0016] According to one embodiment, the first electrodes are intended to be brought to the same potential.

[0017] According to one embodiment, the semiconductor region is made of a material different from that of the gallium nitride layer, preferably silicon or silicon carbide.

[0018] One embodiment provides a method of making a device as described, the method comprising the following steps: a) forming a trench inside the gallium nitride layer; b) form the first electrodes on either side of the trench; c) filling the trench with the semiconductor region; and d) form the MOS transistors.

[0019] According to one embodiment, the method further comprises, after step d), the step of forming the second electrode(s).

[0020] According to one embodiment, the conductive region(s) are formed in step b). Brief description of the drawings

[0021] These and other features and advantages will be set forth in detail in the following description of particular embodiments and modes of implementation. made without limitation in relation to the attached figures among which:

[0022] [Fig.l] is a schematic and partial sectional view of an example of a transistor;

[0023] [Fig.2] is an electrical diagram equivalent to the transistor of [Fig.l];

[0024] [Fig. 3] is a schematic and partial sectional view of an electronic device according to a first embodiment;

[0025] [Fig.4] is an electrical diagram equivalent to the electronic device of [Fig.3];

[0026] [Fig. 5] is a schematic and partial sectional view of an electronic device according to a second embodiment;

[0027] [Fig.6] is a schematic and partial sectional view of an electronic device according to a third embodiment;

[0028] [Fig.7] is a schematic and partial sectional view of an electronic device according to a fourth embodiment;

[0029] [Fig.8] is a schematic and partial sectional view illustrating a step of an embodiment of a method for producing the electronic device of [Fig.3];

[0030] [Fig.9] is a schematic and partial sectional view illustrating a subsequent step in the method of implementing the method for producing the electronic device of [Fig.3];

[0031] [Fig. 10] is a schematic and partial sectional view, further illustrating a subsequent step in the method of implementing the method for producing the electronic device of [Fig. 3];

[0032] [Fig. 1 1] is a schematic and partial sectional view, further illustrating a subsequent step in the method of implementing the method for producing the electronic device of [Fig. 3];

[0033] [Fig. 12] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the electronic device of [Fig. 3];

[0034] [Fig. 13] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the electronic device of [Fig. 3];

[0035] [Fig. 14] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the electronic device of [Fig. 3]; and

[0036] [Fig. 15] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the electronic device of [Fig. 3]. Description of the embodiments

[0037] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments and modes of implementation may have the same references and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the embodiments and modes of implementation described have been represented and are detailed. In particular, the applications and systems likely to benefit from the electronic devices described are not detailed, the embodiments and modes of implementation of the present description being in particular compatible with the usual applications and systems comprising normally blocked transistors with high electron mobility based on gallium nitride.

[0039] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0040] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0041] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%, or, when it comes to angular values, to within 10°, preferably to within 5°.

[0042] In the following description, unless otherwise specified, the terms insulating and conducting mean electrically insulating and electrically conducting respectively.

[0043] [Fig.l] is a schematic and partial sectional view of an example of a high-electron-mobility transistor 100 (HEMT). The HEMT transistor 100 is, in this example, normally off.

[0044] In the example shown, the HEMT transistor 100 is formed on a substrate 102, for example a wafer or a piece of wafer of which only a part is shown in [Fig.l]. For example, the substrate 102 is made of a semiconductor material, for example silicon, sapphire, etc.

[0045] In the orientation of [Fig.l], a layer 104 covers an upper face 102T of the substrate 102. For example, the layer 104 is made of gallium nitride (GaN), for example of intrinsic gallium nitride, i.e. not doped intensively. tional.

[0046] In the example shown, another layer 106, for example made of aluminum-gallium nitride (AlGaN), covers an upper face 104T of the layer 104 and yet another layer 108, for example made of silicon nitride (SiN), covers an upper face 106T of the layer 106.

[0047] The transistor 100 comprises a gate region 110G. The gate region 110G of the transistor 100 is said to be recessed in the gallium nitride layer 104. More precisely, in the example shown, the gate region 110G extends vertically, from an upper face 108T of the layer 108, towards the upper face 102T of the substrate 102. Each layer 106, 108 thus comprises two separate parts, located on either side of the gate region 110G.

[0048] In the example shown, the gate region 110G of the transistor 100 comprises a gate electrode 112G (G). The electrode 112G has a T-shaped section, a vertical portion of which passes through the layers 108 and 106 and partially penetrates into the thickness of the layer 104 and a horizontal portion of which extends above the layer 108.

[0049] In the example shown, the sides of the vertical part of the T formed by the grid electrode 112G are inclined such that they approach each other at the bottom of the electrode 112G. This makes it easier for electrons to pass from one side of the electrode 112G to the other.

[0050] The gate electrode 112G is made of a conductive material. For example, the electrode 112G is made of a metal or a metal alloy, for example an alloy based on titanium nitride (TiN) and tungsten (W).

[0051] In the example shown, yet another layer 114 insulates the electrode 112G from the layers 104, 106 and 108. The layer 114 is made of an insulating material, for example alumina (A12O3).

[0052] The insulating layer 114 covers lateral faces 116L, 116R, or walls, and a lower face 116B, or bottom, of the vertical part of the T formed by the electrode 112G. In addition, the insulating layer 114 extends laterally on either side of the vertical part and under the horizontal part of the T formed by the electrode 112G. The layer 114 extends over and in contact with the upper face 108T of the layer 108.

[0053] In the example shown, the horizontal part of the T formed by the electrode 112G extends over and in contact with parts of the layer 114. These parts of the layer 114 are thus interposed vertically between the layer 108 and the horizontal part of the T formed by the electrode 112G.

[0054] The parts of the layer 114 located directly above the gate electrode 112G can be considered as being part of the gate region 110G of the transistor 100.

[0055] In the example shown, the insulating layer 114 has a thickness sens- possibly constant. For example, the thickness of the layer 114 is equal to approximately 30 nm, plus or minus 20%. This makes it possible to properly isolate the gate electrode 112G from the gallium nitride layer 104 while maintaining a relatively low threshold voltage Vth, for example of the order of 1 V.

[0056] The transistor 100 further comprises two other electrodes 112S and 112D. The electrodes 112S and 112D are located on either side of the gate electrode 112G of the transistor 100. The electrode 112S is for example closer to the gate electrode 112G than the electrode 112D. The electrodes 112S, 112G and 112D of the transistor 100 extend perpendicular to the section plane of [Fig.l], along a direction commonly called the width (W) of the transistor 100. The section plane of [Fig.l] is thus oriented parallel to another direction commonly called the length (L) of the transistor 100 and perpendicular to the upper face 108T of the layer 108.

[0057] For example: - the electrode 112S is separated from the electrode 112G by a distance of between 1 and 2 pm, for example equal to approximately 1 pm; and - the electrode 112D is separated from the electrode 112G by a distance of between 10 and 20 pm, for example equal to approximately 10 pm, in order to ensure voltage resistance of, for example, up to 1,000 V (the gallium nitride of the layer 104 can theoretically withstand a maximum electric field of the order of 2 MV / cm; however, this field is in practice limited to approximately 1 MV / cm due to defects present in the layer 104).

[0058] In the example shown, the electrodes 112S and 112D each extend vertically, from the upper face of the insulating layer 114, towards the upper face 102T of the substrate 102. More precisely, in the example shown, the electrodes 112S and 112D each pass through the layers 114, 108 and 106 and partially penetrate into the thickness of the layer 104.

[0059] The electrodes 112S and 112D are each made of a conductive material, for example a metal or a metal alloy. The electrodes 112S and 112D are for example made of the same material as the electrode 112G.

[0060] For example, when the transistor 100 is in operation, the electrode 112S is a source electrode (S) and the electrode 112D is a drain electrode (D). The electrode 112D being further away from the electrode 112G than the electrode 112S, this makes it possible to apply a high potential, for example of the order of 650 V, to the electrode 112D without risk of breakdown of the transistor 100, the electrodes 112S and 112G generally being subjected to potentials of the order of a few volts.

[0061] In the HEMT transistor 100, a two-dimensional electron gas 2DEG, symbolized in [Fig.l] by a dotted line, is formed inside the layer 104 in the vicinity of an interface between layers 104 and 106. The electrodes 112S and 112D of the HEMT transistor 100 are each in contact with the two-dimensional electron gas 2DEG.

[0062] In the example shown where the HEMT transistor 100 is normally off, the two-dimensional electron gas 2DEG is interrupted by the gate region 110G. More specifically, in this example, the two-dimensional electron gas 2DEG is discontinuous and comprises two parts located on either side of the gate region 110G of the transistor 100 (to the left and right of the region 110G, in the orientation of [Fig.l]).

[0063] When a voltage Vgs lower than the threshold voltage Vth of the transistor 100, for example substantially zero, is applied between the gate electrode 112G and the source electrode 112S, the gate region 110G embedded in the gallium nitride layer 104 prevents electrons from flowing between the source electrode 112S and the drain electrode 112D. The transistor 100 is then in a blocked state.

[0064] On the other hand, when the voltage Vgs applied between the gate electrode 112G and the source electrode 112S exceeds the threshold voltage Vth of the transistor 100, electrons can flow between the source electrode 112S and the drain electrode 112D. The transistor 100 is then in an on state.

[0065] In the on state, the electrons flow from one part of the two-dimensional electron gas 2DEG to the other, bypassing the gate region 110G. More precisely, when the transistor 100 is on and subjected to a bias voltage applied between its drain D and its source S, the electrons then take, to flow from one side of the gate G to the other, a conduction path located inside the layer 104 along an interface between the layer 104 and the insulating layer 114.

[0066] The conduction path taken by the electrons to bypass the gate region 110G is symbolized, in [Fig.l], by arrows 118L, 118B and 118R. More precisely, in the orientation of [Fig.l]: - arrow 118L symbolizes a path taken by the electrons to descend along the 116L side of the grid electrode 112G located on the source electrode 112S side; - arrow 118B symbolizes a path taken by the electrons to move horizontally under the bottom 116B of the grid electrode 112G; and - arrow 118R symbolizes a path taken by the electrons to go up along the other side 116R of the gate electrode 112G opposite the side 116L, located on the drain electrode 112D side.

[0067] Although this has not been shown in [Fig.l], the transistor 100 may further comprise other elements such as insulating layers coating the layer 114 and / or a portion of the gate electrode 112G, field plates, contact recovery elements, etc.

[0068] A disadvantage of HEMT transistors similar to transistor 100 is that they have, in the on state, a high drain-source resistance Ron which degrades their electrical performance. This is notably due to resistances associated with the 118L, 118B and 118R conduction paths taken by electrons to bypass the 110G gate region, which are the cause of a decrease in electron mobility.

[0069] Another disadvantage of these transistors comes from defects present inside the gallium nitride layer 104 and which induce, on the conduction paths 118L, 118B and 118R, trapping of electrons. This causes, undesirably, a hysteresis phenomenon observable by measuring variations in drain current Id as a function of the gate-source voltage Vgs (Id(Vgs) curves) as well as a phenomenon of attenuation of the drain current Id after biasing the transistor, also called current collapse phenomenon.

[0070] In order to reduce the on-state resistance Ron of the transistor 100, one could consider providing a structure in which the insulating layer 114 would be omitted and where the gate electrode 112G would not penetrate inside the gallium nitride layer 104. This would amount, for example, to ensuring that the electrode 112G stops in the thickness of the layer 106, before the interface between the layer 106 and the layer 104. This would thus form a Schottky-type gate, which would make it possible to locally interrupt or attenuate the two-dimensional electron gas 2DEG directly above the gate electrode 112G so as to obtain a normally off transistor. However, this would not make it possible to achieve a threshold voltage Vth greater than approximately 1 V, which proves problematic for most applications using HEMT transistors.

[0071] One could also consider producing a structure in which the gate region 110G would not be embedded in the layers 108, 106 and 104. This would amount, for example, to forming the gate electrode 112G on and in contact with the layer 108. For example, one could in particular provide for an implantation of fluorine ions (F+) in the layer 106, directly above the gate electrode 112G, which would have the effect of attenuating or interrupting the two-dimensional electron gas 2DEG under the gate of the transistor 100. This would, however, tend to complicate control of the threshold voltage Vth.

[0072] Alternatively, it would be possible to omit layer 114, to produce gate electrode 112G above layer 108 and to insert a layer of P-type doped gallium nitride (p-GaN) between the gate electrode and layer 108. However, this would not make it possible to achieve a threshold voltage Vth that is sufficiently high for the intended applications.

[0073] One could also consider reducing the width of the lower face 116B of the vertical part of the T formed by the grid region 110G, so as to reduce the length of the horizontal conduction path 118B. However, this would not significantly reduce the on-state resistance Ron of the transistor 100.

[0074] [Fig.2] is an electrical diagram equivalent to transistor 100 of [Fig. 1].

[0075] As illustrated in [Fig.2], the resistance Ron in the on state of the transistor 100, between its source terminal 112S and its drain terminal 112D, can be decomposed into: - a resistance Rgs, corresponding to a conduction path using the part of the two-dimensional electron gas 2DEG located between the source electrode 112S and the grid electrode 112G; - another resistor Rtl, corresponding to the conduction path 118L taken by the electrons to descend along the side 116L of the electrode 112G; - yet another resistance Rg, corresponding to the conduction path 118B taken by the electrons to move horizontally under the bottom 116B of the electrode 112G; - yet another resistor Rt2 corresponding to the conduction path 118R taken by the electrons to go up along the side 116R of the electrode 112G; and - yet another resistance Rgd, corresponding to a conduction path using the part of the two-dimensional electron gas 2DEG located between the gate electrode 112G and the drain electrode 112D.

[0076] The resistors Rgs, Rtl, Rg, Rt2 and Rgd, whose series association is equivalent to the resistance Ron by neglecting the ohmic contact resistances of source and drain, are detrimental to the operation of the transistor 100 as has been explained previously in relation to [Fig.l]. In particular, the resistors Rtl and Rt2 generally have a significant value, which strongly impacts the resistance Ron in the on state of the transistor 100.

[0077] [Fig. 3] is a schematic and partial sectional view of an electronic device 300 according to a first embodiment.

[0078] The device 300 is for example formed on a substrate 302 similar to the substrate 102 previously described in relation to [Fig.l].

[0079] In the orientation of [Fig.3], a layer 304 covers an upper face 302T of the substrate 302. For example, the layer 304 is made of gallium nitride (GaN), for example intrinsic gallium nitride, i.e. not intentionally doped.

[0080] In the example shown: - another layer 306, for example made of aluminum-gallium nitride (AlGaN), covers an upper face 304T of the layer 304; - yet another layer 308, for example a silicon nitride (SiN) passivation layer, covers an upper face 306T of the layer 306; and - yet another layer 310, for example made of alumina (A12O3), covers an upper face 308T of the layer 308.

[0081] According to one embodiment, the device 300 comprises a semiconductor region 312, located on the gallium nitride layer 304, and two electrodes 314L (D) and 314R (D), located on either side of the semiconductor region 312. In the example shown, the semiconductor region 312 and the electrodes 314L and 314R partially penetrate inside the gallium nitride layer 304. The electrodes 314L and 314R are isolated from the region 312, in other words the electrodes 314L and 314R are not in contact with the region 312. Each electrode 314L, 314R is for example separated from the region 312 by a distance of between 10 and 20 μm, for example equal to approximately 10 μm, in order to ensure a voltage resistance for example up to 1000 V.

[0082] The semiconductor region 312 is made of a different material than that of the layer 304. The region 312 is preferably made of silicon (Si) or silicon carbide (SiC).

[0083] In the device 300, a two-dimensional electron gas 2DEG, symbolized in [Fig. 3] by a dotted line, is present in the layer 304 near an interface between the layers 304 and 306. The electrodes 314L and 314R of the device 300 are both in contact with the two-dimensional electron gas 2DEG. In the example shown, the two-dimensional electron gas 2DEG is interrupted by the region 312 and thus comprises two parts located on either side of the region 312 (to the left and to the right of the region 312, in the orientation of [Fig. 3]).

[0084] In the example shown, flanks 312L and 312R of the semiconductor region 312, located respectively opposite the electrodes 314L and 314R, are coated with conductive regions 316L and 316R. The conductive regions 316L and 316R extend for example over the entire height of the flanks 312L and 312R of the semiconductor region 312 and extend onto and in contact with an upper face 310T of the layer 310. In particular, in this example, the conductive regions 316L and 316R penetrate inside the layer 304 of gallium nitride and each contact a portion of the two-dimensional electron gas 2DEG. Each portion of the two-dimensional electron gas 2DEG thus extends laterally between one of the conductive regions 316L, 316R and the electrode 314L, 314R facing it.

[0085] According to one embodiment, the device 300 further comprises two insulated gate field effect transistors T1 and T2 (MOSFET), also called MOSFET transistors or, more simply, MOS transistors. The transistors T1 and T2 are more precisely lateral MOS transistors formed in and on the semiconductor region 312. In the example shown, each MOS transistor T1, T2 comprises a gate region 318G located directly above a channel region 318C between a channel region 318S and a gate region 318C. source and a drain region 318D. Regions 318S and 318D are formed in the semiconductor region 312. Region 318C is also located in the semiconductor region 312. The gate region 318G of each MOS transistor T1, T2 comprises, for example, an insulating region 320, located on and in contact with an upper face of the region 312 above the channel region 318C, and a conductive region 322 covering an upper face of the insulating region 320. Regions 320 and 322, for example, respectively form a gate insulator, or oxide, and a gate electrode of the MOS transistor.

[0086] The drain regions 318D of the transistors T1 and T2 are respectively located on and in contact with portions of the conductive regions 316L and 316R. In this way, the conductive regions 316L and 316R make it possible to establish electrical contact between, on the one hand, the drain regions 318D of the transistors T1 and T2 and, on the other hand, the portions of the two-dimensional electron gas located on the side of the electrodes 314L and 314R of the device 300. The conductive regions 316L and 316R each have a substantially zero resistance, thus advantageously allowing electrons to flow easily between the portions of the two-dimensional electron gas 2DEG and the drain regions 318D of the transistors T1 and T2.

[0087] In the example shown, the device 300 further comprises another electrode 314C (S) located between the two MOS transistors T1 and T2. The electrode 314C is carried by the semiconductor region 312. More precisely, in this example, the electrode 314C is located on and in contact with the upper face of the region 312 directly above a well 324 formed in the region 312.

[0088] The source regions 318S and 318D of the drain regions of the MOS transistors T1 and T2 are for example doped with a first conductivity type, for example n-type, while the well 324 and the other parts of the semiconductor region 312 are for example doped with a second conductivity type opposite to the first conductivity type, p-type in this example. More precisely, the regions 318S and 318D are for example heavily doped n-type (n+), while the well 324 is heavily doped p-type (p+) and the remaining parts of the region 312 are lightly doped p-type (p-). In this case, the channel regions 318C of the MOS transistors T1 and T2 are lightly doped p-type. Alternatively, well 324 may however be omitted, with electrode 314C then being in direct contact with a portion of lightly doped p-type region 312.

[0089] The electrodes 314L and 314R of the device 300 are intended to be brought to the same potential, for example equal to approximately 650 V, while the electrode 314C is brought to a reference potential, for example ground (0 V). The electrodes 314L and 314R are for example comparable to drain electrodes of the device 300 while the electrode 314C is comparable to a source electrode of the device 300.

[0090] Each MOS transistor T1, T2 is configured to control the passage of an electric current between one of the electrodes 314L, 314R and the electrode 314C, for example as a function of a control potential applied to the gate electrode 322 of the transistor. The transistors T1 and T2 are for example controlled simultaneously by the application, on their respective gate electrodes 322, of a common potential (with respect to the source electrode 314C) making it possible, depending on its value, to interrupt or establish the current between the electrode 314L, 314R and the electrode 314C.

[0091] When the transistor T1, T2 is in an on state, an electric current flows between the electrode 314L, 314R and the electrode 314C. This electric current passes more precisely: - by the part of the two-dimensional electron gas 2DEG located between the electrode 314L, 314R and the conductive region 316L, 316R opposite this electrode; - by the conductive region 316L, 316R; - by the drain regions 318D, channel regions 318C and source regions 318S of the transistor T1, T2; and - through well 324.

[0092] An advantage of the device 300 lies in the fact that it makes it possible to decouple the voltage holding function, performed by the distance separating each electrode 314L, 314R from the semiconductor region 312, and the switching function, performed by the lateral MOS transistors T1 and T2. This allows the device 300 to have an operation similar to that of a HEMT transistor whose source electrode would correspond to the electrode 314C, whose drain electrode would correspond to the electrodes 314L and 314R and whose control would be carried out by biasing the gate electrodes 322 of the MOS transistors T1 and T2.

[0093] Because the switching function is performed by the MOS transistors T1 and T2, which each have a threshold voltage of the order of 5 V, the device 300 advantageously has a threshold voltage higher than that of the HEMT transistor 100 of [Fig.l].

[0094] Furthermore, the p-type doping (p+) of the well 324 advantageously makes it possible to form a good ohmic contact, and therefore to obtain a low contact resistance, between the electrode 314C and the region 312. This improves the energy efficiency of the device 300 by reducing its resistance Ron in the on state.

[0095] The device 300 is also more compact than a device in which at least one transistor analogous to transistors T1 and T2 would be located outside the region delimited by electrodes 314L and 314R, for example on a separate chip.

[0096] [Fig.4] is an electrical diagram equivalent to the electronic device 300 of [Fig.3].

[0097] The resistance Ron in the on state of the device 300, between its electrodes 314L, 314R and its electrode 314C, can be broken down into two resistors RL and RR associated in parallel. Each resistor RL, RR more precisely comprises a series association: - a resistance RdsL, RdsR corresponding to a conduction path using the part of the two-dimensional electron gas 2DEG located between the electrode 314L, 314R and the conductive region 316L, 316R; and - another resistor RcL, RcR corresponding to a conduction path through the channel region 318C of the transistor Tl, T2.

[0098] The resistance RdsL is for example substantially equal to the resistance RdsR, apart from manufacturing variations. Similarly, the resistance RcL is for example substantially equal to the resistance RcR, apart from manufacturing variations.

[0099] In the diagram of [Fig.4], contact resistances as well as resistances corresponding to conduction paths through the conductive regions 316L, 316L, through the drain regions 318D and 318S of the source and through the well 324 are not represented, these resistances being able for example to be considered as negligible compared to the resistances RdsL, RdsR, RcL and RcR.

[0100] Each resistance RdsL, RdsR of the device 300 is for example substantially equivalent to the resistance Rgd of the transistor 100. Each resistance RcL, RcR is lower than the resistances Rtl, Rg and Rt2. This comes in particular from the fact that the conduction paths through the region 318C have a shorter length and a lower resistivity than the conduction paths 118L, 118B and 118R inside the gallium nitride layer 304. The device 300 thus advantageously has a resistance Ron in the on state lower than that of the transistor 100. Furthermore, the device 300 advantageously makes it possible to avoid the trapping and current collapse phenomena previously mentioned in relation to [Fig.l].

[0101] [Fig. 5] is a schematic and partial sectional view of an electronic device 500 according to a second embodiment. The device 500 of [Fig. 5] comprises elements in common with the device 300 of [Fig. 3]. These common elements will not be detailed again below. The device 500 of [Fig. 5] differs from the device 300 of [Fig. 3] mainly in that the conductive regions 316L and 316R of the device 500 do not cover the sides 312L and 312R of the semiconductor region 312.

[0102] More specifically, in the device 500, each conductive region 316L, 316R comprises, for example, a conductive via 502L, 502R partially penetrating inside the gallium nitride layer 304. The via 502L, 502R contacts the part of the two-dimensional electron gas 2DEG located on the side of the electrode 314L, 314R. As illustrated in [Fig.5], each conductive region 316L, 316R further comprises a portion extending over and in contact with the drain region 318D of the transistor T1, T2.

[0103] The conductive regions 316L and 316R of the device 500 advantageously make it possible, as previously described in relation to [Fig. 3], to facilitate the circulation of electrons between the parts of the two-dimensional electron gas 2DEG and the drain regions 318D of the transistors T1 and T2.

[0104] In the example shown, the device 500 optionally further comprises a layer 504 formed inside the gallium nitride layer 304. The layer 504 is for example an insulating layer doped with the second conductivity type, in this example the p type, and called a back-barrier layer. For example, the layer 504 is made of aluminum gallium nitride (AlGaN) and has an aluminum content of, for example, between 10 and 15%. The layer 504 has for example a thickness of between 50 and 100 nm and is located at a distance of approximately 50 nm from a lower face 312B of the region 312.

[0105] The presence of the layer 504 in the device 500 advantageously makes it possible to confine the electrons in a thin part of the layer 304, between the layer 504 and the upper face 304T of the layer 304. This avoids, or limits, a volume trapping of the electrons inside the layer 304. In addition, the layer 504 advantageously makes it possible to further isolate the semiconductor region 312 with respect to the substrate 302, thus avoiding or limiting for example the appearance of a vertical current, coming from the substrate 302, following an interruption of the current flowing between the electrodes 314L, 314R and the electrode 314C when the device 500 is switched from the on state to the off state.

[0106] Another advantage of this embodiment lies in the fact that the conductive vias 502L and 502R can be produced independently of the semiconductor region 312. This allows in particular greater freedom in adjusting the dimensions of these vias. The vias 502L and 502R and the electrodes 314L and 314R can furthermore advantageously be produced during the same step, for example at the end of production of the device 500.

[0107] [Fig. 6] is a schematic and partial sectional view of an electronic device 600 according to a third embodiment. The device 600 of [Fig. 6] comprises elements in common with the device 500 of [Fig. 5]. These common elements will not be detailed again below. The device 600 of [Fig. 6] differs from the device 500 of [Fig. 5] mainly in that the semiconductor region 312 does not penetrate inside the gallium nitride layer 304.

[0108] More precisely, in the device 600, the lower face 312B of the semiconductor region 312 is located at the level of the layer 308, for example on and in contact with the upper face 308T of the layer 308 or in the thickness of the layer 308. lower face 312B of region 312 is thus isolated from gallium nitride layer 304 by all or part of layer 308 and by layer 306. In device 600, region 312 has, compared to devices 300 and 500, a lesser thickness. This advantageously makes it possible to limit or avoid lateral leaks in region 312 and to obtain better electrostatic control. The thickness of region 312 is for example adapted as a function of an intensity of a current flowing in device 600 in the on state, that is to say when transistors T1 and T2 are controlled in the on state.

[0109] Compared to the device 500, the device 600 is furthermore devoid of the layer 504 in the example illustrated in [Fig. 6]. Alternatively, the layer 504 may however be provided in the device 600 to obtain advantages similar to those set out in relation to [Fig. 5].

[0110] By way of example, the semiconductor region 312 is produced by a silicon-on-insulator (SOI) wafer manufacturing process, for example the process known under the trade name “SMART CUT” from the company SOITEC. In this case, a thin layer of silicon is for example transferred above the layer 304, for example by bonding to the layer 308. This thin layer of silicon is then thinned by grinding, until a thickness of for example between 50 and 100 nm is obtained, then etched so as to form the region 312 of each device 600. The semiconductor region 312 can thus advantageously be made of a crystalline material, for example silicon or crystalline silicon carbide, within which the mobility of the electrons is greater due to a low presence of defects. This makes it possible to further reduce the on-state resistance Ron of the device 600.

[0111] Another advantage of the device 600 lies in the fact that a portion of the two-dimensional electron gas 2DEG is present under the semiconductor region 312, between the two conductive vias 502L and 502R. This makes it possible to deplete, by electrostatic effect, the p-type doped region 312. As a result, the threshold voltage of the device 600 is increased in particular compared to the device 500.

[0112] As a variant, the semiconductor region 312 may in this case be undoped, with the exception of the regions 318S and 318D and possibly the well 324, due to the presence of the two-dimensional electron gas 2DEG under the region 312. The channel regions 318C of the transistors T1 and T2 are in this case undoped.

[0113] [Fig.7] is a schematic and partial sectional view of an electronic device 700 according to a fourth embodiment. The device 700 of [Fig.7] comprises elements in common with the device 600 of [Fig.6]. These common elements will not be detailed again below.

[0114] The device 700 of [Fig.7] differs from the device 600 of [Fig.6] mainly in that the device 700 comprises two electrodes 702L (S) and 702R (S) carried by the semiconductor region 312 and located on either side of the transistors T1 and T2 on and in contact with the source regions 318S of these transistors. Furthermore, in the device 700, the two-dimensional electron gas 2DEG is electrically connected to the drain regions 318D of the transistors T1 and T2 by a single conductive region 704. The region 704 comprises for example a conductive via 706 completely crossing the region 312, the layer 308 and the layer 306 and partially penetrating inside the layer 304 of gallium nitride. In order to obtain low contact resistances, the conductive region 704 may, as illustrated in [Fig.7], comprise a portion extending laterally over and in contact with the drain regions 318D of the transistors T1 and T2, the transistors T1 and T2 being located on either side of the conductive via 706.

[0115] In the example shown, the source regions 318S of the transistors T1 and T2 are separated from the upper face 310T of the layer 310 by heavily doped regions 708 of the second conductivity type, here the p type (p+). The regions 708 located on either side of the conductive via 706 contact the electrodes 702L and 702R respectively. The regions 708 contribute to maintaining the potential of the part of the lightly doped p type (p-) layer 312 at the value of the source potential. Alternatively, the regions 708 are omitted.

[0116] An advantage of the device 700 lies in the fact that the electrodes 702L and 702R ensure better current distribution. This thus makes it possible to limit or avoid heating of the device 700 in the on state.

[0117] Figures 8 to 15 below illustrate successive steps of an example of an embodiment of a method for producing the device 300 of [Fig.3].

[0118] [Fig.8] is a schematic and partial sectional view illustrating a step in the method of implementing the method for producing the device 300 of [Fig.3].

[0119] During this step, the layers 304, 306, 308 and 310 are successively produced, in this order, on the side of the face 302T of the substrate 302. More precisely: - the layer 304 extends continuously and over the entire upper face 302T of the substrate 302; - the layer 306 extends continuously and over the entire upper face 304T of the layer 304; - the layer 308 extends continuously and over the entire upper face 306T of the layer 306; and - the layer 310 extends continuously and over the entire upper face 308T of the layer 308.

[0120] Layers 304, 306, 308 and 310 are for example produced by epitaxy. Although this is not shown in [Fig.8], an intermediate layer of aluminum nitride (AIN) can be intercalated between layers 304 and 306. If necessary, this makes it possible to promote the epitaxy of the aluminum-gallium nitride layer 306 on the gallium nitride layer 304 by adaptation of the lattice parameter.

[0121] In [Fig.8], the two-dimensional electron gas 2DEG extends laterally and continuously in the layer 304, under the upper face 304T of the layer 304.

[0122] [Fig.9] is a schematic and partial sectional view illustrating a subsequent step in the method of implementing the method for producing the device 300 of [Fig.3].

[0123] During this step, a trench 902 is made extending vertically towards the substrate 302 from the upper face 310T of the layer 310. More precisely, in the example shown, the trench 902 passes through the layers 310, 308 and 306 and partially penetrates into the thickness of the layer 304. The trench 902 stops in the layer 304 and does not reach the upper face 302T of the substrate 302.

[0124] For example, trench 902 is produced by atomic layer etching (ALE).

[0125] The trench 902 has side walls 902L and 902R and a bottom 902B which correspond respectively to the sides 312L and 312R and to the bottom 312B of the future semiconductor region 312 of the device 300.

[0126] In the example shown, the side walls 902L and 902R of the trench 902 are oblique. More precisely, the trench 902 is for example etched so that its side walls 902L and 902R each form an angle α with respect to a normal to the upper face 310T of the layer 310. By way of example, the angle α formed by the walls 902L and 902R is between 5° and 45°, for example equal to approximately 10°. The trench 902 thus has a flared profile comprising an opening (at the top, in the orientation of [Fig. 9]) wider than its bottom 902B (at the bottom, in the orientation of [Fig. 9]). The inclination of the side walls 902L and 902R of the trench 902 results for example from an isotropic chemical etching step. As a variant, the trench 902 may have side walls 902L and 902R that are substantially vertical, that is to say, whose angle α is equal to approximately 0°.

[0127] For example, trench 902 has: - a maximum width Lmax between 0.4 and 1 pm, for example equal to approximately 0.5 pm; and - a minimum width Lmin between 0.2 and 0.4 pm, for example equal to approximately 0.3 pm.

[0128] Alternatively, the side walls 902L and 902R of the trench 902 are substantially vertical, the angle α being in this case equal to approximately 0°.

[0129] The electrodes 314L and 314R are then formed on either side of the trench 902. For example, the electrodes 314L and 314R are obtained by deposition then local etching of a metallic layer (not shown) coating the upper face of layer 310.

[0130] At the end of this step, the two-dimensional electron gas 2DEG is discontinuous. More precisely, the trench 902 separates the two-dimensional electron gas 2DEG into two parts located on either side of the trench 902. The layers 306, 308 and 310 are further separated each into two parts of disjoint layers located on either side of the trench 902.

[0131] [Fig. 10] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the device 300 of [Fig. 3],

[0132] During this step, a conductive layer 1002 is deposited on the structure. The conductive layer 1002 covers the upper face 310T of the parts of the layer 310 as well as the side walls 902L, 902R and the bottom 902B of the trench 902.

[0133] For example, the conductive layer 1002 is produced by a conformal deposition technique, for example by chemical vapor deposition (CVD). This avoids, or limits, the presence of crystalline defects at the interface between the layers 304 and 1002, these defects being capable of forming trap states for the electrons.

[0134] [Fig. 11] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the device 300 of [Fig. 3],

[0135] During this step, the conductive layer 1002 is etched so as to expose the bottom 902B of the trench 902. For this purpose, a portion of the layer 1002 coating the bottom 902B of the trench 902 is eliminated. The layer 1002 is thus separated into two separate portions. More precisely, at the end of the etching, the conductive regions 316L and 316R are obtained, respectively coating the walls 902L and 902R of the trench 902. Given that the electrodes 314L and 314R are at the same potential, it is possible alternatively to provide a single-piece conductive region, i.e. continuously coating the sides 902L, 902R and the bottom 902B of the trench 902.

[0136] In the example shown, the layer 1002 is further etched on the side of the electrodes 314L and 314R, that is to say on the left and on the right in the orientation of [Fig. 11], so as to expose parts of the upper face 310T of the layer 310 located between the electrodes 314L, 314R and the future semiconductor region 312.

[0137] By way of example, the conductive regions 316L and 316R are produced by a wet etching process of the layer 1002. This makes it possible in particular to obtain low roughness at the bottom 902B of the trench 902.

[0138] The wet etching may be preceded by a dry etching step, for example plasma-assisted. In this case, the wet etching allows an improvement in the state of surface, obtained at the end of the dry etching step, of the bottom 902B of the trench 902.

[0139] [Fig. 12] is a schematic and partial sectional view, illustrating a further step in the mode of implementation of the method for producing the device 300 of [Fig. 3],

[0140] During this step, the semiconductor region 312 is produced inside the trench 902. In the example shown, the region 312 completely fills the trench 902 and extends laterally onto and in contact with an upper face of the parts of the conductive regions 316L and 316R located above the parts of the layer 310.

[0141] The semiconductor region 312 is for example produced by a conformal deposition technique, for example by chemical vapor deposition (CVD) of lightly doped p-type polycrystalline silicon (p-).

[0142] [Fig. 13] is a schematic and partial sectional view, illustrating a further step in the method of implementing the method for producing the device 300 of [Fig. 3],

[0143] During this step, the semiconductor region 312 is doped to form the regions 318D and 318S of the future MOS transistors T1 and T2 and the well 324. For example, the doping of the region 312 is carried out by ion implantation.

[0144] [Fig. 14] is a schematic and partial sectional view, illustrating a further step in the mode of implementing the method for producing the device 300 of [Fig. 3],

[0145] During this step, the gate oxide 320 of each future MOS transistor T1, T2 is produced on and in contact with the drain regions 318D, channel regions 318C and source regions 318S of the transistor. For example, an oxide layer, for example alumina (A12O3), having a thickness of between 10 and 30 nm is deposited on the structure and then etched so as to form the gate oxides 320 of the future MOS transistors T1 and T2.

[0146] [Fig. 15] is a schematic and partial sectional view, illustrating a further step in the mode of implementing the method for producing the device 300 of [Fig. 3],

[0147] During this step, the gate electrode 322 of each MOS transistor T1, T2 is produced on and in contact with the corresponding gate oxide 320. For example, a conductive layer, for example made of an alloy of titanium nitride (TiN) and tungsten (W), is deposited on the structure and then etched so as to form the gate electrodes 322 of the MOS transistors T1 and T2.

[0148] From the structure described in relation to [Fig. 15], the electrode 314C is then produced in order to obtain the device 300 exposed in relation to [Fig. 3]. By way of example, the electrode 314C is obtained by deposition then local etching of a metal layer (not shown) coating the structure. The electrode 314C of the device 300 ([Fig.3]) is more precisely formed on and in contact with an upper face of the well 324 previously formed inside the semiconductor region 312.

[0149] Various embodiments, implementations, and variations have been described. Those skilled in the art will understand that certain features of these various embodiments, implementations, and variations could be combined, and other variations will occur to those skilled in the art.

[0150] From the above indications, the person skilled in the art is in particular capable of providing devices similar to the devices 300, 600 and 700 but comprising an insulating layer similar to the layer 504 of the device 500 inside the layer 304 of gallium nitride.

[0151] Furthermore, the adaptation of the method for producing the device 300 described in relation to figures 8 to 15 in order to obtain the devices 500, 600 and 700 of figures 6, 7 and 8 respectively, as well as the devices of the other embodiments and variants mentioned in the present description, is also within the reach of those skilled in the art.

[0152] Finally, the practical implementation of the embodiments, implementation modes and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the person skilled in the art is capable of choosing the materials of the conductive regions 316L, 316R and 704, as well as the doping rates of each of the regions 312, 318S, 318D, 708 and of the well 324 depending on the intended application.

Claims

Claims

1. Electronic device (300; 500; 600; 700) comprising: - a semiconductor region (312) located on a layer (304) of gallium nitride and partially penetrating said layer; - two electrodes (314L, 314R), located on either side and insulated from the semiconductor region, the electrodes partially penetrating the layer of gallium nitride; and - two lateral MOS transistors (Tl, T2) formed in and on the semiconductor region.

2. Device according to claim 1, in which each transistor (T1, T2) is configured to control the passage of an electric current between one of said electrodes (314L, 314R) and one or more second electrodes (314C; 702L, 702R) carried by the semiconductor region (312).

3. A device according to claim 1 or 2, wherein each transistor (T1, T2) comprises a gate region (318G) located directly above a channel region (318C) between source (318S) and drain (318D) regions formed in the semiconductor region (312).

4. Device according to claim 3, in which the source regions (318S) of the transistors (T1, T2) are doped with a first conductivity type and separated by a well (324) formed in the semiconductor region (312) and doped with a second conductivity type, opposite to the first conductivity type.

5. Device according to any one of claims 2 to 4, wherein the drain region (318D) of each transistor (T1, T2) is connected, via a two-dimensional electron gas (2DEG), to one of said electrodes (314L, 314R).

6. Device according to claim 5, further comprising one or more conductive regions (316L, 316R; 704) contacting the drain regions (318D) of the transistors (T1, T2) and partially penetrating the gallium nitride layer (304).

7. Device according to claim 6, comprising exactly two conductive regions (316L, 316R) covering opposite sides (312L, 312R) of the semiconductor region (312) located opposite said electrodes (314L, 314R) and a single second electrode (314C) located between the transistors (T1, T2).

8. A device according to claim 6, comprising exactly two regions conductive (316L, 316R) comprising conductive vias (502L, 502R) located on either side of the semiconductor region (312) and a single second electrode (314C) located between the transistors (Tl, T2).

9. Device according to claim 6, comprising a single conductive region (704) comprising a conductive via (706) crossing the semiconductor region (312) and exactly two second electrodes (702L, 702R) located on either side of the transistors (Tl, T2).

10. A device according to any one of claims 1 to 9, wherein the semiconductor region (312) partially penetrates inside the gallium nitride layer (304).

11. A device according to any one of claims 1 to 9, wherein a lower portion (312B) of the semiconductor region (312) is insulated from the gallium nitride layer (304).

12. Device according to any one of claims 1 to 11, in which the first electrodes (314L, 314R) are intended to be brought to the same potential.

13. Device according to any one of claims 1 to 12, in which the semiconductor region (312) is made of a material different from that of the gallium nitride layer (304), preferably silicon or silicon carbide.

14. A method of producing a device (300; 500; 600; 700) according to any one of claims 1 to 13, the method comprising the following steps: a) forming a trench (902) inside the gallium nitride layer (304); b) forming the first electrodes (314L, 314R) on either side of the trench; c) filling the trench with the semiconductor region (312); and d) forming the MOS transistors (T1, T2).

15. A method according to claim 14 for producing a device according to claim 2, further comprising, after step d), the step of forming the second electrode(s) (314C; 702L, 702R).

16. A method according to claim 14 for producing a device according to claim 6, wherein the conductive region(s) (316L, 316R; 704) are formed in step b).

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