High-mobility electronic transistor with reduced access resistance and method for manufacturing a high-mobility electronic transistor with reduced access resistance

Abstract

The invention relates to a high electron mobility transistor (400) comprising: A stack of layers comprising a passivation layer (401) and a heterojunction comprising a first semiconductor layer (402), a second semiconductor layer (403) and a two-dimensional electron gas (404) at their interface, a surface of the passivation layer (401) being in contact with the first semiconductor layer (402); A metallic source contact (405) and / or a metallic drain contact and a gate electrode (406); An n+ doped region (407) located inside the heterojunction;the metallic source contact (405) and / or the metallic drain contact being positioned in a recess formed in the layer stack, said metallic source contact (405) and / or said metallic drain contact having a thickness defined by an upper face (405a) and a lower face (405b) substantially parallel to the layer plane, the upper face (405a) being flat, the lower face (405b) being in contact with the n+ doped area (407) and below the interface between the first semiconductor layer (401) and the second semiconductor layer (402), said metallic source contact (405) and / or said metallic drain contact further having a lateral face (405c), the n+ doped area extending from the lateral face of the metallic source contact (405) and / or from the lateral surface of the drain contact towards the gate electrode (406) over a length of between 300 and 1000 nm. Figure to be published with the abbreviation: FIGURE 4;

Description

Title of the invention: High-mobility electronic transistor with reduced access resistance and method for manufacturing a high-mobility electronic transistor with reduced access resistance TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates to the field of high-electron-mobility field-effect transistors for high-frequency applications. One object of the invention is a high-electron-mobility transistor with reduced access resistance. Another object of the invention is a method for manufacturing such a transistor. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Many electronic applications require devices operating at high frequencies, for example above the X band with a frequency around 10 GHz. Examples of such devices include power amplifiers, low-noise amplifiers, oscillators, and switches. Such devices can be used in radar, telecommunications, and embedded electronics for the automotive, transportation, and aerospace industries, as well as in medical applications and home automation.

[0003] High-frequency electronic devices often employ high electron mobility transistors (HEMTs). These transistors are also known as heterojunction field-effect transistors. A HEMT comprises a superposition of two semiconductor layers with different band gap energies. This superposition results in the formation of a quantum well at the interface between the two layers. The quantum well confines electrons to form a two-dimensional electron gas (2DEG). For example, the layer with the higher band gap energy, or barrier layer, could be made of AlGaN. The layer with the lower band gap energy, or channel layer, could be made of GaN.

[0004] Figure 1 shows a schematic cross-sectional view of a HEMT transistor according to the prior art. The HEMT transistor includes a heterojunction comprising a first semiconductor layer or barrier layer made of AlGaN and a second semiconductor layer or channel layer made of GaN, as well as a passivation layer P above the barrier layer. A two-dimensional electron gas (2DEG) is formed at the AlGan / GaN interface. The transistor in [Fig. 1] further comprises a source contact (S), a drain contact (D), and a gate electrode (G). The 2DEG gas is electrically connected to the source contact (S) and the drain contact (D). The gate electrode (G) has a T-shaped form, with its gate foot close to the AlGaN barrier layer. The gate foot is in direct contact with the barrier in the case of a Schottky gate, or with a very thin dielectric between the gate electrode and the barrier in the case of a Metal-Insulator-Semiconductor (MIS) gate.

[0005] HEMT transistors must have the lowest possible source resistance or access resistance Rs in order to avoid degradation of the intrinsic performance of the transistor, the resistance Rs being defined as the resistance between the source metal and the foot of the T-gate. Indeed, the source resistance degrades the intrinsic transconductance, the transition frequency and the maximum oscillation frequency of the transistors.

[0006] It is important to consider that Rs must be minimal both at room temperature and at the operating temperature of the transistor access region. In power mode, a HEMT operates at a junction temperature of 175°C to 225°C. The access regions are therefore at temperatures above 100°C, for example, between 100 and 150°C.

[0007] The source or access resistance is the sum of several resistances, the most important of which are: • The resistance of the ohmic contact: RC(T°) • The resistance of the 2DEG gas: R2deg(T°) over a length Lgs separating the source metal and the base of the grid. This resistance increases by a factor of approximately 2.2 at 150°C.

[0008] The techniques usually used to reduce source resistance are as follows: • improve the contact resistance Rc; • reduce the distance between the grid and the source Lgs; this technique is limited by lithography, the drawing rules between the source contact and the grid foot and by the increase in grid-source parasitic capacitances Cpgs; • reduce the layer resistance of the 2DEG, R2deg; this technique is limited not only by the characteristics of the heterojunction but also and especially by the fact that this resistance increases sharply with temperature due to the degradation of electron mobility; • introduce a very heavily doped layer between the contact and the 2DEG (n+ layer).

[0009] An example of a HEMT transistor with low access resistance is disclosed in The document “GaN-on-Si mm-wave RF Devices Integrated in a 200mm CMOS Compatible 3-Level Cu BEOL” by B. Parvais et al., IEDM 2020. Figure 2 shows a cross-sectional view of such a device according to the state of the art. In this case, the HEMT access is a lateral ohmic contact, or “full recess” in English terminology. This approach allows direct contact between the 2DEG and the ohmic contact metal using an etching of the passivation and barrier layers. Such an etching of the passivation and barrier layers is also called a recess.

[0010] This technique makes it possible to obtain a good ohmic contact resistance, on the order of 0.3 Ohm.mm. The metal of the ohmic contact of the access point is produced by deposition and etching and must extend beyond the contact opening. As shown in [Fig. 2], such a contact does not allow the ohmic contact to be brought sufficiently close to the base of the T-grid, with a distance Lgs of 0.64 pm. Moreover, this approach presents a technological difficulty in the etching of the ohmic metal. Indeed, the excessive overhang of the ohmic metal from the contact leads to a parasitic gate-source capacitance Cpgs. This results in a significant degradation of the transition frequency, with a reduction of around 25%. This prevents the use of this device in the millimeter-wave or high-frequency range.

[0011] Moreover, the resistance of the 2DEG is then on the order of 0.3 Ohm.mm at room temperature and greater than 0.6 Ohm.mm at operating temperature, which strongly penalizes the source access resistance during the use of the device.

[0012] This technology is therefore not suitable for achieving a very compact source access for high-frequency components.

[0013] Another example of a HEMT transistor having low access resistance is described in the paper “Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications” by Keisuke Shinohara et al., published in IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 60, No. 10, 2013.

[0014] Figure 3 illustrates a schematic cross-sectional view of such a state-of-the-art device. In this case, the contact is made in three steps. First, the AlGaN / GaN heterostructure is etched, then a heavily n+-doped GaN layer is locally re-epitaxialized in the etched area. Finally, a metallic contact is made on the n+ GaN.

[0015] This type of access offers very good performance but is difficult to implement because it requires: • excellent control of barrier etching; the quality of GaN n+ re-epitaxy on the etch background and flank is highly dependent on the etch background morphology; • Reintroduction of the wafer into equipment for metal-organic chemical vapor deposition (MOCVD); this is necessary for epitaxy. of III-N semiconductor material combining atoms from column III of the periodic table of elements with nitrogen N, which makes compatibility with a CMOS type cleanroom difficult due to possible contamination and increases the cost; • a localized growth of GaN material which is difficult to mask.

[0016] Even though this technique is very efficient, it is very difficult to integrate into a low-cost industrial process and into a CMOS-compatible cleanroom.

[0017] A person skilled in the art is therefore unaware of a HEMT transistor with low access resistance that is suitable for high-frequency applications and simple to manufacture. In other words, there is currently no HEMT transistor with very low access resistance for high-frequency power components (>30 GHz) that can be produced using a low-cost industrial process and manufactured in a CMOS-compatible cleanroom. Summary of the invention

[0018] The invention aims to at least partially solve the problems mentioned above by providing a HEMT transistor with very low access resistance and reduced source-to-gate and / or drain-to-gate parasitic capacitance, while also being very compact. Furthermore, the HEMT transistor according to the invention exhibits excellent temperature behavior, making it particularly well-suited for high-frequency power applications.

[0019] To this end, an object of the invention relates to a high electronic mobility transistor comprising: • a stack of layers comprising a passivation layer and a heterojunction comprising a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at their interface, a surface of the passivation layer being in contact with the first semiconductor layer; • a metallic source contact and / or a metallic drain contact and a grid electrode; • an n+ doped zone located inside the Theterojunction; the source metallic contact and / or the drain metallic contact being positioned at a recess formed in the layer stack, said source metallic contact and / or said drain metallic contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being flat, the lower face being in contact with the n+ doped area and below the interface between the first semiconductor layer and the second semiconductor layer, said source metal contact and / or said drain metal contact further having a side face, the n+ doped area extending from the side face of the source metal contact and / or from the side face of the drain metal contact to the gate electrode over a length between 300 and 1000 nm.

[0020] In what follows, the invention is described with respect to the source metal contact. However, each characteristic of the source metal contact can also refer to the drain metal contact or to both the source and drain metal contacts. In other words, the transistor according to the invention can have a very low source access resistance, a very low drain access resistance, or a very low source and drain resistance. The n+ doped region is understood to be a region of the heterojunction doped n+ by ion implantation. n+ doping is understood to mean high n doping (i.e., with a donor concentration greater than 10¹⁹ cm³ and preferably greater than 10²⁰ cm³). The n+ doped region makes it possible to reduce the expansion of the two-dimensional electron gas between the source metal contact and the gate electrode while moving said source metal contact further away from the gate electrode.In other words, the source metal contact is set back from the end of the n+ doped area, the setback being the distance between the lateral face of the source contact closest to the gate electrode and the end of the n+ doped area.

[0021] Thanks to the invention, the layer resistance of the n+ doped zone is lower than the resistance of the two-dimensional electron gas and much less sensitive to temperature and the reduction of the extension of the two-dimensional electron gas makes it possible to reduce the access resistance of the source contact.

[0022] Removing the source metal contact from the gate reduces the parasitic capacitance between the source contact and the gate electrode, making the transistor according to the invention very well suited to the high-frequency regime.

[0023] The electrical contact between the metallic source contact and the two-dimensional electron gas is achieved by the fact that the lower face of the source contact is in contact with the n+ doped area. In other words, the source contact forms a recess or niche extending below the interface between the first semiconductor layer or barrier layer and the second semiconductor layer or channel layer.

[0024] In a transistor according to the invention, the contact resistance between the lower face of the source contact and the n+ doped area is very low and very insensitive to the operating temperature, which makes it possible to reduce the source access resistance.

[0025] The flat upper surface of the metallic contact is understood to be a metallic surface having a uniform thickness and a surface free from deformations such as bumps or holes. The flatness of the surface allows the metal at the source contact to be "planed" and prevents its lateral expansion. The surface flatness also allows for optimal control of the subsequent lithography of the grid base, and therefore excellent control of the lithographed shapes and their positioning.

[0026] The flat upper face of the contact makes it possible to obtain a compact, thin and non-overflow contact by further reducing the parasitic capacitances between the source contact and the grid.

[0027] Furthermore, it is observed that the source access is efficient and very insensitive to the operating temperature of the transistor according to the invention.

[0028] The transistor according to the invention may also have one or more of the following characteristics, considered individually or in all technically possible combinations: • the n+ doped zone is an implanted zone having a Gaussian-type spatial doping profile along the direction normal to the plane of the layers; • the lower face of the source metal contact and / or the lower face of the drain metal contact is below the two-dimensional electron gas; • the lower face of the source metallic contact and / or the lower face of the drain metallic contact is at the peak of the Gaussian-type doping spatial profile in the direction normal to the plane of the layers; • the distance Lgs between the grid electrode and the end of the n+ doped area is between 200 nm and 400 nm; • the n+ doped zone is doped with a Si or Ge type dopant with a concentration greater than or equal to 1020 cm3; • the first semiconductor layer comprises AlGaN and the second semiconductor layer comprises GaN; • the first semiconductor layer comprises a material chosen from the group comprising: AlGaN, AIN, InGaAlN, ScAIN; • the first semiconductor layer is a bilayer chosen from the group of bilayers including: AlGaN / AIN, AlGaN / GaN, InAlN / AlN, InGaAlN / AIN, or ScAlN / AlN. • The second semiconductor layer is made of GaN or AlGaN; • the transistor further includes a drain contact having the same structure as the source contact.

[0029] Another object of the invention is a method for manufacturing a high electronic mobility transistor comprising the following steps: • provision of a high electron mobility transistor substrate comprising a layer stack including a passivation layer and a heterojunction comprising a first semiconductor layer, a second a semiconductor layer and a two-dimensional gas of electrons at their interface; • formation of an n+ doped zone by ion implantation inside the heterojunction and activation annealing of the n+ doped zone; • deposition of a dielectric layer in contact with the passivation layer; • etching of the layer stack and the dielectric layer to form a recess directly above and in contact with the n+ doped area, said recess being adapted to accommodate a metallic source and / or drain contact, the lower face of the recess being located below the interface between the first semiconductor layer or barrier layer and the second semiconductor layer or channel layer; • deposition of a metallic layer intended to form the source metallic contact and / or the drain metallic contact; • mechano-chemical polishing of the metallic layer to obtain a planarized top surface of the source contact and / or a planarized top surface of the drain contact; • definition and deposition of a grid electrode, the n+ doped area extending from a lateral face of the source metal contact and / or from a lateral surface of the drain metal contact to the grid electrode over a length between 300 and 1000 nm.

[0030] The process according to the invention makes it possible to obtain an n+ doped area ensuring a very efficient electrical contact which reduces the access resistance of the transistor.

[0031] The process according to the invention is reliable, precise, uniform, reproducible and feasible in a CMOS compatible cleanroom.

[0032] An example of a high electron mobility transistor substrate used in the process according to the invention includes a high resistivity Si < 111> substrate, an AIN nucleation layer, a stress management layer, a GaN or low AlGaN buffer layer, a confinement barrier layer, a GaN channel layer and an AlGaN barrier layer.

[0033] The method according to the invention may also comprise one or more of the steps below, considered individually or in all technically possible combinations: • the n+ doped zone formation step includes a mono-energetic implantation of Si or Ge ions, with an implantation energy between 60 keV and 80 keV (for Si); • the activation annealing of the n+ doped zone includes a heat treatment at 975°C for 10 hours, 1000°C for three hours or at 1050°C for one hour; • the process further includes a photolithography step to define an implantation area intended to accommodate the n+ doped area; • Monoenergetic implantation of Si or Ge ions involves the creation of an n+ doped region with a Gaussian-type spatial doping profile along the direction normal to the plane of the layers. The use of multi-energy implantations does not allow the desired performance to be achieved; • the implantation step is only carried out for the source contact; • The implantation step is performed both for the source contact and for the drain contact. BRIEF DESCRIPTION OF THE FIGURES

[0034] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which:

[0035] Fig. 1 illustrates a schematic cross-sectional view of a HEMT transistor according to the prior art;

[0036] Fig. 2 represents a TEM image of a HEMT transistor according to the prior art and having a "full-recess" type contact with protruding metal;

[0037] Fig. 3 represents a schematic cross-sectional view of a HEMT transistor according to the prior art and comprising a source or drain contact made by etching and re-epitaxy;

[0038] Figure 4 represents a schematic cross-sectional view of part of a HEMT transistor according to the invention;

[0039] Figure 5 represents a TEM cross-section of a transistor according to the invention;

[0040] Figure 6 represents the implantation profile of Si ions according to an embodiment of the transistor according to the invention;

[0041] Figure 7 schematically illustrates the process according to the invention;

[0042] Figures 8a to 8p illustrate the results of the different stages of the process according to the invention of [Fig.7];

[0043] Fig. 9 illustrates the variation of the effective contact resistance of the transistor, Rc, as a function of the variation in operating temperature of the device according to the invention;

[0044] Fig. 10 illustrates the variation of the transition resistance RT as a function of the operating temperature of the device according to the invention;

[0045] Fig. 11 illustrates the variation of the resistance of the n+ doped zone as a function of the operating temperature of the device according to the invention;

[0046] Fig. 12 illustrates the variation of the n+ doped GaN metal contact resistance as a function of the operating temperature of the device according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0047] Figure 3 shows a schematic cross-sectional view of a high-electron-mobility transistor 400 according to the invention. In particular, Figure 3 shows the portion of the transistor 400 comprising a source contact 405 and a gate electrode 406. The transistor 400 according to the invention comprises a stack of layers including a passivation layer 401 and a heterojunction comprising a first semiconductor layer 402 and a second semiconductor layer 403.

[0048] The first semiconductor layer 402 has a higher band gap energy than the second semiconductor layer 403. The first semiconductor layer 402 is also called the barrier layer or barrier. The second semiconductor layer 403 is also called the channel layer or channel. A two-dimensional electron gas or 2DEG 404 is formed at the interface between the barrier layer 402 and the channel layer 403. The passivation layer 401 is in contact with the first semiconductor layer 402.

[0049] According to one embodiment, the passivation layer 401 is a bilayer comprising layers 401a and 401b. According to one embodiment, layers 401a and 401b are made of SiO2 and SiN respectively.

[0050] The transistor 400 according to the invention further comprises the source metal contact 405, a drain metal contact (not shown), and the gate electrode 406. Figure 4 shows only the source contact. The gate electrode 406 is positioned between the source and drain metal contacts. In one embodiment, the gate electrode 406 may be T-shaped, with a gate foot close to the barrier layer 402.

[0051] In other words, [Fig. 4] represents half of the structure of the transistor 400 according to the invention, the drain contact not being shown. According to one embodiment of the invention, the transistor 400 is symmetrical with a drain contact identical to the source contact. The gate-drain distance is greater than or equal to the gate-source distance.

[0052] The transistor 400 according to the invention further comprises an n+ doped region 407 located inside the heterojunction. In other words, one end 408 of the n+ doped region 407 is positioned between the source metal contact 405 or drain and the gate foot.

[0053] The n+ 407 doped zone is obtained by ionic implantation of an n-type dopant.

[0054] According to the embodiment shown in [Fig. 4], the barrier layer 402 is in AlGaN, the GaN channel layer 403, and the n+-doped region 407 are obtained through localized silicon implantation with a Gaussian profile. The ion implantation is combined with optimized activation annealing at 975°C for 10 hours, 1000°C for 3 hours, or 1050°C for 1 hour to form an n+-doped region and a contact efficient.

[0055] According to one embodiment, the heterojunction is a type III-N heterostructure based on Al, In or Ga. Examples of such heterostructures are AlGaN / AlN / GaN, AlGaN / GaN, InGaAlN / AlN / GaN, or AlGaN / AlN / AlGaN in which the channel is made of AlGaN.

[0056] According to one embodiment, the heterojunction is a type III-N heterostructure based on ScAlN. Examples of such heterostructures are ScAlN / GaN or ScAIN / AIN / GaN.

[0057] The source or drain metallic contact 405 is located at a recess 409 formed in the stack of layers. The metallic contact 405 has a thickness defined by an upper face 405a of the metallic contact and a lower face 405b of the metallic contact. The two lower and upper faces of the metallic contact 405 are substantially parallel to the planes of the layers.

[0058] The upper face 405a is flat so as to reduce parasitic capacitances between the grid electrode 406 and the source or drain metal contact 405. In other words, the thickness of the source or drain contact 405 is constant over the entire region of the contact 406. Equivalently, the thickness of the contact 405 is equal to the thickness of the recess.

[0059] The arrangement of the upper face 405a of the metal contact 405 makes it possible to achieve a very compact, thin, and seamless contact, thereby minimizing parasitic capacitances Cpgs between the contact metal 405 and the grid metal. The planarization also improves the control of subsequent lithographs.

[0060] The lower face 405b is in contact with the n+ doped implanted area 407. In other words, the metallic contact 405 forms a recess RE with respect to the surface of the barrier layer 402 and the lower face 405b of the contact 405 is below the interface between the first semiconducting layer 402 and the second semiconducting layer 403.

[0061] The recess RE under the barrier layer 402 reduces the metal / semiconductor layer contact resistance Rc to very low values ​​on the order of 50-70 mOhm.mm. This is possible by positioning the ohmic metal on the n+ doped channel area 407 and not on the barrier layer 402, which has a larger band gap. The minimum depth of the recess RE must be such that the ohmic metal is deposited on the surface of the n+ doped area 407 or, at most, at the depth of the peak of the implantation profile of the n+ doped area 407.

[0062] The contact 405 further comprises a lateral face 405c substantially normal to the plane of the layers. The RET distance between the lateral face 405c and the end 408 of the n+ doped zone 407 is between 300 nm and 1000 nm. In other words, the metallic contact 405 is recessed relative to the end 408 of the n+ doped zone. 407.

[0063] The layer resistance Rsheet associated with the implanted n+ region 407 is very low and less than 60-90 ohms / sq. This allows the metal contact 405 to be moved further away from the gate electrode 406 without significantly increasing the access resistance. In particular, the n+ layer is at least three times more efficient than the 2DEG at room temperature and five times more efficient at 100°C. The RET retraction must be large enough to limit the parasitic capacitance Cpgs and small enough to avoid increasing the resistance of the n+ layer.

[0064] According to one embodiment, the RET distance is between 300 nm and 1000 nm. The RET distance here is equal to 500 nm.

[0065] The transition resistance Rt between the implanted region and the intrinsic region is low thanks to an optimized ionic implantation of Si.

[0066] According to one embodiment, the implantation is mono-energetic at 70 kV / 3-5*1015 / cm2 through a 30 nm surface layer. The use of a multi-energy implantation, common in wide bandgap semiconductors to generate doped cells, would not give similar results because it would lead to a high resistance Rt.

[0067] The distance Lgs between the tip 408 of the doped n+ 407 region and the grid root must be sufficiently large so as not to degrade the voltage withstand capacity of the grid-source or grid-drain junction. In one embodiment, Lgs is greater than or equal to 200 nm.

[0068] The Si implantation exhibits lateral dispersion that must not approach the grid base too closely. Lgs must be sufficiently small to limit the contribution of the 2DEG gas to Rs; for example, Lgs must be less than 400 nm. In one embodiment, Lgs is equal to 300 nm.

[0069] According to one embodiment, the metallic contact 405 comprises a Ti / Al bilayer with a Ti layer thickness between 3nm and 20nm and a total thickness of 200nm + / - 50nm.

[0070] Figure 4 also shows the distribution of source and drain access resistances: the contact resistance Rc, the resistance of the n+ implanted region Rn+, the transition resistance RT, and the resistance of the two-dimensional electron gas 2DEG, R2DEG*

[0071] The access resistance Rs of a source contact of the transistor 400 according to the invention is, at room temperature, T = 30°C:

[0072] Rs = Rc + Rn+ + Rt + R2deg = 0.3 Ohm.mm;

[0073] At T = 150°C: Rs = Rc + Rn+ + Rt + R2deg = 0.35 Ohm.mm

[0074] It can be seen that the access of a transistor 400 according to the invention is efficient and very insensitive to temperature thanks to: • to the small achievable length Lgs, on the order of 300 nm; • to the compensation of R2deg(T°) by Rt(T°) The 400 transistor according to the invention is obtained by a planar process and is compatible with CMOS-type cleanroom manufacturing. Figure 5 shows a TEM cross-section of a 400 transistor according to the invention. Both the source and drain contacts are visible in Figure 5.

[0075] Figure 6 shows the Si implantation profile as a function of depth along a direction normal to the plane of the layers. The implantation profile was obtained for an energy of 70 keV and a dose of 3 × 10¹⁵ / cm² through the surface passivation layer 401 formed by a SiO₂ / SiN bilayer. The position of the metal / GaN n⁺ ohmic contact interface is represented by the dashed line. The profile has a projected penetration depth Rp (for "Projected Range") of 64.5 nm, a dispersion sigma of 23 nm, and a lateral extension of 40 nm. The lateral extension represents the lateral overhang of the profile below the mask.

[0076] Figure 7 schematically represents process 700 according to the invention. The steps of process 700 according to the invention are illustrated in Figures 8a to 8p.

[0077] The process 700 according to the invention includes a step 701 of providing a high electron mobility transistor substrate comprising a layer stack including a passivation layer and a heterojunction comprising a first semiconductor layer and a second semiconductor layer forming a two-dimensional electron gas at their interface. An example of a high electron mobility transistor substrate used in step 701 is illustrated in [Fig. 8a]. According to one embodiment, the high electron mobility transistor substrate comprises a high-resistivity Si111 substrate, an AIN nucleation layer, a stress management layer, a GaN or low-AlGaN buffer layer, a confinement barrier layer, a GaN channel layer, and an AlGaN barrier layer.According to another embodiment, the high electron mobility transistor substrate comprises a Sic or GaN substrate instead of a Si substrate. In the case of a GaN substrate, the epitaxy is initially performed on a GaN wafer.

[0078] In the case of [Fig. 8a], the first semiconductor layer is made of AlGaN and the second semiconductor layer is made of GaN. The stack of [Fig. 8a] further comprises a high-resistance Si substrate (HR).

[0079] Step 702 includes the ionic implantation of an n-type dopant, illustrated in [Fig. 8b]. In the example illustrated in [Fig. 8b], the implantation is carried out symmetrically in two different areas corresponding to the source contact and the drain contact.

[0080] According to one embodiment, the ion implantation step 702 is preceded by a photolithography step 702a for defining an implantation zone. The photolithography stage is known to those skilled in the art.

[0081] According to one embodiment, the dopant is Silicon or Germanium.

[0082] According to one embodiment, step 702 includes a single implantation Si ion energy of 70 kV / 3-5*10¹⁵ / cm² through a 30 nm surface layer. An implantation profile according to the invention is described in [Fig. 6]. The use of multi-energy implantation, common in wide-bandgap semiconductors for generating doped cells, is not the most suitable because it leads to a high transition resistance Rt.

[0083] The process 700 further includes a step 703 of annealing the dopant. According to one embodiment, the dopant is Si and the annealing can be carried out at 975°C for 10 hours, 1000°C for three hours or at 1050°C for one hour.

[0084] A long annealing at low temperature makes it possible to avoid plastic deformation of the GaN / Si wafers.

[0085] Si is an n+ dopant very suitable for creating a localized n+ doped zone: • It is activatable at low temperature in IIIN compounds such as AIN, AlGaN or GaN; • It has a solubility greater than 4*1020 / cm3 allowing very high doping, for example greater than 1020 / cm3 and negligible diffusion; • This is an element compatible with CMOS and planar technologies.

[0086] According to one embodiment, the annealing step 703 is preceded by the removal of the resin used for the lithography step. The resin removal and dopant annealing step 703 is illustrated in [Fig. 8c].

[0087] The process 700 according to the invention further comprises a step 704 of depositing a dielectric layer in contact with the passivation layer. The step 704 of depositing a dielectric layer is illustrated in [Fig. 8d].

[0088] The process 700 includes an etching step 705 of the layer stack and the dielectric layer to form a recess directly above and in contact with the implanted area, said recess being intended to accommodate a metallic source or drain contact, the distance separating an end of the implanted area and a lateral wall of the recess being between 300 nm and 1000 nm, the lower face of the recess being located below the interface between the first and second semiconductor layers. In one embodiment, the etching step 705 includes a photolithography step 705a to define the region to be etched.

[0089] Step 705 of photolithography and stack etching is illustrated in [Fig.8e].

[0090] According to one embodiment, the engraving carried out during step 705 is a dry engraving.

[0091] According to one embodiment, the engraving step 705 also includes the removal of the resin used during the photolithography substep. The stack of layers obtained after the removal of the resin is illustrated in [Fig.8f].

[0092] The process 700 according to the invention further comprises a step 706 of depositing a metallic layer intended to form the source or drain contact followed by a step 707 of mechano-chemical polishing of the metallic layer to obtain a planarized upper surface of the metallic source or drain contact.

[0093] Step 706 is also illustrated in [Fig. 8g]. The result of step 707, the mechano-chemical polishing of the metallic layer, is illustrated in [Fig. 8h]. According to one embodiment, step 706 comprises the deposition of a Ti / Al metallic bilayer with a Ti layer thickness of between 3 nm and 20 nm and a total thickness of 200 nm + / - 50 nm.

[0094] According to one embodiment, step 707 further comprises a substep 707b of annealing the metal. At the end of step 707, a metal contact having a planarized surface is obtained.

[0095] Step 707 reduces the parasitic capacitance between the contact metal and the grid electrode and optimizes the subsequent lithography.

[0096] The process 700 further includes a step 708 of defining and depositing a grid electrode.

[0097] According to one embodiment, step 708 further comprises the substeps: • 708a of deposition of a dielectric layer; step 708a is illustrated in the [Fig.8i]; • 708b photolithography to define the grid base; step 708b including the deposition of a layer of resin is illustrated in [Fig.8j]; • 708c engraving of the grid base and removal of the resin used during the step 708b of photolithography to define the grid foot; step 708c is illustrated in [Fig.8k]; • 708d of deposition of a metal used for the grid electrode; step 708d is illustrated in [Fig.81]; • 708th step of polishing the metal used for the grid base; step 708th is illustrated in [Fig.8m]; • 708f of deposition of a metallic layer intended to form the grid head; step 708f is illustrated in [Fig.8n]; • 708g of photolithography to define the grid head; the 708g step is illustrated in [Fig.8o]; • 708 hours of engraving excess grid head metal and resin removal used to define the grid head; step 708g is illustrated in [Fig.8p].

[0098] The method 700 according to the invention is robust because it allows for alignment tolerances between the ohmic contact metal, the n+ doped zone and the grid head thanks to planar technology. Furthermore, thanks to ion implantation technology, the 700 process according to the invention is precise, uniform and reproducible.

[0099] According to one embodiment of method 700 of the invention, it is possible to provide drain access in addition to source access. If method 700 of the invention is used only for source access, drain access is provided without a Si implantation step. In other words, the Si implantation is concealed at the drain contact, and the drain contact is of the "full recess" type.

[0100] Figures 9 to 12 illustrate the variation of the different terms contributing to the access resistance of the device as a function of its operating temperature. Figure 9 shows that the overall contact resistance Rc + Rn + Rt decreases with operating temperature. It decreases from 0.2 ohm.mm² to 0.11 ohm.mm² between 30°C and 150°C, which is very favorable for the source or drain resistance of the transistor.

[0101] This behavior is due to the strong decrease, from 0.11 to 0.024 Ohm.mm of the transition resistance Rt with temperature, illustrated in [Fig. 10], while the resistance of the n+ doped region increases by only 3%, as shown in [Fig. 11] and the metal / n+ contact resistance remains constant and equal to about 47 mOhm.mm, as shown in [Fig. 12].

[0102] The source or drain resistance of the transistor according to the invention varies very little with temperature, which makes the 400 transistor according to the invention particularly suitable for high frequency power applications.

Claims

Demands

1. A high-electron-mobility transistor (400) comprising: • a layer stack comprising a passivation layer (401) and a heterojunction comprising a first semiconductor layer (402), a second semiconductor layer (403) and a two-dimensional electron gas (404) at their interface, a surface of the passivation layer (401) being in contact with the first semiconductor layer (402); • a metallic source contact (405) and / or a metallic drain contact and a gate electrode (406); • an n+ doped region (407) located inside the heterojunction;the source metal contact (405) and / or the drain metal contact being positioned in a recess formed in the layer stack, said source metal contact (405) and / or said drain metal contact having a thickness defined by an upper face (405a) and a lower face (405b) substantially parallel to the layer plane, the upper face (405a) being planar, the lower face (405b) being in contact with the n+ doped area (407) and below the interface between the first semiconductor layer (401) and the second semiconductor layer (402), said source metal contact (405) and / or said drain metal contact further having a lateral face (405c), the n+ doped area extending from the lateral face of the source metal contact (405) and / or from the lateral surface of the drain metal contact towards the gate electrode (406) over a length between 300 and 1000 nm.;

2. Transistor (400) according to claim 1 characterized in that the n+ doped area (407) is an implanted area having a Gaussian-type spatial doping profile along the direction normal to the plane of the layers.

3. Transistor (400) according to any one of the preceding claims characterized in that the lower face (405b) of the source metal contact (405) and / or the lower face of the drain metal contact is below the two-dimensional electron gas (403).

4. Transistor (400) according to any one of the preceding claims characterized in that the distance (Lgs) between the grid electrode (406) and the n+ doped area (407) is between 200 nm and 400 nm.

5. Transistor (400) according to any one of the preceding claims characterized in that the n+ doped area (407) is doped with a Si or Ge type dopant with a concentration greater than or equal to 1020 cm3.

6. Transistor (400) according to any one of the preceding claims characterized in that the first semiconductor layer (402) comprises AlGaN and the second semiconductor layer (403) comprises GaN.

7. A method for manufacturing (700) a high electron mobility field-effect transistor comprising the following steps: • providing (701) a high electron mobility transistor substrate comprising a layer stack including a passivation layer and a heterojunction comprising a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at their interface; • forming an n+ doped region (702) by ion implantation inside the heterojunction and annealing (703) to activate the n+ doped region; • deposition of a dielectric layer (704) in contact with the passivation layer;• etching (705) of the layer stack and the dielectric layer to form a recess perpendicular to and in contact with the n+ doped area, said recess being configured to accommodate a metallic source and / or drain contact, the lower face of the recess being located below the interface between the first semiconductor layer and the second semiconductor layer; • deposition of a metallic layer (706) intended to form the metallic source contact and / or the metallic drain contact; • chemical-mechanical polishing (707) of the metallic layer to obtain a planarized upper surface of the source contact and / or upper surface of the drain contact; • definition and deposition of a gate electrode (708), the n+ doped area extending from a lateral face of the me- contact; metallical source and / or from a lateral face of the drain metal contact to the grid electrode over a length between 300 and 1000 nm.

8. Manufacturing process (700) according to the preceding claim characterized in that the step of forming the n+ doped zone (702) comprises a monoenergetic implantation of Si or Ge ions, with an implantation energy between 60 keV and 80 keV.

9. Manufacturing process (700) according to claim 7 or claim 8 characterized in that the activation annealing (703) of the n+ doped zone comprises a heat treatment at 975°C for 10 hours, 1000°C for three hours or at 1050°C for one hour.

10. Manufacturing method (700) according to any one of claims 7 to 9 characterized in that it further comprises a photolithography step to define an implantation area intended to accommodate the n+ doped area.