Transistor MOSFET

Abstract

MOSFET Transistor This description relates to a transistor (200) comprising, on a semiconductor layer (220), a stack of a gate insulator (232) and a gate region (230) on the gate insulator, wherein the gate region comprises a first portion (230A) and a second portion (230B) between the first portion and the gate insulator. The first portion has a first length (L3A) in a first lateral direction (X) of the transistor, and the second portion has a second length (L3B) in the first direction (X) shorter than the first length. Figure for the abstract: Fig. 2

Description

Title of the invention: MOSFET transistor technical field

[0001] This description relates generally to electronic components and more particularly to MOSFET type field-effect transistors (from the English "Metal Oxide Semiconductor Field Effect Transistor"). Previous technique

[0002] MOSFET type transistors are field-effect transistors comprising a conductive gate, for example metallic, electrically isolated from a semiconductor substrate by a dielectric layer called gate insulator.

[0003] Various realizations of MOSFET transistors have already been proposed.

[0004] It would be desirable to overcome at least in part some of the drawbacks of known realizations of MOSFET transistors.

[0005] We are particularly interested here in improving the electrical performance of MOSFET transistors intended for radio frequency (RF) signal switching applications, also called RF switches, for example for frequencies between 400 MHz and 20 GHz. Summary of the invention

[0006] One embodiment overcomes all or part of the disadvantages of known MOSFET transistors.

[0007] One embodiment provides a transistor comprising, on a semiconducting layer, a stacking of a gate insulator and a gate region on the gate insulator, in which the gate region comprises a first portion and a second portion between the first portion and the gate insulator, the first portion has a first length in a first lateral direction of the transistor, and the second portion has a second length in the first direction lower than the first length.

[0008] According to one embodiment, the transistor further comprises: - a source region and a drain region within a body region of the semiconductor layer, with the upper part of the body region, between the source region and the drain region, constituting a channel region of the transistor, the first direction being parallel to the length direction of the channel region, between the source region and the drain region; and the grid region above the body region, for example above the channel region.

[0009] According to one embodiment, the transistor further comprises a lightly doped drain region between the channel region and each source and drain region.

[0010] According to one embodiment, the second portion is centered in the first direction with respect to the first portion.

[0011] According to one embodiment, the thickness of the grid insulator is variable in the first direction, the grid insulator comprising a first region having a first thickness opposite a central area of ​​the grid region, and a second region having a second thickness, greater than the first thickness, opposite the lateral edges of the lower portion of the grid region.

[0012] According to one embodiment, the transistor includes an oxide layer covering at least the sides of the gate region, and, for example, an insulating spacer against the oxide layer.

[0013] According to one embodiment, the oxide layer: - includes, for example, a reoxidation layer in the grid region, for example, thermal reoxidation; - has a thickness greater than or equal to 5 nm; and / or - is also positioned on, for example covers, the first portion of the grid region.

[0014] According to one embodiment, the cavity between the semiconductor layer and the first portion of the gate region contains a material with a low dielectric constant.

[0015] According to one embodiment, the second portion of the grid region comprises, for example, a polycrystalline silicon-germanium alloy, the first portion being, for example, polycrystalline silicon.

[0016] According to one embodiment, the distance, in the first direction, between the lateral edges of the first portion and the second portion is between 1 and 30 nm, for example between 1 and 20 nm, or even between 1 and 10 nm.

[0017] One embodiment provides an electronic device comprising at least one transistor according to one embodiment.

[0018] One embodiment provides a radio frequency switch comprising at least one transistor according to one embodiment.

[0019] One embodiment provides a method for manufacturing a transistor, the method comprising the formation of a gate region on a semiconductor layer coated with a gate insulator layer, said formation comprising: - a step of forming a conductive grid layer on the grid insulating layer; - a first anisotropic etching step, adapted to etch the conductive grid layer preferentially in a direction perpendicular to the plane of the semiconductor layer, to a depth less than the thickness of said gate conductive layer, so as to form a first portion of the gate region having a first length in a first lateral direction of the transistor; then - a second etching step, less anisotropic than the first etching step, adapted to etch the conductive grid layer in the direction perpendicular to the grid insulator layer and in the first direction, so as to form a second portion of the grid region having a second length in the first direction shorter than the first length.

[0020] According to one embodiment, the formation of the grid region further comprises, after the second etching step, a third etching step adapted to etch the grid insulator layer preferentially in the perpendicular direction.

[0021] According to one embodiment, the method further comprises, after the formation of the grid region: - a step of depositing a layer of material with a low dielectric constant onto the semiconductor layer, preferably at least up to the level of the first portion of the gate region; then - an etching step of a portion of the material layer not covered by the first portion of the grid region; so as to fill the cavity between the semiconductor layer and the first portion of the gate region of the low dielectric constant material.

[0022] According to one embodiment, the formation of the grid region further comprises, after the second etching step, the formation of at least one oxide layer against the flanks of said grid region, for example by a thermal reoxidation technique of the grid region.

[0023] According to one embodiment, the grid insulation layer has a first thickness and the formation of the grid region further comprises, after the second etching step, a thermal oxidation step of the grid insulation layer so that said grid insulation layer reaches a second thickness greater than the first thickness opposite the edges of the second portion of the grid region and substantially retains the first thickness opposite a central area of ​​said grid region.

[0024] According to one embodiment: - the gate conductive layer formation step includes the formation of a layer of polycrystalline silicon-germanium alloy on a polycrystalline silicon layer; - the first etching step is adapted to etch the polycrystalline silicon layer; and - the second etching stage is adapted to etch the layer in the polycrystalline silicon-germanium alloy. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] Fig. 1A represents, by way of a cross-sectional view, an example of an electronic device comprising a MOSFET transistor;

[0027] Fig.1B represents, by way of a cross-sectional view, another example of an electronic device comprising a MOSFET transistor;

[0028] [Fig.2] represents, by a cross-sectional view, an electronic device comprising a MOSFET transistor according to one embodiment;

[0029] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E] and [Fig.3F] are cross-sectional views, partially and schematically illustrating successive steps of an example of a manufacturing process for a MOSFET transistor according to the embodiment of [Fig.2];

[0030] Figure 4 shows, in cross-section, an electronic device comprising a MOSFET transistor according to another embodiment; and

[0031] Fig. 5 represents, by way of a cross-sectional view, an electronic device comprising a MOSFET transistor according to another embodiment. Description of the implementation methods

[0032] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, not all steps in the manufacturing process of a MOSFET transistor have been described, as they can be carried out using standard microelectronics processes. Similarly, not all details of the MOSFET transistors have been described. Furthermore, not all applications of the described transistors have been detailed.

[0034] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0035] In the following description, when referring to positional qualifiers absolute, such as the terms "front", "back", "up", "down", "left", "right", etc., or relative, such as the terms "above", "below", "superior", "inferior", etc., or orientation qualifiers, such as the terms "horizontal", "vertical", etc., refers, unless otherwise specified, to the orientation of the figures or to a MOS transistor in a normal operating position.

[0036] In the following description, a length corresponds to a dimension in a first lateral direction of a MOSFET transistor, which corresponds to the X direction shown in the figures, corresponding to a direction parallel to the conduction direction of the transistor; a thickness or depth corresponds to a dimension in the vertical Z direction (perpendicular direction) shown in the figures; and a width corresponds to a dimension in a second lateral Y direction, orthogonal to the X direction. Thus, the channel length of the transistor is defined as the dimension, along the X direction, of a channel-forming region of the transistor, corresponding approximately to the distance between a source region and a drain region of the transistor.

[0037] In the following description, for the sake of brevity, a MOSFET transistor may be referred to as a transistor.

[0038] The transistors represented in the following description are, for example, N-channel MOS transistors (NMOS), that is to say, transistors whose source and drain regions are N-type doped, for example doped with arsenic or phosphorus atoms, while the body region is P-type doped, for example doped with boron atoms.

[0039] Alternatively, the transistors shown may be P-channel MOS transistors (PMOS), i.e. transistors whose source and drain regions are P-type doped, for example doped with boron atoms, while the body region is N-type doped, for example doped with arsenic or phosphorus atoms.

[0040] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0041] Figure 1A shows an example of an electronic device comprising a MOSFET transistor 100 formed in and on a semiconductor layer 120. The device includes a buried insulating layer 110 beneath the semiconductor layer 120. The layers 110 and 120 correspond, for example, to a Semiconductor-on-Insulator (SOI) stack, the device then comprising a substrate in contact with and beneath the buried insulating layer 110 (substrate not shown). The semiconductor layer 120 is, for example, on and in contact with the buried insulating layer 110.

[0042] The semiconductor layer 120 is, for example, made of silicon, for example, monocrystalline silicon, and the buried insulating layer 110 is, for example, made of silicon dioxide. silicon (SiO2).

[0043] The transistor 100 comprises a source region 124 and a drain region 126 formed in a region of the semiconductor layer 120 called the body region 122.

[0044] An upper portion 122A of the body region 122, between the source region 124 and the drain region 126, constitutes the channel-forming region of the transistor 100, or "channel region". The channel region 122A has a length L1 (in the first lateral direction X). By way of example, the source region 124, the drain region 126, and the body region 122 are flush with the upper surface of the semiconductor layer 120.

[0045] The transistor 110 further comprises a gate region 130 situated above the body region 122. The gate region 130 is, for example, made of polycrystalline silicon. The gate region 130 may have a length L3 of between 50 nm and 300 nm, for example between 100 nm and 200 nm.

[0046] The grid region 130 is separated from the body region 122 by an insulating layer 132, called the grid insulator layer, or grid insulator. By way of example, the grid insulator is made of silicon dioxide (SiO2) and has, for example, a thickness of between approximately 1 nm and 10 nm.

[0047] By way of example, in [Fig. 1 A], the grid insulator layer 132 is on and in contact with the semiconductor layer 120 and the grid region 130 is on and in contact with the grid insulator layer 132.

[0048] On either side of the gate region 130, on parts of the semiconductor layer 120 not covered by said gate region, and on the side walls (flanks) of the gate region 130, the transistor 100 includes a thin protective oxide layer 134, for example a layer of SiO2.

[0049] In addition, the transistor 100 includes an insulating spacer 136 which coats the sides of the gate region 130 covered by the oxide layer 134 and which extends over the parts of the semiconductor layer 120 covered by the oxide layer 134. The insulating spacer 136 is, for example, made of silicon nitride (SiN).

[0050] In certain MOS transistors, a lightly doped drain (LDD) region 128 is formed between the channel region 122A and each source 124 / drain 126 region by doping, generally by ion implantation, the semiconductor layer 120 from its upper surface. This LDD region 128 is formed after the gate region 130, and generally after the formation of the oxide layer 134. Thus, the gate region 130, with the oxide layer 134 typically on the flanks of the gate region, serves as a protective mask during the doping operation of the semiconductor layer to form the LDD region 128. The LDD region allows for a reduction in the depth of the implanted area in order to limit the effects of parasitic electrostatic coupling between the source and drain regions.

[0051] However, the doping operation to form these LDD regions often results in significant overlap of these LDD regions under the gate region 130. Indeed, during the doping operation, the dopant can diffuse over a certain length under the gate region. This overlap is represented by the length L2 in [Fig. 1A]. This creates an overlap capacitance Cov, which increases the parasitic capacitance Coff, in the off state, of the transistor, potentially leading to a reduction in the performance of the transistor, for example, a switch transistor, and therefore, for example, a reduction in the isolation function of radio frequency antennas comprising such switch transistors.

[0052] To reduce overlap, and thus reduce the Cov overlap capacity, as illustrated in [Fig. 1B], one technique consists of forming an offset spacer 138 on the side walls of the grid region 130' and on the thin protective oxide layer 134'. The offset L4 formed by the offset spacer 138 is, for example, between 3 and 20 nm.

[0053] Thus, we see that the overlap length L2' is reduced compared to the overlap length L2 of [Fig. 1A]. The overlap length L2' nevertheless maintains a minimum value so as not to compromise gate control over the entire length of channel L1 in case of overlap loss, and to avoid increasing the resistance at the overlap, thereby avoiding an increase in the resistance Ron of the transistor.

[0054] The shift spacer 138 is formed after the formation of the grid region 130' and before the formation of the LDD region 128'. Thus, the shift spacer 138 forms a protective mask that extends the mask formed by the grid region for the doping operation. This allows the dopant to diffuse over a shorter length under the grid region, thereby reducing overlap.

[0055] If it is desired to maintain approximately the same channel length L1, a gate region 130' of length L3' reduced by approximately twice the offset value L4 can be formed. Since the RF voltage Vmax, which is the maximum voltage that can be applied to a transistor, for example for an RF switch, without risking damage, increases with the channel length, it is also possible to choose to increase the channel length.

[0056] Thus, an offset spacer makes it possible to reduce the Coff.Ron product, without reducing the RF voltage Vmax.

[0057] The offset spacer is generally formed by a layer deposition process, after formation of the grid region 130' and the thin oxide layer 134', for example a chemical vapor deposition (CVD) process with tetraethyl orthosilicate (TEOS) as a precursor to form a SiO2 layer. Then, portions of the SiO2 layer are etched to primarily retain the SiO2 deposited on the sides of the grid region 130', which forms the offset spacer 138. These operations generally require forming an etching mask, then removing that mask.

[0058] Thus, one disadvantage of this technique is that it adds steps necessary for the formation of a shift spacer in the manufacturing process of the transistor, and therefore of the electronic device.

[0059] The inventors propose a MOSFET transistor that meets the improvement needs described above and overcomes all or part of the drawbacks of the transistors described above. In particular, the inventors propose a MOSFET transistor that improves the trade-off between Coff.Ron, which they seek to minimize, and the RF voltage Vmax, which they seek to maximize, without complicating the transistor manufacturing process, in particular without adding time-consuming and costly steps.

[0060] Embodiments of MOSFET transistors will be described below. The embodiments described are not limiting, and various variations will become apparent to those skilled in the art from the indications in this description.

[0061] Fig. 2 represents, by way of a cross-sectional view, an electronic device comprising a MOSFET 200 transistor according to one embodiment.

[0062] Similar to transistor 100 in [Fig. 1A], MOSFET transistor 200 is formed in and on a semiconductor layer 220. The device includes a buried insulating layer 210 beneath the semiconductor layer 220. Layers 210 and 220 correspond, for example, to a SOI-type stacking, the device then comprising a substrate in contact with and beneath the buried insulating layer 210 (substrate not shown). The semiconductor layer 220 is, for example, on and in contact with the buried insulating layer 210.

[0063] The semiconductor layer 220 is, for example, made of silicon, for example, single-crystal silicon. The semiconductor layer 220 can have a thickness between 10 nm and 500 nm, for example between 50 nm and 200 nm, for example on the order of 60 nm or on the order of 160 nm.

[0064] By way of example, the buried insulating layer 210 is made of silicon dioxide (SiO2). The buried insulating layer 210 can have a thickness between 100 nm and 600 nm, for example between 200 nm and 450 nm, for example on the order of 400 nm.

[0065] The transistor 200 comprises a source region 224 and a drain region 226 formed in a region of the semiconductor layer 220, called the body region 222.

[0066] An upper portion 222A of the body region 222, between the source region 224 and the drain region 226, constitutes the channel region of the transistor 200. The channel region 222A has a length LL

[0067] A slightly doped drain region (LDD) 228 is formed between the channel region 222A and each source region 224 / drain 226.

[0068] By way of example, the source 224, drain 226 and body 222 regions are flush with the top face of the semiconductor layer 220.

[0069] The transistor 210 further includes a gate region 230 located above the body region 222, for example above the channel region 222A.

[0070] Transistor 200 differs from transistor 100 in [Fig. 1A] essentially in that the gate region 230 comprises an upper portion 230A (first portion) and a lower portion 230B (second portion). The upper portion 230A has a length L3A (first length) greater than the length L3B (second length) of the lower portion 230B, so that the upper portion extends beyond the lower portion on both sides. The lower portion is, for example, centered in the X direction with respect to the upper portion, but this is not a limiting factor.

[0071] The grid region 230 thus has a shape with a notch 231 in its lower part. The length L5 of the notch 231 corresponds approximately to half the difference between L3A and L3B, and can vary, for example, between 5 and 25 nm, or even between 5 and 15 nm. This value can be controlled, as explained in the manufacturing process example described in relation to Figures 3A to 3F.

[0072] The lower portion 230B of the gate region 230 reduces the overlap between the LDD region 228 and the gate region 230, thereby reducing the overlap capacitance Cov, while the upper portion 230A of the gate region 230 forms a protective mask during the doping operation of the semiconductor layer 220 to form the LDD region 228. This protective mask can be sized to reduce dopant diffusion during this doping operation. Furthermore, this reduces the number of process operations compared to the transistor 100' of [Fig. 1B], as the shape of the gate region is obtained by adapting the etching of the gate region, without necessarily adding steps such as those required for forming a shift spacer. This is illustrated in the manufacturing process example in Figures 3A to 3F.

[0073] According to one example, the first and second portions of the gate region 230 shown are made of polycrystalline silicon, but this is not limiting, as for example described in connection with [Fig.5].

[0074] The height H3A (first height) of the upper portion 230A and the height H3B (second height) of the lower portion 230B can vary. For example, increasing the height H3B further reduces the overlap capacity of Cov.

[0075] For example, grid region 230 has: - a first length L3A between 60 and 500 nm, for example between 80 and 200 nm; - a second length L3B between 30 and 490 nm or between 50 and 470 nm, for example between 50 and 190 nm or between 70 and 170 nm, or even between 50 and 80 nm; - a total height H3 between 50 and 140 nm, for example between 70 and 110 nm; - a first height H3A between 40 and 90 nm, for example between 60 and 80 nm; - a second height H3B between 10 and 50 nm, for example between 10 and 30 nm.

[0076] The grid region 230 is separated from the body region 222 by an insulating layer 232 (grid insulator). By way of example, the grid insulator is made of silicon dioxide (SiO2).

[0077] The gate insulator has, for example, a thickness of between about 1 nm and 10 nm. The gate insulator can have a thickness of between about 1 and 4.5 nm, for example about 2.1 nm, for a so-called GO1 transistor ("Gate Oxide 1" in English), that is to say a transistor with a thin gate insulator, or a thickness of between about 5 and 7.5 nm, for example about 6.5 nm, for a so-called GO2 transistor ("Gate Oxide 2" in English), that is to say a transistor with a thick gate insulator.

[0078] By way of example, in [Fig.2], the grid insulator layer 232 is on and in contact with the semiconductor layer 220 and the lower portion 230B of the grid region 230 is on and in contact with the grid insulator layer 232.

[0079] On either side of the gate region 230, on portions of the semiconductor layer 220 not covered by the lower portion 230B of the gate region, and on the flanks of the gate region 230, the transistor 200 includes a thin protective oxide layer 234, for example, a SiO2 layer. The thickness of the thin oxide layer is, for example, between 2 and 10 nm, or even between 2 and 5 nm. On the flanks of the gate region 230, the thin protective oxide layer 234 conforms to the shape of said gate region.

[0080] In addition, the transistor 200 includes an insulating spacer 236 which coats the sides of the gate region 230 covered by the oxide layer 234 and which extends over the parts of the semiconductor layer 220 covered by the oxide layer 234. The insulating spacer 236 is, for example, made of silicon nitride (SiN).

[0081] Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E and Fig. 3F are cross-sectional views partially and schematically illustrating successive steps of an example of a manufacturing process for a MOSFET 200 transistor according to the embodiment of Fig. 2.

[0082] Fig. 3A represents a starting structure comprising a buried insulating layer 210, surmounted by a semiconducting layer 320. The structure of Fig. 3A further comprises a grid insulator layer 332 on the semiconducting layer 320, and a grid conductive layer 330 on the grid insulator layer 332.

[0083] The conductive grid layer 330 is surmounted by a masking layer 302. The masking layer 302 partially covers the upper surface 330A of the conductive grid layer 330 for an etching step which is detailed below in relation to [Fig.3B].

[0084] Fig. 3B corresponds to a structure obtained after an etching step of the conductive grid layer 330 of the structure illustrated in Fig. 3A. During this step, the conductive grid layer 330 is etched, from its upper surface 330A, so that only the part of the conductive grid layer 330 located under the masking layer 302 remains, the parts of the conductive grid layer 330 not covered by the masking layer 302 being removed.

[0085] The engraving step is carried out in at least two consecutive steps: - a first anisotropic etching step adapted to etch the gate conductive layer 330 from the upper surface 330A of said layer preferentially in the vertical Z direction; this etching is carried out to a depth H3A, corresponding to the height of the upper portion 230A of the future gate region 230; then - a second etching step, less anisotropic (or more isotropic) than the first etching step, adapted to etch the rest of the gate conductive layer 330 vertically to a depth H3B and laterally to a length L5 towards the center of the future gate region, forming the lower portion 230B of the gate region 230.

[0086] For example, the first etching step is carried out with dichlorine (Cl2) and carbon tetrafluoride (CF4), for example for a duration of between 10 and 70 seconds.

[0087] For example, the second etching step is carried out with hydrogen bromide (HBr), for example for a duration of between 50 and 150 seconds.

[0088] The upper portion 230A has a length L3A greater than the length L3B of the lower portion 230B, such that the upper portion extends beyond the lower portion on both sides. The height H3A of the upper portion 230A and the height H3B of the lower portion 230B can be defined by adjusting the etching conditions and the transition between the first and second etching steps. The length L5 can be modified by adjusting the conditions of the second etching step, for example, to make it more or less anisotropic.

[0089] By way of example, the engraving process shown then comprises a third etching step of the grid insulator layer 332 so that, at the end of this etching, only the grid insulator 232 remains under the grid region 230. This third etching step is preferably an anisotropic etching adapted to etch the grid insulator layer 332 preferentially in the vertical Z direction.

[0090] Alternatively, the etching process can be adapted to etch the material of the conductive grid layer 330 selectively with respect to the material of the grid insulating layer 332. The grid insulating layer 332 can then act as a barrier to the etching so that the etching stops on the upper surface of the grid insulating layer 332 (shown as dotted lines in [Fig. 3B]). According to this alternative, after the etching step, the grid insulating layer 332 is still present, even in the parts not covered by the grid region 230.

[0091] Figure [Fig. 3C] corresponds to a structure obtained at the end of: - a step of forming a thin protective oxide layer 334, for example a SiO2 layer, on the flanks of the gate region 230 and on the semiconducting layer 320, for example by a CVD technique; on the flanks of the gate region 230, the thin protective oxide layer 334 conforms to the shape of said gate region; and - of a first ion implantation step to form lightly doped drain regions (LDD) 328 in the semiconductor layer 320.

[0092] The order of these two steps can be reversed.

[0093] Figure [Fig. 3D] corresponds to a structure obtained at the end of: - a step to remove the masking layer 302; then - of a step of forming an insulating layer 336 which coats the sides of the grid region 230 covered by the oxide layer 334 and which extends over the parts of the semiconductor layer 320 covered by the oxide layer 334.

[0094] The [Fig.3E] corresponds to a structure obtained after an etching step of the insulating layer 336 so as to form insulating spacers 236 on the sides of the grid region 230 covered by the oxide layer 334.

[0095] Figure [Fig. 3F] corresponds to a structure obtained at the end of: - an etching step of the parts of the oxide layer 334 not covered by the insulating spacers 236, forming the thin protective oxide layer 234; then - a second ion implantation stage to form the source 224 and drain 226 regions in the semiconductor layer 320, forming the semiconductor layer 220 with the source, drain, body and channel regions.

[0096] For an NMOS transistor, the first and second ion implantation stages can use n-type dopants such as arsenic (As) or phosphorus (P). For a PMOS transistor, the first and second ion implantation stages can use p-type dopants such as boron (B).

[0097] Figure 4 shows, in cross-section, an electronic device comprising a MOSFET 400 transistor according to another embodiment.

[0098] The transistor 400 differs from the transistor 200 of [Fig.2] essentially in that the thickness e1 of the gate insulator 432 under a central area of ​​the gate region 430 is less than the thickness e2 of the gate insulator 432 under peripheral areas of the gate region, for example especially around areas where the gate insulator 432 is not covered by the lower portion 430B of the gate region 430.

[0099] By way of example, between the gate region 430 and the semiconductor layer 220, the gate insulator 432 has a decreasing thickness from the edges of the lower portion 430B of the gate region 430 towards the center of said gate region. For example, the thickness of the gate insulator decreases substantially continuously between thickness e2 and thickness el, in the X direction of the transistor channel length from the edges of the lower portion 430B of the gate region 430 to a central area of ​​the gate region.

[0100] By way of example, the thickness el is between 1 and 6 nm, or even between 2 and 3 nm, and the thickness e2 is between 5 and 10 nm, or even between 5 and 7 nm.

[0101] This increase in thickness can be achieved by a thermal oxidation step of the grid insulating layer 432, after the etching step forming the grid region 430. By way of example, the thermal oxidation step is carried out at a temperature between 300°C and 1200°C, for example between 500°C and 1000°C, for example on the order of 900°C. By way of example, the thermal oxidation step is a rapid thermal oxidation, carried out for a duration between 1 second (s) and 2 minutes (min), for example between 20 s and 1 min, for example on the order of 35 s.

[0102] Providing a relatively thick gate insulator 432 (thickness e2) under a peripheral area of ​​the gate region 430 reduces the parasitic capacitance Coff, in the off state, of the transistor 400, between the semiconductor layer 220 and the gate region 430. Conversely, maintaining a relatively thin gate insulator 432 (thickness e1) under a central area of ​​the gate region 430 reduces, or does not significantly increase, the on-state resistance Ron of the transistor. This allows for a particularly advantageous reduction in the Ron.Coff product, especially for RF signal switching applications.

[0103] This effect of reducing the Ron.Coff product can be particularly enhanced insofar as the gate region of the transistor includes a notch in its lower part. Indeed, oxidation, and thus the increase in thickness, can occur substantially below the notch and thus at a reduced overlap zone. due to this grid region shape, and the combination of decreasing the overlap length and increasing the insulation thickness at this overlap zone further reduces the parasitic capacitance Coff.

[0104] Furthermore, [Fig. 4] shows, for example, a slot length L5' shorter than the slot length L5 of transistor 200 in [Fig. 2]. This feature is not necessarily combined with the previously described feature.

[0105] [Fig.5] represents, by way of a cross-sectional view, an electronic device comprising a MOSFET 500 transistor according to another embodiment.

[0106] Transistor 500 differs from transistor 200 of [Fig.2] mainly by three characteristics which can be considered individually or in combination.

[0107] The transistor 500 may include an oxide layer 534, for example in SiO2, thicker than the oxide layer 234 of [Fig.2], for example greater than 5 nm.

[0108] This thicker oxide layer can be obtained by a reoxidation step of the gate region 530 (for example, by a conventional thermal reoxidation technique used in microelectronics), after the etching step intended to form said gate region. It can then be called the "gate region reoxidation layer" or simply the "reoxidation layer." This reoxidation step can be followed (or preceded) by chemical vapor deposition (CVD), for example, with TEOS as a precursor.

[0109] This thicker oxide layer can further reduce the overlap capacity of Cov.

[0110] The cavity formed by the notch 531 in the lower part of the grid region 530 can be filled with a low-K material 538, i.e. a material with a lower dielectric constant than that of SiO2, for example a silicon oxycarbide (SiCO3), or a silicon-boron carbonitride (SiBCN).

[0111] This can be achieved by a step of depositing a layer of low-K material on the semiconductor layer 220, after the etching step intended to form said gate region, and for example after the step of forming the oxide layer 534, then by a step of etching the layer of low-K material, the upper portion 530A of the gate region protecting the part of low-K material disposed under it during this etching step.

[0112] The low-K material layer preferably has a thickness at least equal to the height H3B of the lower portion 530B of the grid region 530.

[0113] This layer of Low-K material in the notch 531 can reduce the lateral capacity of said notch, as well as the overlap capacity Cov, and thus further reduce the capacity Coff.

[0114] The lower portion 530B of the gate region 530 can be processed to constitute, for example, a polycrystalline silicon-germanium (SiGe) alloy. This can be achieved by forming a conductive gate layer of polycrystalline SiGe beneath the conductive gate layer of polycrystalline Si (using a standard microelectronics technique). For example, the first etching step is adapted to etch polycrystalline Si, and the second etching step is adapted to etch polycrystalline SiGe. The two etching steps can be chained together in the same etching platform or in separate platforms (for example, SiGe can be wet-etched, while Si is dry-etched).

[0115] This feature of the grid region can improve the control of the etching of the grid region 530 and in particular improve the control of the formation of the notch 531 between the first 530A and second 530B portions of the grid region 530. This feature can also reduce the depletion of polysilicon.

[0116] The embodiments presented can be combined with each other. For example, one or more of the features described in relation to [Fig. 5] can be combined with features described in relation to [Fig. 2] and / or with [Fig. 4].

[0117] Furthermore, for each embodiment described, the length L5 of the notch formed in the grid region can vary, for example between 1 and 30 nm, preferably between 1 and 25 nm, and even more preferably between 5 and 25 or even between 5 and 15 nm.

[0118] Thus, these embodiments can minimize the Ron.Coff product of a MOSFET transistor without impacting other performance factors of the transistor, for example, without affecting the maximum applicable RF voltage Vmax. Furthermore, this effect can be combined with other improvements to minimize the Ron.Coff product and / or maximize the RF Vmax, for example, with improvements to the MOSFET transistor's structure itself.

[0119] The embodiments can find applications for electronic components used in RF (radio frequency) communication applications, for example, for RF signal switching technologies (RF switch) and / or radio antenna front-end modules (FEMs). For RF switches, the embodiments particularly allow for the reduction of parasitic capacitances without degrading the RF voltage Vmax and for the reduction of gate-induced drain leakage, thus enabling improved switch performance at a lower cost, for example, by achieving a higher operating speed.

[0120] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will appear to the person of the trade.

[0121] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Transistor (200; 400; 500) comprising, on a semiconducting layer (220), a stacking of a gate insulator (232; 432; 532) and a gate region (230; 430; 530) on the gate insulator, wherein the gate region comprises a first portion (230A; 430A; 530A) and a second portion (230B; 430B; 530B) between the first portion and the gate insulator, the first portion has a first length (L3A) in a first lateral direction (X) of the transistor, and the second portion has a second length (L3B) in the first direction (X) shorter than the first length; in which the transistor comprises an oxide layer (234; 434; 534) covering at least the sides of the gate region (230), said oxide layer having a thickness greater than or equal to 5 nm.

2. Transistor (200; 400; 500) according to claim 1, further comprising: - a source region (224) and a drain region (226) in a body region (222) of the semiconductor layer (220), an upper portion of the body region, between the source region and the drain region, constituting a channel region (222A) of the transistor, the first direction (X) being parallel to the length direction of the channel region, between the source region and the drain region; and the gate region (230; 430; 530) overlying the body region (222), for example overlying the channel region (222A).

3. Transistor (200; 400; 500) according to claim 2, further comprising a lightly doped drain region (228) between the channel region (222A) and each source (224) and drain (226) region.

4. Transistor (200; 400; 500) according to any one of claims 1 to 3, wherein the second portion (230B; 430B; 530B) is centered in the first direction (X) with respect to the first portion (230A; 430A; 530A).

5. Transistor (400) according to any one of claims 1 to 4, wherein the thickness of the gate insulator (432) is variable in the first direction (X), the gate insulator (432) comprising a first region having a first thickness (e1) opposite a central area of ​​the gate region (430), and a second region having a second thickness (e2), greater than the first thickness, opposite the lateral edges of the lower portion (430B) of the gate region.

6. Transistor (200; 400; 500) according to any one of claims 1 to 5, wherein the transistor comprises an insulating spacer (236; 436; 536) against the oxide layer.

7. Transistor (500) according to any one of claims 1 to 6, wherein the oxide layer (534): - comprises, for example consists of, a reoxidation layer of the gate region (530), for example thermal reoxidation; and / or - is also positioned on, for example covers, the first portion (530A) of the gate region.

8. Transistor (500) according to any one of claims 1 to 7, wherein the cavity (531) between the semiconductor layer (220) and the first portion (530A) of the gate region (530) contains a low dielectric constant material (538).

9. Transistor (500) according to any one of claims 1 to 8, wherein the second portion (530B) of the gate region (530) comprises, for example, is made of, a polycrystalline silicon-germanium alloy, the first portion (530A) being, for example, made of polycrystalline silicon.

10. Transistor (200; 400; 500) according to any one of claims 1 to 9, wherein the distance (L5, L5'), in the first direction (X), between the lateral edges of the first portion and the second portion is between 1 and 30 nm, for example between 1 and 20 nm, or even between 1 and 10 nm.

11. Electronic device comprising at least one transistor according to any one of claims 1 to 10.

12. Radio frequency switch comprising at least one transistor according to any one of claims 1 to 10.

13. A method for manufacturing a transistor, the method comprising the formation of a gate region (230) on a semiconductor layer (320) coated with a gate insulator layer (332), said formation comprising: - a step of forming a gate conductive layer (330) on the gate insulator layer; - a first anisotropic etching step, adapted to etch the gate conductive layer (330) preferentially in a direction (Z) perpendicular to the plane of the semiconductor layer (320), to a depth (H3A) less than the thickness of said gate conductive layer, so as to form a first portion (230A) of the gate region having a first length (L3A) in a first lateral direction (X) of the transistor; then - a second etching step, less anisotropic than the first etching step, adapted to etch the gate conductive layer (330) in the perpendicular direction (Z) to the gate insulator layer (332) and in the first direction (X), so as to form a second portion (230B) of the gate region (230) having a second length (L3B) in the first direction (X) shorter than the first length; wherein the formation of the gate region (230) further comprises, after the second etching step, the formation of at least one oxide layer against the flanks of said gate region, said oxide layer having a thickness greater than or equal to 5 nm.

14. Method according to claim 13, wherein the formation of the grid region (230) further comprises, after the second etching step, a third etching step adapted to etch the grid insulator layer (332) preferably in the perpendicular direction (Z).

15. A method according to claim 13 or 14, further comprising, after the formation of the gate region: - a step of depositing a layer of low dielectric constant material on the semiconductor layer, preferably at least up to the level of the first portion (530A) of the gate region (530); then - a step of etching a part of the layer of material not covered by the first portion of the gate region; so as to fill the cavity (531) between the semiconductor layer and the first portion of the gate region with the low dielectric constant material (538).

16. A method of any one of claims 13 to 15, wherein the formation of the oxide layer is achieved by a thermal reoxidation technique of the grid region.

17. A method according to any one of claims 13 to 16, wherein the grid insulation layer has a first thickness (el) and the formation of the grid region further comprises, after the second etching step, a thermal oxidation step of the grid insulation layer such that said grid insulation layer attains a second thickness (e2) greater than the first thickness (el) opposite the edges of the second portion of the grid region and retains substantially the first thickness opposite a central zone of said grid region.

18. A method according to any one of claims 13 to 17, in which : - the gate conductive layer formation step includes the formation of a layer of polycrystalline silicon-germanium alloy on a polycrystalline silicon layer; - the first etching step is adapted to etch the polycrystalline silicon layer; and - the second etching stage is adapted to etch the layer in the polycrystalline silicon-germanium alloy.