Semiconductor device comprising a capacitive stack and a pillar and its manufacturing process

Abstract

Semiconductor device comprising a capacitive stack and a pillar and its manufacturing method. The invention relates to a semiconductor device comprising: • a substrate comprising at least one cavity, and • a three-dimensional structure formed in the substrate comprising: - a three-dimensional capacitor comprising a capacitive stack, the capacitive stack being at least partially housed in at least one cavity of the substrate, - a pillar extending along the thickness of the substrate from the upper face of said substrate, characterized in that at least one cavity extends along the thickness of the substrate from the upper face of said substrate, and the capacitor is configured to delimit, on the upper face of the substrate, a contour of an inscribed portion, the pillar being arranged in the inscribed portion of the substrate.The invention will find its application particularly in the field of capacitive storage components, especially integrated solid-state supercapacitors. Figure for the abstract: Fig. 2.

Description

Title of the invention: Semiconductor device comprising a capacitive stack and a pillar and its manufacturing process. Technical field

[0001] The present invention relates to the field of microelectronic component integration, more particularly for electronic products, related semiconductor products, and their manufacturing processes. The invention will find its application more particularly in the field of capacitive storage components, especially integrated solid-state supercapacitors. STATE OF THE ART

[0002] Capacitors are important components of integrated circuits (ICs) and semiconductor devices, for example, for use as information storage cells in memory devices, or as energy storage cells. They are present in many electronic functions, such as analog signal processing and power converters. Whether integrated on the silicon chip or externally by discrete components, they contribute significantly to the system size. Since the capacitance density available on silicon technologies is limited to a few nF / mm², electronic circuits often use external components to implement the capacitance requirements on the chip.

[0003] Silicon on-chip capacitors can have different architectures. For example, MIM (Metal / Insulator / Metal) capacitors, widely used in integrated circuits, comprise two metal plates with an insulator between them. Currently, MIM capacitors are normally manufactured at the back-end-of-line (BEOL) level of interconnects. The space for integrating capacitors is often limited and placed on top of the circuit surface to minimize the additional footprint of these capacitors. Since the capacitance of a capacitor is linearly proportional to its surface area, the lack of available space at the BEOL limits the number of conventional MIM capacitors that can be placed there, resulting in insufficient power density when the capacitors are used as energy storage devices.

[0004] In the search for high-performance on-chip integrated energy storage solutions, increasing the specific surface area of ​​the capacitive structure using a three-dimensional (3D) architecture has proven to be an excellent approach that significantly increases capacity density while allowing for a reduction in chip area. The technological advantage of 3D capacities lies in the fact that the capacities are stackable and have a surface area developed in the (x;y) plane of the substrate, but also in height / thickness z, allowing for significant space savings and a larger developed surface area of ​​the capacity than a planar capacity.

[0005] In line with Moore's Law, current processors are becoming increasingly faster and more power-hungry. For example, with the advent of 5G technology and three-dimensional integration for artificial intelligence and machine learning processors, power density remains a major challenge for capacitors used for energy storage. Similar capacitance challenges exist when capacitors are used as information storage devices.

[0006] For example, US patent 20210305358 A1 proposes a new optimization approach to meet the specifications of new development applications. This patent reveals the use of the interconnection layer to add capacitive functionality. Interconnections are often perpendicular to the useful silicon surface and represent a significant area. This patent proposes using the interconnection surface as one of the capacitor's electrodes. Similar to a coaxial cable, the second electrode of the capacitor is wound around the interconnections. The benefit is therefore to increase the capacitance density per unit area of ​​the useful silicon (in the horizontal plane) while also reducing costs, since certain capacitor manufacturing steps can be combined with the interconnection manufacturing process.However, this solution has limitations, notably the electrical coupling between the interconnection and the first electrode of the capacitor, which, while improving its local use in storage filtering related to the signal passing through the interconnections, reduces the possibilities for independent use of the capacitor and the interconnection.

[0007] There is therefore a need to propose a solution for integrating solid ionic capacitance that meets the new requirements for high capacitance density and overcomes at least partially the limitations of the state of the art. SUMMARY

[0008] To achieve this objective, according to one embodiment, a semiconductor device is provided comprising a substrate including at least one cavity, and a three-dimensional structure formed in the substrate comprising: • a three-dimensional capacitor comprising a capacitive stack, the capacitive stack being at least partially housed in at least one cavity of the substrate, • a pillar extending along the thickness of the substrate from the upper face of said substrate, Characterized in that at least one cavity extends along the thickness of the substrate from the upper face of said substrate, and the three-dimensional capacitor is configured to delimit, on the upper face of the substrate, a contour of an inscribed portion, the pillar being arranged in the inscribed portion of the substrate.

[0009] The advantage of the device according to the invention is to increase the capacitance value per unit area of ​​useful Silicon (in the horizontal plane) while benefiting from the cost reduction, because certain manufacturing steps of the three-dimensional capacitor can be shared with the manufacturing of the pillar while retaining the independent functionalities of the capacitor and the pillar.

[0010] The invention makes it possible to take advantage of the surfaces around the pillars which can play various roles such as electrical, thermal or mechanical and at the same time overcome the limitations of the solutions proposed in the prior art.

[0011] The absence of electrical coupling between the three-dimensional capacitor and the pillar, while having shared manufacturing steps, makes it possible to reduce manufacturing costs.

[0012] The capacitor is said to be three-dimensional in that it has a three-dimensional structure which makes it possible to increase the developed surface area without increasing the horizontal surface area of ​​silicon and consequently increase the associated storage capacity. BRIEF DESCRIPTION OF THE FIGURES

[0013] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0014] [Fig.1] Fig.1 represents a top view of a semiconductor device according to a first embodiment of the invention.

[0015] [Fig.2] The [Fig.2] represents a view along section AA of the [Fig.1].

[0016] [Fig.3] The [Fig.3] represents a view according to section BB of the [Fig.2].

[0017] [Fig.4] Fig.4 represents a top view of a semiconductor device according to a second embodiment of the invention.

[0018] [Fig.5] Fig.5 represents a view along section CC of Fig.4

[0019] [Fig.6] The [Fig.6] represents a view along section DD of the [Fig.4].

[0020] [Fig.7] The [Fig.7] represents a view along section EE of the [Fig.5].

[0021] [Fig.8] [Fig.8] represents a cross-sectional view of the semiconductor device in a full stack.

[0022] [Fig.9] Figures 9 to 15 represent the steps of a manufacturing process for a semiconductor device according to the invention.

[0023] [Fig. 10]

[0024] [Fig. 11]

[0025] [Fig. 12]

[0026] [Fig. 13]

[0027] [Fig. 14]

[0028] [Fig. 15]

[0029] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the layers and the size ratios of the pillar and cavities are not representative of reality. DETAILED DESCRIPTION

[0030] Before proceeding to a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0031] - As an example, pillar 400 is arranged in the center of the inscribed portion 202;

[0032] - By way of example, the three-dimensional structure 200 comprises a first conforming layer comprising a first part forming the first electrode layer 501 of the capacitive stack 500 and a second conforming part 404 arranged in the pillar 400, the first part 501 and the second part 404 being electrically disconnected from each other. This arrangement makes it possible to share manufacturing steps between the pillar and the capacitive stack without linking their electrical operation;

[0033] - By way of example, the transverse distance 104 to the thickness 103 of the substrate 100 between the center of a cavity and the center of the pillar 400 is less than or equal to lOOpm;

[0034] - By way of example, the transverse distance 104 to the thickness 103 of the substrate 100 the distance between the center of a cavity and the center of the pillar 400 is less than or equal to 5pm;

[0035] - By way of example, at least one cavity of the capacitor 300 is a trench 301;

[0036] - By way of example, trench 301 is circular and arranged in the form of a circle around pillar 400;

[0037] - By way of example, the capacitor 300 comprises at least two trenches 301 circular and concentric;

[0038] - By way of example, at least one cavity of the capacitor is a column 302;

[0039] - By way of example, the capacitor 300 comprises a plurality of columns 302,

[0040] - By way of example, the plurality of columns 302 is arranged in a circular fashion around pillar 400;

[0041] - By way of example, the width 401 of a pillar is 20 times greater than the width 303 of a cavity of the three-dimensional capacitor 300, the widths 401,303 being taken transversely to the thickness 103 of the substrate 100;

[0042] - By way of example, the three-dimensional capacitor 300 comprises from 2 to 20 cavities.

[0043] - By way of example, pillar 400 comprises a metallic material so as to fill the pillar 400 at the level of the upper face 100 of the substrate 100;

[0044] - By way of example, the cavity is open only on the upper face 101 of the substrate 100;

[0045] - By way of example, pillar 400 is only open on its upper face 101 of substrate 100;

[0046] - By way of example, the semiconductor device includes a sub- layer adjacent and a layer superadjacent to the substrate;

[0047] - By way of example, the three-dimensional structure is intended to be arranged at the end interconnection line (BEOL);

[0048] - By way of example, the three-dimensional structure is located at the level of interconnects coupled to a processor, or to the back of a processor,

[0049] - By way of example, the capacitive stack-up 500 comprises a first layer electrode 501, an intermediate layer 502 and a second layer of electrode 503.

[0050] According to another aspect, the process for manufacturing a semiconductor device comprises the following steps: • formation of at least one cavity of the capacitor (300) in the substrate (100) and extending along the thickness (103) of the substrate (100) from the upper face (101) of the substrate (100), • formation of a pillar (400) in the substrate (100) and extending along the thickness (103) of the substrate (100) from the upper face (101) of said substrate (100), characterized in that the capacitor (300) is configured to delimit on the upper face (101) of the substrate (100) a contour (201) of an inscribed portion (202), the pillar (400) being arranged in the inscribed portion (202) of the substrate (100).

[0051] By way of example, the process comprises the following steps: - conformal deposition of a first layer on the surface of the three-dimensional structure (200) such that a first part of the first layer forms a first layer (501) of the capacitive stack (500) of the capacitor (300) and a second part (404) of the first layer is formed in the pillar (400) and, - the removal of part of the first layer (500) on the upper face (101) of the substrate (100) between the pillar (400) and the capacitive stack (500) so that the pillar (400) and the capacitive stack (500) are not electrically connected.

[0052] By microelectronic component, we mean any type of device made using microelectronic means. These devices include, in particular, in addition to devices with a purely electronic purpose, micromechanical or electromechanical devices (MEMS, NEMS...),

[0053] Vertical means that which is directed along the thickness of the stack or substrate, that is to say along the principal direction of extension of the stack or substrate, and horizontal means that which is perpendicular to the vertical. The top and bottom being vertically opposite.

[0054] Transverse is understood to mean a direction perpendicular to a longitudinal direction. The longitudinal direction is understood to mean the thickness of the stack or substrate. A cross-section is a cut perpendicular to the longitudinal axis. A cross-section is a cut perpendicular to the thickness of the substrate stack.

[0055] The width of a cavity or pillar is defined as the dimension of the cavity or pillar transverse to the thickness.

[0056] The term "upper," used in particular to describe a face of the substrate, here serves only to designate one of the two faces of the substrate (the other being the lower face), without making any assumption about the relative position of the faces along a vertical direction. The upper face could thus also have been called the front face, as opposed to a rear face.

[0057] The shapes or dimensions given for certain components of the present invention are always only indicative and are understood as including substantially equivalent shapes and dimensions.

[0058] A parameter "approximately equal to / greater than / less than" or "of the order of" a given value means that this parameter is equal to / greater than / less than the given value, to within 10% or even 5% of that value.

[0059] It is specified that within the framework of the present invention, the term "on", "over", "covers", "above", "underlying", or "below", or their equivalents, do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but it does mean that the first layer at least partially covers the second layer, either by being directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0060] A substrate, film, layer, chip or protrusion "based on" a material A means a substrate, film, layer, chip or protrusion comprising this material A and possibly other materials, for example dopant elements.

[0061] The term “coating” refers to a layer that is formed, in particular by modification of the underlying layer or by a deposit on this underlying layer.

[0062] The term “conforming” means a layer geometry which, within manufacturing tolerances, has an identical thickness despite changes in layer direction, for example at the protrusion flanks.

[0063] The word "dielectric" refers to a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator.

[0064] The use of the indefinite article "a" or "an" for an element or a step does not exclude, unless otherwise stated, the presence of a plurality of such elements or steps.

[0065] The terms "first", "second" and "third", etc. are used simply as labels, and are not intended to impose numerical requirements on their objects.

[0066] By "coupled" we mean that two or more elements are in direct physical or electrical contact.

[0067] The invention relates to a semiconductor device comprising a three-dimensional structure 200 formed in a substrate 100.

[0068] Basic capacitor structures are essentially stacks of layers along one direction, the thickness 103 of the substrate. In this sense, their shape is monotonic in that direction. The 3D shape here refers to a geometry more complex than a stack of layers along a single direction; it can be a shape defined by one or more cavities or trenches in which layers are present with a stacking that extends in several directions, depending on the surface area of ​​the cavity or trench that is covered. 3D structures also cover structures with several functionally connected cavities or trenches, typically to form parts of a single capacitor 300.

[0069] The semiconductor device comprises a substrate 100.

[0070] The three-dimensional structure 200 can be implemented or made in a substrate 100, such as a semiconductor substrate.

[0071] In one embodiment, the semiconductor substrate 100 can be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure.

[0072] In other embodiments, the semiconductor substrate 100 can be formed using alternative materials, which may or may not be combined with silicon, which include, but are not limited to, germanium, indium antimonide, the lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of materials from Group III-V or Group IV.

[0073] Although a few examples of materials from which the substrate 100 can be formed are described here, any material that can serve as a foundation on which a semiconductor device can be constructed falls within the spirit and scope of this disclosure.

[0074] The three-dimensional structure 200 is formed in the substrate 100, more particularly in a part of the substrate. For the remainder of this description, the substrate is defined as comprising an upper face 101 opposite a lower face 102.

[0075] The three-dimensional structure 200 comprises at least one pillar 400. Preferably, the three-dimensional structure comprises one pillar 400, but may comprise several pillars 400. The pillar 400 extends along the thickness 103 of the substrate 100. The pillar 400 is open at the upper face 101 of the substrate 100. The pillar 400 may or may not be open at the lower face 102 of the substrate 100.

[0076] According to different embodiments, the pillar 400 is a vertical structure that can have various functions, whether electrical, thermal, or packaging. For example, the pillar 400 can be an interconnect, a via or through-silicon via (TSV for "Through Silicon Via," i.e., via through silicon; one can also encounter through-glass vias, known as "TGV"), a vertical thermal dissipation structure, or a vertical encapsulation structure.

[0077] An example of an implementation is illustrated in [Fig. 8], which shows a three-dimensional assembly 600 comprising two electronic chips, for example two processors 610, and a passive interposer 620 that allows their interconnection and their connection to another level through copper pillars 630, thus achieving a signal redistribution level. Advantageously, the three-dimensional structure 200 according to the invention is arranged at the level of the passive interposer 620.

[0078] The pillar 400 having a depth 402 extending along the thickness 103 of the substrate 100 and a width 401 extending transversely to the thickness 103 of the substrate 100. As an example, the width 401 of the pillar 400 is greater than or equal to 2pm.

[0079] The pillar 400 has lateral walls 403 having a main vertical component. Preferably, the lateral walls 403 of the pillar 400 are vertical, that is to say extending along the thickness 103 of the substrate 100.

[0080] According to a preferred embodiment, the pillar 400 has a circular cross-section relative to the substrate thickness. Other pillar 400 shapes can be considered, such as polygonal, parallelepiped, or oval.

[0081] The pillar 400 is open at the upper face 101 of the substrate 100 and may or may not be open at the lower face 102 of the substrate 100. According to the embodiments illustrated in the figures, the pillars 400 are not open at the lower face 102 of the substrate 100. Subsequent manufacturing steps of the semiconductor device may, however, include the addition of an underlying layer at the lower face 102 of the substrate 100, resulting in the pillar 400 being open at the lower face 102 of the substrate 100.

[0082] The semiconductor device according to the invention comprises a three-dimensional structure 200.

[0083] The three-dimensional structure 200 is formed in a part of the substrate 100 and includes a three-dimensional capacitor 300. The three-dimensional capacitor 300 includes a capacitive stack 500 at least partially housed in a cavity formed in the substrate 100. The three-dimensional capacitor 300 thus has a three-dimensional structure allowing to increase the developed surface area and the associated storage capacity.

[0084] Advantageously, according to the invention, the substrate 100 comprises at least one cavity. The substrate 100, more specifically the three-dimensional structure 200, can comprise up to 20 cavities, more specifically from 2 to 10 cavities. Advantageously, where the substrate comprises several cavities, the cavities comprise the same capacitive stacking 500 so as to optimize the capacity of the condenser 300. The following description refers to one cavity, but applies to all the cavities when the three-dimensional structure 200 comprises more than one cavity. The cavity extends along the thickness 103 of the substrate 100 from the upper face 101 of said substrate 100. The cavity thus penetrates the substrate 100. Advantageously, the cavity and the pillar 400 extend along the same principal direction parallel to the thickness 103 of the substrate 100.

[0085] The cavity is open at the upper face 101 of the substrate 100 and advantageously non-open at the lower face 102 of the substrate 100 so as to allow the arrangement of the capacitive stack 500 on the largest possible substrate surface.

[0086] In the rest of the description, the three-dimensional capacitor 300 can simply be called capacitor 300.

[0087] According to the invention, the capacitor 300 is configured to delimit on the upper face 101 of the substrate 100, a contour 201 of an inscribed portion 202.

[0088] The contour 201 may be of various shapes such as for example circular, ovoid, parallelepiped, polygonal.

[0089] Advantageously, according to the invention the inscribed portion 202 comprises at least one pillar 400. Preferably, the pillar 400 is arranged in the inscribed portion 202 defined by the capacitor 300.

[0090] According to a preferred embodiment, pillar 400 is arranged at the center of the inscribed portion 202. More specifically, the center of pillar 400 corresponds to the center of the inscribed portion 202.

[0091] Advantageously, the three-dimensional structure 200 comprises a first conforming layer including a first portion forming the first electrode layer 501 of the capacitive stack 500 and a second portion 404 arranged in the pillar 400, more specifically covering the lateral walls 403 of the pillar 400. The first electrode layer 501 and the second portion 404 are advantageously identical, in particular since they are preferably formed simultaneously by a single deposition of a first layer. Preferably, the first portion forming the first electrode layer 501 and the second portion 404 arranged in the pillar 400 are electrically disconnected from each other. The electrical disconnection of the first part forming the first electrode layer 501 and of the second part 404 arranged in the pillar 400 is advantageously achieved by partial withdrawal 504 of the first layer, in particular on the upper face 101 of the substrate 100.

[0092] The arrangement of the three-dimensional capacitor 300 in a three-dimensional structure 200 comprising a pillar 400 allows a saving of space by using a part of substrate 100 conventionally used while allowing a pooling of steps in particular the deposition of the first layer without however implying a functional link between the capacitor 300 and the pillar 400.

[0093] According to a preferred embodiment, the width 401 of the pillar 400 is at least 20 times greater than the width 303 of a cavity, preferably 50 times greater than the width 303 of a cavity.

[0094] According to a first embodiment, the cavity of the capacitor 300 is a trench 301. A trench 301 is understood to be a cavity in the substrate 100 having a length greater than its width 303. The length is understood as the direction transverse to the thickness and the width. Preferably, the ratio between the length and the width is greater than or equal to 2, preferably greater than or equal to 20. By way of example, the trench 301 has a depth, that is to say a dimension extending in a direction parallel to the thickness 103, of approximately 20 pm.

[0095] According to this first embodiment, trench 301 is straight or curved. The straight trench 301 can be a straight line extending in a single direction or extending in several directions, thus forming a broken line. The trench 301 curve perhaps a continuous curve following a single direction or extending in several directions and thus forming a curved line.

[0096] According to a preferred embodiment of this first configuration, the capacitor 300 may include a trench 301 that defines the contour 201 of the inscribed portion 202. The trench 301 is thus closed upon itself, and the ends of the trench 302 meet. Depending on the shape of the trench 301, the inscribed portion 202 can be of any shape. Preferably, the trench 301 is, for example, circular, polygonal, or parallelepiped-shaped.

[0097] In this possibility, pillar 400 is at the center of inscribed portion 202 and trench 301 forms contour 200 of inscribed portion 202.

[0098] The capacitor 300 may comprise several cavities and, in particular, several trenches 301. According to the preferred embodiment, the capacitor 300 comprises several self-enclosed and concentric trenches 301. Preferably, the trenches 301 are circular, as illustrated in Figures 1 and 3. The trenches 301 advantageously comprise the same capacitive stack 500 so as to increase the capacitance surface area of ​​the capacitor 300.

[0099] According to a second embodiment, the cavity of the capacitor 300 is a column 302. A column is understood to be a cavity in the substrate 100 having a length substantially equivalent to its width. Preferably, the ratio between the length and the width is on the order of 1. By way of example, the length and width are 1 Opm and the depth is on the order of 20 pm.

[0100] Each column 302 has a circular, ovoid, parallelepiped, or polygonal cross-section. All columns 302 may or may not have the same cross-sectional shape.

[0101] Advantageously, in this second embodiment, the capacitor 300 comprises at least three columns 302. The columns 302 are thus advantageously arranged so as to define a contour 201 of an inscribed portion 202.

[0102] Advantageously, the contour 201 of the inscribed portion 202 is formalized by the set of lines 203 connecting successive columns 302 to one another. Preferably, the contour 201 is formed by the set of lines 203 connecting the columns 302 closest to the pillar 400.

[0103] The columns 302 are advantageously arranged around the pillar 400 so as to form an advantageously circular contour 201 as illustrated in [Fig.4].

[0104] As a preferred example, the transverse distance 104 to the thickness 103 separating the center of the pillar 400 from the center of a cavity is less than or equal to 100pm.

[0105] As a preferred example, the transverse distance 104 to the thickness 103 separating the center of the pillar 400 from the center of a cavity is greater than or equal to 5pm.

[0106] According to a third embodiment, the first and second embodiments are combined. The capacitor 300 comprises at least one trench 301 and at least one column 302.

[0107] Regardless of the embodiment described above, the capacitor 300 comprises a capacitive stack 500 including a first electrode layer 501 advantageously formed at least by the first part of a first layer 501, an intermediate layer 502 and a second electrode layer 503.

[0108] Preferably, the first electrode layer 501 covers the lateral walls of at least one cavity, preferably of all the cavities of the three-dimensional structure 200, and of the upper face 101 of the substrate 100 exposed between the cavities. As a preferred example, the first electrode layer 501 is selected from materials such as TiN, TaN, W, Ni, Pt, and Ru.

[0109] Preferably, the intermediate layer 502 is a dielectric ionic material and covers the first electrode layer 501. The intermediate layer 502 may be a solid-state electrolyte. As a preferred example, the dielectric is an ionic conductor. By way of example, the ionic conductor has a high ionic conductivity at room temperature, at least 1 pS.cm-1, and also has a low associated activation energy, generally less than 0.6 eV.The 502 intermediate layer may comprise A12O3, HfO2, ZrO2, TiO2, Nb2O5, Ta2O5, SrTiOx, BaTiOx, Ga2O3, Y2O3, a rare earth oxide, a solid-state electrolyte, a glass electrolyte, a ceramic electrolyte, LiPON, an ionic antiperovskite, Li3ClO, a doped Li(3-2x)DxC10 where D is a divalent cationic dopant, hafnium silicate, zirconium silicate, hafnium dioxide, hafnium zirconate, zirconium dioxide, aluminium oxide, titanium oxide, silicon nitride, carbon-doped silicon nitride, silicon carbide and hafnium nitride silicate, a high k dielectric material, or an alloy thereof.

[0110] Preferably, the second electrode layer 503 covers the intermediate layer 502. As a preferred example, the second electrode layer 503 is TiN, TaN, W, Ni, Pt, Ru.

[0111] The first electrode layer 501, the second electrode layer 503, and the second part 404 may comprise W, Mo, Ti, Ta, Al, TaN, TiN, TiC, WN, MoN, MoC, Co, Ni, Cu, Ru, Pd, Pt, Ir, IrOx, graphene, MnO2, Li, RuOx, ITO, SrRuOx, a metal oxide, graphitic carbon, an alkali metal, a low work function metal, a transition metal oxide, a Co oxide, LiCoO2, NaCoO2, a transition metal dichalcogenide, a spinel oxide, LiMn2O4, LiNiMnO4, a conducting polymer or a conducting metal.

[0112] Advantageously, the first electrode layer 501 extends at its ends onto the upper face 101 relative to the intermediate layer 502. the second layer of electrode 503 so as to allow the connection of the first layer of electrode 501 and the second layer of electrode 503 separately.

[0113] According to one possibility, either or both of the first electrode layer 501 and the second electrode layer 503 is an ion intercalation electrode. In the case where both the first electrode layer 501 and the second electrode layer 503 are intercalation electrodes, the semiconductor device includes a micro-battery.

[0114] Advantageously, the pillar 400 comprises the second portion 404 of the first conforming layer covering the side walls 403. According to one possibility, the pillar 400 comprises a metallic material 405 filling the entire remaining volume and providing a level surface with the upper face 101 of the substrate 100. The presence of the second portion 404 of the first conforming layer in the pillar 400 may be of interest as an interdiffusion barrier between the substrate 100 and the metallic material 405, or also as a diffusion barrier for ions from the metallic material 405 to the substrate 100. The second portion 404 of the first conforming layer acts as a diffusion barrier between the substrate 100 and the metallic material 405, or also as an additional chemical barrier to improve the encapsulation of the components.

[0115] According to one possibility, the pillar 400 comprises a portion of the second electrode layer 503. A portion of the second electrode layer 503 is arranged on the metallic material 405 so as to at least partially cover the metallic material 405. This portion of the second electrode layer 503 facilitates / optimizes electrical, thermal, or mechanical contact between the metallic material 405 and the subsequent layers. By way of example, this portion of the second metallic layer 503 is identical to the second metallic layer 503 described above with reference to capacitive stacking.

[0116] The term "inscribed" means that the capacitor 300 has a three-dimensional shape extending onto the upper face 101 of the substrate, delimiting two surface areas on this upper face 101: an inner part of the capacitor 300, which is the inscribed area, and an outer part. The shape of the capacitor 300 provides it with an inner edge (as is the case for a circular trench 301), or a border of cavity placement (as is the case if the capacitor 300 is formed with several cavities, for example, of the column type 302, which surrounds an inner part according to a profile, regular or irregular, delimiting this surface). By joining the edges of these cavities spaced around the inscribed surface, the shape of this border is revealed. The cavities then act like posts delimiting a surface of the ground, with barriers joining the posts revealing the shape of this surface, which is the inscribed surface.The outline of this surface, formed by the capacitor, can therefore be . continuous (as in the case of a trench with a closed contour, for example circular) or discrete as in the case of via-shaped cavities.

[0117] According to one possibility, the semiconductor device according to the invention is made on the back side of a CMOS technology.

[0118] According to one possibility, the semiconductor device includes an underlying layer such as, for example, a substrate comprising a transistor and / or an overlying layer.

[0119] According to one possibility, the semiconductor device is made at the end of the line of interconnections also called in English Back end of Line (BEOL).

[0120] An example of the integration of a semiconductor device according to the invention is illustrated in [Fig.8].

[0121] According to another aspect, the invention relates to a method for manufacturing a semiconductor device as described above. The various steps of the method are illustrated in Figures 9 to 15.

[0122] The manufacturing process begins as illustrated in [Fig.9] with the presence of substrate 100.

[0123] The manufacturing process advantageously includes a step a) comprising the fabrication of at least one cavity and at least one pillar 400 in a substrate 100. This first fabrication step is carried out by a plasma etching step, more commonly known as deep ion reactive etching or DRIE, and understood by those skilled in the art. Advantageously, the arrangement of the at least one cavity and the pillar 400 is defined such that the cavity defines a contour of an inscribed portion with the pillar arranged within the inscribed portion. The semiconductor device obtained at the end of step a) is illustrated in [Fig. 10].

[0124] Following step a), the process includes a step b) comprising the conformal deposition of a first layer onto the three-dimensional structure 200, i.e. in the cavity and in the pillar as well as on the upper face 101 of the substrate 100. The conformal deposition is carried out by conventional methods known to those skilled in the art, such as chemical vapor deposition (CVD) or atomic deposition (ALD). The semiconductor device obtained at the end of step b) is illustrated in [Fig. 11].

[0125] Preferably, the process then includes a step c) of filling the pillar 400. The filling is carried out by conventional methods known to those skilled in the art, such as electrochemical deposition or electroless deposition. The semiconductor device obtained at the end of step c) is illustrated in [Fig. 12].

[0126] Preferably, the process includes a step d) of advantageously partial removal 504 of the first layer so as to electrically disconnect a first part of the first layer 501 and a second part 404 of the first layer. Preferably, the removal of the first layer is carried out at the face upper 101 of substrate 100, preferably between the cavity and the pillar 400. Removal is carried out by conventional methods known to those skilled in the art, such as chemical etching or plasma etching, both coupled with photolithography for pattern definition. The semiconductor device obtained at the end of step d) is illustrated in [Fig. 13].

[0127] This step d) can be carried out before or after step c).

[0128] Preferably, the process then includes the successive steps to carry out the continuation of the capacitive stack 500. The process includes the conformal deposition of the intermediate layer 502 and then the conformal deposition of the second electrode layer 503. The realization of the capacitive stack 500 is carried out by the conventional methods known to those skilled in the art such as: atomic deposition or ALD.

[0129] According to one possibility, the conformal deposition of the intermediate layer 502 is carried out only as illustrated in [Fig. 14] or the conformal deposition of the intermediate layer 502 is carried out over the whole of the three-dimensional structure 200 and the process includes a step of removing the intermediate layer 502 outside the capacitor 300.

[0130] Similarly, the conformal deposition of the second electrode layer 503 is carried out only as illustrated in [Fig. 15] or the conformal deposition of the second electrode layer 503 is carried out on the entire three-dimensional structure 200 and the process includes a step of removing the second electrode layer 503 from the capacitor 300 and advantageously from the pillar 400 forming a first part of the second layer 503 participating in the capacitive stacking and a second part of the second layer 503 on the pillar 400. The first part and the second part are electrically disconnected from each other.

[0131] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

[0132] List of references 100. Substrate 101. Top surface 102. Lower surface 103. Thickness 104. Transverse distance 200. Three-dimensional structure 201. Outline 202. Portion registered 203. Line 300. Three-dimensional capacitor 301. Trench 302. Columns 303. Cavity width 400. Pillar 401. Pillar width 402. Pillar Depth 403. Side walls 404. Second part of the first layer 405. Metal 500. Capacitive stacking 501. First electrode layer 502. Intermediate layer 503. Second layer 600. Three-dimensional assembly 610. Processor 620. Passive interposer 630. Copper Pillars

Claims

1.

2. Demands Semiconductor device comprising: • a substrate (100) comprising at least one cavity, and • a three-dimensional structure (200) formed in the substrate (100) comprising: i. a three-dimensional capacitor (300) comprising a capacitive stack (500), the capacitive stack (500) being at least partially housed in at least one cavity of the substrate (100), ii. a pillar (400) extending along the thickness (103) of the substrate (100) from the upper face (101) of said substrate (100), Characterized in that at least one cavity extends along the thickness (103) of the substrate (100) from the upper face (101) of said substrate (100), and the three-dimensional capacitor (300) is configured to delimit, on the upper face (101) of the substrate (100), a contour (201) of an inscribed portion (202), the pillar (400) being arranged in the inscribed portion (202) of the substrate (100), and the capacitive stack (500) comprises a first electrode layer (501), an intermediate layer (502) and a second electrode layer (503) and the three-dimensional structure (200) comprises a first conforming layer including a first part forming the first electrode layer (501) of the capacitive stack (500) and a second conforming part (404) arranged in the pillar (400), the first part (501) and the second part (404) being electrically disconnected from each other, and the intermediate layer (502) is an ionically conductive dielectric material. Semiconductor device according to the preceding claim in which the ionically conductive dielectric material has an ionic conductivity at room temperature of at least 1 pS.cm-1.

3. Semiconductor device according to any one of the preceding claims wherein the ionically conductive dielectric material has an associated activation energy of less than 0.6eV.

4. Semiconductor device according to any one of the preceding claims wherein the pillar (400) is arranged at the center of the inscribed portion (202).

5. Semiconductor device according to any one of the preceding claims wherein the transverse distance (104) to the thickness (103) of the substrate (100) between the center of a cavity and the center of the pillar (400) is less than or equal to 100pm.

6. Semiconductor device according to any one of the preceding claims wherein the transverse distance (104) to the thickness (103) of the substrate (100) between the center of a cavity and the center of the pillar (400) is less than or equal to 5pm.

7. Semiconductor device according to any one of the preceding claims wherein at least one cavity of the capacitor (300) is a trench (301).

8. Semiconductor device according to the preceding claim in which the trench (301) is circular and arranged in the form of a circle around the pillar (400).

9. Semiconductor device according to any one of the two preceding claims wherein the capacitor (300) comprises at least two circular and concentric trenches (301).

10. Semiconductor device according to any one of claims 1 to 5 wherein at least one cavity of the capacitor is a column (302).

11. Semiconductor device according to the preceding claim the capacitor (300) comprises a plurality of columns (302).

12. Semiconductor device according to the preceding claim in which the plurality of columns (302) is arranged in a circular fashion around the pillar (400).

13. Semiconductor device according to any one of the preceding claims wherein the pillar (400) comprises a metallic material so as to fill the pillar (400) level with the upper face (100) of the substrate (100).

14. Processor comprising a semiconductor device according to any one of the preceding claims wherein the three-dimensional structure is located at interconnects coupled to the processor, or at the rear of the processor.

15. A method for manufacturing a device according to any one of claims 1 to 14 comprising a step a) comprising forming at least one cavity of a three-dimensional capacitor (300) and at least one pillar (400) in a substrate (100), the capacitor (300) being configured to delimit on the upper face (101) of the substrate (100) a contour (201) of an inscribed portion (202), the pillar (400) being arranged in the inscribed portion (202) of the substrate (100), a step b) comprising conformally depositing a first layer on the three-dimensional structure (200), i.e. in the cavity and in the pillar (400) as well as on the upper face (101) of the substrate (100), such that a first part of the first layer forms a first layer (501) of a capacitive stack (500) of the capacitor (300) and that a second part (404) of the first layer is formed in the pillar (400), a step c) of filling the pillar (400),a step d) of partial removal of the first layer so as to electrically disconnect the first part of the first layer (501) and the second part (404) of the first layer, step d) being able to be carried out before or after step c).,

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