SEMICONDUCTOR LAYER TRANSFER PROCESS

Abstract

A SEMICONDUCTIVE LAYER TRANSFER METHOD One aspect of the invention relates to a method for transferring a semiconductor layer (40) from a donor substrate (10) to a receiving substrate (20), the method comprising the following successive steps: first implantation (S120) of first light ions (3a) in the donor substrate (10) at a predetermined implantation depth (30) so as to form a buried brittle plane (300), epitaxy (S130) on the donor substrate (10) of the semiconductor layer (40) to be transferred, second implantation (S140) of second light ions (3b) in the donor substrate (10) through the semiconductor layer (40) to be transferred at the level of the brittle plane (300), assembly (S150) by bonding of the receiving substrate (20) and the donor substrate (10) coated with the semiconductor layer (40) to be transferred, the semiconductor layer (40) to be transferred being disposed between the recipient (20) and donor (10) substrates, and fracturing (S160) by annealing,said fracturing annealing (S160), of the donor substrate (10) along the buried brittle plane (300), the first ions (3a) being chosen and implanted at a first dose (D1) so that, during epitaxy (S130), there is no fracturing at the predetermined implantation depth (30), and the second ions (3b) being chosen and implanted at a second dose (D2) so that, during fracturing annealing (S160), fracturing of the donor substrate (10) occurs.

Description

Title of the invention: LAYER TRANSFER METHOD SEMICONDUCTOR TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of semiconductor layer transfer processes.

[0002] The present invention relates more particularly to a method for transferring a semiconductor layer by ion implantation, assembly, and fracturing, in which the semiconductor layer is reduced to defects before the assembly step. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] To increase the integration density of integrated circuits, a new technique called 3D monolithic integration consists of stacking layers of electronic devices on top of each other.

[0004] Electronic devices are typically transistors. Each layer or level of transistors is formed in a semiconductor layer called the active layer. The first level of transistors is formed on the surface of an initial substrate, also called a wafer. The second level of transistors is made from a semiconductor layer formed on top of the first level of transistors, that is, above the surface of the initial substrate.

[0005] To obtain such a semiconductor layer, it is possible to transfer a semiconductor layer from another substrate, called the donor substrate, onto the initial substrate, referred to as the receiving substrate. A known transfer technique called Smart Cut™ is based on the combination of light ion implantation in the donor substrate, molecular adhesion assembly of the donor and receiving substrates, and fracture annealing of the donor substrate.

[0006] This process comprises 1) providing a donor substrate, generally a silicon wafer, 2) implanting ions, most often light ions such as hydrogen, through the surface of the donor substrate to create nanocavities buried within the donor substrate, at a depth determined by the implantation depth, and to delimit the semiconductor layer to be transferred, 3) assembling the donor substrate onto a recipient substrate, and then 4) a final annealing (heating) of the assembly, which activates the formation of dihydrogen (H2). This gas feeds the nanocavities and causes them to grow. Due to the mechanical stress created by the interface between the assembled donor and recipient substrates, the nanocavities widen and cluster laterally at the depth determined by the implantation, creating microcracks and a final fracture that rapidly propagates to the entire wafer. The separation of the semiconductor layer from the donor substrate and its transfer to the recipient substrate is then carried out.

[0007] This process offers numerous advantages and is well-established. However, some problems remain, including a particular issue inherent to the light ion implantation step. Indeed, light ion implantation induces defects in the semiconductor layer that impair its electrical performance, and therefore its quality. These defects are related to the fact that the ions induce defects of various kinds (vacancies, interstitials, hydrogenated complexes, nanocavities) not only around the determined implantation depth, but also along their path in the donor substrate. Thus, defects are present in the semiconductor layer, due to the light ion implantation, with a density proportional to the dose at which the implantation is performed. These defects affect the mobility of the charge carriers, and therefore the electrical characteristics of the semiconductor layer.It should be noted that the heating that takes place during fracture annealing does not effectively heal defects formed by implantation and may even lead to the growth / formation of new defects or cavities.

[0008] It is essential to reduce this number of defects in the semiconductor layer in order to guarantee satisfactory electrical performance for the electronic components that will be manufactured there, and this, by maintaining an implantation dose adapted to the transfer of said semiconductor layer.

[0009] To achieve this, a commonly used solution consists of reducing the number of defects after the transfer step by subjecting the receiving substrate (which includes the transferred semiconductor layer) to high temperatures, i.e., temperatures exceeding 900°C or 1000°C, applied for extended periods, for example, several hours. However, such temperatures are unsuitable when the semiconductor layer has been transferred onto a receiving substrate containing a layer of pre-formed electronic devices. Indeed, they cause a degradation of the performance, particularly the electrical performance, of the electronic devices in this underlying layer. It is therefore impossible to reduce the defects created by the implantation of light ions in this way.

[0010] In the context of a semiconductor layer transfer process based on light ion implantation, there is therefore a need to reduce the number of defects in the semiconductor layer other than by annealing carried out at high temperature after fracturing. Summary of the invention

[0011] The invention offers a solution to the problems mentioned above, by replacing the single implantation step with two implantation steps and by performing an epitaxial step of the semiconductor layer between the two implantation steps. Furthermore, the implantation conditions of each of the implantation steps, in particular the implanted ions and the chosen implantation dose(s), are adapted according to the epitaxial and fracturing annealing to induce fracturing only during the fracturing annealing.

[0012] One aspect of the invention thus relates to a method for transferring a semiconductor layer from a donor substrate to a recipient substrate, the method comprising the following successive steps: • initial implantation of first light ions into the donor substrate at a predetermined implantation depth so as to form a fragile plane buried at the predetermined implantation depth, • Epitaxy on the donor substrate of the semiconductor layer to be transferred, • Second implantation of second light ions into the donor substrate through the semiconductor layer to be transferred at the level of the fragile plane, • assembly by bonding of the receiving substrate and the donor substrate coated with the semiconductor layer to be transferred, the semiconductor layer to be transferred being placed between the receiving and donor substrates, and • annealing of the donor substrate along the buried brittle plane, a process in which: • The first ions are selected and implanted in an initial dose so that, during epitaxy, there is no fracturing at the predetermined implantation depth, • The second ions are chosen and implanted at a second dose so that, during the fracturing annealing, the donor substrate is fractured.

[0013] Thus, the implantation of the first light ions, that is to say ions whose atomic mass is less than or equal to 11, is carried out with a dose such that the first ions do not induce, during the epitaxy of the semiconductor layer to be transferred, fracturing at the predetermined implantation depth.

[0014] Under these conditions, the thermal budget (defined by the temperature and the duration of application of this temperature) used during the epitaxial stage does not lead to the growth and clustering of nanocavities in the buried fragile plane, that is, nanocavities formed at the implantation depth predetermined by the initial implantation. There are several reasons for this, including the fact that the density of nanocavities and / or the quantity of gas produced is insufficient.

[0015] It should be noted that if a single implantation were performed before epitaxy, then the implanted ions would necessarily be chosen so that, at the implanted dose, fracturing would occur after assembly of the donor and recipient substrates. The implanted dose The temperature would therefore be high enough that the heat treatment inherent in epitaxy would lead to fracturing of the donor substrate. To avoid this, the epitaxy temperature would need to be limited to a maximum of 400°C. However, it is currently not possible to form a semiconductor layer at such a temperature.

[0016] The first implantation therefore makes it possible to carry out epitaxy without fracturing the donor substrate or without creating defects in the semiconductor layer.

[0017] Furthermore, the epitaxy of the semiconductor layer is followed by the second implantation. This second implantation is performed at approximately the same depth as the first implantation (taking into account the epitaxial thickness) so that, during fracture annealing, fracturing of the donor substrate is achieved due to the cumulative effect of the ions implanted during the first and second implantations. The implantation depth is primarily a function of the ion implantation energy. Software (of the SRIM type for "Stopping and Range of Ions in Matter") allows for the simulation of the required implantation energies. The two implantations take place in approximately the same plane. A difference of a few nanometers is possible, as the implanted ions can reach the nanocavities of the brittle plane during fracture annealing.

[0018] The semiconductor layer formed is thus advantageously traversed only by the ions implanted during the second implantation in a much smaller quantity than the light ions required when a single implantation is conventionally carried out.

[0019] The number of defects in the semiconductor layer is thus reduced before the transfer and without resorting to a high-temperature annealing step.

[0020] According to a first embodiment, the process comprises, between the first implantation of light ions and the epitaxial step of the semiconductor layer to be transferred, an additional surface preparation step comprising the following successive substeps: • Deoxidation of a free surface of the donor substrate, • annealing of the donor substrate under an atmosphere including hydrogen at a temperature greater than or equal to 400°C (and advantageously greater than or equal to 500°C) for a period of between 5 seconds and 10 minutes.

[0021] The higher the thermal budget of this hydrogen annealing, referred to as H2 annealing, the lower the residual contamination by oxygen atoms at the interface between the substrate and the epitaxially deposited semiconductor layer, and the better the quality of the transferred semiconductor layer. A better understanding of the impact of H2 annealing conditions on the quality of deposited films can be obtained by referring to Hartmann et al., “A benchmark of 300mm RP-CVD chambers for the low temperature epitaxy of Si and SiGe”, ECS Transactions, 86 (7) 219-231 (2018).

[0022] Thus, the surface of the donor substrate is prepared for the epitaxy of the semiconductor layer to be transferred. This contributes to the formation of a semiconductor layer with a reduced number of defects.

[0023] According to a second embodiment, the process comprises the additional steps of: • before the first implantation, a step of depositing a sacrificial layer onto a free surface of the donor substrate, • after the first implantation and before the epitaxy step of the semiconductor layer to be transferred, a step of removal of the sacrificial layer.

[0024] The combination of the deposition and removal of the sacrificial layer aims to prepare the surface for the epitaxy of the semiconductor layer to be transferred.

[0025] According to a first development of this second embodiment, the sacrificial layer is a dielectric layer.

[0026] The dielectric layer is, for example, a silicon oxide layer. It acts as a protective layer, preserving the surface of the donor substrate from contamination or impurities. Since epitaxy is performed on this surface, the semiconductor layer to be transferred will be formed under better conditions, and its quality will be improved.

[0027] According to a second development of this second embodiment, the sacrificial layer comprises a stack of a first sublayer of silicon and germanium alloy, called the first etching stop layer, and a second sublayer of dielectric material disposed on the first sublayer, and the step of removing the sacrificial layer comprises the selective removal of the second dielectric sublayer from the first etching stop layer and then the removal of the first etching stop layer.

[0028] The first etching stop layer, like the dielectric layer, helps to preserve the surface on which the epitaxy will be carried out from impurities that could degrade the semiconductor layer.

[0029] Removing the first etching stop layer improves surface preparation by obtaining a lower surface roughness.

[0030] According to an alternative embodiment of the second preceding development, the step of epitaxy of the semiconductor layer to be transferred is carried out less than 30 minutes after the step of removing the first arrest layer.

[0031] Preferably, the step of epitaxy of the semiconductor layer to be transferred is carried out less than 10 minutes after the step of removing the first arrest layer.

[0032] This short delay helps to limit the risk of contamination of the surface on which the epitaxy of the semiconductor layer to be transferred will be carried out.

[0033] According to another alternative embodiment of the second development, the step of The removal of the first etching stop layer and the epitaxy step of the semiconductor layer to be transferred are carried out in the same equipment.

[0034] Thus, the risk of surface contamination is reduced and the process is simplified.

[0035] Advantageously, the process includes, after the step of removing the first etching stop layer and before the step of epitaxy of the semiconductor layer to be transferred, an additional step of annealing the donor substrate carried out in the same equipment as the step of removing the first stop layer and the step of epitaxy of the semiconductor layer to be transferred.

[0036] This annealing step of the donor substrate carried out in-situ in the epitaxy equipment makes it possible to complete the step of removing the first etching stop layer and to improve the quality of the surface on which the semiconductor layer to be transferred will be formed.

[0037] Advantageously, the additional step of annealing the donor substrate is carried out under the following temperature, pressure and time conditions: 500°C, 2666 Pa (or 20 Torr), 2 minutes.

[0038] With such a thermal budget, the properties of the layer (or fragile plane) damaged by the first implantation are still compatible with a layer transfer after the second implantation.

[0039] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the process according to one aspect of the invention may have one or more complementary characteristics from among the following, compatible with all the previous embodiment variants and considered individually or according to all technically possible combinations.

[0040] The first light ions are helium ions, hydrogen ions, boron ions, a mixture of helium ions and hydrogen ions or a mixture of hydrogen ions and boron ions.

[0041] The second light ions are helium ions, hydrogen ions or a mixture of helium ions and hydrogen ions.

[0042] It should be noted that it is particularly advantageous to use hydrogen ions for the second implantation, rather than helium ions, because the latter induce fewer defects, even if the implantation dose is higher.

[0043] The semiconductor layer to be transferred is a layer of silicon (or Si), germanium (or Ge), a silicon and germanium alloy (or SiGe), a silicon, germanium and carbon alloy (or SiGeC), a germanium and tin alloy (or GeSn) or a silicon, germanium and tin alloy (SiGeSn), or a stack of a silicon sublayer and a silicon and germanium alloy sublayer (Si / SiGe).

[0044] At a basic level, the semiconductor layer to be transferred comprises a first an active sublayer of silicon (or Si), germanium (or Ge), a silicon-germanium alloy (or SiGe), a silicon-germanium-carbon alloy (or SiGeC), a germanium-tin alloy (or GeSn) or a silicon-germanium-tin alloy (SiGeSn), and a second etching stop sublayer such as a silicon-germanium alloy etching stop sublayer, disposed under the first active sublayer, and the receiving substrate has, after the fracturing step, a residual layer from the donor substrate, the process then comprising the following successive steps: • Removal of the residual layer from the donor substrate by selectively etching said residual layer relative to the second etching stop sublayer, • Removal of the second etching stop underlayer.

[0045] Thanks to the etching stop sub-layer and the selective etching step of the residual layer after transfer, no chemical-mechanical polishing is required to remove the residual layer from the donor substrate. Furthermore, the surface roughness of the transferred layer is reduced and its thickness controlled to achieve thinner layers. The quality of the transferred layer is thus further improved.

[0046] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0047] The figures are presented for illustrative purposes only and are not in any way limiting to the invention. • Figures IA to IG schematically represent steps in the transfer process according to the invention, • Figure [Fig. 2] represents several variants of the epitaxy step of the transfer process from [Fig. 1A] to IG, • Figure [Fig. 3] shows the final multilayer structure obtained with the transfer process from figures IA to IG, • Figures 4A to 4K schematically represent a first specific embodiment of the process of figures IA to IG, allowing for improvement of the quality of the semiconductor layer, • Figures 5A to 5M schematically represent a second specific embodiment of the process shown in Figures IA to IG, which also improves the quality of the semiconductor layer, • Figure [Fig. 6] schematically represents a first test substrate used to determine the first implantation dose, • Figure 7 is a synoptic diagram representing the sequence of steps for determining the first maximum dose of the first step. implantation of the [Fig.1B], • Figure [Fig. 8] schematically represents a second test substrate used to determine the second implantation dose, • Fig. 9 is a synoptic diagram representing the sequence of steps to determine the second minimum dose of the second implantation step of Fig. 1D. • Figure 10 represents the defect density generated in a silicon substrate by hydrogen ion implantation and by the implantation of a mixture of helium and hydrogen ions. • Figure

[11] represents the etching rate of a SiGe layer, as a function of the partial etching pressure and as a function of the percentage of Ge in the SiGe alloy, • The [Fig. 12] is a synoptic diagram representing the sequence of steps to implement an additional surface preparation step, this step being between the second and third steps of the process shown in figures IA to IG.

[0048] Unless otherwise specified, the same element appearing on different figures has a unique reference. DETAILED DESCRIPTION

[0049] Figures IA to IG represent a schematic cross-sectional view of steps SI 10 to S160 of a process for transferring a semiconductor layer 40 from a donor substrate 10 to a recipient substrate 20, which makes it possible to obtain a semiconductor layer 40 reduced in defects.

[0050] The term “defects” means nano-cavities, gaps, interstitials, hydrogenated complexes, bubbles, exfoliations present in the semiconductor layer or on its surface, and causing a degradation of its electrical performance.

[0051] This transfer process includes, like the prior art Smart Cut™ process, the implantation of light ions, the assembly of two substrates by bonding and a fracture annealing.

[0052] The transfer process according to the invention is remarkable in that it comprises, before the actual transfer carried out by the bonding steps S150 and fracturing steps S160 ([Fig.1E] and [Fig.1F]), two implantation steps S120 and S140 ([Fig.1B] and [Fig.1D]) of light ions and an epitaxy step S130 ([Fig.1C]) intercalated between these two implantation steps S120 and S140.

[0053] With reference to [Fig. 1 A], the transfer process begins in the first step S110 with the provision of a donor substrate 10. The donor substrate 10 designates a support substrate, preferably a semiconductor substrate, for example silicon. In a way Generally, a plate or slice is referred to as a "substrate".

[0054] The donor substrate 10 has an upper face 11, called the free surface, which is substantially flat.

[0055] With reference to [Fig. 1B], the first step S110 is followed by a step S120 of implanting first light ions 3a into the donor substrate 10, through the free surface 11, at a predetermined depth 30, referred to as the implantation depth. This first implantation S120 creates defects in the donor substrate 10 in a so-called fragile plane 300 located at the implantation depth 30. The plane 300 is called fragile because the defects created weaken the donor substrate 10.

[0056] The implantation depth 30 is, for example, between 100 nm and 1000 nm. It is measured from the free surface 11 and perpendicular to that same surface. For example, the implantation S120 of the first ions is carried out at an energy such that the maximum of the profile of the implanted ions is found at a depth of approximately 300 nm.

[0057] This implantation energy depends on the ion species or species chosen. If the first species implanted is helium, it is on the order of 35 keV to obtain an implantation depth of 300 nm.

[0058] Light ions are species defined by an atomic mass less than or equal to 11. The first ions 3a are preferably chosen from hydrogen (or H), helium (or He), boron (or B), a mixture of helium and hydrogen (or "He+H") or a mixture of hydrogen and boron (or "H+B"). It is known that these species make it possible to create a buried fragile plane capable of leading to a transfer by Smart Cut™.

[0059] In the Smart Cut™ process, the light ion implantation step is classically associated with an annealing step carried out at an annealing temperature generally between 350°C and 600°C to fracture the donor substrate and transfer the semiconductor layer.

[0060] In the process according to the invention, the S120 step of implanting the first ions 3a is not followed by a "classical" annealing step, but is followed by an S130 epitaxy step, illustrated [Fig.1C], aimed at forming the semiconductor layer 40.

[0061] Figure [Fig.2] presents several variants of the embodiment of this S130 epitaxy step.

[0062] At the end of this step S130, the semiconductor layer 40 can be a semiconductor layer 410, preferably thin, i.e. of thickness between 5 nm and 30 nm, and formed of a material among the following: silicon (or Si), germanium (or Ge), silicon and germanium alloy (or SiGe), silicon, germanium and carbon alloy (or SiGeC), germanium and tin alloy (or GeSn) or silicon, germanium and tin alloy (SiGeSn).

[0063] The semiconductor layer 40 can, alternatively, be a stack of sub- Semiconductor layers, for example, a stack of a silicon sublayer and a silicon-germanium alloy (Si / SiGe) sublayer, or preferably, a stack of a first active sublayer 430 and a second stop sublayer 420, such as a stop sublayer made of silicon-germanium alloy (SiGe). The stop sublayer 420 is positioned below the active sublayer 430.

[0064] The active sublayer 430 is then similar to the semiconductor layer 410, that is to say, it is made of one of the following materials: silicon (or Si), silicon-germanium alloy (or SiGe), silicon-germanium-carbon alloy (SiGeC), germanium-tin alloy (or GeSn), or silicon-germanium-tin alloy (SiGeSn), and its thickness is between 2 nm and 30 nm. The etching stop sublayer 420 is preferably made of a SiGe alloy with a germanium concentration between 20% and 50%. The etching stop sublayer 420 may also have a thickness between 5 nm and 150 nm.

[0065] More generally, the stack of semiconductor sublayers may comprise several alternating active and non-etching sublayers (not shown in [Fig. 2]). The thickness of the active and non-etching sublayers may vary according to their position in the stack, as may the Si / Ge ratio forming the non-etching sublayer.

[0066] This epitaxial step S130 is carried out in epitaxial equipment and consists of growing, in a directed manner, from the free surface 11 of the donor substrate 10 implanted with the first ions, a crystal corresponding to the desired crystal for the single-crystal semiconductor layer 40. The epitaxial step may include the formation of a crystalline sublayer, called a nucleation sublayer (not shown), on the free surface 11. The semiconductor layer 40 is then epitaxially grown following this sublayer. The semiconductor layer 40 can be formed by chemical vapor deposition (CVD) techniques, such as reduced pressure chemical vapor deposition (RP-CVD) or plasma-enhanced chemical vapor deposition (PECVD).Techniques such as molecular beam epitaxy (MBE) can also be used. In RP-CVD, to deposit Si or SiGe layers at low temperature (500°C and below), one can use the operating points described in Hartmann et al., “Potentialities of disilane for the low temperature epitaxy of intrinsic and boron-doped SiGe”, Thin Solid Films 557, 19 (2014), Aubin et al., “Epitaxial growth of Si and SiGe at temperatures lower than 500 °C with disilane and germane”, Thin Solid Films 602, 36 (2016) or Hartmann et al., “A benchmark of germane and digermane for the low temperature growth of intrinsic . and heavily in-situ boron-doped SiGe”, ECS Transactions 75 (8), 281 (2016).

[0067] To deposit layers of pure Ge at temperatures less than or equal to 500°C, epitaxy conditions similar to those described in Aubin et al., “Very low temperature epitaxy of Ge and Ge rich SiGe alloys with Ge2H 6 in a Reduced Pressure - Chemical Vapour Deposition tool”, Journal of Crystal Growth 445, 65 (2016).

[0068] Finally, growth conditions allowing the epitaxial deposition of GeSn or SiGeSn layers at temperatures less than or equal to 350°C can be found in Aubin and Hartmann, “GeSn growth kinetics in reduced pressure Chemical vapor deposition from Ge2H6 and SnC14”, Journal of Crystal Growth 482, 30 (2018) and Khazaka et al., “Growth and characterization of SiGeSn pseudomorphic layers on 200mm Ge virtual substrates”, Semiconductor Science and Technology 33, 124011 (2018).

[0069] These techniques require the application of a temperature Tep, called the epitaxial temperature Tep, which can vary between 300°C and 600°C for a duration dep, called the epitaxial duration dep, which can range from 1 min to 120 min. The epitaxial temperature Tep is, for example, 500°C and the epitaxial duration dep is 10 minutes.

[0070] It should be noted that the temperatures involved in this S130 epitaxy step can produce the same effects as fracturing annealing on the first implanted 3a ions. For this reason, the first implantation (and in particular the first implanted 3a ions and the first implantation dose(s) chosen) is determined according to the temperature and duration conditions of the S130 epitaxy step, in order to avoid (and not achieve) fracturing of the donor substrate 10 during the S130 epitaxy step. Indeed, otherwise, in the absence of any particular mechanical constraint (or stiffener) in the donor substrate 10 (which is not yet assembled to the receiving substrate 20), the gas-supplied nanocavities are free to expand both laterally and vertically, which causes the appearance of bubbles, blisters, exfoliations on the surface and in the semiconducting layer 40 being formed, which will therefore be defective.

[0071] For this purpose, light ions that do not generate bubbling within the thermal budget of S130 epitaxy can be chosen as the first ions 3a. This will be the case, for example, if boron or helium is implanted. The heavier the implanted atom (He, B), the more advantageous it is to implant it before S130 epitaxy to limit damage to the transferred semiconductor layer 40.

[0072] Preferably, the first light ions 3a are helium ions.

[0073] If the first implantation S120 is performed with hydrogen, a first dose DI will be used that is lower than a first threshold SI, from which the first light ions 3a induce, during epitaxy S130, fracturing at the depth predetermined implantation 30.

[0074] The first SI threshold can be predetermined experimentally using a first test substrate 6 as shown in [Fig. 6]. The first test substrate 6 comprises several test zones, for example, four test zones Q11, Q12, Q13, and Q14. Each test zone is subjected to first ion implantation with a test dose and to heat treatment at the epitaxial temperature Tep S130 for the duration dep of the epitaxial process.

[0075] The first SI threshold is then determined by visual inspection and searching for the presence of surface exfoliations which indicates that fracturing and therefore layer transfer would take place if a mechanically constraining interface (such as the interface between the donor substrate 10 and recipient substrate 20 when they are assembled) were present.

[0076] Preferably, the first threshold SI is determined by following the sequence of steps S710 to S730 of [Fig.7].

[0077] These steps are as follows: • S710 implantation of the first 3a light ions on a first Qll test area of ​​the test substrate 6, at the implantation energy of the first 3a light ions, and with a low first DTli test dose, for example of le16 / cm2. • S720 heat treatment of test substrate 6 at the Tep epitaxy temperature for the duration of dep epitaxy, • S730 control of the free surface 66 of the test substrate 6, preferably visual control on images of the test area acquired by optical microscopy, • If the free surface 66 is deteriorated (exit “D” of step S730), the first SI threshold is equal to the first test dose DTli, • If the free surface is not damaged (exit “ND” from step S730), the first test dose DT12 is increased (DT12 > DT11) and the implantation steps S710, heat treatment S720 and control S730 are repeated on the next test area Q12, applying the increased test dose D12 to the implantation step S710.

[0078] By "deteriorated free surface", we mean the presence of blisters or exfoliations on the free surface 66. These damages correspond to dark spots on optical microscopy images and are easily detectable (cf. points P in image IMG1 of [Fig.7]).

[0079] By "undamaged free surface 66", we mean the absence of blisters or exfoliation on the free surface 66. On the images acquired by optical microscopy, no dark spot is detected (cf. IMG2 of [Fig.7]).

[0080] For this first S120 implantation, several ions can also be combined 3a and in particular helium and / or boron with hydrogen. The more species are implanted during this first implantation, the less will be needed during the second implantation and therefore the less damage will be done to the epitaxial layer.

[0081] After the epitaxial step S130 described above, a second light ion implantation step, referred to as the second light ion implantation step S140, is carried out. This step S140 is illustrated [Fig. 1D] and is associated with the subsequent step S160, illustrated [Fig. 1E], consisting of a fracture annealing step S150 carried out at a fracture annealing temperature TRF and for a fracture annealing time dRF.

[0082] The second ions 3b are light species such as helium He, hydrogen H or a mixture of helium and hydrogen (“H+He”). The second ions 3b can be the same as the first ions 3a.

[0083] Preferably, the second light 3b ions comprise or are hydrogen ions.

[0084] The depth of this second implantation S140 is the implantation depth 30 determined during the first implantation S120 of the first ions 3a, plus the thickness of the epitaxially grown semiconductor layer 40. The energy at which the second implantation S140 is performed is such that the maximum of the implantation profile is superimposed on that of the first implantation S120.

[0085] With reference to [Fig.1D], the second implantation S140 is carried out in the donor substrate 10, through the semiconducting layer 40 to be transferred, so that the second ions 3b reach the buried fragile plane 300.

[0086] The fragile plane 300 is then a plane in which the density of nano-cavities and the overall content of light ions, i.e. the cumulative content of first 3a light ions and second 3b light ions, allow, during the S160 fracturing annealing step, the formation of gas complexes to be triggered, leading to the fracturing of the donor substrate 10.

[0087] For this, the second implantation S140 is accomplished with 3b ions implanted in one or more doses such that, during the fracturing annealing S160, the accumulation of the first 3a ions and the second 3b ions induces fracturing of the donor substrate 10, along the buried brittle plane 300.

[0088] If the second implantation S140 includes hydrogen ions implanted at a second dose D2, this dose is preferably predetermined experimentally, based, similarly to the determination of the first threshold SI, on the presence / absence of surface exfoliations of a second test substrate such as the second test substrate 8 illustrated [Fig.8].

[0089] In a manner analogous to the first substrate 6 test, the second substrate 8 test can be divided into several test zones, for example four zones Q21, Q22, Q23 and Q24.

[0090] Steps S910 to S950 (see [Fig. 9]) are carried out there. They consist of: • the implantation S910 of the first 3a ions on a first zone Q21, at the implantation energy of the first ions. For example, Helium ions are implanted with an energy of 35 keV (so as to create a fragile plane at a depth of 300 nm relative to the surface) and a dose DI of 2e16 / cm2), • S920 epitaxy of the second test substrate 8 at the epitaxial temperature Tep and for the epitaxial duration dep, to create an epitaxial layer, for example, of 30 nm • The S930 implantation of the second 3b ions with an implantation energy such that these ions reach the buried fragile plane. If the implanted ions are hydrogen, they will be implanted with an energy of 24 keV to reach the fragile plane located 330 nm from the surface. These ions will be implanted with a second low DT2i test dose, for example equal to 1E16 / cm2. • S940 heat treatment of the second substrate 8 test at the fracturing annealing temperature TRF and during the fracturing annealing time d^, • S950 control of the free surface quality 88 of the second test substrate 8, • if the surface quality is deteriorated (output “D” of the S950 control step), the second dose D2 is equal to or greater than the second test dose DT21, • if the surface quality is not deteriorated (output “ND” of the control step S950), the test dose DT2i is increased and the test steps S910 to S930 are repeated on another test area Q22, the implantation step S930 of the second 3b ions being accomplished with the second increased test dose DT22.

[0091] By applying these steps, we obtain, for example, the fracturing conditions given in Table 1 or the fracturing conditions given in Table 2. By "fracture conditions" we mean all the parameters related to the S120 implantation of the first ions, the S130 epitaxy, the S140 implantation of the second ions, and the S160 fracture annealing.

[0092] [Tables 1] Implantation of the first light ions S120 Epitaxy S130 30 nm Si Implantation of the second light ions S140 Fracture annealing S160 Light ions He H Energy (keV) 36 2 Dose ( / cm2) 1.346 146 Temperature (°C) 400 500 Duration (min) 15 1 h

[0093] [Tables2] Implantation of the first light ions S120 Epitaxy S130 30 nm Si Implantation of the second light ions S140 Fracture annealing S160 Light ions He H Energy (keV) 36 24 Dose ( / cm2) 246 246 Temperature (°C) 500 500 Duration (min) 15 1 h

[0094] It should be noted that using a higher PET epitaxy temperature (500°C, see table 2 compared to 400°C, see table 1) leads to a higher first dose DI (2e16 / cm2 compared to 1.3e16 / cm2) and a higher second dose D2 (2e16 / cm2 compared to 9e15 / cm2).

[0095] It should also be noted that, in this case, the overall dose (He 36 keV 2e16 / cm2 and H 24 keV 2e16 / cm2) is higher than the dose applied in a standard manner in the case of a single implantation of light ions. However, the defects created are fewer in number, notably because the helium ions do not cross the transferred semiconductor layer 40. As illustrated in [Fig. 10], the density of displaced atoms is indeed lower when hydrogen ions are implanted, compared to helium ions, even for an implantation dose of hydrogen ions more than twice that of helium ions.

[0096] With reference to [Fig. 1E], the process then comprises a step S150 of assembling by bonding the receiving substrate 20 and the donor substrate 10 coated with the semiconductor layer 40 to be transferred. The donor substrate 10 having been previously inverted, the semiconductor layer 40 to be transferred is placed between the receiving substrate 20 and the donor substrate 10, in the assembly 1 formed.

[0097] The receiving substrate 20 is a substrate preferably comprising one or more layers of electronic devices 210.

[0098] This S150 assembly step is carried out using a conventional bonding process, preferably a molecular adhesion bonding process, also called direct bonding.

[0099] The assembly step S150 is followed by an annealing step S160, also called the annealing step S160, of the donor substrate 10 along the buried brittle plane 300. The annealing temperature of the fracturing process is in the range of 400°C to 600°C, and preferably less than or equal to 500°C. The duration of the annealing process is preferably between 30 minutes and 180 minutes.

[0100] At the end of this S160 annealing fracturing step, a portion 10b of the donor substrate 10 is separated from the receiving substrate 20 on which the transferred semiconductor layer 40 is placed, as well as a residual layer 10a from the donor substrate 10. The transfer of the semiconductor layer 40 is thus carried out.

[0101] With reference to [Fig. IG], the fracturing step S160 can be followed by an optional removal step S170 of the residual layer 10a from the donor substrate 10 until the semiconductor layer 40 is reached. At the end of this S170 removal step of the residual layer 10a, the final semiconductor structure 3, illustrated [Fig.3], is obtained.

[0102] Figures 4A to 4K schematically represent a first particular embodiment of the transfer process which has just been described in general terms.

[0103] Figures 5A to 5M schematically represent a second particular embodiment of the transfer process.

[0104] The steps of supplying SI 10 of the donor substrate 10, of first implantation S120, and of second implantation S140, illustrated respectively in [Fig.4A] and in [Fig.5A], in [Fig.4C] and [Fig.5D], and in [Fig.4G] and [Fig.51], are as described above, respectively in relation to [Fig.1A], [Fig.1B], and [Fig.1D].

[0105]

[0106] Common to both of these particular embodiments, the epitaxial step S130 comprises two substeps S130A and S130B to form a semiconductor layer 40 comprising the active sublayer 430 and the etching stop sublayer 420 illustrated [Fig.2], as well as two additional steps S170 (see [Fig.4J] and [Fig.5L]) and S180 (see [Fig.4K] and [Fig.5M]) carried out after the assembly steps S150 (see [Fig.4H] ​​and [Fig.5J]) and S160 fracturing (see [Fig.41] and [Fig.5K]) and aimed at releasing the active sublayer 430.

[0107] With reference to [Fig.4E] (first embodiment) and [Fig.5G] (second embodiment), step S130A consists of the growth by epitaxy of the so-called etching stop sublayer 420 from the free surface 11 of the donor substrate 10. The epitaxy temperature is for example 500°C.

[0108] With reference to [Fig.4F] (first embodiment) and [Fig.5H] (second embodiment), step S130B consists of the growth by epitaxy of the so-called active sublayer 430 from the etching stop sublayer 420. This epitaxy S130B is preferably carried out at the same epitaxy temperature as the epitaxy S130A of the etching stop sublayer, i.e. here 500°C.

[0109] With reference to [Fig.4J] (first embodiment) and [Fig.5L] (second embodiment), the receiving substrate 20 has, after the fracturing step S160, a residual layer 10a from the donor substrate 10 on the surface of the etching stop sublayer 420. The step S170 is then a removal step S170 of the residual layer 10a from the donor substrate 10, by selectively etching said residual layer 10a with respect to the second etching stop sublayer 420. This selective etching is preferably a wet etching.

[0110] Step S180, which follows step S170, is a selective etching (preferably wet) removal step of the etching stop sub-layer 420 with respect to the active sub-layer 430.

[0111] At the end of step S180 of removal of the etching stop underlayer 430, the active underlayer 430 is released and advantageously presents a smooth surface and a reduced thickness.

[0112] Also in common with the first embodiment and the second embodiment, the transfer process further includes one or more steps aimed at preparing the free surface 11 of the donor substrate 10 for the S130 epitaxy of the semiconductor layer 40.

[0113] In the first embodiment, the surface preparation for S130 epitaxy includes the additional steps SI 15 and S125 illustrated respectively [Fig.4B] and [Fig.4D].

[0114] In the second embodiment, the surface preparation for S130 epitaxy includes the additional steps S115A, S115B and S125A and S125B, illustrated respectively in [Fig.5B], [Fig.5C] and [Fig.5E] and [Fig.5F].

[0115] The surface preparation as carried out in the first embodiment is described first below.

[0116] Step SI 15 ([Fig.4B]) takes place before the implantation S120 of the first ions 3a, and consists of the formation of a sacrificial layer 50 on the free surface 11 of the substrate donor 10. Preferably, the sacrificial layer 50 is a dielectric layer 500, for example a silicon oxide (or SiO2) layer.

[0117] The dielectric layer 500 is obtained by oxide growth or by deposition of the dielectric from the free surface 11 of the donor substrate 10.

[0118] At the end of step SI 15, the donor substrate 10 therefore comprises a so-called sacrificial dielectric layer which advantageously protects the free surface from defects and impurities (for example, carbon or oxygen atoms). In the implantation step S120 of the first ions 3a, the first ions 3a will be implanted through the sacrificial dielectric layer 50,520.

[0119] Step S125 ([Fig. 4D]) takes place after the S120 implantation of the first ions and before step S130 of epitaxy of the semiconductor layer 40 to be transferred. Step S125 consists of the removal of the sacrificial layer 50,510 formed in step S15.

[0120] This removal is for example carried out by wet etching using a hydrofluoric acid-based solution.

[0121] At the end of step S125, the free surface 11 of the donor substrate 10 advantageously presents a clean surface, that is to say free of impurities or contaminants.

[0122] In the second embodiment (see [Fig.4C]), the sacrificial layer 50 comprises a stack of a first sub-layer 510, called the first etching stop layer 510, and a second dielectric sub-layer 520 disposed on the first sub-layer 510.

[0123] Thus, step SI 15A is a step for forming the first etching stop layer 510 and step S115B is a step for forming the second dielectric sublayer 520.

[0124] The dielectric is preferably silicon oxide.

[0125] The first etching stop layer 510 is for example a silicon and germanium alloy layer (SiGe) with the following proportions 25% (Si) and 50% (Ge).

[0126] In step SI 15A, the formation of the first etching stop layer 510 is preferably carried out by epitaxial growth from the free surface 11 of the donor substrate 10. The thickness of the first etching stop layer 510 thus obtained is between 10 and 50 nm. The epitaxy of the first etching stop layer 510 may further be preceded by a surface preparation step carried out according to state-of-the-art processes, preferably at temperatures above 650°C, and even more preferably at temperatures above 850°C.

[0127] In the SI 15B step, the second dielectric sublayer 520 is obtained by oxide growth from the surface of the first etching stop layer 510, or by deposition of the dielectric on the surface of the first etching stop layer 510, this to obtain a second dielectric sublayer 520 with a thickness between 5 and 50 nm.

[0128] The S125A removal step ([Fig.5E]) is an S125A removal step of the second dielectric sublayer 520.

[0129] The removal of the second dielectric sublayer 520 is for example carried out using a wet etching based on a solution comprising hydrogen fluoride.

[0130] The S125B removal step ([Fig.5F]) of the first etching stop layer 510 can be carried out outside the epitaxy equipment or in the epitaxy equipment (this is referred to as in-situ removal).

[0131] In the first case (outside of the epitaxial equipment), step S125B consists of carrying out a wet etch selective with respect to the SiGe, for example using a wet etch based on a solution comprising acetic acid, hydrogen fluoride, and hydrogen peroxide (or H2O2), and then carrying out the epitaxial step S130 in a time interval preferably between 10 minutes and 30 minutes.

[0132] In other words, the time interval between the S125B wet etching removal step of the first etching stop layer 510 and the S130 epitaxy step of the semiconductor layer 40 to be transferred is then preferably between 10 minutes and 30 minutes.

[0133] In the second case, the S125B removal step of the first etching stop layer 510 is carried out in the epitaxial equipment. In other words, the S125B removal step of the first etching stop layer 510 and the S130 epitaxial step are carried out in the same epitaxial equipment.

[0134] The S125B removal is then carried out by wet etching with a solution comprising hydrochloric acid (or HCl) and preferably at a temperature below 500°C. Advantageously, the etching is selective with respect to the silicon of the donor substrate 10. With reference to [Fig. 1 1], a partial pressure of HCl from 23998 Pa to 47996 Pa (i.e., 180 or 360 Torr) can be used. At a temperature of 500°C, the etching rates (or ER for Etching Rate), represented on the ordinate axis, are such that the etching of SiGe is selective with respect to the silicon of the donor substrate 10. Advantageously, the etching selectivity, that is to say the ratio between the etching rate of a SiGe layer and that of Si, is on the order of 13 for a Ge concentration in the etching stop layer 510 of 20%, on the order of 50 for a Ge concentration of 30% and on the order of 186 for a Ge concentration of 40%.

[0135] The S125B removal step is then followed by the S130 epitaxy step described previously, which can then, in addition, be followed by an extra step S132 (not shown) of annealing after epitaxy of the donor substrate 10, carried out in the same epitaxy equipment as the S125B removal step of the first arrest layer 510 and the S130 epitaxy step of the 40 semiconductor layer to be transferred.

[0136] The first and second embodiments represent two ways of preparing the free surface 11 of the donor substrate 10 for S130 epitaxy.

[0137] A third way of preparing the free surface 11 is shown [Fig. 12] with step S122. This step S122 consists of carrying out, between the implantation S120 of the first light ions and the epitaxial step S130 of the semiconductor layer 40 to be transferred, the following successive substeps: • S122A deoxidation of the free surface 11 of the donor substrate 10, • S122B annealing of the donor substrate 10, under an atmosphere comprising hydrogen at a temperature above 400°C, for a period of time between 5 seconds and 10 minutes, typically.

[0138] The deoxidation step S122A is, for example, carried out chemically under hydrogen fluoride (or HF), and is followed by surface cleaning by an SCI™ process (i.e., exposure of the surface to an NH4OH:H2O2:H2O chemical solution, leading to the formation of a silicon oxide) and then a SICONI™ process (i.e., (i) conversion, by means of a remote plasma based on NH3 and NF3, of the silicon oxide formed by the SCI™ process into an oxide salt, followed by sublimation of this salt under a neutral gas at a temperature below 200°C). The temperatures used are then preferably less than or equal to 500°C.

[0139] The annealing step S122B, which follows the deoxidation step S122A, is preferably carried out in epitaxial equipment. The annealing temperature may be below 500°C. To obtain optimal surface preparation, the temperature may be higher, for example, above 500°C, 650°C, or even above 800°C. In this case, the annealing time is preferably as short as possible, in the range of 5 seconds to 10 minutes.

[0140] Following this additional step S122, the free surface 11 of the donor substrate 10 is, before epitaxy S130, advantageously reduced in contaminants (carbon, fluorine, oxygen, etc.).

[0141] The process may further comprise, after epitaxy S130 and before implantation S140 of the second ions 3b, an additional step S135 (not shown) of forming an oxide layer by epitaxial growth from the semiconductor layer 40 formed at the end of step S130 (or S130B). This step S135 is preferably carried out under an oxidation plasma at a temperature below 500°C or below 400°C. It may also be carried out by plasma-assisted chemical vapor deposition.

[0142] Using two implantation steps (first implantation S120 and second implantation S140) carried out respectively with the first ions 3a and the first dose(s) and with the second ions 3b and the second dose(s), and By interposing the epitaxy of the semiconductor layer 40 between these two implantation steps, the transfer process makes it possible to limit the negative impact of implantation, that is to say, to limit the damage or defects induced by the implanted species, along their path in the donor substrate 10. The process therefore makes it possible to obtain a semiconductor layer 40 reduced in defects, this before the S150-S160 transfer step.

[0143] There are several explanations for this: first, the first ions 3a and the first dose(s) are adapted so that, during epitaxy, the first ions 3a do not induce the growth of the nano-cavities towards the free surface 11 and into the semiconductor layer 40 being formed; second, the semiconductor layer 40 is only crossed by the second ions 3b, at a second dose reduced compared to a dose corresponding to a single implantation.

[0144] Fracture annealing temperatures of 500°C or less can be used, as described above, which makes the transfer process compatible with 3D monolithic integration.

Claims

Demands

1. A method for transferring a semiconductor layer (40) from a donor substrate (10) to a recipient substrate (20), the method comprising the following successive steps: - first implantation (S 120) of first light ions (3a) in the donor substrate (10) at a predetermined implantation depth (30) so as to form a buried fragile plane (300) at the predetermined implantation depth (30), - epitaxy (S130) on the donor substrate (10) of the semiconductor layer (40) to be transferred, - second implantation (S 140) of second light ions (3b) in the donor substrate (10) through the semiconducting layer (40) to be transferred at the level of the fragile plane (300), - assembly (S 150) by bonding the receiving substrate (20) and the donor substrate (10) covered with the semiconductor layer (40) to be transferred, the semiconductor layer (40) to be transferred being disposed between the receiving substrate (20) and the donor substrate (10), and - fracturing (S 160) by annealing, called fracturing annealing (S 160), of the donor substrate (10) along the buried brittle plane (300), process in which: - the first ions (3a) are chosen and implanted at a first dose (Dl) so that, during epitaxy (S130), there is no fracturing at the predetermined implantation depth (30), - the second ions (3b) are chosen and implanted at a second dose (D2) so that, during the fracturing annealing (S 160), the fracturing of the donor substrate (10) takes place.

2. The method according to claim 1, wherein: - the first light ions (3a) are helium ions, hydrogen ions, boron ions, a mixture of helium and hydrogen ions or a mixture of hydrogen and boron ions, and - the second light ions (3b) are helium ions, hydrogen ions or a mixture of helium and hydrogen ions.

3. A method according to any one of claims 1 to 2 comprising, between the first implantation (S120) and the epitaxial step (S130) of the semiconductor layer (40) to be transferred, an additional surface preparation step (S122) comprising the following successive substeps: - deoxidation (S122A) of a free surface (11) of the donor substrate (10), - annealing (S122B) of the donor substrate (10) under an atmosphere comprising hydrogen at a temperature greater than or equal to 400°C, for a period of between 5 seconds and 10 minutes.

4. A method according to any one of claims 1 to 2, comprising the additional steps of: - before the first implantation (S 120), a deposition step (SI 15) of a sacrificial layer (50) on a free surface (11) of the donor substrate (10), - after the first implantation (S 120) and before the epitaxy step (S 130) of the semiconductor layer (40) to be transferred, a removal step (S 125) of the sacrificial layer (50).

5. Method according to claim 4 wherein the sacrificial layer (50) is a dielectric layer (500).

6. A method according to claim 4 wherein the sacrificial layer (50) comprises a stack of a first sublayer of silicon and germanium alloy (510), referred to as the first etching stop layer (510), and a second sublayer (520) of dielectric material disposed on the first sublayer (510), and the removal step (S 125) of the sacrificial layer (50) comprises the removal (S 125A) of the second sublayer (520) of dielectric material and then the removal (S125B) of the first etching stop layer (510).

7. A method according to claim 6 wherein the epitaxy step (S 130) of the semiconductor layer (40) to be transferred is carried out less than 30 minutes after the removal step (S125B) of the first arrest layer.

8. A method according to claim 6, wherein the removal step (S125B) of the first etching stop layer (510) and the epitaxy step (S130) of the semiconductor layer (40) to be transferred are carried out in the same equipment.

9. Method according to claim 8 comprising, after the step of removing (S125B) the first arrest layer and before the step of epitaxy (S130) of the semiconductor layer (40) to be transferred, an additional step (S132) of annealing the donor substrate (10) carried out in the same equipment as the step of removing (S1225B) the first etching arrest layer (510) and the step of epitaxy (S130) of the semiconductor layer (40) to be transferred.

10. A process according to claim 9 wherein the annealing (S 132) of the donor substrate (10) is carried out under the following temperature, pressure and time conditions: 500°C, 2666 Pa, 2 minutes.

11. A method according to any one of claims 1 to 10 wherein the semiconductor layer (40) to be transferred is a layer (410) of silicon (or Si), germanium (or Ge), a silicon and germanium alloy (or SiGe), a silicon, germanium and carbon alloy (or SiGeC), a germanium and tin alloy (or GeSn) or a silicon, germanium and tin alloy (SiGeSn), or a stack of a silicon sublayer and a silicon and germanium alloy sublayer (Si / SiGe).

12. A method according to any one of claims 1 to 11 wherein the semiconductor layer (40) to be transferred comprises a first so-called active sublayer (430) of silicon (or Si), germanium (or Ge), a silicon-germanium alloy (or SiGe), a silicon-germanium-carbon alloy (or SiGeC), a germanium-tin alloy (or GeSn) or a silicon-germanium-tin alloy (SiGeSn), and a second so-called etching stop sublayer (420) such as an etching stop sublayer of silicon-germanium alloy, disposed under the first active sublayer (430), and the receiving substrate (20) has, after the fracturing step (S160), a residual layer (10a) from the donor substrate (10),the process then comprising the following successive steps: - Removal (S 170) of the residual layer (10a) from the donor substrate (10) by selective etching of said residual layer (10a) with respect to the second etching stop sublayer, (420), with a selectivity greater than 10, Removal (S 180) of the second etching stop underlayer (420).

Images