High-mobility field-effect transistor with improved reliability

Abstract

The invention relates to a high-mobility field-effect transistor (100) comprising: a stack (10) along a Z-axis comprising: a substrate (SUB), a buffer layer (BUF) deposited on the substrate, comprising a binary, ternary, or quaternary nitride compound, a barrier layer (Bar) comprising nitrogen (N) and one to five elements selected from indium (In), aluminum (Al), gallium (Ga), boron (B), and scandium (Sc), a layer (L2D) of a two-dimensional insulating material (Mat2D) disposed between the barrier layer and the buffer layer, called the 2D layer, the barrier layer and the buffer layer being configured to form a two-dimensional electron gas (9) in a region, called a channel, located in the buffer layer or the barrier layer and situated in the vicinity of an interface with the 2D layer, a source (S), a drain (D), and a gate (G) deposited on a top face (12). of the barrier layer, between the source and the drain. Figure 7

Description

Description Title of the invention: High mobility field effect transistor improved reliability FIELD OF THE INVENTION

[0001] The invention lies in the field of high mobility field effect transistors. electronics called HEMT transistors (acronym of the Anglo-Saxon expression "High Electron Mobility Transistor") in GaN technology and for applications microwaves, typically at frequencies up to 40 GHz, or even 80 GHz in the near future.

[0002] More particularly, the invention relates to improving the reliability of the transistor. HEMT. The invention applies to RF power HEMT transistors and to transistors for switching. STATE OF THE ART

[0003] — [Fig.1] schematically represents a section of the structure of a transistor Classical elementary HEMT, in an XZ plane, produced on a SUBO substrate. Class- Typically, an insulating or semiconducting SUBO substrate is used, for example comprising silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or sapphire (Al,Oz), on which a stack is made along the Z axis of at least two layers of semiconductor that extend in the XY plane.

[0004] A first BUFO layer called a buffer layer, or “buffer” (term used in Anglo-Saxon literature), typically has a wide band gap (so-called wide gap semiconductor material) comprising a material from the family of III-N, a family of semiconductors composed of elements from Mendeleev's column 3 and nitrogen, which may be, for example, a binary compound such as GaN or a compound ternary such as AIGaN, or more precisely Al,Ga,N.

[0005] — A second Bar0 layer called a barrier layer typically has a band gap larger than that of the BUFO buffer layer. This layer comprises a material based on a quaternary, ternary or binary nitride compound of elements of column III, called III-N, based on Al, Ga, In, B or Sc.

[0006] For example, with a GaN buffer layer, the barrier layer comprises Al, Gay,.N, of In, ,AL,N or ScAIN or a sequence In,,AL,N / AIN or Al,Ga, N / AIN. The thickness of the barrier layer is typically between 3 nm and 40 nm, the thickness of the buffer layer is typically between 0.2 um and 3 um. The BUFO buffer layer and Bar0 barrier layer are classically made by epitaxy by MOCVD or by MBE. For example, we can cite a buffer layer based on GaN with a barrier layer based on AIGaN or InAIN, and more pre- specifically based on Al,Ga,,N or In;Al,.;N, with x typically between 15% and 35% and z typically between 15% and 25%. Additional layers may be present either on the surface or between the buffer layer and the barrier layer. The interface between the buffer layer and the barrier layer constitutes a Het heterojunction which also extends in the XY plane. A two-dimensional electron gas 9 (called 2DEG for "Two-Dimensional Electron Gas") is located in the buffer layer in the vicinity of the Het heterojunction. The use of these III-N materials makes it possible to obtain an electron density higher than a few 10!? / cm? without doping the barrier layer, thanks to their spontaneous and piezoelectric polarization. A HEMT transistor typically comprises a source S, a drain D and a gate G. The source S and the drain D are in electrical contact with 2DEG. The X axis is defined as the alignment axis of S, G and D. The gate G is deposited on the upper face 12 of the barrier layer Bar between the source S and the drain D, and is used to control the transistor. Typically the gate-source distance is between 0.4 and 1 um and the gate-drain distance is between 0.6 and 3 um. The gate length Lg is defined as the dimension of the gate along the X axis. The conductance between the source S and the drain D is modulated by the electrostatic action of the gate G, classically of the Schottky type or of the MIS type (for metal / insulator / semiconductor), and the voltage Vas applied between the gate and the source controls the transistor. The electrons of the 2DEG are mobile in the XY plane and have a high electron mobility je, typically greater than 1000cm? / Vs. In normal operation of the transistor these electrons cannot circulate in the Z direction because they are confined in the potential well forming in the XY plane in the vicinity of the heterojunction het. The electron gas 9, confined in what is called the channel of the transistor, is therefore able to carry a current L, circulating between the drain and the source. Conventionally in operation a potential difference V4 is applied between the source S and the drain D, with typically a source S to ground, and the value of the current Ips is a function of the applied voltage V, between the gate G and the source S. The transistor effect is based on the modulation of the number of free carriers in the channel between contacts S and D (and therefore of the current flowing between the source and the drain) by the electrostatic action of the control electrode G. The voltage amplitude V;, to be applied is inversely proportional to the transconductance gm of the transistor, this transconductance being itself inversely proportional to the thickness of the barrier. It is the transistor amplification effect which makes it possible to transform a weak signal applied to the gate into a stronger signal recovered on the drain. Preferably for RF applications, the G grid has a T shape and is consisting of a trunk topped with at least one hat (there may be several on top of each other). The two branches of the hat are not necessarily symmetrical, and the drain or source side branch may even be non-existent (so-called l'-shaped grid). The base of the trunk is commonly called the gate foot. When the transistors are in operation, it is known that the electric field at the foot of the gate is very high. Furthermore, according to the state of the art, the face 12 is covered with a dielectric layer called passivation, because the upper face 12 of the barrier layer Bar0 must be protected from contact with the outside. Conventionally, the dielectric materials used are: ALO3, SisN,, SiO,, SIOxNy, BN or AIN. Standard HEMT transistors as described above are made with growth of the buffer and barrier layers along the

[0001] axis. In transistors made according to this growth, the electron gas 9 is located in the buffer layer. Another type of transistor is obtained with growth along the

[0001] axis, also called N-face. With this type of epitaxy the electron gas 9 is located in the barrier. Conventionally, HEMT transistors used for applications of interest (RF, switching) have a source S connected to the electrical ground, typically to a ground plane conventionally made by a metallization layer placed on the side of the substrate opposite the buffer layer (lower side of SUBO in [Fig.1]). The connection is for example made using connection holes also called "via holes" which pass through the substrate from the source to the ground plane. Structurally, there is a mesh mismatch between the barrier layer and the buffer layer, which generates defects that propagate in the structure. These defects constitute points of weakness of the transistor which, under the action of a high electric field and mechanical stresses induced by inverse piezoelectric effect, will be at the origin of a degradation of the performances (increase of the gate current in particular) or even a failure of the components. This zone of intense electric field has been identified in the literature as impacting the reliability of the devices (see for example the publication “Correlation between Physical Defects and performance in AIGaN / GaN High Electron Mobility Transistor Devices” Transactions on electrical and Electronic materials, Vol 11, n°2, p49-53 (2010). Thus the presence of defects due to the buffer layer / barrier layer mesh mismatch combined with the strong electric field present at the foot of the gate in these HEMT structures leads to component reliability problems. To improve reliability, one solution is to reduce the intensity of the electric field by reducing the voltages applied to the transistor, in particular the drain voltage Ve. This would however be at the expense of the added power efficiency (PAE) and the power available at the output of the transistor. One solution to reduce mesh mismatch defects is to use a layer barrier having a mesh in agreement with that of the buffer layer. For a GaN buffer layer a barrier layer in In(17%)A1(83%)N has been proposed but poses many additional problems. In addition, for GaN technology components to operate at millimeter frequencies (>10 GHz) with sufficient performance, it is necessary to modify a number of parameters defining the transistor. Among these modifications, those of primary importance are: - reducing the thickness of the Bar barrier which, by bringing the gate closer to the electron channel, improves the transconductance gm and therefore the gain of the transistor. A thin barrier typically has a thickness between 3 and 6 nm. - increasing the number of carriers in structures to reduce access resistance. However, the increase in carrier density in the n-channel and the reduction in barrier thickness contribute to further increasing the value of the electric field in the structure when the transistor is in operation. This increase in the electric field is particularly pronounced for InAI(Ga)N / GaN or Al(x>30%)Gal-xN transistor processes for which the electron density in the channel is in the range 1.2x10!* / cm? to 2.5x10"* / cm?. The particularly intense electric field in these materials can locally reach an intensity greater than several MV / cm. This results in a further reduced robustness of this process. Thus, to date, there is no satisfactory technological solution to address this reliability problem linked to the presence of defects due to the buffer layer / barrier layer mesh mismatch, exacerbated for transistors operating at high frequency as explained above. An aim of the present invention is to remedy the aforementioned drawbacks by proposing an original HEMT transistor structure integrating a layer of two-dimensional material. DESCRIPTION OF THE INVENTION The present invention relates to a high mobility field effect transistor comprising: a stack along a Z axis comprising: a substrate, a buffer layer deposited on the substrate, comprising a first material semiconductor being a binary or ternary or quaternary compound of nitride, a barrier layer comprising a second semiconductor material being a compound comprising nitrogen and from one to five elements chosen from indium, aluminum, gallium, boron and scandium, a layer of two-dimensional insulating material disposed between the layer barrier and the buffer layer, called 2D layer, the barrier layer and the buffer layer being configured to form a two-dimensional electron gas in a region, called a channel, located in the buffer layer or the barrier layer and situated in the vicinity of an interface with the 2D layer, a source, a drain, and a grid deposited on an upper face of the barrier layer, between the source and the drain. According to one embodiment, the 2D layer has a band gap greater than or equal to 4 eV. According to one embodiment, the buffer layer has an electronic affinity %1, the barrier layer has an electronic affinity x, the 2D layer has an electronic affinity yet in which the electronic affinities verify the relationship: %-X <-0.5 eV, with i = 1 or 2 corresponding to the layer in which said channel is located. According to one embodiment, the 2D layer comprises 1 to 10 monolayers of said two-dimensional material. According to one embodiment, the first semiconductor material is gallium nitride or aluminum nitride or AIGaN. According to one embodiment, the second semiconductor material (SC2) is chosen from: AIN; InAIN; AIGaN; IMAIGaN; ScAIN; ScGaN. According to one embodiment, the second semiconductor material (SC2) is chosen from: BN; BGaAIN; BAIN; BGaAIIMN. According to one embodiment, the two-dimensional material is h-BN. The invention also relates to a method of producing a high mobility field effect transistor. According to a first variant, the method comprises the steps consisting of: having an assembly comprising a buffer layer deposited on a substrate, the buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound, growing a layer of two-dimensional insulating material on an upper face of said buffer layer, growing a barrier layer on said layer of two-dimensional material, said barrier layer comprising a second semiconductor material being a compound comprising nitrogen and from one to five elements selected from indium, aluminum, gallium, boron and scandium, the barrier layer and the buffer layer being configured to form a two-dimensional electron gas in an area called a channel, located in the layer buffer or barrier layer and located in the vicinity of an interface with the 2D layer, producing a source, a drain, and a gate deposited on an upper face of the barrier layer between the source and the drain. According to a second variant, the method comprises the steps consisting of: having an assembly comprising a buffer layer deposited on a substrate, the buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound, having a 2D layer of a two-dimensional material grown on an auxiliary substrate, transferring said 2D layer onto an upper face of said buffer layer and removing the auxiliary substrate, growing a barrier layer on said layer of two-dimensional material, said barrier layer comprising a second semiconductor material being a compound comprising nitrogen and from one to five elements selected from indium, aluminum, gallium, boron and scandium, the barrier layer and the buffer layer being configured to form a two-dimensional electron gas in a zone called a channel, located in the buffer layer or the barrier layer and situated in the vicinity of an interface with the 2D layer, producing a source, a drain, and a gate deposited on an upper face of the barrier layer between the source and the drain. The following description presents several exemplary embodiments of the device of the invention: these examples are not limiting of the scope of the invention. These exemplary embodiments present both the essential characteristics of the invention as well as additional characteristics linked to the embodiments considered. The invention will be better understood and other characteristics, aims and advantages thereof will appear during the detailed description which follows and with reference to the appended drawings given as non-limiting examples and in which: The already cited [Fig.1] schematically represents a section of the structure of a classic elementary HEMT transistor. [Fig.2] illustrates an example of a monolayer of a 2D material of type MX. [Fig.3] illustrates a stack of three monolayers of a 2D DMCT MS type material, [Fig.4] on the left illustrates a two-layer stack of the hexagonal h-BN variety seen in perspective, [Fig.4] on the right illustrates a monolayer seen from above. [Fig.5] illustrates the stacking of two monolayers of h-BN seen from above in slight perspective. [Fig.6] illustrates the structure of a transistor comprising two hBN layers according to the state of the art. [Fig.7] illustrates a HEMT transistor according to the invention. [Fig.8] illustrates an example of the valence bands BV and conduction bands BC of a HEMT structure according to the invention BUF / L2D / Bar for GaN / h-BN / AIN materials (energy E in eV). [Fig.9] represents the diagrams of the conduction bands (respectively BCO and BC) simulated for a conventional structure without 2D material (A) and for a structure according to the invention with a 2D material inserted between the buffer layer and the barrier (B). [Fig.10] represents the power gain as a function of frequency for the conventional structure without 2D material and for the structure according to the invention in which a monolayer of a 2D material, here h-BN, is inserted between the barrier and the buffer layer. DETAILED DESCRIPTION OF THE INVENTION The HEMT transistor according to the invention integrates a two-dimensional layer of material into its structure in an original way. We will first recall what two-dimensional materials are and how, in the state of the art, they are used in transistor-type electronic devices. Two-dimensional materials have been developed recently. They have a planar structure and are composed of one to a few monolayers L, each monolayer comprising a few atomic planes (typically 1 to 5), the number of planes being a function of the atomic structure. The chemical bonds within a monolayer are covalent. A well-known example of this type of material are transition metal dichalcogenides DCMT with the general chemical formula MX, MX; or MX; with M metal and X chalcogen such as S, Te or Se, exhibiting a 2D structure. For example : MX: M: Fe, Ga: X: S, Se, Te MX: FeSe, FeS, GaSe, GaTe MX”: M: Mo. W, Zr, Hf, Pt, Nb, Ta, V, Ti, Cr, Ni….; X: S, Se, Te MX3: M: Ti, Zr; X: S, Se, Te There are currently dozens of distinct MX lamellar compounds known that can be isolated as monolayers. [Fig.2] illustrates an example of a monolayer 30 of a 2D material of type MX; comprising 3 atomic planes AtL, a plane of metallic atoms M (light spheres) sandwiched between two planes of atoms X (dark spheres). [Fig.3] illustrates a stack of three monolayers 30 of a 2D material of type DMCT MS; (S sulfur). For multi-layer materials, the monolayers stack and are held together by van der Waals forces. The electronic properties of DCMTs depend on their chemical formula and the number of layers; they can be metallic or semiconducting. The publication by Fu et al. “Monolayer transition metal disulfide: synthesis, characterization and applications” (Progress in natural science: Materials International 26 (2016) 221-231) describes a FET transistor with a MoS channel, ([Fig.6](a) of the publication) used here for its conductive properties. Another well-known example is boron nitride BN and more specifically its hexagonal variety h-BN, as illustrated in Figures 4 and 5. [Fig. 4] on the left illustrates a stack of two layers of the hexagonal variety of h-BN seen in perspective, the figure on the right a monolayer seen from above. [Fig. 5] illustrates the stack of two monolayers L seen from above in slight perspective. The band structure depends on the number of layers (see for example the publication D. Wickramaratne et al, “Monolayer to Bulk Properties of Hexagonal Boron Nitride”, J. Phys. Chem. C 2018, 122, 25524-25529). The structure of h-BN is similar to that of graphene, with a two-dimensional honeycomb lattice. For bulk h-BN, the BN distance is 0.1446 nm and the inter-plane distance is 0.33 nm. The 2D unit cell of h-BN comprises one B atom and one N atom. Each monolayer or elementary sheet of h-BN consists of one atomic plane. During stacking, to form a multilayer crystal, a boron atom from one layer is superimposed on a nitrogen atom from the superimposed layer and vice versa. The h-BN material is insulating regardless of the number of layers. Other 2D insulating materials are described in the literature and can be used in the invention, for example: GaS, GaSe, GeS,, GeSe,, Ga,N3, SrTiO,, MoO4,.. 2D insulating materials are for example described in the publication by Lu et- al, “Synthesis and Applications of Wide Bandgap 2D Layered Semiconductors Reaching the Green and Blue Wavelengths”, ACS Appl. Electron. Mater. 2, 1777 (2020). It should be noted that research efforts remain to determine the ideal 2D insulating material, see for example the publication by Illarionov et al., “Insulators for 2D nanoelectronics: the gap to bridge”, Nature Communications 11, 3385 (2020). A few layers of h-BN can be used as a tunnel barrier. The electronic and optical properties of 2D layers (graphene and DCMT) are much better when these layers are based on an h-BN multilayer or / and are covered with h-BN multilayers. For example, the electronic properties of a MoS layer, such as the electronic mobility of charge carriers, are significantly improved by encapsulation between two layers of h-BN, hBN(Top) and hBN(Bot) such as as described in the publication "Multi-terminal transport measurement of MoS; using Van der Waals heterostructure device platform" by Xu Cui et al, NATURE NANO-TECHNOLOGY, VOL 10, June 2015 (DOI: 10.1038 / NNANO.2015.70) and illustrated [Fig.6]. The measurement of the electron mobility of the MoS; layer is carried out by taking the contacts 20 via a graphene electrode Graph connected to a metal M. The device is produced on an oxidized silicon substrate SiO; on Si. A use of h-BN in an electronic device of this type typically requires the production, over a large area, of a 2D material consisting of 20 to a hundred monolayers of BN. Classically, the surface properties of 2D materials are different from the surface properties of bulk materials. 2D materials differ from usual 3D bulk materials for which, on the surface, the atoms have unsatisfied chemical bonds, called dangling bonds. Indeed, these two-dimensional materials have the particularity of having a stable surface. For 2D materials without crystalline defects deposited on a flat surface, all the atoms of a monolayer are linked together by covalent bonds, all the chemical bonds are satisfied, there are no dangling bonds on its surface. For multi-layer materials, the monolayers stack and are held together by Van der Waals forces (electrostatic attraction, not chemical bonds). The basic idea of ​​the invention is to solve the aforementioned mesh mismatch problem by inserting a layer of an insulating two-dimensional Mat2D material between the barrier layer and the buffer layer. This is an original arrangement and it was not obvious that such an insertion would not cause a degradation of the transistor performance, which the inventors established by simulation (see below). A HEMT transistor 100 according to the invention is illustrated [Fig.7] for the case of growth along

[0001] . The transistor 100 comprises a stack 10 along a Z axis comprising: -a SUB substrate, - a BUF buffer layer deposited on the substrate, comprising a first semiconductor material SCI which is a binary or ternary or quaternary nitride compound, -a barrier layer Bar comprising a second semiconductor material SC2 which is a compound comprising nitrogen (N) and one to five elements chosen from indium (In), aluminum (AI), gallium (Ga), boron (B), and scandium (Sc). The various possible combinations of materials are determined by the laws of solid-state physics and the technological capabilities of the structures, which are likely to progress over time. The barrier material is therefore a binary, ternary, quaternary, or quinary nitride compound. The buffer layer has a first band gap G1 and the barrier layer Bar has a second band gap G2. The stack also includes an L2D layer of a two-dimensional insulating Mat2D material disposed between the barrier layer and the buffer layer. 11 is called the BUF / L2D interface and 13 the L2D / Bar interface. The barrier layer, the two-dimensional L2D layer and the buffer layer are configured to form a two-dimensional electron gas 9 in an area called a channel, located in the buffer layer or the barrier layer and located in the vicinity of an interface with the 2D layer. For the case of growth along

[0001] illustrated [Fig.7] the electron gas 9 is located in the buffer layer and arranged in the vicinity of the upper face 11 of the buffer layer (corresponding to the interface 11 BUF / L2D). For the case of growth along

[0001] the electron gas 9 is located in the barrier layer and arranged in the vicinity of the lower face 13 of the barrier layer (corresponding to the 13 Bar / L2D interface). The transistor 100 also comprises, in a conventional manner, a source S, a drain D, and a gate G deposited on the upper face 12 of the barrier layer between the source and the drain. The insertion of a layer of 2D materials into a HEMT structure makes it possible to release the stresses generated in the barrier layer due to the strong mismatch in lattice parameters between the two materials constituting the barrier and the buffer layer respectively, and therefore to potentially improve the robustness of these components by preventing the appearance of crystal defects in the barrier during transistor operation. The epitaxy of a 2D material layer on a III-V material or of a III-V material on a 2D material is called Quasi Van der Waals. For the epitaxy of a III-V material on a 2D material see for example the publication by Liang et al “Quasi Van der Waals epitaxy nitride materials and devices on two dimension materials” nano Energy 69, 104463 (2020)). For the epitaxy of a 2D material on a II-V material see for example the publication by Wan et al “Epitaxial Single Layer MoS2 on GaN with Enhanced Valley Helicity”, Adv. Mater. 30, 1703888 (2018). Similarly, the bonds between the III-V layer and the 2D material are called Quasi Van der Waals At the level of epitaxy of the 2D material on the SCI material of the buffer layer, the absence of dangling bond of the 2D material according to the growth direction allows during epitaxy to align the 2D material according to the orientation of the buffer layer, and exerts a low constraint in the plane. At the level of epitaxy of the barrier layer on the 2D material, the absence of dangling bonds on the surface of the L2D layer allows growth of the SC2 material according to its lattice parameter. The semiconductor material is free to organize itself according to its own structure without constraints from the L2D layer and there are then no more epitaxy constraints (due to the difference in the lattice parameters of the buffer layer and the barrier layer), as is the case in state-of-the-art epitaxies where this 2D material is not inserted between these two layers. The reduction of stresses and defects in the HEMT structure, due to the presence of the 2D material layer, helps improve the reliability of the component. Added to this is a filtering effect of dislocations which are also important vectors of failure modes. Thus an improvement in robustness, directly linked to the stress state of the barrier and the density of emerging defects, is obtained. The 2D material must be of an insulating type, like the SC2 material of the barrier (so-called large gap semiconductor, no doping, no or very few carriers) in order to maintain the confinement of electrons in the channel located in the buffer layer. According to a preferred embodiment, the first semiconductor material SCI of the buffer layer is gallium nitride GaN. According to another embodiment, the SCI material is AIGaN or AIN. According to one embodiment, the second semiconductor material SC2 of the barrier layer comprises aluminum and is chosen from: AIN; InAIN; AIGaN, ScAIN, InAIGaN. These materials are conventional for nitride-based HEMT technology. According to one embodiment, the second semiconductor material SC2 comprises boron, such as: BN, BGaN, BAIN, BInN, BGaAIN, BGaAlInN.….. The use of Boron is not possible in conventional nitride-based HEMT technology because BN has too great a lattice mismatch with the GaN or AIGaN buffer layer material. Since this constraint is lifted thanks to the presence of the L2D layer, the use of Boron becomes possible in a HEMT transistor according to the invention. The presence of the 2D layer should not change the location of the channel in the buffer layer. According to a preferred embodiment, the insulating 2D layer has a third band gap G3 greater than or equal to 4 eV. As an illustration, an AIN barrier has a band gap equal to 6 eV at room temperature. According to one embodiment, the 2D material is h-BN, which has a G3 band gap of approximately 6 eV. [Fig.8] illustrates an example of the valence bands BV and conduction bands BC of a HEMT structure according to the invention BUF / L2D / Bar for GaN / h-BN / AIN materials (energy E in eV). We are here in the case of growth along

[0001] with G2>G1. Preferably, the 2D material layer has a limited number of L monolayers so that the transconductance gm, which is inversely proportional to the thickness of the barrier, remains sufficiently high. Typically, the L2D layer has 1 to 10 monolayers. For high-frequency operation of the HEMT (20-40 GHz), the number of layers is limited to less than 5, preferably 1 to 3. The inventors have shown by simulation that the 2D material layer does not degrade the electrical performance of the "equivalent" transistor without a 2D layer. This result is not obvious given the difficulty of designing components with good gain performance while operating at high frequency (10-90 GHz). However, it is important to carefully choose the material of the barrier layer by simulation to obtain the desired performance. In other words, starting from a conventional HEMT structure with good performance used as reference performance, the structure of the HEMT transistor according to the invention will possibly have a barrier material different from that of the conventional HEMT to obtain performance comparable to the reference performance. In conventional III-N-based components for which growth occurs along the

[0001] crystallographic axis, the choice of barrier and buffer layer materials is made in such a way that the alignment of the conduction bands and the fixed electric charge surface density 00 induced by piezoelectric effects, at the Bar0 barrier layer / BUFO buffer layer interface, allow the formation of a two-dimensional electron channel located in the buffer layer. For this, the fixed charge must be positive and the electronic affinity of the BarO barrier, noted Yo, must be smaller than that of the BUFO buffer layer, noted xp: : Xo2 < Xoi (1) This condition ensures that the channel is located in the buffer layer and not in the barrier. For example Yp1 7 Yoan= 4EV, Xo2 7 Yax= 2€V and Yo2-Xo1 = XAiN-XGan = -2€V This is the optimal configuration for good RF performance because the mobility and saturation speed of electrons are greater than those of holes. The situation is modified when a 2D material is inserted between the barrier and the buffer layer. In this situation, a fixed positive O2 charge surface density appears at the barrier / 2D material interface and a negative O3 charge surface density at the 2D material / buffer layer interface. The O3 density at the 2D material / buffer layer interface thus tends to repel electrons, which can prevent the formation of an electron-conducting channel if the materials (III-N and 2D) constituting this interface are not judiciously selected. We must have 103l<|o2|. This choice of materials and respective thicknesses must be such that: 1 / a two-dimensional channel forms very close to the 2D material / buffer layer interface. 2 / this channel is located in the buffer layer (in the III-N material). 3 / this channel is filled with electrons. Conditions 1 / and 2 / impose a constraint on the electronic affinities of the materials constituting this interface. Condition 3 / imposes a constraint on the choice of the barrier which must cause a fixed surface charge density 02 at interface 13 which is positive. Let %, and x be the electronic affinities respectively of the buffer layers BUF and barrier Bar in the structure according to the invention, and y; the electronic affinity of the 2D material. Preferably for optimal operation the affinity “must verify a condition close to that verified by the barrier in a classic HEMT (condition (1)) with respect to the buffer, i.e.: Y3-X1 <0 (2) After many simulations a refined condition of condition (2) was established as follows: Ya-4 < -0.5 eV (3) This condition is necessary if we do not want an electron gas to form in the 2D material. For example Y:= Yn-an= 2.5eV verifies condition (3) with respect to Yçan! Ya 7 yh- BN-yGaN = -1.5eV An example of realization is given in [Fig.9] for the case of growth along the crystallographic axis

[0001] . [Fig.9] represents the simulated conduction band diagrams (respectively BCO and BC), when no electrical voltage is applied to the component, for an example of a conventional structure without 2D material (A) and for a non-limiting example of a structure according to the invention with a 2D material inserted between the buffer layer and the barrier (B). Er represents the Fermi level, the energy Ec of the conduction band is in eV. Configuration A: Classic structure; The Bar0 barrier layer is made of AlsoGazoN with a thickness of 4 nm and the BUFO buffer layer is made of GaN. The fixed charge surface density ol induced at the interface Het BUFO buffer layer / Bar0 barrier layer is positive. The performance of this transistor is taken as a reference. Configuration B: structure according to the invention with a L2D layer of 2D material inserted between the Bar barrier layer and the BUF buffer layer; The Bar barrier layer is made of AIN with a thickness of 4 nm, the L2D layer is made of h-BN with a thickness of 0.5 nm, and the BUFO buffer layer is made of GaN. Note that the use of AIN as a barrier layer with a GaN buffer is not possible in a conventional HEMT because the meshes of these two materials are too different. The replacement of AIGaN (configuration A) by AIN for the barrier of configuration B made it possible to adjust the performance of the transistor according to the invention (in terms of electron density at the interfaces) in order to make them equivalent to the performance of the reference transistor (see below [Fig.10]). The spontaneous polarizations 03 and 02 (with |o3I < lo2l) located respectively at the interfaces 11 (buffer layer / 2D materials) and 13 (2D material / barrier) induce a fixed surface density of electric charge, respectively negative and positive. In both configurations A and B a two-dimensional electron channel localized in the buffer layer is formed. For the case of growth along the

[0001] axis (N-face oriented growth) the sign of the charges at the interfaces is reversed. In this case, for example, the GaN buffer can be replaced by AIN and the AIN barrier can be replaced by Al,Ga,.N. The structure according to the invention is thus of the Al,Ga,xN (Bar) / h-BN (Mat2D) / AIN (BUF) type. In this case the electron gas is formed in the barrier. Condition (3) on the affinities is then expressed with respect to y, of SC2: Y3-72< -0.5 eV (4) Thus, in a synthetic way, the condition on affinities is expressed as: Y3-7;S -0.5 eV (5) with i=l or 2 corresponding to the layer in which the channel is located. [Fig.10] represents the power gain MAG (in small signal) as a function of the frequency F for the classic structure A without 2D material (in black, curve 4) and for the structure B according to the invention in which a monolayer of a 2D material, here h-BN, (in gray, curve 5) is inserted between the barrier and the buffer layer. The simulation (performed by TCAD "Technology Computer Aided Design") shows that these two structures have the same RF performance, the structure with a 2D material being potentially more robust than the one without, due to the absence of epitaxial constraints in the barrier. This comparison was made for a HEMT transistor optimized to work in Q band (40 to 50 GHz). According to another aspect, the invention relates to a method for producing a high mobility field effect transistor. In a first step, an assembly is provided comprising a buffer layer BUF deposited on a substrate SUB, the buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound. According to a first variant of the method according to the invention, a L2D layer of two-dimensional insulating Mat2D material on the upper face 11 of the buffer layer. Typically, growth is carried out by Quasi Van der Waals epitaxy. Then a Bar barrier layer is grown on the two-dimensional material layer, the barrier layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and comprising aluminum. Typically the growth is carried out by Quasi Van der Waals epitaxy. Conventionally, the barrier layer and the buffer layer are configured to form a two-dimensional electron gas 9 in a zone of the buffer layer called a channel arranged in the vicinity of the upper face 11 of the buffer layer. Finally, a source S, a drain D, and a gate G are produced in a conventional manner, which is deposited on an upper face 12 of the barrier layer between the source and the drain. According to a second variant, a layer of the two-dimensional material Mat2D grown on an auxiliary substrate SUB' is also provided. This substrate is, for example, copper, nickel or a metal catalyst. Then the 2D layer is transferred to an upper face 11 of the buffer layer and the auxiliary substrate is removed. Then the barrier layer Bar is grown on the two-dimensional material layer L2D. Finally, we make the source, the drain and the grid in the classic way.

Claims

Claims

1. A high mobility field effect transistor (100) comprising: a stack (10) along a Z axis comprising: a substrate (SUB), a buffer layer (BUF) deposited on the substrate, comprising a first semiconductor material (SC1) being a compound binary or ternary or quaternary nitride, a barrier layer (Bar) comprising a second material semiconductor (SC2) being a compound comprising nitrogen (N) and one to five elements chosen from indium (In), aluminum (Al), gallium (Ga), boron (B) and scandium (Sc), a layer (L2D) of a two-dimensional material (Mat2D) insulation placed between the barrier layer and the buffer layer, called 2D layer, the barrier layer and the buffer layer being configured to form a two-dimensional electron gas (9) in a region, called a channel, located in the buffer layer or barrier layer and situated at neighborhood of an interface with the 2D layer, a source (S), a drain (D), and a grid (G) deposited on a upper face (12) of the barrier layer, between the source and the drain.

2. Transistor according to one of the preceding claims in which the 2D layer has a band gap (G3) greater than or equal to 4 eV.

3. Transistor according to one of the preceding claims in which the buffer layer has an electron affinity y,, the barrier layer has an electron affinity x”, the 2D layer has an affinity electronic 3 and in which the electronic affinities verify the relationship: Y3-2;£ -0.5 eV with i = | or 2 corresponding to the layer in which is located said channel.

4. Transistor according to one of the preceding claims in which the 2D layer comprises 1 to 10 monolayers of said bidi- material monthly.

5. Transistor according to one of the preceding claims in which the The first semiconductor material (SCI) is gallium nitride (GaN) or aluminum nitride (AIN) or AlGaN.

6. Transistor according to one of the preceding claims in which the second semiconductor material (SC2) is chosen from: AIN; InAIN; AIGaN; MAIGaN ; ScAIN; ScGaN.

7. Transistor according to one of claims 1 to 5 in which the second semiconductor material (SC2) is chosen from: BN; BGaAIN; BATH; BGaAlInN.

8. Transistor according to one of the preceding claims in which the two-dimensional material is h-BN.

9. Method of producing a high mobility field effect transistor comprising the steps of: have a set including a buffer layer (BUF) deposited on a substrate (SUB), the buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary compound of nitride, grow a layer (L2D) of two-dimensional material (Mat2D) insulating on an upper face (11) of said layer buffer, grow a barrier layer (Bar) on said layer of two-dimensional material, said barrier layer comprising a second semiconductor material being a compound comprising nitrogen (N) and one to five selected elements among indium (In), aluminum (AI), gallium (Ga), boron (B) and scandium (Sc), the barrier layer and the buffer layer being configured to form a two-dimensional electron gas (9) in an area called a channel, located in the buffer layer or barrier layer and situated at neighborhood of an interface with the 2D layer, make a source {S), a drain (D), and a grid (G) deposited on an upper face (12) of the barrier layer between the source and drain.

10. Method of producing a high mobility field effect transistor comprising the steps of: have a set including a buffer layer (BUF) deposited on a substrate (SUB), the buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary compound of nitride, have a 2D layer of a two-dimensional material (Mat2D) grown on an auxiliary substrate (SUB'), transferring said 2D layer onto an upper face (11) of the so-called buffer layer and remove the auxiliary substrate, grow a barrier layer (Bar) on said layer of two-dimensional material, said barrier layer comprising a second semiconductor material being a compound comprising nitrogen (N) and one to five selected elements among indium (In), aluminum (Al), gallium (Ga), boron (B) and scandium (Sc), the barrier layer and the buffer layer being configured to form a two-dimensional electron gas (9) in an area called a channel, located in the buffer layer or barrier layer and situated at neighborhood of an interface with the 2D layer, make a source (S), a drain (D), and a deposited grid (G) on an upper face (12) of the barrier layer between the source and drain.